2019-09-19 14:43:19 +00:00
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From c1fffc2a7dbf7e59aaef36378fb14d1c3dc016a6 Mon Sep 17 00:00:00 2001
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2019-08-09 17:50:30 +00:00
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From: Eric Anholt <eric@anholt.net>
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Date: Fri, 3 Aug 2018 11:22:27 +0200
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2019-12-23 12:42:55 +00:00
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Subject: [PATCH] drm/vc4: Fix TILE_Y_OFFSET definitions
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2019-08-09 17:50:30 +00:00
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Y_OFFSET field starts at bit 8 not 7.
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Signed-off-by: Eric Anholt <eric@anholt.net>
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Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
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Link: https://patchwork.freedesktop.org/patch/msgid/20180803092231.26446-1-boris.brezillon@bootlin.com
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---
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drivers/gpu/drm/vc4/vc4_regs.h | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_regs.h
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+++ b/drivers/gpu/drm/vc4/vc4_regs.h
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@@ -1043,8 +1043,8 @@ enum hvs_pixel_format {
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#define SCALER_PITCH0_TILE_LINE_DIR BIT(15)
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#define SCALER_PITCH0_TILE_INITIAL_LINE_DIR BIT(14)
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/* Y offset within a tile. */
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-#define SCALER_PITCH0_TILE_Y_OFFSET_MASK VC4_MASK(13, 7)
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-#define SCALER_PITCH0_TILE_Y_OFFSET_SHIFT 7
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+#define SCALER_PITCH0_TILE_Y_OFFSET_MASK VC4_MASK(13, 8)
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+#define SCALER_PITCH0_TILE_Y_OFFSET_SHIFT 8
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#define SCALER_PITCH0_TILE_WIDTH_R_MASK VC4_MASK(6, 0)
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#define SCALER_PITCH0_TILE_WIDTH_R_SHIFT 0
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