2020-03-01 09:11:06 +00:00
|
|
|
CONFIG_ARCH_32BIT_OFF_T=y
|
2020-03-01 09:01:09 +00:00
|
|
|
CONFIG_ARCH_CLOCKSOURCE_DATA=y
|
|
|
|
|
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
|
|
|
|
|
CONFIG_ARCH_MMAP_RND_BITS_MAX=15
|
|
|
|
|
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
|
|
|
|
|
CONFIG_ARCH_SUSPEND_POSSIBLE=y
|
2020-03-10 17:34:33 +00:00
|
|
|
CONFIG_AT803X_PHY=y
|
2020-03-01 09:01:09 +00:00
|
|
|
CONFIG_BLK_MQ_PCI=y
|
|
|
|
|
CONFIG_BOARD_SCACHE=y
|
|
|
|
|
CONFIG_BOUNCE=y
|
|
|
|
|
CONFIG_CEVT_R4K=y
|
|
|
|
|
CONFIG_CLKDEV_LOOKUP=y
|
|
|
|
|
CONFIG_CLKSRC_MIPS_GIC=y
|
|
|
|
|
CONFIG_CLONE_BACKWARDS=y
|
|
|
|
|
CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
|
|
|
|
|
CONFIG_CMDLINE_BOOL=y
|
|
|
|
|
# CONFIG_CMDLINE_OVERRIDE is not set
|
|
|
|
|
CONFIG_COMMON_CLK=y
|
|
|
|
|
# CONFIG_COMMON_CLK_BOSTON is not set
|
2020-03-01 09:11:06 +00:00
|
|
|
CONFIG_COMPAT_32BIT_TIME=y
|
2020-03-01 09:01:09 +00:00
|
|
|
CONFIG_CPU_GENERIC_DUMP_TLB=y
|
2020-03-01 09:11:06 +00:00
|
|
|
CONFIG_CPU_HAS_LOAD_STORE_LR=y
|
2020-03-01 09:01:09 +00:00
|
|
|
CONFIG_CPU_HAS_PREFETCH=y
|
|
|
|
|
CONFIG_CPU_HAS_RIXI=y
|
|
|
|
|
CONFIG_CPU_HAS_SYNC=y
|
|
|
|
|
CONFIG_CPU_LITTLE_ENDIAN=y
|
|
|
|
|
CONFIG_CPU_MIPS32=y
|
|
|
|
|
# CONFIG_CPU_MIPS32_R1 is not set
|
|
|
|
|
CONFIG_CPU_MIPS32_R2=y
|
|
|
|
|
CONFIG_CPU_MIPSR2=y
|
|
|
|
|
CONFIG_CPU_MIPSR2_IRQ_EI=y
|
|
|
|
|
CONFIG_CPU_MIPSR2_IRQ_VI=y
|
|
|
|
|
CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
|
|
|
|
|
CONFIG_CPU_R4K_CACHE_TLB=y
|
|
|
|
|
CONFIG_CPU_RMAP=y
|
|
|
|
|
CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
|
|
|
|
|
CONFIG_CPU_SUPPORTS_HIGHMEM=y
|
|
|
|
|
CONFIG_CPU_SUPPORTS_MSA=y
|
|
|
|
|
CONFIG_CRC16=y
|
|
|
|
|
CONFIG_CRYPTO_ACOMP2=y
|
|
|
|
|
CONFIG_CRYPTO_AEAD=y
|
|
|
|
|
CONFIG_CRYPTO_AEAD2=y
|
|
|
|
|
CONFIG_CRYPTO_DEFLATE=y
|
|
|
|
|
CONFIG_CRYPTO_HASH2=y
|
2020-03-01 09:11:06 +00:00
|
|
|
CONFIG_CRYPTO_HASH_INFO=y
|
2021-03-05 20:07:40 +00:00
|
|
|
CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
|
2020-03-01 09:01:09 +00:00
|
|
|
CONFIG_CRYPTO_LZO=y
|
|
|
|
|
CONFIG_CRYPTO_MANAGER=y
|
|
|
|
|
CONFIG_CRYPTO_MANAGER2=y
|
|
|
|
|
CONFIG_CRYPTO_NULL2=y
|
|
|
|
|
CONFIG_CRYPTO_RNG2=y
|
|
|
|
|
CONFIG_CSRC_R4K=y
|
|
|
|
|
CONFIG_DEBUG_PINCTRL=y
|
2020-12-02 15:42:07 +00:00
|
|
|
CONFIG_DIMLIB=y
|
2020-03-01 09:01:09 +00:00
|
|
|
CONFIG_DMA_NONCOHERENT=y
|
2020-03-01 09:11:06 +00:00
|
|
|
CONFIG_DMA_NONCOHERENT_CACHE_SYNC=y
|
|
|
|
|
# CONFIG_DTB_GNUBEE1 is not set
|
|
|
|
|
# CONFIG_DTB_GNUBEE2 is not set
|
2020-03-01 09:01:09 +00:00
|
|
|
CONFIG_DTB_RT_NONE=y
|
|
|
|
|
CONFIG_DTC=y
|
|
|
|
|
CONFIG_EARLY_PRINTK=y
|
|
|
|
|
CONFIG_FIXED_PHY=y
|
2020-03-01 09:11:06 +00:00
|
|
|
CONFIG_FW_LOADER_PAGED_BUF=y
|
2020-03-01 09:01:09 +00:00
|
|
|
CONFIG_GENERIC_ATOMIC64=y
|
|
|
|
|
CONFIG_GENERIC_CLOCKEVENTS=y
|
|
|
|
|
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
|
|
|
|
|
CONFIG_GENERIC_CMOS_UPDATE=y
|
|
|
|
|
CONFIG_GENERIC_CPU_AUTOPROBE=y
|
2020-03-01 09:11:06 +00:00
|
|
|
CONFIG_GENERIC_GETTIMEOFDAY=y
|
|
|
|
|
CONFIG_GENERIC_IOMAP=y
|
2020-03-01 09:01:09 +00:00
|
|
|
CONFIG_GENERIC_IRQ_CHIP=y
|
|
|
|
|
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
|
|
|
|
|
CONFIG_GENERIC_IRQ_IPI=y
|
|
|
|
|
CONFIG_GENERIC_IRQ_SHOW=y
|
2020-03-01 09:11:06 +00:00
|
|
|
CONFIG_GENERIC_LIB_ASHLDI3=y
|
|
|
|
|
CONFIG_GENERIC_LIB_ASHRDI3=y
|
|
|
|
|
CONFIG_GENERIC_LIB_CMPDI2=y
|
|
|
|
|
CONFIG_GENERIC_LIB_LSHRDI3=y
|
|
|
|
|
CONFIG_GENERIC_LIB_UCMPDI2=y
|
2020-03-01 09:01:09 +00:00
|
|
|
CONFIG_GENERIC_PCI_IOMAP=y
|
2020-03-01 09:11:06 +00:00
|
|
|
CONFIG_GENERIC_PHY=y
|
|
|
|
|
CONFIG_GENERIC_PINCONF=y
|
2020-03-01 09:01:09 +00:00
|
|
|
CONFIG_GENERIC_SCHED_CLOCK=y
|
|
|
|
|
CONFIG_GENERIC_SMP_IDLE_THREAD=y
|
|
|
|
|
CONFIG_GENERIC_TIME_VSYSCALL=y
|
|
|
|
|
CONFIG_GPIOLIB=y
|
2020-03-01 09:11:06 +00:00
|
|
|
CONFIG_GPIOLIB_IRQCHIP=y
|
|
|
|
|
CONFIG_GPIO_GENERIC=y
|
2020-03-01 09:01:09 +00:00
|
|
|
CONFIG_GPIO_MT7621=y
|
|
|
|
|
# CONFIG_GPIO_RALINK is not set
|
|
|
|
|
CONFIG_GPIO_WATCHDOG=y
|
|
|
|
|
# CONFIG_GPIO_WATCHDOG_ARCH_INITCALL is not set
|
2020-12-02 15:42:07 +00:00
|
|
|
CONFIG_GRO_CELLS=y
|
2020-03-01 09:01:09 +00:00
|
|
|
CONFIG_HANDLE_DOMAIN_IRQ=y
|
|
|
|
|
CONFIG_HARDWARE_WATCHPOINTS=y
|
|
|
|
|
CONFIG_HAS_DMA=y
|
|
|
|
|
CONFIG_HAS_IOMEM=y
|
|
|
|
|
CONFIG_HAS_IOPORT_MAP=y
|
|
|
|
|
CONFIG_HIGHMEM=y
|
2020-03-01 09:11:06 +00:00
|
|
|
CONFIG_HZ=250
|
|
|
|
|
CONFIG_HZ_250=y
|
2020-03-01 09:01:09 +00:00
|
|
|
CONFIG_HZ_PERIODIC=y
|
|
|
|
|
CONFIG_I2C=y
|
|
|
|
|
CONFIG_I2C_BOARDINFO=y
|
|
|
|
|
CONFIG_I2C_MT7621=y
|
|
|
|
|
CONFIG_INITRAMFS_SOURCE=""
|
|
|
|
|
CONFIG_IRQCHIP=y
|
|
|
|
|
CONFIG_IRQ_DOMAIN=y
|
|
|
|
|
CONFIG_IRQ_DOMAIN_HIERARCHY=y
|
|
|
|
|
CONFIG_IRQ_FORCED_THREADING=y
|
|
|
|
|
CONFIG_IRQ_MIPS_CPU=y
|
|
|
|
|
CONFIG_IRQ_WORK=y
|
2020-03-01 09:11:06 +00:00
|
|
|
CONFIG_LED_TRIGGER_PHY=y
|
2020-03-01 09:01:09 +00:00
|
|
|
CONFIG_LIBFDT=y
|
2020-03-01 09:11:06 +00:00
|
|
|
CONFIG_LOCK_DEBUGGING_SUPPORT=y
|
2020-03-01 09:01:09 +00:00
|
|
|
CONFIG_LZO_COMPRESS=y
|
|
|
|
|
CONFIG_LZO_DECOMPRESS=y
|
|
|
|
|
CONFIG_MDIO_BUS=y
|
|
|
|
|
CONFIG_MDIO_DEVICE=y
|
2020-03-01 09:11:06 +00:00
|
|
|
CONFIG_MEMFD_CREATE=y
|
|
|
|
|
CONFIG_MFD_SYSCON=y
|
2020-03-01 09:01:09 +00:00
|
|
|
CONFIG_MIGRATION=y
|
2020-04-28 13:57:41 +00:00
|
|
|
CONFIG_MIKROTIK=y
|
|
|
|
|
CONFIG_MIKROTIK_RB_SYSFS=y
|
2020-03-01 09:01:09 +00:00
|
|
|
CONFIG_MIPS=y
|
|
|
|
|
CONFIG_MIPS_ASID_BITS=8
|
|
|
|
|
CONFIG_MIPS_ASID_SHIFT=0
|
2020-12-02 15:42:07 +00:00
|
|
|
CONFIG_MIPS_CBPF_JIT=y
|
2020-03-01 09:01:09 +00:00
|
|
|
CONFIG_MIPS_CLOCK_VSYSCALL=y
|
|
|
|
|
CONFIG_MIPS_CM=y
|
|
|
|
|
# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set
|
|
|
|
|
# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set
|
|
|
|
|
# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
|
|
|
|
|
CONFIG_MIPS_CMDLINE_FROM_DTB=y
|
|
|
|
|
CONFIG_MIPS_CPC=y
|
|
|
|
|
CONFIG_MIPS_CPS=y
|
2020-03-01 09:11:06 +00:00
|
|
|
# CONFIG_MIPS_CPS_NS16550_BOOL is not set
|
2020-03-01 09:01:09 +00:00
|
|
|
CONFIG_MIPS_CPU_SCACHE=y
|
|
|
|
|
# CONFIG_MIPS_ELF_APPENDED_DTB is not set
|
|
|
|
|
CONFIG_MIPS_GIC=y
|
|
|
|
|
CONFIG_MIPS_L1_CACHE_SHIFT=5
|
|
|
|
|
CONFIG_MIPS_MT=y
|
|
|
|
|
CONFIG_MIPS_MT_FPAFF=y
|
|
|
|
|
CONFIG_MIPS_MT_SMP=y
|
|
|
|
|
# CONFIG_MIPS_NO_APPENDED_DTB is not set
|
2020-03-01 09:11:06 +00:00
|
|
|
CONFIG_MIPS_NR_CPU_NR_MAP=4
|
2020-03-01 09:01:09 +00:00
|
|
|
CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y
|
|
|
|
|
CONFIG_MIPS_RAW_APPENDED_DTB=y
|
|
|
|
|
CONFIG_MIPS_SPRAM=y
|
|
|
|
|
CONFIG_MODULES_USE_ELF_REL=y
|
|
|
|
|
CONFIG_MT7621_WDT=y
|
|
|
|
|
# CONFIG_MTD_CFI_INTELEXT is not set
|
|
|
|
|
CONFIG_MTD_CMDLINE_PARTS=y
|
2020-03-01 09:11:06 +00:00
|
|
|
CONFIG_MTD_NAND_CORE=y
|
|
|
|
|
CONFIG_MTD_NAND_ECC_SW_HAMMING=y
|
2020-04-01 03:19:12 +00:00
|
|
|
CONFIG_MTD_NAND_MT7621=y
|
2020-03-01 09:01:09 +00:00
|
|
|
CONFIG_MTD_PHYSMAP=y
|
2020-03-01 09:11:06 +00:00
|
|
|
CONFIG_MTD_RAW_NAND=y
|
2020-03-24 10:22:00 +00:00
|
|
|
CONFIG_MTD_ROUTERBOOT_PARTS=y
|
2020-03-01 09:01:09 +00:00
|
|
|
CONFIG_MTD_SPI_NOR=y
|
ramips: add support for Ubiquiti UniFi 6 Lite
Hardware
--------
MediaTek MT7621AT
256M DDR3
32M SPI-NOR
MediaTek MT7603 2T2R 802.11n 2.4GHz
MediaTek MT7915 2T2R 802.11ax 5GHz
Not Working
-----------
- Bluetooth (connected to UART3)
UART
----
UART is located in the lower left corner of the board. Pinout is
0 - 3V3 (don't connect)
1 - RX
2 - TX
3 - GND
Console is 115200 8N1.
Boot
----
1. Connect to the serial console and connect power.
2. Double-press ESC when prompted
3. Set the fdt address
$ fdt addr $(fdtcontroladdr)
4. Remove the signature node from the control FDT
$ fdt rm /signature
5. Transfer and boot the OpenWrt initramfs image to the device.
Make sure to name the file C0A80114.img and have it reachable at
192.168.1.1/24
$ tftpboot; bootm
Installation
------------
1. Connect to the booted device at 192.168.1.20 using username/password
"ubnt".
2. Update the bootloader environment.
$ fw_setenv devmode TRUE
$ fw_setenv boot_openwrt "fdt addr \$(fdtcontroladdr);
fdt rm /signature; bootubnt"
$ fw_setenv bootcmd "run boot_openwrt"
3. Transfer the OpenWrt sysupgrade image to the device using SCP.
4. Check the mtd partition number for bs / kernel0 / kernel1
$ cat /proc/mtd
5. Set the bootselect flag to boot from kernel0
$ dd if=/dev/zero bs=1 count=1 of=/dev/mtdblock4
6. Write the OpenWrt sysupgrade image to both kernel0 as well as kernel1
$ dd if=openwrt.bin of=/dev/mtdblock6
$ dd if=openwrt.bin of=/dev/mtdblock7
7. Reboot the device. It should boot into OpenWrt.
Below are the original installation instructions prior to the discovery
of "devmode=TRUE". They are not required for installation and are
documentation only.
The bootloader employs signature verification on the FIT image
configurations. This way, booting unauthorized image without patching
the bootloader is not possible. Manually configuring the bootcmd in the
U-Boot envronment won't work, as this is restored to the default value
if modified.
The bootloader is made up of three different parts.
1. The SPL performing early board initialization and providing a XModem
recovery in case the PBL is missing
2. The PBL being the primary U-Boot application and containing the
control FDT. It is LZMA packed with a uImage header.
3. A Ubiquiti standalone U-Boot application providing the main boot
routine as well as their recovery mechanism.
In a perfect world, we would only replace the PBL, as the SPL does not
perform checks on the PBLs integrity. However, as the PBL is in the same
eraseblock as the SPL, we need to at least rewrite both.
The bootloader will only verify integrity in case it has a "signature"
node in it's control device-tree. Renaming the signature node to
something else will prevent this from happening.
Warning: These instructions are based on the firmware intially
shipped with the device and potentially brick your device in a way it
can only be recovered using a SPI flasher.
Only (!) proceed if you understand this!
1. Extract the bootloader from the U-Boot partition using the OpenWrt
initramfs image.
2. Split the bootloader into it's 3 components:
$ dd if=bootloader.bin of=spl.bin bs=1 skip=0 count=45056
$ dd if=bootloader.bin of=pbl.uimage bs=1 skip=45056 count=143360
$ dd if=bootloader.bin of=ubnt.uimage bs=1 skip=188416
3. Strip the uImage header from the PBL
$ dd if=pbl.uimage of=pbl.lzma bs=64 skip=1
4. Decompress the PBL
$ lzma -d pbl.lzma --single-stream
The decompressed PBL sha256sum should be
d8b406c65240d260cf15be5f97f40c1d6d1b6e61ec3abed37bb841c90fcc1235
5. Open the decompressed PBL using your favorite hexeditor. Locate the
control FDT at offset 0x4CED0 (0xD00DFEED). At offset 0x4D5BC, the
label for the signature node is located. Rename the "signature"
string at this offset to "signaturr".
The patched PBL sha256sum should be
d028e374cdb40ba44b6e3cef2e4e8a8c16a3b85eb15d9544d24fdd10eed64c97
6. Compress the patched PBL
$ lzma -z pbl --lzma1=dict=67108864
The resulting pbl.lzma file should have the sha256sum
7ae6118928fa0d0b3fe4ff81abd80ecfd9ba2944cb0f0a462b6ae65913088b42
7. Create the PBL uimage
$ SOURCE_DATE_EPOCH=1607909492 mkimage -A mips -O u-boot -C lzma
-n "U-Boot 2018.03 [UniFi,v1.1.40.71]" -a 84000000 -e 84000000
-T firmware -d pbl.lzma patched_pbl.uimage
The resulting patched_pbl.uimage should have the sha256sum
b90d7fa2dcc6814180d3943530d8d6b0d6a03636113c94e99af34f196d3cf2ce
8. Reassemble the complete bootloader
$ dd if=patched_pbl.uimage of=aligned_pbl.uimage bs=143360 count=1
conv=sync
$ cat spl.bin > patched_uboot.bin
$ cat aligned_pbl.uimage >> patched_uboot.bin
$ cat ubnt.uimage >> patched_uboot.bin
The resulting patched_uboot.bin should have the sha256sum
3e1186f33b88a525687285c2a8b22e8786787b31d4648b8eee66c672222aa76b
9. Transfer your patched bootloader to the device. Also install the
kmod-mtd-rw package using opkg and load it.
$ insmod mtd-rw.ko i_want_a_brick=1
Write the patched bootloader to mtd0
$ mtd write patched_uboot.bin u-boot
10. Erase the kernel1 partition, as the bootloader might otherwise
decide to boot from there.
$ mtd erase kernel1
11. Transfer the OpenWrt sysupgrade image to the device and install
using sysupgrade.
FIT configurations
------------------
In the future, the MT7621 UniFi6 family can be supported by a single
OpenWrt image.
config@1: U6 Lite
config@2: U6 IW
config@3: U6 Mesh
config@4: U6 Extender
config@5: U6 LR-EA (Early Access - GA is MT7622)
Signed-off-by: David Bauer <mail@david-bauer.net>
2020-12-12 13:34:00 +00:00
|
|
|
CONFIG_MTD_SPLIT_FIT_FW=y
|
2020-03-01 09:01:09 +00:00
|
|
|
CONFIG_MTD_SPLIT_MINOR_FW=y
|
|
|
|
|
CONFIG_MTD_SPLIT_SEAMA_FW=y
|
|
|
|
|
CONFIG_MTD_SPLIT_TPLINK_FW=y
|
|
|
|
|
CONFIG_MTD_SPLIT_TRX_FW=y
|
|
|
|
|
CONFIG_MTD_SPLIT_UIMAGE_FW=y
|
|
|
|
|
CONFIG_MTD_UBI=y
|
|
|
|
|
CONFIG_MTD_UBI_BEB_LIMIT=20
|
|
|
|
|
CONFIG_MTD_UBI_BLOCK=y
|
|
|
|
|
CONFIG_MTD_UBI_WL_THRESHOLD=4096
|
2020-04-06 05:17:47 +00:00
|
|
|
CONFIG_MTD_VIRT_CONCAT=y
|
2020-03-01 09:11:06 +00:00
|
|
|
# CONFIG_MTK_HSDMA is not set
|
2020-03-01 09:01:09 +00:00
|
|
|
CONFIG_NEED_DMA_MAP_STATE=y
|
2020-03-01 09:11:06 +00:00
|
|
|
CONFIG_NET_DEVLINK=y
|
|
|
|
|
CONFIG_NET_DSA=y
|
|
|
|
|
CONFIG_NET_DSA_MT7530=y
|
|
|
|
|
CONFIG_NET_DSA_TAG_MTK=y
|
2020-03-01 09:01:09 +00:00
|
|
|
CONFIG_NET_FLOW_LIMIT=y
|
|
|
|
|
CONFIG_NET_MEDIATEK_SOC=y
|
2020-03-01 09:11:06 +00:00
|
|
|
CONFIG_NET_SWITCHDEV=y
|
2020-03-01 09:01:09 +00:00
|
|
|
CONFIG_NET_VENDOR_MEDIATEK=y
|
2020-04-09 06:09:48 +00:00
|
|
|
# CONFIG_NET_VENDOR_RALINK is not set
|
2020-03-01 09:01:09 +00:00
|
|
|
CONFIG_NR_CPUS=4
|
|
|
|
|
CONFIG_OF=y
|
|
|
|
|
CONFIG_OF_ADDRESS=y
|
|
|
|
|
CONFIG_OF_EARLY_FLATTREE=y
|
|
|
|
|
CONFIG_OF_FLATTREE=y
|
|
|
|
|
CONFIG_OF_GPIO=y
|
|
|
|
|
CONFIG_OF_IRQ=y
|
2020-03-01 09:11:06 +00:00
|
|
|
CONFIG_OF_KOBJ=y
|
2020-03-01 09:01:09 +00:00
|
|
|
CONFIG_OF_MDIO=y
|
|
|
|
|
CONFIG_OF_NET=y
|
|
|
|
|
CONFIG_PADATA=y
|
|
|
|
|
CONFIG_PCI=y
|
|
|
|
|
CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
|
|
|
|
|
CONFIG_PCI_DOMAINS=y
|
2020-03-01 09:11:06 +00:00
|
|
|
CONFIG_PCI_DOMAINS_GENERIC=y
|
|
|
|
|
CONFIG_PCI_DRIVERS_GENERIC=y
|
|
|
|
|
CONFIG_PCI_MT7621=y
|
|
|
|
|
CONFIG_PCI_MT7621_PHY=y
|
2020-03-01 09:01:09 +00:00
|
|
|
CONFIG_PERF_USE_VMALLOC=y
|
|
|
|
|
CONFIG_PGTABLE_LEVELS=2
|
|
|
|
|
CONFIG_PHYLIB=y
|
2020-03-01 09:11:06 +00:00
|
|
|
CONFIG_PHYLINK=y
|
2020-03-01 09:01:09 +00:00
|
|
|
# CONFIG_PHY_RALINK_USB is not set
|
|
|
|
|
CONFIG_PINCTRL=y
|
|
|
|
|
CONFIG_PINCTRL_RT2880=y
|
|
|
|
|
# CONFIG_PINCTRL_SINGLE is not set
|
2021-02-20 13:45:26 +00:00
|
|
|
CONFIG_PINCTRL_SX150X=y
|
2021-03-05 20:07:40 +00:00
|
|
|
CONFIG_PLUGIN_HOSTCC="g++"
|
2020-03-01 09:01:09 +00:00
|
|
|
CONFIG_POWER_RESET=y
|
|
|
|
|
CONFIG_POWER_RESET_GPIO=y
|
|
|
|
|
CONFIG_POWER_SUPPLY=y
|
|
|
|
|
CONFIG_QUEUED_RWLOCKS=y
|
|
|
|
|
CONFIG_QUEUED_SPINLOCKS=y
|
|
|
|
|
CONFIG_RALINK=y
|
|
|
|
|
# CONFIG_RALINK_WDT is not set
|
|
|
|
|
CONFIG_RATIONAL=y
|
|
|
|
|
CONFIG_RCU_NEED_SEGCBLIST=y
|
|
|
|
|
CONFIG_RCU_STALL_COMMON=y
|
|
|
|
|
CONFIG_REGMAP=y
|
2020-03-01 09:11:06 +00:00
|
|
|
CONFIG_REGMAP_MMIO=y
|
2020-03-01 09:01:09 +00:00
|
|
|
CONFIG_REGULATOR=y
|
|
|
|
|
CONFIG_REGULATOR_FIXED_VOLTAGE=y
|
|
|
|
|
CONFIG_RESET_CONTROLLER=y
|
|
|
|
|
CONFIG_RFS_ACCEL=y
|
|
|
|
|
CONFIG_RPS=y
|
|
|
|
|
CONFIG_RTC_CLASS=y
|
|
|
|
|
CONFIG_RTC_DRV_BQ32K=y
|
|
|
|
|
CONFIG_RTC_DRV_PCF8563=y
|
|
|
|
|
CONFIG_RTC_I2C_AND_SPI=y
|
|
|
|
|
CONFIG_RTC_MC146818_LIB=y
|
|
|
|
|
CONFIG_SCHED_SMT=y
|
|
|
|
|
CONFIG_SERIAL_8250_NR_UARTS=3
|
|
|
|
|
CONFIG_SERIAL_8250_RUNTIME_UARTS=3
|
2020-03-01 09:11:06 +00:00
|
|
|
CONFIG_SERIAL_MCTRL_GPIO=y
|
2020-03-01 09:01:09 +00:00
|
|
|
CONFIG_SERIAL_OF_PLATFORM=y
|
2020-03-01 09:11:06 +00:00
|
|
|
CONFIG_SGL_ALLOC=y
|
2020-03-01 09:01:09 +00:00
|
|
|
CONFIG_SMP=y
|
|
|
|
|
CONFIG_SMP_UP=y
|
|
|
|
|
# CONFIG_SOC_MT7620 is not set
|
|
|
|
|
CONFIG_SOC_MT7621=y
|
|
|
|
|
# CONFIG_SOC_RT288X is not set
|
|
|
|
|
# CONFIG_SOC_RT305X is not set
|
|
|
|
|
# CONFIG_SOC_RT3883 is not set
|
|
|
|
|
CONFIG_SPI=y
|
|
|
|
|
CONFIG_SPI_MASTER=y
|
2020-03-01 09:11:06 +00:00
|
|
|
CONFIG_SPI_MEM=y
|
2020-03-01 09:01:09 +00:00
|
|
|
CONFIG_SPI_MT7621=y
|
|
|
|
|
# CONFIG_SPI_RT2880 is not set
|
|
|
|
|
CONFIG_SRCU=y
|
|
|
|
|
CONFIG_SWPHY=y
|
|
|
|
|
CONFIG_SYNC_R4K=y
|
|
|
|
|
CONFIG_SYSCTL_EXCEPTION_TRACE=y
|
|
|
|
|
CONFIG_SYS_HAS_CPU_MIPS32_R1=y
|
|
|
|
|
CONFIG_SYS_HAS_CPU_MIPS32_R2=y
|
|
|
|
|
CONFIG_SYS_HAS_EARLY_PRINTK=y
|
|
|
|
|
CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
|
|
|
|
|
CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
|
|
|
|
|
CONFIG_SYS_SUPPORTS_HIGHMEM=y
|
|
|
|
|
CONFIG_SYS_SUPPORTS_HOTPLUG_CPU=y
|
|
|
|
|
CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
|
|
|
|
|
CONFIG_SYS_SUPPORTS_MIPS16=y
|
|
|
|
|
CONFIG_SYS_SUPPORTS_MIPS_CPS=y
|
|
|
|
|
CONFIG_SYS_SUPPORTS_MULTITHREADING=y
|
|
|
|
|
CONFIG_SYS_SUPPORTS_SCHED_SMT=y
|
|
|
|
|
CONFIG_SYS_SUPPORTS_SMP=y
|
2020-12-02 15:42:07 +00:00
|
|
|
CONFIG_SYS_SUPPORTS_ZBOOT=y
|
2020-03-01 09:11:06 +00:00
|
|
|
CONFIG_TARGET_ISA_REV=2
|
2020-03-01 09:01:09 +00:00
|
|
|
CONFIG_TICK_CPU_ACCOUNTING=y
|
|
|
|
|
CONFIG_TIMER_OF=y
|
|
|
|
|
CONFIG_TIMER_PROBE=y
|
|
|
|
|
CONFIG_TREE_RCU=y
|
|
|
|
|
CONFIG_TREE_SRCU=y
|
|
|
|
|
CONFIG_UBIFS_FS=y
|
|
|
|
|
CONFIG_UBIFS_FS_ADVANCED_COMPR=y
|
|
|
|
|
CONFIG_UBIFS_FS_LZO=y
|
|
|
|
|
CONFIG_UBIFS_FS_ZLIB=y
|
|
|
|
|
CONFIG_USB_SUPPORT=y
|
|
|
|
|
CONFIG_USE_OF=y
|
|
|
|
|
CONFIG_WATCHDOG_CORE=y
|
|
|
|
|
CONFIG_WEAK_ORDERING=y
|
|
|
|
|
CONFIG_WEAK_REORDERING_BEYOND_LLSC=y
|
|
|
|
|
CONFIG_XPS=y
|
|
|
|
|
CONFIG_ZLIB_DEFLATE=y
|
|
|
|
|
CONFIG_ZLIB_INFLATE=y
|
