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60 lines
2.4 KiB
Diff
60 lines
2.4 KiB
Diff
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From db90a5e5fc2fbd843b29eb8110ed5e03604a2887 Mon Sep 17 00:00:00 2001
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From: Jonathan Bell <jonathan@raspberrypi.com>
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Date: Wed, 20 Sep 2023 13:04:54 +0100
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Subject: [PATCH] arm: dt: add dtparams for PCIe reset timing override
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The Pi 5 variant gets two parameters so that the CM4-compatible
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name will also work on Pi 5.
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Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
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---
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arch/arm/boot/dts/bcm2711-rpi-cm4.dts | 2 ++
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arch/arm/boot/dts/bcm2712-rpi-5-b.dts | 2 ++
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arch/arm/boot/dts/overlays/README | 7 +++++++
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3 files changed, 11 insertions(+)
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--- a/arch/arm/boot/dts/bcm2711-rpi-cm4.dts
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+++ b/arch/arm/boot/dts/bcm2711-rpi-cm4.dts
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@@ -446,5 +446,7 @@ i2c_csi_dsi0: &i2c0 {
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cam1_reg = <&cam1_reg>,"status";
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cam1_reg_gpio = <&cam1_reg>,"gpio:4",
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<&cam1_reg>,"gpio:0=", <&gpio>;
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+
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+ pcie_tperst_clk_ms = <&pcie0>,"brcm,tperst-clk-ms:0";
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};
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};
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--- a/arch/arm/boot/dts/bcm2712-rpi-5-b.dts
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+++ b/arch/arm/boot/dts/bcm2712-rpi-5-b.dts
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@@ -814,6 +814,8 @@ spi10_cs_pins: &spi10_cs_gpio1 {};
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pciex1 = <&pciex1>, "status";
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pciex1_gen = <&pciex1> , "max-link-speed:0";
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pciex1_no_l0s = <&pciex1>, "aspm-no-l0s?";
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+ pciex1_tperst_clk_ms = <&pciex1>, "brcm,tperst-clk-ms:0";
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+ pcie_tperst_clk_ms = <&pciex1>, "brcm,tperst-clk-ms:0";
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random = <&random>, "status";
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rtc_bbat_vchg = <&rpi_rtc>, "trickle-charge-microvolt:0";
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spi = <&spi0>, "status";
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--- a/arch/arm/boot/dts/overlays/README
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+++ b/arch/arm/boot/dts/overlays/README
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@@ -280,6 +280,10 @@ Params:
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(2711 only, but not applicable on CM4S)
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N.B. USB-A ports on 4B are subsequently disabled
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+ pcie_tperst_clk_ms Add N milliseconds between PCIe reference clock
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+ activation and PERST# deassertion
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+ (CM4 and 2712, default "0")
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+
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pciex1 Set to "on" to enable the external PCIe link
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(2712 only, default "off")
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@@ -290,6 +294,9 @@ Params:
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PCIe link for devices that have broken
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implementations (2712 only, default "off")
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+ pciex1_tperst_clk_ms Alias for pcie_tperst_clk_ms
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+ (2712 only, default "0")
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+
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spi Set to "on" to enable the spi interfaces
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(default "off")
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