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38 lines
1.3 KiB
Diff
38 lines
1.3 KiB
Diff
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From: Jernej Skrabec <jernej.skrabec@siol.net>
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Allwinner H6 PWM is similar to that in A20 except that it has additional
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bus clock and reset line.
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Note that first PWM channel is connected to output pin and second
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channel is used internally, as a clock source to AC200 co-packaged chip.
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This means that any combination of these two channels can be used and
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thus it doesn't make sense to add pinctrl nodes at this point.
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Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
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Signed-off-by: Clément Péron <peron.clem@gmail.com>
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---
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arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 10 ++++++++++
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1 file changed, 10 insertions(+)
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diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
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index 29824081b43b..6d4bde488f15 100644
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--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
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@@ -245,6 +245,16 @@
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status = "disabled";
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};
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+ pwm: pwm@300a000 {
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+ compatible = "allwinner,sun50i-h6-pwm";
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+ reg = <0x0300a000 0x400>;
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+ clocks = <&osc24M>, <&ccu CLK_BUS_PWM>;
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+ clock-names = "mod", "bus";
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+ resets = <&ccu RST_BUS_PWM>;
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+ #pwm-cells = <3>;
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+ status = "disabled";
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+ };
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+
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pio: pinctrl@300b000 {
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compatible = "allwinner,sun50i-h6-pinctrl";
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reg = <0x0300b000 0x400>;
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