openwrt/target/linux/bcm27xx/patches-6.1/950-0730-bcm2711-rpi-ds-Switch-to-dma40-channel-for-hdmi-audi.patch

From e73d889889d4795cc1640ec0a6f813bfe585b838 Mon Sep 17 00:00:00 2001
From: Dom Cobley <popcornmix@gmail.com>
Date: Thu, 4 May 2023 16:09:49 +0100
Subject: [PATCH] bcm2711-rpi-ds: Switch to dma40 channel for hdmi
 audio

Also tweak the flags:
Remove NO_WAIT_RESP (27)
Add BURST_LENGTH (30)

The AXI path from DMA controller to HDMI audio fifo
is long, and may have considerable delay.

When using DMA without waiting for responses it is
very easy to overfill the fifo as when the fifo
removes DREQ there may be large numbers of writes
in flight.

This means the DREQ fifo threshold must be set low
enough to accommodate the maximum number of in flight
writes (unknown by something like 24),
which means the 32 element fifo only requests data
when it contains fewer than 8 entries, making it
susceptable to underflow.

If we wait for write responses we can set the DREQ
fifo threshold much higher as there are a controlled
number of writes in flight.

However the overall bandwidth is reduced by setting
this, so also enable a burstsize of 4 to improve
bandwidth.

Signed-off-by: Dom Cobley <popcornmix@gmail.com>
---
 arch/arm/boot/dts/bcm2711-rpi-ds.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

--- a/arch/arm/boot/dts/bcm2711-rpi-ds.dtsi
+++ b/arch/arm/boot/dts/bcm2711-rpi-ds.dtsi
@@ -364,7 +364,7 @@
 		 <&firmware_clocks 14>,
 		 <&dvp 0>,
 		 <&clk_27MHz>;
-	dmas = <&dma (10|(1<<27)|(1<<24)|(10<<16)|(15<<20))>;
+	dmas = <&dma40 (10|(1<<30)|(1<<24)|(10<<16)|(15<<20))>;
 	status = "disabled";
 };
 
@@ -397,7 +397,7 @@
 		 <&firmware_clocks 14>,
 		 <&dvp 1>,
 		 <&clk_27MHz>;
-	dmas = <&dma (17|(1<<27)|(1<<24)|(10<<16)|(15<<20))>;
+	dmas = <&dma40 (17|(1<<30)|(1<<24)|(10<<16)|(15<<20))>;
 	status = "disabled";
 };