mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-30 18:47:06 +00:00
29 lines
943 B
Diff
29 lines
943 B
Diff
|
From 075b3ca8a4223742abc6da2406afe206d97f3d52 Mon Sep 17 00:00:00 2001
|
||
|
|
From: Robert Marko <robimarko@gmail.com>
|
||
|
|
Date: Wed, 16 Nov 2022 22:48:33 +0100
|
||
|
|
Subject: [PATCH] arm64: dts: qcom: ipq8074: fix Gen2 PCIe QMP PHY
|
||
|
|
|
||
|
|
Serdes register space sizes are incorrect, update them to match the
|
||
|
|
actual sizes from downstream QCA 5.4 kernel.
|
||
|
|
|
||
|
|
Fixes: 942bcd33ed45 ("arm64: dts: qcom: Fix IPQ8074 PCIe PHY nodes")
|
||
|
|
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
||
|
|
---
|
||
|
|
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++--
|
||
|
|
1 file changed, 2 insertions(+), 2 deletions(-)
|
||
|
|
|
||
|
|
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
||
|
|
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
||
|
|
@@ -277,9 +277,9 @@
|
||
|
|
status = "disabled";
|
||
|
|
|
||
|
|
pcie_phy1: phy@8e200 {
|
||
|
|
- reg = <0x8e200 0x16c>,
|
||
|
|
+ reg = <0x8e200 0x130>,
|
||
|
|
<0x8e400 0x200>,
|
||
|
|
- <0x8e800 0x4f4>;
|
||
|
|
+ <0x8e800 0x1f8>;
|
||
|
|
#phy-cells = <0>;
|
||
|
|
#clock-cells = <0>;
|
||
|
|
clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
|