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53 lines
1.5 KiB
Diff
53 lines
1.5 KiB
Diff
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From 1f1c12e85defba9459b41ec95b86f23b4791f1ab Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Mon, 4 Aug 2014 20:43:25 +0200
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Subject: [PATCH 23/57] MIPS: ralink: mt7620: fix usb issue during frequency
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scaling
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If the USB HCD is running and the cpu is scaled too low, then the USB stops
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working. Increase the idle speed of the core to fix this if the kernel is
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built with USB support.
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The values are taken from the Ralink SDK Kernel.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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arch/mips/ralink/mt7620.c | 19 +++++++++++++++++++
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1 file changed, 19 insertions(+)
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--- a/arch/mips/ralink/mt7620.c
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+++ b/arch/mips/ralink/mt7620.c
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@@ -36,6 +36,12 @@
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#define PMU1_CFG 0x8C
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#define DIG_SW_SEL BIT(25)
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+/* clock scaling */
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+#define CLKCFG_FDIV_MASK 0x1f00
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+#define CLKCFG_FDIV_USB_VAL 0x0300
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+#define CLKCFG_FFRAC_MASK 0x001f
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+#define CLKCFG_FFRAC_USB_VAL 0x0003
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+
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/* does the board have sdram or ddram */
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static int dram_type;
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@@ -337,6 +343,19 @@ void __init ralink_clk_init(void)
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ralink_clk_add("10000b00.spi", sys_rate);
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ralink_clk_add("10000c00.uartlite", periph_rate);
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ralink_clk_add("10180000.wmac", xtal_rate);
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+
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+ if (IS_ENABLED(CONFIG_USB)) {
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+ /*
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+ * When the CPU goes into sleep mode, the BUS clock will be too low for
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+ * USB to function properly
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+ */
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+ u32 val = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
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+
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+ val &= ~(CLKCFG_FDIV_MASK | CLKCFG_FFRAC_MASK);
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+ val |= CLKCFG_FDIV_USB_VAL | CLKCFG_FFRAC_USB_VAL;
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+
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+ rt_sysc_w32(val, SYSC_REG_CPU_SYS_CLKCFG);
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+ }
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}
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void __init ralink_of_remap(void)
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