2022-03-27 10:54:03 +00:00
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From: qizhong cheng <qizhong.cheng@mediatek.com>
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Date: Mon, 27 Dec 2021 21:31:10 +0800
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Subject: [PATCH] PCI: mediatek: Assert PERST# for 100ms for power and clock to
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stabilize
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Described in PCIe CEM specification sections 2.2 (PERST# Signal) and
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2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should
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be delayed 100ms (TPVPERL) for the power and clock to become stable.
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Link: https://lore.kernel.org/r/20211227133110.14500-1-qizhong.cheng@mediatek.com
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Signed-off-by: qizhong cheng <qizhong.cheng@mediatek.com>
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Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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Acked-by: Pali Rohár <pali@kernel.org>
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---
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--- a/drivers/pci/controller/pcie-mediatek.c
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+++ b/drivers/pci/controller/pcie-mediatek.c
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2024-01-26 21:55:30 +00:00
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@@ -708,6 +708,13 @@ static int mtk_pcie_startup_port_v2(stru
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2022-03-27 10:54:03 +00:00
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*/
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writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);
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+ /*
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+ * Described in PCIe CEM specification sections 2.2 (PERST# Signal) and
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+ * 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should
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+ * be delayed 100ms (TPVPERL) for the power and clock to become stable.
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+ */
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+ msleep(100);
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+
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/* De-assert PHY, PE, PIPE, MAC and configuration reset */
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val = readl(port->base + PCIE_RST_CTRL);
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val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |
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