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53 lines
2.0 KiB
Diff
53 lines
2.0 KiB
Diff
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From 49502408007b77ff290ce62e6218cefaeedcb31a Mon Sep 17 00:00:00 2001
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From: Vasily Khoruzhick <anarsoul@gmail.com>
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Date: Thu, 9 Mar 2023 17:03:49 -0800
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Subject: [PATCH] mmc: sdhci-of-dwcmshc: properly determine max clock on
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Rockchip
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Currently .get_max_clock returns the current clock rate for cclk_emmc
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on rk35xx, thus max clock gets set to whatever bootloader set it to.
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In case of u-boot, it is intentionally reset to 50 MHz if it boots
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from eMMC, see mmc_deinit() in u-boot sources. As a result, HS200 and
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HS400 modes are never selected by Linux, because dwcmshc_rk35xx_postinit
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clears appropriate caps if host->mmc->f_max is < 52MHz
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cclk_emmc is not a fixed clock on rk35xx, so using
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sdhci_pltfm_clk_get_max_clock is not appropriate here.
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Implement rk35xx_get_max_clock that returns actual max clock for cclk_emmc.
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Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
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Acked-by: Adrian Hunter <adrian.hunter@intel.com>
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Link: https://lore.kernel.org/r/20230310010349.509132-1-anarsoul@gmail.com
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Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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---
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drivers/mmc/host/sdhci-of-dwcmshc.c | 9 ++++++++-
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1 file changed, 8 insertions(+), 1 deletion(-)
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--- a/drivers/mmc/host/sdhci-of-dwcmshc.c
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+++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
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@@ -126,6 +126,13 @@ static unsigned int dwcmshc_get_max_cloc
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return pltfm_host->clock;
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}
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+static unsigned int rk35xx_get_max_clock(struct sdhci_host *host)
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+{
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+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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+
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+ return clk_round_rate(pltfm_host->clk, ULONG_MAX);
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+}
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+
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static void dwcmshc_check_auto_cmd23(struct mmc_host *mmc,
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struct mmc_request *mrq)
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{
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@@ -343,7 +350,7 @@ static const struct sdhci_ops sdhci_dwcm
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.set_clock = dwcmshc_rk3568_set_clock,
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.set_bus_width = sdhci_set_bus_width,
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.set_uhs_signaling = dwcmshc_set_uhs_signaling,
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- .get_max_clock = sdhci_pltfm_clk_get_max_clock,
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+ .get_max_clock = rk35xx_get_max_clock,
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.reset = rk35xx_sdhci_reset,
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.adma_write_desc = dwcmshc_adma_write_desc,
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};
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