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104 lines
3.5 KiB
Diff
104 lines
3.5 KiB
Diff
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From 6e933a804c7db8be64f367f33e63cd7dcc302ebb Mon Sep 17 00:00:00 2001
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From: Daniel Golle <daniel@makrotopia.org>
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Date: Tue, 14 Mar 2023 00:34:45 +0000
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Subject: [PATCH 2/2] net: ethernet: mtk_eth_soc: only write values if needed
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Only restart auto-negotiation and write link timer if actually
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necessary. This prevents losing the link in case of minor
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changes.
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Fixes: 7e538372694b ("net: ethernet: mediatek: Re-add support SGMII")
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Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
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Tested-by: Bjørn Mork <bjorn@mork.no>
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Signed-off-by: Daniel Golle <daniel@makrotopia.org>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/ethernet/mediatek/mtk_sgmii.c | 24 +++++++++++------------
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1 file changed, 12 insertions(+), 12 deletions(-)
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--- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
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+++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c
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@@ -38,20 +38,16 @@ static int mtk_pcs_config(struct phylink
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const unsigned long *advertising,
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bool permit_pause_to_mac)
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{
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+ bool mode_changed = false, changed, use_an;
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struct mtk_pcs *mpcs = pcs_to_mtk_pcs(pcs);
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unsigned int rgc3, sgm_mode, bmcr;
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int advertise, link_timer;
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- bool changed, use_an;
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advertise = phylink_mii_c22_pcs_encode_advertisement(interface,
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advertising);
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if (advertise < 0)
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return advertise;
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- link_timer = phylink_get_link_timer_ns(interface);
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- if (link_timer < 0)
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- return link_timer;
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-
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/* Clearing IF_MODE_BIT0 switches the PCS to BASE-X mode, and
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* we assume that fixes it's speed at bitrate = line rate (in
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* other words, 1000Mbps or 2500Mbps).
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@@ -77,13 +73,16 @@ static int mtk_pcs_config(struct phylink
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}
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if (use_an) {
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- /* FIXME: Do we need to set AN_RESTART here? */
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- bmcr = SGMII_AN_RESTART | SGMII_AN_ENABLE;
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+ bmcr = SGMII_AN_ENABLE;
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} else {
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bmcr = 0;
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}
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if (mpcs->interface != interface) {
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+ link_timer = phylink_get_link_timer_ns(interface);
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+ if (link_timer < 0)
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+ return link_timer;
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+
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/* PHYA power down */
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regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL,
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SGMII_PHYA_PWD, SGMII_PHYA_PWD);
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@@ -101,16 +100,17 @@ static int mtk_pcs_config(struct phylink
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regmap_update_bits(mpcs->regmap, mpcs->ana_rgc3,
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RG_PHY_SPEED_3_125G, rgc3);
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+ /* Setup the link timer */
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+ regmap_write(mpcs->regmap, SGMSYS_PCS_LINK_TIMER, link_timer / 2 / 8);
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+
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mpcs->interface = interface;
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+ mode_changed = true;
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}
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/* Update the advertisement, noting whether it has changed */
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regmap_update_bits_check(mpcs->regmap, SGMSYS_PCS_ADVERTISE,
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SGMII_ADVERTISE, advertise, &changed);
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- /* Setup the link timer and QPHY power up inside SGMIISYS */
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- regmap_write(mpcs->regmap, SGMSYS_PCS_LINK_TIMER, link_timer / 2 / 8);
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-
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/* Update the sgmsys mode register */
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regmap_update_bits(mpcs->regmap, SGMSYS_SGMII_MODE,
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SGMII_REMOTE_FAULT_DIS | SGMII_SPEED_DUPLEX_AN |
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@@ -118,7 +118,7 @@ static int mtk_pcs_config(struct phylink
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/* Update the BMCR */
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regmap_update_bits(mpcs->regmap, SGMSYS_PCS_CONTROL_1,
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- SGMII_AN_RESTART | SGMII_AN_ENABLE, bmcr);
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+ SGMII_AN_ENABLE, bmcr);
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/* Release PHYA power down state
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* Only removing bit SGMII_PHYA_PWD isn't enough.
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@@ -132,7 +132,7 @@ static int mtk_pcs_config(struct phylink
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usleep_range(50, 100);
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regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, 0);
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- return changed;
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+ return changed || mode_changed;
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}
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static void mtk_pcs_restart_an(struct phylink_pcs *pcs)
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