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openwrt/target/linux/imx6/patches-3.10/110-gateworks-ventana.patch

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imx6: update Ventana dts Update the Ventana device-tree to match upstream: - Add IMX6Q/IMX6DL variants for GW54xx/GW53xx/GW52xx/GW51xx - align pinctrl with upstream - consolidate multiple patches into one Signed-off-by: Tim Harvey <tharvey@gateworks.com> SVN-Revision: 39644
2014-02-20 17:26:10 +00:00
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -117,6 +117,15 @@ dtb-$(CONFIG_ARCH_MXC) += \
imx6dl-sabresd.dtb \
imx6dl-wandboard.dtb \
imx6q-arm2.dtb \
+ imx6q-gw51xx.dtb \
+ imx6q-gw52xx.dtb \
+ imx6q-gw53xx.dtb \
+ imx6q-gw54xx.dtb \
+ imx6q-gw5400-a.dtb \
+ imx6dl-gw51xx.dtb \
+ imx6dl-gw52xx.dtb \
+ imx6dl-gw53xx.dtb \
+ imx6dl-gw54xx.dtb \
imx6q-sabreauto.dtb \
imx6q-sabrelite.dtb \
imx6q-sabresd.dtb \
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -212,6 +212,30 @@
MX6Q_PAD_SD4_DAT0__NAND_DQS 0x00b1
>;
};
+
+ /* No strobe */
+ pinctrl_gpmi_nand_2: gpmi-nand-2 {
+ fsl,pins = <
+ MX6Q_PAD_NANDF_CLE__NAND_CLE 0xb0b1
+ MX6Q_PAD_NANDF_ALE__NAND_ALE 0xb0b1
+ MX6Q_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
+ MX6Q_PAD_NANDF_RB0__NAND_READY_B 0xb000
+ MX6Q_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
+ MX6Q_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
+ MX6Q_PAD_NANDF_CS2__NAND_CE2_B 0xb0b1
+ MX6Q_PAD_NANDF_CS3__NAND_CE3_B 0xb0b1
+ MX6Q_PAD_SD4_CMD__NAND_RE_B 0xb0b1
+ MX6Q_PAD_SD4_CLK__NAND_WE_B 0xb0b1
+ MX6Q_PAD_NANDF_D0__NAND_DATA00 0xb0b1
+ MX6Q_PAD_NANDF_D1__NAND_DATA01 0xb0b1
+ MX6Q_PAD_NANDF_D2__NAND_DATA02 0xb0b1
+ MX6Q_PAD_NANDF_D3__NAND_DATA03 0xb0b1
+ MX6Q_PAD_NANDF_D4__NAND_DATA04 0xb0b1
+ MX6Q_PAD_NANDF_D5__NAND_DATA05 0xb0b1
+ MX6Q_PAD_NANDF_D6__NAND_DATA06 0xb0b1
+ MX6Q_PAD_NANDF_D7__NAND_DATA07 0xb0b1
+ >;
+ };
};
i2c1 {
@@ -230,6 +254,12 @@
MX6Q_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
>;
};
+ pinctrl_i2c2_2: i2c2grp-2 {
+ fsl,pins = <
+ MX6Q_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
+ MX6Q_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+ >;
+ };
};
i2c3 {
@@ -239,6 +269,12 @@
MX6Q_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
>;
};
+ pinctrl_i2c3_2: i2c3grp-2 {
+ fsl,pins = <
+ MX6Q_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
+ MX6Q_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
+ >;
+ };
};
uart1 {
@@ -248,6 +284,12 @@
MX6Q_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
>;
};
+ pinctrl_uart1_2: uart1grp-2 {
+ fsl,pins = <
+ MX6Q_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
+ MX6Q_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
+ >;
+ };
};
uart2 {
@@ -257,6 +299,21 @@
MX6Q_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
>;
};
+ pinctrl_uart2_3: uart2grp-3 {
+ fsl,pins = <
+ MX6Q_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
+ MX6Q_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
+ >;
+ };
+ };
+
+ uart3 {
+ pinctrl_uart3_3: uart3grp-3 {
+ fsl,pins = <
+ MX6Q_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
+ MX6Q_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
+ >;
+ };
};
uart4 {
@@ -267,6 +324,15 @@
>;
};
};
+
+ uart5 {
+ pinctrl_uart5_1: uart5grp-1 {
+ fsl,pins = <
+ MX6Q_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
+ MX6Q_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
+ >;
+ };
+ };
usbotg {
pinctrl_usbotg_1: usbotggrp-1 {
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -37,6 +37,18 @@
compatible = "fsl,imx6dl-iomuxc";
reg = <0x020e0000 0x4000>;
+ /* shared pinctrl settings */
+ audmux {
+ pinctrl_audmux_1: audmux-1 {
+ fsl,pins = <
+ MX6DL_PAD_SD2_DAT0__AUD4_RXD 0x80000000
+ MX6DL_PAD_SD2_DAT1__AUD4_TXFS 0x80000000
+ MX6DL_PAD_SD2_DAT2__AUD4_TXD 0x80000000
+ MX6DL_PAD_SD2_DAT3__AUD4_TXC 0x80000000
+ >;
+ };
+ };
+
enet {
pinctrl_enet_1: enetgrp-1 {
fsl,pins = <
@@ -105,6 +117,59 @@
};
};
+ gpmi-nand {
+ /* No strobe */
+ pinctrl_gpmi_nand_2: gpmi-nand-2 {
+ fsl,pins = <
+ MX6DL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
+ MX6DL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
+ MX6DL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
+ MX6DL_PAD_NANDF_RB0__NAND_READY_B 0xb000
+ MX6DL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
+ MX6DL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
+ MX6DL_PAD_NANDF_CS2__NAND_CE2_B 0xb0b1
+ MX6DL_PAD_NANDF_CS3__NAND_CE3_B 0xb0b1
+ MX6DL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
+ MX6DL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
+ MX6DL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
+ MX6DL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
+ MX6DL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
+ MX6DL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
+ MX6DL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
+ MX6DL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
+ MX6DL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
+ MX6DL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
+ >;
+ };
+ };
+
+ i2c1 {
+ pinctrl_i2c1_1: i2c1grp-1 {
+ fsl,pins = <
+ MX6DL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
+ MX6DL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ >;
+ };
+ };
+
+ i2c2 {
+ pinctrl_i2c2_2: i2c2grp-2 {
+ fsl,pins = <
+ MX6DL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
+ MX6DL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+ >;
+ };
+ };
+
+ i2c3 {
+ pinctrl_i2c3_2: i2c3grp-2 {
+ fsl,pins = <
+ MX6DL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
+ MX6DL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
+ >;
+ };
+ };
+
uart1 {
pinctrl_uart1_1: uart1grp-1 {
fsl,pins = <
@@ -112,6 +177,30 @@
MX6DL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
>;
};
+ pinctrl_uart1_2: uart1grp-2 {
+ fsl,pins = <
+ MX6DL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
+ MX6DL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
+ >;
+ };
+ };
+
+ uart2 {
+ pinctrl_uart2_3: uart2grp-3 {
+ fsl,pins = <
+ MX6DL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
+ MX6DL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
+ >;
+ };
+ };
+
+ uart3 {
+ pinctrl_uart3_3: uart3grp-3 {
+ fsl,pins = <
+ MX6DL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
+ MX6DL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
+ >;
+ };
};
uart4 {
@@ -123,7 +212,22 @@
};
};
+ uart5 {
+ pinctrl_uart5_1: uart5grp-1 {
+ fsl,pins = <
+ MX6DL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
+ MX6DL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
+ >;
+ };
+ };
+
usbotg {
+ pinctrl_usbotg_1: usbotggrp-1 {
+ fsl,pins = <
+ MX6DL_PAD_GPIO_1__USB_OTG_ID 0x17059
+ >;
+ };
+
pinctrl_usbotg_2: usbotggrp-2 {
fsl,pins = <
MX6DL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
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