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98 lines
3.0 KiB
Diff
98 lines
3.0 KiB
Diff
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From 233c77d4f1d12e4337fba1146d5197f4c0f9107d Mon Sep 17 00:00:00 2001
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From: Matthew McClintock <mmcclint@codeaurora.org>
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Date: Wed, 25 Jul 2018 10:37:45 +0200
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Subject: [PATCH] ARM: dts: qcom: ipq4019: use v2 of the kpss bringup mechanism
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v1 was the incorrect choice here and sometimes the board
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would not come up properly.
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Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
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Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
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Signed-off-by: John Crispin <john@phrozen.org>
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Signed-off-by: Andy Gross <andy.gross@linaro.org>
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---
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arch/arm/boot/dts/qcom-ipq4019.dtsi | 25 +++++++++++++++++--------
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1 file changed, 17 insertions(+), 8 deletions(-)
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--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
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@@ -52,7 +52,8 @@
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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- enable-method = "qcom,kpss-acc-v1";
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+ enable-method = "qcom,kpss-acc-v2";
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+ next-level-cache = <&L2>;
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qcom,acc = <&acc0>;
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qcom,saw = <&saw0>;
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reg = <0x0>;
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@@ -71,7 +72,8 @@
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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- enable-method = "qcom,kpss-acc-v1";
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+ enable-method = "qcom,kpss-acc-v2";
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+ next-level-cache = <&L2>;
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qcom,acc = <&acc1>;
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qcom,saw = <&saw1>;
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reg = <0x1>;
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@@ -90,7 +92,8 @@
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cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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- enable-method = "qcom,kpss-acc-v1";
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+ enable-method = "qcom,kpss-acc-v2";
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+ next-level-cache = <&L2>;
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qcom,acc = <&acc2>;
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qcom,saw = <&saw2>;
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reg = <0x2>;
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@@ -109,7 +112,8 @@
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cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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- enable-method = "qcom,kpss-acc-v1";
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+ enable-method = "qcom,kpss-acc-v2";
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+ next-level-cache = <&L2>;
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qcom,acc = <&acc3>;
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qcom,saw = <&saw3>;
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reg = <0x3>;
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@@ -124,6 +128,11 @@
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>;
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clock-latency = <256000>;
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};
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+
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+ L2: l2-cache {
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+ compatible = "cache";
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+ cache-level = <2>;
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+ };
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};
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pmu {
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@@ -292,22 +301,22 @@
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};
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acc0: clock-controller@b088000 {
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- compatible = "qcom,kpss-acc-v1";
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+ compatible = "qcom,kpss-acc-v2";
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reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
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};
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acc1: clock-controller@b098000 {
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- compatible = "qcom,kpss-acc-v1";
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+ compatible = "qcom,kpss-acc-v2";
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reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
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};
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acc2: clock-controller@b0a8000 {
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- compatible = "qcom,kpss-acc-v1";
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+ compatible = "qcom,kpss-acc-v2";
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reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
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};
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acc3: clock-controller@b0b8000 {
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- compatible = "qcom,kpss-acc-v1";
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+ compatible = "qcom,kpss-acc-v2";
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reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
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};
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