2017-07-18 05:02:51 +00:00
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#include "mt7621.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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/ {
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compatible = "phicomm,k2p", "mediatek,mt7621-soc";
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model = "Phicomm K2P";
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2018-07-16 08:27:22 +00:00
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aliases {
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2018-08-28 04:54:27 +00:00
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led-boot = &led_blue;
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led-failsafe = &led_blue;
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led-running = &led_blue;
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led-upgrade = &led_blue;
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2018-07-16 08:27:22 +00:00
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};
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2018-12-30 11:42:53 +00:00
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leds {
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2017-07-18 05:02:51 +00:00
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compatible = "gpio-leds";
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stat_r {
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2020-09-27 17:40:51 +00:00
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label = "red:status";
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2020-03-03 21:22:24 +00:00
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gpios = <&gpio 13 GPIO_ACTIVE_HIGH>;
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2017-07-18 05:02:51 +00:00
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};
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stat_y {
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2020-09-27 17:40:51 +00:00
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label = "yellow:status";
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2020-03-03 21:22:24 +00:00
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gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
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2017-07-18 05:02:51 +00:00
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};
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2018-07-16 08:27:22 +00:00
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led_blue: stat_b {
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2020-09-27 17:40:51 +00:00
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label = "blue:status";
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2020-03-03 21:22:24 +00:00
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gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
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2017-07-18 05:02:51 +00:00
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};
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};
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2018-12-30 11:17:25 +00:00
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keys {
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2019-09-20 12:03:02 +00:00
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compatible = "gpio-keys";
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2017-07-18 05:02:51 +00:00
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reset {
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label = "reset";
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2020-03-03 21:22:24 +00:00
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gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
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2017-07-18 05:02:51 +00:00
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linux,code = <KEY_RESTART>;
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};
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};
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};
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&spi0 {
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status = "okay";
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2020-05-07 14:15:27 +00:00
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flash@0 {
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2017-07-18 05:02:51 +00:00
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compatible = "jedec,spi-nor";
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reg = <0>;
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2022-06-11 17:34:13 +00:00
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spi-max-frequency = <50000000>;
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2017-07-18 05:02:51 +00:00
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2018-08-01 20:32:34 +00:00
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "u-boot";
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reg = <0x0 0x30000>;
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read-only;
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};
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partition@30000 {
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label = "u-boot-env";
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reg = <0x30000 0x10000>;
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read-only;
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};
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factory: partition@40000 {
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label = "factory";
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reg = <0x40000 0x10000>;
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read-only;
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};
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partition@50000 {
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label = "permanent_config";
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reg = <0x50000 0x50000>;
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read-only;
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};
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partition@a0000 {
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2018-11-28 03:28:35 +00:00
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compatible = "denx,uimage";
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2018-08-01 20:32:34 +00:00
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label = "firmware";
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reg = <0xa0000 0xf60000>;
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};
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2017-07-18 05:02:51 +00:00
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};
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};
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};
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&pcie {
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status = "okay";
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2018-07-21 14:19:46 +00:00
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};
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2017-07-18 05:02:51 +00:00
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2018-07-21 14:19:46 +00:00
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&pcie0 {
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2022-01-09 04:16:06 +00:00
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wifi@0,0 {
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compatible = "mediatek,mt76";
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2018-07-21 14:19:46 +00:00
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reg = <0x0000 0 0 0 0>;
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mediatek,mtd-eeprom = <&factory 0x0>;
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2022-01-09 04:16:06 +00:00
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/* 5 GHz (phy1) does not take the address from calibration data,
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but setting it manually here works */
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nvmem-cells = <&macaddr_factory_4>;
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nvmem-cell-names = "mac-address";
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2017-07-18 05:02:51 +00:00
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};
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};
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2020-03-18 15:38:58 +00:00
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&gmac0 {
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2021-04-02 21:50:02 +00:00
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nvmem-cells = <&macaddr_factory_e000>;
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nvmem-cell-names = "mac-address";
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2017-07-18 05:02:51 +00:00
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};
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2022-07-05 22:20:32 +00:00
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&gmac1 {
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status = "okay";
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label = "wan";
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phy-handle = <ðphy4>;
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nvmem-cells = <&macaddr_factory_e006>;
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nvmem-cell-names = "mac-address";
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};
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&mdio {
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ethphy4: ethernet-phy@4 {
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reg = <4>;
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};
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};
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2020-03-18 15:38:58 +00:00
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&switch0 {
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ports {
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port@0 {
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status = "okay";
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label = "lan1";
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};
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port@1 {
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status = "okay";
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label = "lan2";
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};
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port@2 {
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status = "okay";
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label = "lan3";
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};
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port@3 {
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status = "okay";
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label = "lan4";
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};
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};
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};
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2019-12-22 20:26:01 +00:00
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&state_default {
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gpio {
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2020-03-13 13:27:03 +00:00
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groups = "i2c", "jtag";
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function = "gpio";
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2017-07-18 05:02:51 +00:00
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};
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};
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2021-04-02 21:50:02 +00:00
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&factory {
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compatible = "nvmem-cells";
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#address-cells = <1>;
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#size-cells = <1>;
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2022-01-09 04:16:06 +00:00
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macaddr_factory_4: macaddr@4 {
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reg = <0x4 0x6>;
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};
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2021-04-02 21:50:02 +00:00
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macaddr_factory_e000: macaddr@e000 {
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reg = <0xe000 0x6>;
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};
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macaddr_factory_e006: macaddr@e006 {
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reg = <0xe006 0x6>;
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};
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};
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