2021-05-05 00:32:27 +00:00
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* prom.c
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* Early intialization code for the Realtek RTL838X SoC
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*
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* based on the original BSP by
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* Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com)
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* Copyright (C) 2020 B. Koblitz
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*
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/string.h>
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#include <linux/of_fdt.h>
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#include <linux/libfdt.h>
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#include <asm/bootinfo.h>
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#include <asm/addrspace.h>
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#include <asm/page.h>
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#include <asm/cpu.h>
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2021-12-30 21:53:55 +00:00
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#include <asm/smp-ops.h>
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#include <asm/mips-cps.h>
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2021-05-05 00:32:27 +00:00
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#include <mach-rtl83xx.h>
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extern char arcs_cmdline[];
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extern const char __appended_dtb;
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struct rtl83xx_soc_info soc_info;
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const void *fdt;
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const char *get_system_type(void)
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{
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return soc_info.name;
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}
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void __init prom_free_prom_memory(void)
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{
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}
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void __init device_tree_init(void)
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{
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if (!fdt_check_header(&__appended_dtb)) {
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fdt = &__appended_dtb;
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pr_info("Using appended Device Tree.\n");
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}
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initial_boot_params = (void *)fdt;
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unflatten_and_copy_device_tree();
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}
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static void __init prom_init_cmdline(void)
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{
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int argc = fw_arg0;
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char **argv = (char **) KSEG1ADDR(fw_arg1);
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int i;
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arcs_cmdline[0] = '\0';
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for (i = 0; i < argc; i++) {
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char *p = (char *) KSEG1ADDR(argv[i]);
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if (CPHYSADDR(p) && *p) {
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strlcat(arcs_cmdline, p, sizeof(arcs_cmdline));
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strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline));
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}
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}
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pr_info("Kernel command line: %s\n", arcs_cmdline);
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}
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void __init identify_rtl9302(void)
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{
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switch (sw_r32(RTL93XX_MODEL_NAME_INFO) & 0xfffffff0) {
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case 0x93020810:
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soc_info.name = "RTL9302A 12x2.5G";
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break;
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case 0x93021010:
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soc_info.name = "RTL9302B 8x2.5G";
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break;
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case 0x93021810:
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soc_info.name = "RTL9302C 16x2.5G";
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break;
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case 0x93022010:
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soc_info.name = "RTL9302D 24x2.5G";
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break;
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case 0x93020800:
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soc_info.name = "RTL9302A";
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break;
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case 0x93021000:
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soc_info.name = "RTL9302B";
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break;
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case 0x93021800:
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soc_info.name = "RTL9302C";
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break;
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case 0x93022000:
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soc_info.name = "RTL9302D";
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break;
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case 0x93023001:
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soc_info.name = "RTL9302F";
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break;
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default:
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soc_info.name = "RTL9302";
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}
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}
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void __init prom_init(void)
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{
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uint32_t model;
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/* uart0 */
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setup_8250_early_printk_port(0xb8002000, 2, 0);
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model = sw_r32(RTL838X_MODEL_NAME_INFO);
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pr_info("RTL838X model is %x\n", model);
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model = model >> 16 & 0xFFFF;
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if ((model != 0x8328) && (model != 0x8330) && (model != 0x8332)
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&& (model != 0x8380) && (model != 0x8382)) {
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model = sw_r32(RTL839X_MODEL_NAME_INFO);
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pr_info("RTL839X model is %x\n", model);
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model = model >> 16 & 0xFFFF;
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}
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if ((model & 0x8390) != 0x8380 && (model & 0x8390) != 0x8390) {
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model = sw_r32(RTL93XX_MODEL_NAME_INFO);
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pr_info("RTL93XX model is %x\n", model);
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model = model >> 16 & 0xFFFF;
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}
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soc_info.id = model;
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switch (model) {
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case 0x8328:
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soc_info.name = "RTL8328";
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soc_info.family = RTL8328_FAMILY_ID;
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break;
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case 0x8332:
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soc_info.name = "RTL8332";
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soc_info.family = RTL8380_FAMILY_ID;
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break;
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case 0x8380:
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soc_info.name = "RTL8380";
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soc_info.family = RTL8380_FAMILY_ID;
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break;
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case 0x8382:
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soc_info.name = "RTL8382";
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soc_info.family = RTL8380_FAMILY_ID;
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break;
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case 0x8390:
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soc_info.name = "RTL8390";
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soc_info.family = RTL8390_FAMILY_ID;
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break;
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case 0x8391:
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soc_info.name = "RTL8391";
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soc_info.family = RTL8390_FAMILY_ID;
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break;
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case 0x8392:
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soc_info.name = "RTL8392";
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soc_info.family = RTL8390_FAMILY_ID;
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break;
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case 0x8393:
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soc_info.name = "RTL8393";
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soc_info.family = RTL8390_FAMILY_ID;
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break;
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case 0x9301:
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soc_info.name = "RTL9301";
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soc_info.family = RTL9300_FAMILY_ID;
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break;
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case 0x9302:
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identify_rtl9302();
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soc_info.family = RTL9300_FAMILY_ID;
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break;
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2022-01-16 07:34:18 +00:00
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case 0x9303:
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soc_info.name = "RTL9303";
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soc_info.family = RTL9300_FAMILY_ID;
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break;
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2021-05-05 00:32:27 +00:00
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case 0x9313:
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soc_info.name = "RTL9313";
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soc_info.family = RTL9310_FAMILY_ID;
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break;
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default:
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soc_info.name = "DEFAULT";
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soc_info.family = 0;
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}
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pr_info("SoC Type: %s\n", get_system_type());
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2021-12-30 21:53:55 +00:00
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/* Early detection of CMP support */
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if(soc_info.family == RTL9310_FAMILY_ID) {
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mips_cm_probe();
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mips_cpc_probe();
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}
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2021-05-05 00:32:27 +00:00
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prom_init_cmdline();
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2021-12-30 21:53:55 +00:00
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#ifdef CONFIG_MIPS_CPS
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if (!register_cps_smp_ops()) {
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return;
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}
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#endif
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#ifdef CONFIG_MIPS_MT_SMP
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if (!register_vsmp_smp_ops()) {
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return;
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}
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#endif
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register_up_smp_ops();
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2021-05-05 00:32:27 +00:00
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}
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