2020-10-24 19:15:20 +00:00
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From patchwork Thu May 28 06:16:46 2020
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From: <chuanjia.liu@mediatek.com>
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To: <robh+dt@kernel.org>, <ryder.lee@mediatek.com>, <matthias.bgg@gmail.com>
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Subject: [PATCH v2 2/4] PCI: mediatek: Use regmap to get shared pcie-cfg base
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Date: Thu, 28 May 2020 14:16:46 +0800
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Message-ID: <20200528061648.32078-3-chuanjia.liu@mediatek.com>
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Cc: devicetree@vger.kernel.org, lorenzo.pieralisi@arm.com,
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srv_heupstream@mediatek.com, "chuanjia.liu" <Chuanjia.Liu@mediatek.com>,
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linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
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linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org
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From: "chuanjia.liu" <Chuanjia.Liu@mediatek.com>
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Use regmap to get shared pcie-cfg base and change
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the method to get pcie irq.
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Signed-off-by: chuanjia.liu <Chuanjia.Liu@mediatek.com>
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---
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drivers/pci/controller/pcie-mediatek.c | 25 ++++++++++++++++++-------
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1 file changed, 18 insertions(+), 7 deletions(-)
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--- a/drivers/pci/controller/pcie-mediatek.c
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+++ b/drivers/pci/controller/pcie-mediatek.c
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@@ -14,6 +14,7 @@
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/kernel.h>
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+#include <linux/mfd/syscon.h>
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#include <linux/msi.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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@@ -23,6 +24,7 @@
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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+#include <linux/regmap.h>
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#include <linux/reset.h>
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#include "../pci.h"
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2021-07-28 21:18:01 +00:00
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@@ -207,6 +209,7 @@ struct mtk_pcie_port {
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2020-10-24 19:15:20 +00:00
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* struct mtk_pcie - PCIe host information
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* @dev: pointer to PCIe device
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* @base: IO mapped register base
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+ * @cfg: IO mapped register map for PCIe config
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* @free_ck: free-run reference clock
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* @mem: non-prefetchable memory resource
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* @ports: pointer to PCIe port information
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2021-07-28 21:18:01 +00:00
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@@ -215,6 +218,7 @@ struct mtk_pcie_port {
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2020-10-24 19:15:20 +00:00
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struct mtk_pcie {
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struct device *dev;
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void __iomem *base;
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+ struct regmap *cfg;
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struct clk *free_ck;
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struct list_head ports;
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2021-07-28 21:18:01 +00:00
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@@ -650,7 +654,7 @@ static int mtk_pcie_setup_irq(struct mtk
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2020-10-24 19:15:20 +00:00
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return err;
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}
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- port->irq = platform_get_irq(pdev, port->slot);
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+ port->irq = platform_get_irq_byname(pdev, "pcie_irq");
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if (port->irq < 0)
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return port->irq;
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2021-07-28 21:18:01 +00:00
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@@ -676,12 +680,11 @@ static int mtk_pcie_startup_port_v2(stru
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2020-10-24 19:15:20 +00:00
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if (!mem)
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return -EINVAL;
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- /* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */
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- if (pcie->base) {
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- val = readl(pcie->base + PCIE_SYS_CFG_V2);
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- val |= PCIE_CSR_LTSSM_EN(port->slot) |
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- PCIE_CSR_ASPM_L1_EN(port->slot);
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- writel(val, pcie->base + PCIE_SYS_CFG_V2);
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+ /* MT7622/MT7629 platforms need to enable LTSSM and ASPM. */
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+ if (pcie->cfg) {
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+ val = PCIE_CSR_LTSSM_EN(port->slot) |
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+ PCIE_CSR_ASPM_L1_EN(port->slot);
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+ regmap_update_bits(pcie->cfg, PCIE_SYS_CFG_V2, val, val);
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}
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/* Assert all reset signals */
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2021-07-28 21:18:01 +00:00
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@@ -985,6 +988,7 @@ static int mtk_pcie_subsys_powerup(struc
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2020-10-24 19:15:20 +00:00
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struct device *dev = pcie->dev;
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struct platform_device *pdev = to_platform_device(dev);
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struct resource *regs;
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+ struct device_node *cfg_node;
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int err;
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/* get shared registers, which are optional */
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2021-07-28 21:18:01 +00:00
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@@ -997,6 +1001,13 @@ static int mtk_pcie_subsys_powerup(struc
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2020-10-24 19:15:20 +00:00
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}
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}
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+ cfg_node = of_parse_phandle(dev->of_node, "mediatek,pcie-cfg", 0);
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+ if (cfg_node) {
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+ pcie->cfg = syscon_node_to_regmap(cfg_node);
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+ if (IS_ERR(pcie->cfg))
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+ return PTR_ERR(pcie->cfg);
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+ }
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+
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pcie->free_ck = devm_clk_get(dev, "free_ck");
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if (IS_ERR(pcie->free_ck)) {
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if (PTR_ERR(pcie->free_ck) == -EPROBE_DEFER)
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