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78 lines
2.9 KiB
Diff
78 lines
2.9 KiB
Diff
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From 132f5d41c2da9f7292f1495fd30cf04a3de8d196 Mon Sep 17 00:00:00 2001
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From: Dom Cobley <popcornmix@gmail.com>
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Date: Fri, 5 May 2023 11:23:50 +0100
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Subject: [PATCH] bcm2835-dma: Need to keep PROT bits set in CS on
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40bit controller
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Resetting them to zero puts DMA channel into secure mode
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which makes further accesses impossible
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Signed-off-by: Dom Cobley <popcornmix@gmail.com>
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---
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drivers/dma/bcm2835-dma.c | 20 ++++++++++++++------
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1 file changed, 14 insertions(+), 6 deletions(-)
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--- a/drivers/dma/bcm2835-dma.c
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+++ b/drivers/dma/bcm2835-dma.c
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@@ -249,6 +249,9 @@ struct bcm2835_desc {
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#define BCM2711_DMA40_DISDEBUG BIT(29)
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#define BCM2711_DMA40_ABORT BIT(30)
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#define BCM2711_DMA40_HALT BIT(31)
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+// we always want to run in supervisor mode
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+#define BCM2711_DMA40_PROT (BIT(8)|BIT(9))
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+
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#define BCM2711_DMA40_CS_FLAGS(x) (x & (BCM2711_DMA40_QOS(15) | \
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BCM2711_DMA40_PANIC_QOS(15) | \
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BCM2711_DMA40_WAIT_FOR_WRITES | \
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@@ -682,7 +685,7 @@ static void bcm2835_dma_abort(struct bcm
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dev_err(c->vc.chan.device->dev,
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"failed to halt dma\n");
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- writel(0, chan_base + BCM2711_DMA40_CS);
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+ writel(BCM2711_DMA40_PROT, chan_base + BCM2711_DMA40_CS);
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writel(0, chan_base + BCM2711_DMA40_CB);
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} else {
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/*
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@@ -742,7 +745,7 @@ static void bcm2835_dma_start_desc(struc
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if (c->is_40bit_channel) {
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writel(to_bcm2711_cbaddr(d->cb_list[0].paddr),
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c->chan_base + BCM2711_DMA40_CB);
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- writel(BCM2711_DMA40_ACTIVE | BCM2711_DMA40_CS_FLAGS(c->dreq),
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+ writel(BCM2711_DMA40_ACTIVE | BCM2711_DMA40_PROT | BCM2711_DMA40_CS_FLAGS(c->dreq),
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c->chan_base + BCM2711_DMA40_CS);
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} else {
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writel(d->cb_list[0].paddr, c->chan_base + BCM2835_DMA_ADDR);
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@@ -775,8 +778,13 @@ static irqreturn_t bcm2835_dma_callback(
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* if this IRQ handler is threaded.) If the channel is finished, it
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* will remain idle despite the ACTIVE flag being set.
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*/
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- writel(BCM2835_DMA_INT | BCM2835_DMA_ACTIVE | BCM2835_DMA_CS_FLAGS(c->dreq),
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- c->chan_base + BCM2835_DMA_CS);
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+ if (c->is_40bit_channel)
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+ writel(BCM2835_DMA_INT | BCM2711_DMA40_ACTIVE | BCM2711_DMA40_PROT |
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+ BCM2711_DMA40_CS_FLAGS(c->dreq),
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+ c->chan_base + BCM2711_DMA40_CS);
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+ else
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+ writel(BCM2835_DMA_INT | BCM2835_DMA_ACTIVE | BCM2835_DMA_CS_FLAGS(c->dreq),
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+ c->chan_base + BCM2835_DMA_CS);
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d = c->desc;
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@@ -1230,14 +1238,14 @@ void bcm2711_dma40_memcpy(dma_addr_t dst
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scb->next_cb = 0;
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writel(to_bcm2711_cbaddr(memcpy_scb_dma), memcpy_chan + BCM2711_DMA40_CB);
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- writel(BCM2711_DMA40_MEMCPY_FLAGS + BCM2711_DMA40_ACTIVE,
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+ writel(BCM2711_DMA40_MEMCPY_FLAGS | BCM2711_DMA40_ACTIVE | BCM2711_DMA40_PROT,
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memcpy_chan + BCM2711_DMA40_CS);
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/* Poll for completion */
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while (!(readl(memcpy_chan + BCM2711_DMA40_CS) & BCM2711_DMA40_END))
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cpu_relax();
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- writel(BCM2711_DMA40_END, memcpy_chan + BCM2711_DMA40_CS);
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+ writel(BCM2711_DMA40_END | BCM2711_DMA40_PROT, memcpy_chan + BCM2711_DMA40_CS);
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spin_unlock_irqrestore(&memcpy_lock, flags);
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}
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