2019-09-04 17:01:23 +00:00
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From deb60e65648c23cb373324ac2272c6468d21fe96 Mon Sep 17 00:00:00 2001
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2019-07-09 18:32:28 +00:00
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From: Annaliese McDermond <nh6z@nh6z.net>
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Date: Mon, 18 Mar 2019 20:37:44 -0700
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2019-09-04 17:01:23 +00:00
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Subject: [PATCH 397/782] ASoC: tlv320aic32x4: Break out clock setting into
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2019-07-09 18:32:28 +00:00
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separate function
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commit bf31cbfbe25001036e1e096b1c260bf871766ea5 upstream.
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Break the clock setting logic out from the main hw_params. It's
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rather large and unweildy and makes for a large function. This
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also better enables some of the following changes to the clock
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tree access in the driver.
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Signed-off-by: Annaliese McDermond <nh6z@nh6z.net>
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Signed-off-by: Mark Brown <broonie@kernel.org>
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---
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sound/soc/codecs/tlv320aic32x4.c | 26 ++++++++++++++++++--------
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1 file changed, 18 insertions(+), 8 deletions(-)
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--- a/sound/soc/codecs/tlv320aic32x4.c
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+++ b/sound/soc/codecs/tlv320aic32x4.c
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@@ -698,17 +698,13 @@ static int aic32x4_set_dai_fmt(struct sn
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return 0;
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}
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-static int aic32x4_hw_params(struct snd_pcm_substream *substream,
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- struct snd_pcm_hw_params *params,
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- struct snd_soc_dai *dai)
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+static int aic32x4_setup_clocks(struct snd_soc_component *component,
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+ unsigned int sample_rate,
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+ unsigned int parent_rate)
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{
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- struct snd_soc_component *component = dai->component;
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- struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
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- u8 iface1_reg = 0;
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- u8 dacsetup_reg = 0;
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int i;
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- i = aic32x4_get_divs(aic32x4->sysclk, params_rate(params));
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+ i = aic32x4_get_divs(parent_rate, sample_rate);
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if (i < 0) {
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printk(KERN_ERR "aic32x4: sampling rate not supported\n");
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return i;
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@@ -765,6 +761,20 @@ static int aic32x4_hw_params(struct snd_
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snd_soc_component_update_bits(component, AIC32X4_BCLKN,
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AIC32X4_BCLK_MASK, aic32x4_divs[i].blck_N);
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+ return 0;
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+}
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+
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+static int aic32x4_hw_params(struct snd_pcm_substream *substream,
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+ struct snd_pcm_hw_params *params,
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+ struct snd_soc_dai *dai)
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+{
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+ struct snd_soc_component *component = dai->component;
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+ struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
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+ u8 iface1_reg = 0;
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+ u8 dacsetup_reg = 0;
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+
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+ aic32x4_setup_clocks(component, params_rate(params), aic32x4->sysclk);
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+
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switch (params_width(params)) {
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case 16:
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iface1_reg |= (AIC32X4_WORD_LEN_16BITS <<
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