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49 lines
1.6 KiB
Diff
49 lines
1.6 KiB
Diff
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From f0548ab9212ef35abe79f46e5f509f4fc9d78699 Mon Sep 17 00:00:00 2001
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From: Xingyu Wu <xingyu.wu@starfivetech.com>
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Date: Mon, 20 Feb 2023 14:33:33 +0800
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Subject: [PATCH 039/122] riscv: dts: starfive: jh7110: Add PLL clock node and
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modify syscrg node
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Add the PLL clock node for the Starfive JH7110 SoC and
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modify the SYSCRG node to add PLL clocks input.
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Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
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---
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arch/riscv/boot/dts/starfive/jh7110.dtsi | 14 ++++++++++++--
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1 file changed, 12 insertions(+), 2 deletions(-)
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--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
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+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
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@@ -452,12 +452,16 @@
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<&gmac1_rgmii_rxin>,
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<&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
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<&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
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- <&tdm_ext>, <&mclk_ext>;
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+ <&tdm_ext>, <&mclk_ext>,
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+ <&pllclk JH7110_CLK_PLL0_OUT>,
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+ <&pllclk JH7110_CLK_PLL1_OUT>,
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+ <&pllclk JH7110_CLK_PLL2_OUT>;
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clock-names = "osc", "gmac1_rmii_refin",
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"gmac1_rgmii_rxin",
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"i2stx_bclk_ext", "i2stx_lrck_ext",
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"i2srx_bclk_ext", "i2srx_lrck_ext",
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- "tdm_ext", "mclk_ext";
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+ "tdm_ext", "mclk_ext",
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+ "pll0_out", "pll1_out", "pll2_out";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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@@ -465,6 +469,12 @@
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sys_syscon: syscon@13030000 {
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compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd";
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reg = <0x0 0x13030000 0x0 0x1000>;
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+
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+ pllclk: clock-controller {
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+ compatible = "starfive,jh7110-pll";
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+ clocks = <&osc>;
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+ #clock-cells = <1>;
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+ };
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};
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sysgpio: pinctrl@13040000 {
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