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78 lines
2.1 KiB
Diff
78 lines
2.1 KiB
Diff
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From e2078ae0c559b6ac91db19262b56d8cf334354cb Mon Sep 17 00:00:00 2001
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From: Andre Przywara <andre.przywara@arm.com>
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Date: Mon, 12 Sep 2022 00:03:22 +0100
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Subject: [PATCH 5001/5006] dt-bindings: phy: Add special clock for Allwinner
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H616 PHY
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The USB PHY IP in the Allwinner H616 SoC requires a quirk that involves
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some resources from port 2's PHY and HCI IP. In particular the PMU clock
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for port 2 must be surely ungated before accessing the REG_HCI_PHY_CTL
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register of port 2. To allow each USB port to be controlled
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independently of port 2, we need a handle to that particular PMU clock
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in the *PHY* node, as the HCI and PHY part might be handled by separate
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drivers.
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Add that clock to the requirements of the H616 PHY binding, so that a
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PHY driver can apply the quirk in isolation, without requiring help from
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port 2's HCI driver.
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Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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---
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.../phy/allwinner,sun8i-h3-usb-phy.yaml | 26 +++++++++++++++++++
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1 file changed, 26 insertions(+)
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--- a/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml
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+++ b/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml
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@@ -36,18 +36,22 @@ properties:
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- const: pmu3
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clocks:
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+ minItems: 4
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items:
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- description: USB OTG PHY bus clock
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- description: USB Host 0 PHY bus clock
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- description: USB Host 1 PHY bus clock
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- description: USB Host 2 PHY bus clock
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+ - description: PMU clock for host port 2
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clock-names:
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+ minItems: 4
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items:
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- const: usb0_phy
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- const: usb1_phy
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- const: usb2_phy
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- const: usb3_phy
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+ - const: pmu2_clk
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resets:
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items:
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@@ -96,6 +100,28 @@ required:
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- resets
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- reset-names
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+allOf:
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+ - if:
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+ properties:
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+ compatible:
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+ contains:
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+ enum:
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+ - allwinner,sun50i-h616-usb-phy
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+ then:
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+ properties:
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+ clocks:
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+ minItems: 5
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+
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+ clock-names:
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+ minItems: 5
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+ else:
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+ properties:
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+ clocks:
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+ maxItems: 4
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+
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+ clock-names:
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+ maxItems: 4
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+
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additionalProperties: false
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examples:
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