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63 lines
2.1 KiB
Diff
63 lines
2.1 KiB
Diff
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From 9d9bf16aa8d966834ac1280f96c37d22552c33d1 Mon Sep 17 00:00:00 2001
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From: Birger Koblitz <git@birger-koblitz.de>
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Date: Wed, 8 Sep 2021 16:13:18 +0200
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Subject: phy: Add PHY hsgmii mode
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This adds RTL93xx-specific MAC configuration routines that allow also configuration
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of 10GBit links for phylink. There is support for the Realtek-specific HISGMI
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protocol.
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Submitted-by: Birger Koblitz <git@birger-koblitz.de>
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---
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drivers/net/phy/phylink.c | 2 ++
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include/linux/phy.h | 3 +++
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2 file changed, 5 insertions(+)
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--- a/drivers/net/phy/phy-core.c
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+++ b/drivers/net/phy/phy-core.c
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@@ -124,6 +124,7 @@ int phy_interface_num_ports(phy_interfac
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case PHY_INTERFACE_MODE_MOCA:
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case PHY_INTERFACE_MODE_TRGMII:
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case PHY_INTERFACE_MODE_USXGMII:
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+ case PHY_INTERFACE_MODE_HSGMII:
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case PHY_INTERFACE_MODE_SGMII:
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case PHY_INTERFACE_MODE_SMII:
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case PHY_INTERFACE_MODE_1000BASEX:
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--- a/drivers/net/phy/phylink.c
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+++ b/drivers/net/phy/phylink.c
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@@ -410,6 +410,7 @@ void phylink_get_linkmodes(unsigned long
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case PHY_INTERFACE_MODE_XGMII:
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case PHY_INTERFACE_MODE_RXAUI:
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+ case PHY_INTERFACE_MODE_HSGMII:
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case PHY_INTERFACE_MODE_XAUI:
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case PHY_INTERFACE_MODE_10GBASER:
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case PHY_INTERFACE_MODE_10GKR:
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@@ -665,6 +666,7 @@ static int phylink_parse_mode(struct phy
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fallthrough;
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case PHY_INTERFACE_MODE_USXGMII:
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case PHY_INTERFACE_MODE_10GKR:
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+ case PHY_INTERFACE_MODE_HSGMII:
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case PHY_INTERFACE_MODE_10GBASER:
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phylink_set(pl->supported, 10baseT_Half);
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phylink_set(pl->supported, 10baseT_Full);
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--- a/include/linux/phy.h
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+++ b/include/linux/phy.h
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@@ -141,6 +141,7 @@ typedef enum {
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PHY_INTERFACE_MODE_XGMII,
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PHY_INTERFACE_MODE_XLGMII,
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PHY_INTERFACE_MODE_MOCA,
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+ PHY_INTERFACE_MODE_HSGMII,
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PHY_INTERFACE_MODE_QSGMII,
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PHY_INTERFACE_MODE_TRGMII,
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PHY_INTERFACE_MODE_100BASEX,
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@@ -248,6 +249,8 @@ static inline const char *phy_modes(phy_
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return "xlgmii";
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case PHY_INTERFACE_MODE_MOCA:
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return "moca";
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+ case PHY_INTERFACE_MODE_HSGMII:
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+ return "hsgmii";
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case PHY_INTERFACE_MODE_QSGMII:
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return "qsgmii";
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case PHY_INTERFACE_MODE_TRGMII:
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