2021-05-16 12:10:05 +00:00
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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#include "mt7621.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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2024-02-07 13:48:43 +00:00
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#include <dt-bindings/leds/common.h>
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2021-05-16 12:10:05 +00:00
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/ {
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compatible = "jcg,q20", "mediatek,mt7621-soc";
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model = "JCG Q20";
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aliases {
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led-boot = &led_status_red;
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led-failsafe = &led_status_red;
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led-running = &led_status_blue;
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led-upgrade = &led_status_blue;
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label-mac-device = &gmac0;
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};
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chosen {
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bootargs = "console=ttyS0,115200";
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};
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leds {
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compatible = "gpio-leds";
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led_status_red: status_red {
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2024-02-07 13:48:43 +00:00
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function = LED_FUNCTION_STATUS;
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color = <LED_COLOR_ID_RED>;
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2021-05-16 12:10:05 +00:00
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gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
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};
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led_status_blue: status_blue {
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2024-02-07 13:48:43 +00:00
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function = LED_FUNCTION_STATUS;
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color = <LED_COLOR_ID_BLUE>;
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2021-05-16 12:10:05 +00:00
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gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
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};
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};
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keys {
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compatible = "gpio-keys";
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reset {
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label = "reset";
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gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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wps {
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label = "wps";
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gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_WPS_BUTTON>;
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};
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};
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ubi-concat {
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compatible = "mtd-concat";
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devices = <&ubiconcat0 &ubiconcat1>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "ubi";
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reg = <0x0 0x5900000>;
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};
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};
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};
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};
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&nand {
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status = "okay";
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "Bootloader";
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reg = <0x0 0x80000>;
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read-only;
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};
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partition@80000 {
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label = "Config";
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reg = <0x80000 0x80000>;
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};
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2024-02-17 14:10:10 +00:00
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partition@100000 {
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2021-05-16 12:10:05 +00:00
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label = "Factory";
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reg = <0x100000 0x80000>;
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read-only;
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2023-10-02 02:12:02 +00:00
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2023-11-07 23:55:58 +00:00
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nvmem-layout {
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compatible = "fixed-layout";
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#address-cells = <1>;
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#size-cells = <1>;
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2023-10-02 02:12:02 +00:00
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2023-11-07 23:55:58 +00:00
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eeprom_factory_0: eeprom@0 {
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reg = <0x0 0xe00>;
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};
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macaddr_factory_3fff4: macaddr@3fff4 {
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reg = <0x3fff4 0x6>;
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};
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2023-10-02 02:12:02 +00:00
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2023-11-07 23:55:58 +00:00
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macaddr_factory_3fffa: macaddr@3fffa {
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reg = <0x3fffa 0x6>;
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};
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2023-10-02 02:12:02 +00:00
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};
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2021-05-16 12:10:05 +00:00
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};
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partition@180000 {
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label = "kernel";
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reg = <0x180000 0x400000>;
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};
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ubiconcat0: partition@580000 {
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label = "ubiconcat0";
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reg = <0x580000 0x1c00000>;
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};
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partition@2180000 {
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label = "firmware_backup";
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reg = <0x2180000 0x2000000>;
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};
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partition@4180000 {
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label = "rootfs_data_back";
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reg = <0x4180000 0x80000>;
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read-only;
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};
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partition@4200000 {
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label = "nvram_config";
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reg = <0x4200000 0x80000>;
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read-only;
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};
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ubiconcat1: partition@4280000 {
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label = "ubiconcat1";
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reg = <0x4280000 0x3d00000>;
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};
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/*
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* last 512 KiB are for the bad block table
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*/
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};
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};
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&pcie {
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status = "okay";
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};
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&pcie1 {
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wifi@0,0 {
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compatible = "mediatek,mt76";
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reg = <0x0000 0 0 0 0>;
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2023-10-02 02:12:02 +00:00
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nvmem-cells = <&eeprom_factory_0>;
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nvmem-cell-names = "eeprom";
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ramips: disable unsupported background radar detection
Background radar detection is not supported on devices that
using MT7905, so disable this feature in the following devices:
asus,rt-ax53u
jcg,q20
tplink,eap615-wall-v1
xiaomi,mi-router-cr6606
xiaomi,mi-router-cr6608
xiaomi,mi-router-cr6609
yuncore,ax820
Devices with MT7915 lacking a DFS antenna also do not support
background DFS:
totolink,x5000r
cudy,x6
Signed-off-by: Shiji Yang <yangshiji66@qq.com>
2022-09-07 08:08:33 +00:00
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mediatek,disable-radar-background;
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2021-05-16 12:10:05 +00:00
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};
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};
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&gmac0 {
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2021-04-02 21:50:02 +00:00
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nvmem-cells = <&macaddr_factory_3fff4>;
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nvmem-cell-names = "mac-address";
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2021-05-16 12:10:05 +00:00
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};
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2022-07-05 22:20:32 +00:00
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&gmac1 {
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status = "okay";
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label = "wan";
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phy-handle = <ðphy0>;
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nvmem-cells = <&macaddr_factory_3fffa>;
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nvmem-cell-names = "mac-address";
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};
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ramips: mt7621-dts: describe switch PHYs and adjust PHY muxing
Currently, the MT7530 DSA subdriver configures the MT7530 switch to provide
direct access to switch PHYs, meaning, the switch PHYs listen on the MDIO
bus the switch listens on. The PHY muxing feature makes use of this.
This is problematic as the PHY may be attached before the switch is
initialised, in which case, the PHY will fail to be attached.
Since commit 91374ba537bd ("net: dsa: mt7530: support OF-based registration
of switch MDIO bus") on mainline Linux, we can describe the switch PHYs on
the MDIO bus of the switch on the device tree.
When the PHY is described this way, the switch will be initialised first,
then the switch MDIO bus will be registered. Only after these steps, the
PHY will be attached.
Describe the switch PHYs on mt7621.dtsi and remove defining the switch PHY
on the SoC's mdio bus node. When the PHY muxing is in use, the interrupts
for the muxed PHY won't work, therefore delete the "interrupts" property on
the devices where the PHY muxing feature is in use.
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
2024-04-28 19:52:51 +00:00
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ðphy0 {
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/delete-property/ interrupts;
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2022-07-05 22:20:32 +00:00
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};
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2021-05-16 12:10:05 +00:00
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&switch0 {
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ports {
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port@1 {
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status = "okay";
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label = "lan1";
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};
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port@4 {
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status = "okay";
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label = "lan2";
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};
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};
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};
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&state_default {
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gpio {
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groups = "jtag", "wdt";
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function = "gpio";
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};
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};
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