2021-03-14 18:22:18 +00:00
|
|
|
From 7e2dc41c745f6d9c571919d98abed2d783fce8fb Mon Sep 17 00:00:00 2001
|
|
|
|
From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
|
|
|
|
Date: Sun, 14 Mar 2021 22:43:32 +0100
|
|
|
|
Subject: [PATCH] net: dsa: bcm_sf2: quick fix for RGMII reg access on BCM4908
|
|
|
|
MIME-Version: 1.0
|
|
|
|
Content-Type: text/plain; charset=UTF-8
|
|
|
|
Content-Transfer-Encoding: 8bit
|
|
|
|
|
|
|
|
BCM4908 has only 1 RGMII register and it's used for port 7.
|
|
|
|
|
|
|
|
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
|
|
|
|
---
|
|
|
|
drivers/net/dsa/bcm_sf2.c | 30 +++++++++++++++++++++++-------
|
|
|
|
drivers/net/dsa/bcm_sf2_regs.h | 1 +
|
|
|
|
2 files changed, 24 insertions(+), 7 deletions(-)
|
|
|
|
|
|
|
|
--- a/drivers/net/dsa/bcm_sf2.c
|
|
|
|
+++ b/drivers/net/dsa/bcm_sf2.c
|
2021-03-17 06:40:49 +00:00
|
|
|
@@ -592,10 +592,19 @@ static void bcm_sf2_sw_mac_config(struct
|
2021-03-14 18:22:18 +00:00
|
|
|
struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
|
|
|
|
u32 id_mode_dis = 0, port_mode;
|
|
|
|
u32 reg, offset;
|
|
|
|
+ u32 rgmii_ctrl;
|
|
|
|
|
|
|
|
if (port == core_readl(priv, CORE_IMP0_PRT_ID))
|
|
|
|
return;
|
|
|
|
|
|
|
|
+ if (priv->type == BCM4908_DEVICE_ID) {
|
|
|
|
+ if (port != 7)
|
|
|
|
+ return;
|
|
|
|
+ rgmii_ctrl = REG_RGMII_11_CNTRL;
|
|
|
|
+ } else {
|
|
|
|
+ rgmii_ctrl = REG_RGMII_CNTRL_P(port);
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
if (priv->type == BCM4908_DEVICE_ID ||
|
|
|
|
priv->type == BCM7445_DEVICE_ID)
|
|
|
|
offset = CORE_STS_OVERRIDE_GMIIP_PORT(port);
|
2021-03-17 06:40:49 +00:00
|
|
|
@@ -623,7 +632,7 @@ static void bcm_sf2_sw_mac_config(struct
|
2021-03-14 18:22:18 +00:00
|
|
|
/* Clear id_mode_dis bit, and the existing port mode, let
|
|
|
|
* RGMII_MODE_EN bet set by mac_link_{up,down}
|
|
|
|
*/
|
|
|
|
- reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
|
|
|
|
+ reg = reg_readl(priv, rgmii_ctrl);
|
|
|
|
reg &= ~ID_MODE_DIS;
|
|
|
|
reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT);
|
|
|
|
reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
|
2021-03-17 06:40:49 +00:00
|
|
|
@@ -638,7 +647,7 @@ static void bcm_sf2_sw_mac_config(struct
|
2021-03-14 18:22:18 +00:00
|
|
|
reg |= RX_PAUSE_EN;
|
|
|
|
}
|
|
|
|
|
|
|
|
- reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
|
|
|
|
+ reg_writel(priv, reg, rgmii_ctrl);
|
|
|
|
|
|
|
|
force_link:
|
|
|
|
/* Force link settings detected from the PHY */
|
2021-03-17 06:40:49 +00:00
|
|
|
@@ -664,6 +673,7 @@ static void bcm_sf2_sw_mac_link_set(stru
|
2021-03-14 18:22:18 +00:00
|
|
|
phy_interface_t interface, bool link)
|
|
|
|
{
|
|
|
|
struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
|
|
|
|
+ u32 rgmii_ctrl;
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
if (!phy_interface_mode_is_rgmii(interface) &&
|
2021-03-17 06:40:49 +00:00
|
|
|
@@ -671,13 +681,21 @@ static void bcm_sf2_sw_mac_link_set(stru
|
2021-03-14 18:22:18 +00:00
|
|
|
interface != PHY_INTERFACE_MODE_REVMII)
|
|
|
|
return;
|
|
|
|
|
|
|
|
+ if (priv->type == BCM4908_DEVICE_ID) {
|
|
|
|
+ if (port != 7)
|
|
|
|
+ return;
|
|
|
|
+ rgmii_ctrl = REG_RGMII_11_CNTRL;
|
|
|
|
+ } else {
|
|
|
|
+ rgmii_ctrl = REG_RGMII_CNTRL_P(port);
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
/* If the link is down, just disable the interface to conserve power */
|
|
|
|
- reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
|
|
|
|
+ reg = reg_readl(priv, rgmii_ctrl);
|
|
|
|
if (link)
|
|
|
|
reg |= RGMII_MODE_EN;
|
|
|
|
else
|
|
|
|
reg &= ~RGMII_MODE_EN;
|
|
|
|
- reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
|
|
|
|
+ reg_writel(priv, reg, rgmii_ctrl);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void bcm_sf2_sw_mac_link_down(struct dsa_switch *ds, int port,
|
2021-03-17 06:40:49 +00:00
|
|
|
@@ -1051,9 +1069,7 @@ static const u16 bcm_sf2_4908_reg_offset
|
2021-03-14 18:22:18 +00:00
|
|
|
[REG_PHY_REVISION] = 0x14,
|
|
|
|
[REG_SPHY_CNTRL] = 0x24,
|
|
|
|
[REG_CROSSBAR] = 0xc8,
|
|
|
|
- [REG_RGMII_0_CNTRL] = 0xe0,
|
|
|
|
- [REG_RGMII_1_CNTRL] = 0xec,
|
|
|
|
- [REG_RGMII_2_CNTRL] = 0xf8,
|
|
|
|
+ [REG_RGMII_11_CNTRL] = 0x014c,
|
|
|
|
[REG_LED_0_CNTRL] = 0x40,
|
|
|
|
[REG_LED_1_CNTRL] = 0x4c,
|
|
|
|
[REG_LED_2_CNTRL] = 0x58,
|
|
|
|
--- a/drivers/net/dsa/bcm_sf2_regs.h
|
|
|
|
+++ b/drivers/net/dsa/bcm_sf2_regs.h
|
|
|
|
@@ -21,6 +21,7 @@ enum bcm_sf2_reg_offs {
|
|
|
|
REG_RGMII_0_CNTRL,
|
|
|
|
REG_RGMII_1_CNTRL,
|
|
|
|
REG_RGMII_2_CNTRL,
|
|
|
|
+ REG_RGMII_11_CNTRL,
|
|
|
|
REG_LED_0_CNTRL,
|
|
|
|
REG_LED_1_CNTRL,
|
|
|
|
REG_LED_2_CNTRL,
|