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185 lines
6.2 KiB
Diff
185 lines
6.2 KiB
Diff
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From 2b0229f67932e4b9e2f458bf286903582bd30740 Mon Sep 17 00:00:00 2001
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From: Lorenzo Bianconi <lorenzo@kernel.org>
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Date: Thu, 1 Aug 2024 09:35:12 +0200
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Subject: [PATCH] net: dsa: mt7530: Add EN7581 support
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Introduce support for the DSA built-in switch available on the EN7581
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development board. EN7581 support is similar to MT7988 one except
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it requires to set MT7530_FORCE_MODE bit in MT753X_PMCR_P register
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for on cpu port.
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Tested-by: Benjamin Larsson <benjamin.larsson@genexis.eu>
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Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
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Reviewed-by: Arınç ÜNAL <arinc.unal@arinc9.com>
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Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/dsa/mt7530-mmio.c | 1 +
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drivers/net/dsa/mt7530.c | 49 ++++++++++++++++++++++++++++++-----
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drivers/net/dsa/mt7530.h | 20 ++++++++++----
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3 files changed, 59 insertions(+), 11 deletions(-)
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--- a/drivers/net/dsa/mt7530-mmio.c
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+++ b/drivers/net/dsa/mt7530-mmio.c
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@@ -11,6 +11,7 @@
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#include "mt7530.h"
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static const struct of_device_id mt7988_of_match[] = {
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+ { .compatible = "airoha,en7581-switch", .data = &mt753x_table[ID_EN7581], },
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{ .compatible = "mediatek,mt7988-switch", .data = &mt753x_table[ID_MT7988], },
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{ /* sentinel */ },
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};
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--- a/drivers/net/dsa/mt7530.c
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+++ b/drivers/net/dsa/mt7530.c
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@@ -1152,7 +1152,8 @@ mt753x_cpu_port_enable(struct dsa_switch
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* the MT7988 SoC. Trapped frames will be forwarded to the CPU port that
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* is affine to the inbound user port.
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*/
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- if (priv->id == ID_MT7531 || priv->id == ID_MT7988)
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+ if (priv->id == ID_MT7531 || priv->id == ID_MT7988 ||
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+ priv->id == ID_EN7581)
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mt7530_set(priv, MT7531_CFC, MT7531_CPU_PMAP(BIT(port)));
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/* CPU port gets connected to all user ports of
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@@ -2207,7 +2208,7 @@ mt7530_setup_irq(struct mt7530_priv *pri
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return priv->irq ? : -EINVAL;
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}
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- if (priv->id == ID_MT7988)
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+ if (priv->id == ID_MT7988 || priv->id == ID_EN7581)
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priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS,
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&mt7988_irq_domain_ops,
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priv);
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@@ -2438,8 +2439,10 @@ mt7530_setup(struct dsa_switch *ds)
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/* Clear link settings and enable force mode to force link down
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* on all ports until they're enabled later.
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*/
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- mt7530_rmw(priv, MT753X_PMCR_P(i), PMCR_LINK_SETTINGS_MASK |
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- MT7530_FORCE_MODE, MT7530_FORCE_MODE);
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+ mt7530_rmw(priv, MT753X_PMCR_P(i),
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+ PMCR_LINK_SETTINGS_MASK |
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+ MT753X_FORCE_MODE(priv->id),
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+ MT753X_FORCE_MODE(priv->id));
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/* Disable forwarding by default on all ports */
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mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
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@@ -2550,8 +2553,10 @@ mt7531_setup_common(struct dsa_switch *d
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/* Clear link settings and enable force mode to force link down
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* on all ports until they're enabled later.
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*/
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- mt7530_rmw(priv, MT753X_PMCR_P(i), PMCR_LINK_SETTINGS_MASK |
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- MT7531_FORCE_MODE_MASK, MT7531_FORCE_MODE_MASK);
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+ mt7530_rmw(priv, MT753X_PMCR_P(i),
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+ PMCR_LINK_SETTINGS_MASK |
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+ MT753X_FORCE_MODE(priv->id),
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+ MT753X_FORCE_MODE(priv->id));
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/* Disable forwarding by default on all ports */
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mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
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@@ -2783,6 +2788,28 @@ static void mt7988_mac_port_get_caps(str
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}
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}
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+static void en7581_mac_port_get_caps(struct dsa_switch *ds, int port,
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+ struct phylink_config *config)
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+{
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+ switch (port) {
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+ /* Ports which are connected to switch PHYs. There is no MII pinout. */
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+ case 0 ... 4:
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+ __set_bit(PHY_INTERFACE_MODE_INTERNAL,
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+ config->supported_interfaces);
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+
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+ config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD;
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+ break;
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+
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+ /* Port 6 is connected to SoC's XGMII MAC. There is no MII pinout. */
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+ case 6:
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+ __set_bit(PHY_INTERFACE_MODE_INTERNAL,
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+ config->supported_interfaces);
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+
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+ config->mac_capabilities |= MAC_10000FD;
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+ break;
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+ }
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+}
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+
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static void
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mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
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phy_interface_t interface)
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@@ -3220,6 +3247,16 @@ const struct mt753x_info mt753x_table[]
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.phy_write_c45 = mt7531_ind_c45_phy_write,
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.mac_port_get_caps = mt7988_mac_port_get_caps,
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},
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+ [ID_EN7581] = {
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+ .id = ID_EN7581,
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+ .pcs_ops = &mt7530_pcs_ops,
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+ .sw_setup = mt7988_setup,
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+ .phy_read_c22 = mt7531_ind_c22_phy_read,
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+ .phy_write_c22 = mt7531_ind_c22_phy_write,
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+ .phy_read_c45 = mt7531_ind_c45_phy_read,
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+ .phy_write_c45 = mt7531_ind_c45_phy_write,
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+ .mac_port_get_caps = en7581_mac_port_get_caps,
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+ },
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};
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EXPORT_SYMBOL_GPL(mt753x_table);
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--- a/drivers/net/dsa/mt7530.h
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+++ b/drivers/net/dsa/mt7530.h
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@@ -19,6 +19,7 @@ enum mt753x_id {
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ID_MT7621 = 1,
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ID_MT7531 = 2,
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ID_MT7988 = 3,
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+ ID_EN7581 = 4,
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};
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#define NUM_TRGMII_CTRL 5
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@@ -64,25 +65,30 @@ enum mt753x_id {
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#define MT7531_CPU_PMAP(x) FIELD_PREP(MT7531_CPU_PMAP_MASK, x)
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#define MT753X_MIRROR_REG(id) ((id == ID_MT7531 || \
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- id == ID_MT7988) ? \
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+ id == ID_MT7988 || \
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+ id == ID_EN7581) ? \
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MT7531_CFC : MT753X_MFC)
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#define MT753X_MIRROR_EN(id) ((id == ID_MT7531 || \
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- id == ID_MT7988) ? \
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+ id == ID_MT7988 || \
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+ id == ID_EN7581) ? \
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MT7531_MIRROR_EN : MT7530_MIRROR_EN)
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#define MT753X_MIRROR_PORT_MASK(id) ((id == ID_MT7531 || \
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- id == ID_MT7988) ? \
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+ id == ID_MT7988 || \
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+ id == ID_EN7581) ? \
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MT7531_MIRROR_PORT_MASK : \
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MT7530_MIRROR_PORT_MASK)
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#define MT753X_MIRROR_PORT_GET(id, val) ((id == ID_MT7531 || \
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- id == ID_MT7988) ? \
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+ id == ID_MT7988 || \
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+ id == ID_EN7581) ? \
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MT7531_MIRROR_PORT_GET(val) : \
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MT7530_MIRROR_PORT_GET(val))
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#define MT753X_MIRROR_PORT_SET(id, val) ((id == ID_MT7531 || \
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- id == ID_MT7988) ? \
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+ id == ID_MT7988 || \
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+ id == ID_EN7581) ? \
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MT7531_MIRROR_PORT_SET(val) : \
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MT7530_MIRROR_PORT_SET(val))
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@@ -355,6 +361,10 @@ enum mt7530_vlan_port_acc_frm {
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MT7531_FORCE_MODE_TX_FC | \
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MT7531_FORCE_MODE_EEE100 | \
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MT7531_FORCE_MODE_EEE1G)
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+#define MT753X_FORCE_MODE(id) ((id == ID_MT7531 || \
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+ id == ID_MT7988) ? \
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+ MT7531_FORCE_MODE_MASK : \
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+ MT7530_FORCE_MODE)
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#define PMCR_LINK_SETTINGS_MASK (PMCR_MAC_TX_EN | PMCR_MAC_RX_EN | \
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PMCR_FORCE_EEE1G | \
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PMCR_FORCE_EEE100 | \
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