mirror of
https://github.com/openwrt/openwrt.git
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45 lines
1.4 KiB
Diff
45 lines
1.4 KiB
Diff
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--- a/arch/arm/boot/dts/ox820.dtsi
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+++ b/arch/arm/boot/dts/ox820.dtsi
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@@ -247,6 +247,15 @@
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};
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};
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+ pcie_phy: pcie-phy@a00000 {
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+ compatible = "oxsemi,ox820-pcie-phy";
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+ reg = <0xa00000 0x10>;
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+ #phy-cells = <0>;
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+ resets = <&reset RESET_PCIEPHY>;
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+ reset-names = "phy";
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+ status = "disabled";
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+ };
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+
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sys: sys-ctrl@e00000 {
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compatible = "oxsemi,ox820-sys-ctrl", "syscon", "simple-mfd";
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reg = <0xe00000 0x200000>;
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--- a/drivers/phy/Kconfig
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+++ b/drivers/phy/Kconfig
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@@ -35,6 +35,13 @@ config PHY_LPC18XX_USB_OTG
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This driver is need for USB0 support on LPC18xx/43xx and takes
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care of enabling and clock setup.
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+config PHY_OXNAS
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+ tristate "Oxford Semi. OX820 PCI-E PHY support"
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+ depends on HAS_IOMEM && OF && (ARM || COMPILE_TEST)
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+ select GENERIC_PHY
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+ help
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+ This option enables support for OXNAS OX820 SoC PCIE PHY.
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+
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config PHY_PISTACHIO_USB
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tristate "IMG Pistachio USB2.0 PHY driver"
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depends on MIPS || COMPILE_TEST
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--- a/drivers/phy/Makefile
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+++ b/drivers/phy/Makefile
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@@ -7,6 +7,7 @@ obj-$(CONFIG_GENERIC_PHY) += phy-core.o
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obj-$(CONFIG_GENERIC_PHY_MIPI_DPHY) += phy-core-mipi-dphy.o
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obj-$(CONFIG_PHY_CAN_TRANSCEIVER) += phy-can-transceiver.o
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obj-$(CONFIG_PHY_LPC18XX_USB_OTG) += phy-lpc18xx-usb-otg.o
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+obj-$(CONFIG_PHY_OXNAS) += phy-oxnas-pcie.o
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obj-$(CONFIG_PHY_XGENE) += phy-xgene.o
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obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o
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obj-$(CONFIG_USB_LGM_PHY) += phy-lgm-usb.o
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