mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-28 17:48:58 +00:00
68 lines
2.6 KiB
Diff
68 lines
2.6 KiB
Diff
|
--- a/arch/mips/ralink/mt7620.c
|
||
|
|
+++ b/arch/mips/ralink/mt7620.c
|
||
|
|
@@ -513,6 +513,7 @@ void __init ralink_clk_init(void)
|
||
|
|
unsigned long sys_rate;
|
||
|
|
unsigned long dram_rate;
|
||
|
|
unsigned long periph_rate;
|
||
|
|
+ unsigned long pcmi2s_rate;
|
||
|
|
|
||
|
|
xtal_rate = mt7620_get_xtal_rate();
|
||
|
|
|
||
|
|
@@ -527,6 +528,7 @@ void __init ralink_clk_init(void)
|
||
|
|
cpu_rate = MHZ(575);
|
||
|
|
dram_rate = sys_rate = cpu_rate / 3;
|
||
|
|
periph_rate = MHZ(40);
|
||
|
|
+ pcmi2s_rate = MHZ(480);
|
||
|
|
|
||
|
|
ralink_clk_add("10000d00.uartlite", periph_rate);
|
||
|
|
ralink_clk_add("10000e00.uartlite", periph_rate);
|
||
|
|
@@ -538,6 +540,7 @@ void __init ralink_clk_init(void)
|
||
|
|
dram_rate = mt7620_get_dram_rate(pll_rate);
|
||
|
|
sys_rate = mt7620_get_sys_rate(cpu_rate);
|
||
|
|
periph_rate = mt7620_get_periph_rate(xtal_rate);
|
||
|
|
+ pcmi2s_rate = periph_rate;
|
||
|
|
|
||
|
|
pr_debug(RFMT("XTAL") RFMT("CPU_PLL") RFMT("PLL"),
|
||
|
|
RINT(xtal_rate), RFRAC(xtal_rate),
|
||
|
|
@@ -559,6 +562,8 @@ void __init ralink_clk_init(void)
|
||
|
|
ralink_clk_add("cpu", cpu_rate);
|
||
|
|
ralink_clk_add("10000100.timer", periph_rate);
|
||
|
|
ralink_clk_add("10000120.watchdog", periph_rate);
|
||
|
|
+ ralink_clk_add("10000900.i2c", periph_rate);
|
||
|
|
+ ralink_clk_add("10000a00.i2s", pcmi2s_rate);
|
||
|
|
ralink_clk_add("10000b00.spi", sys_rate);
|
||
|
|
ralink_clk_add("10000b40.spi", sys_rate);
|
||
|
|
ralink_clk_add("10000c00.uartlite", periph_rate);
|
||
|
|
--- a/arch/mips/ralink/rt288x.c
|
||
|
|
+++ b/arch/mips/ralink/rt288x.c
|
||
|
|
@@ -75,6 +75,7 @@ void __init ralink_clk_init(void)
|
||
|
|
ralink_clk_add("300100.timer", cpu_rate / 2);
|
||
|
|
ralink_clk_add("300120.watchdog", cpu_rate / 2);
|
||
|
|
ralink_clk_add("300500.uart", cpu_rate / 2);
|
||
|
|
+ ralink_clk_add("300900.i2c", cpu_rate / 2);
|
||
|
|
ralink_clk_add("300c00.uartlite", cpu_rate / 2);
|
||
|
|
ralink_clk_add("400000.ethernet", cpu_rate / 2);
|
||
|
|
ralink_clk_add("480000.wmac", wmac_rate);
|
||
|
|
--- a/arch/mips/ralink/rt305x.c
|
||
|
|
+++ b/arch/mips/ralink/rt305x.c
|
||
|
|
@@ -200,6 +200,8 @@ void __init ralink_clk_init(void)
|
||
|
|
|
||
|
|
ralink_clk_add("cpu", cpu_rate);
|
||
|
|
ralink_clk_add("sys", sys_rate);
|
||
|
|
+ ralink_clk_add("10000900.i2c", uart_rate);
|
||
|
|
+ ralink_clk_add("10000a00.i2s", uart_rate);
|
||
|
|
ralink_clk_add("10000b00.spi", sys_rate);
|
||
|
|
ralink_clk_add("10000b40.spi", sys_rate);
|
||
|
|
ralink_clk_add("10000100.timer", wdt_rate);
|
||
|
|
--- a/arch/mips/ralink/rt3883.c
|
||
|
|
+++ b/arch/mips/ralink/rt3883.c
|
||
|
|
@@ -108,6 +108,8 @@ void __init ralink_clk_init(void)
|
||
|
|
ralink_clk_add("10000100.timer", sys_rate);
|
||
|
|
ralink_clk_add("10000120.watchdog", sys_rate);
|
||
|
|
ralink_clk_add("10000500.uart", 40000000);
|
||
|
|
+ ralink_clk_add("10000900.i2c", 40000000);
|
||
|
|
+ ralink_clk_add("10000a00.i2s", 40000000);
|
||
|
|
ralink_clk_add("10000b00.spi", sys_rate);
|
||
|
|
ralink_clk_add("10000b40.spi", sys_rate);
|
||
|
|
ralink_clk_add("10000c00.uartlite", 40000000);
|