2022-02-04 13:57:50 +00:00
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From 58a6cc3c7eecd16208cd16b92b4eaf8385e69696 Mon Sep 17 00:00:00 2001
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From: Eugen Hristev <eugen.hristev@microchip.com>
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Date: Tue, 13 Apr 2021 12:57:16 +0200
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Subject: [PATCH 174/247] media: atmel: atmel-isc: extend pipeline with extra
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modules
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Newer ISC pipelines have the additional modules of
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Defective Pixel Correction -> DPC itself,
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Defective Pixel Correction -> Green Disparity Correction (DPC_GDC)
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Defective Pixel Correction -> Black Level Correction (DPC_BLC)
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Vertical and Horizontal Scaler -> VHXS
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Some products have this full pipeline (sama7g5), other products do not (sama5d2)
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Add the modules to the isc base, and also extend the register range to include
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the modules.
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Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
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Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
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Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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---
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drivers/media/platform/atmel/atmel-isc-base.c | 11 ++++++--
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drivers/media/platform/atmel/atmel-isc.h | 28 +++++++++++--------
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2 files changed, 25 insertions(+), 14 deletions(-)
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--- a/drivers/media/platform/atmel/atmel-isc-base.c
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+++ b/drivers/media/platform/atmel/atmel-isc-base.c
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2022-03-02 13:11:44 +00:00
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@@ -2324,8 +2324,14 @@ int isc_pipeline_init(struct isc_device
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2022-02-04 13:57:50 +00:00
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struct regmap_field *regs;
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unsigned int i;
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- /* WB-->CFA-->CC-->GAM-->CSC-->CBC-->SUB422-->SUB420 */
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+ /*
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+ * DPCEN-->GDCEN-->BLCEN-->WB-->CFA-->CC-->
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+ * GAM-->VHXS-->CSC-->CBC-->SUB422-->SUB420
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+ */
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const struct reg_field regfields[ISC_PIPE_LINE_NODE_NUM] = {
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+ REG_FIELD(ISC_DPC_CTRL, 0, 0),
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+ REG_FIELD(ISC_DPC_CTRL, 1, 1),
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+ REG_FIELD(ISC_DPC_CTRL, 2, 2),
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REG_FIELD(ISC_WB_CTRL, 0, 0),
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REG_FIELD(ISC_CFA_CTRL, 0, 0),
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REG_FIELD(ISC_CC_CTRL, 0, 0),
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2022-03-02 13:11:44 +00:00
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@@ -2333,6 +2339,7 @@ int isc_pipeline_init(struct isc_device
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2022-02-04 13:57:50 +00:00
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REG_FIELD(ISC_GAM_CTRL, 1, 1),
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REG_FIELD(ISC_GAM_CTRL, 2, 2),
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REG_FIELD(ISC_GAM_CTRL, 3, 3),
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+ REG_FIELD(ISC_VHXS_CTRL, 0, 0),
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REG_FIELD(ISC_CSC_CTRL + isc->offsets.csc, 0, 0),
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REG_FIELD(ISC_CBC_CTRL + isc->offsets.cbc, 0, 0),
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REG_FIELD(ISC_SUB422_CTRL + isc->offsets.sub422, 0, 0),
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2022-03-02 13:11:44 +00:00
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@@ -2351,7 +2358,7 @@ int isc_pipeline_init(struct isc_device
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2022-02-04 13:57:50 +00:00
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}
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/* regmap configuration */
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-#define ATMEL_ISC_REG_MAX 0xbfc
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+#define ATMEL_ISC_REG_MAX 0xd5c
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const struct regmap_config isc_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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--- a/drivers/media/platform/atmel/atmel-isc.h
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+++ b/drivers/media/platform/atmel/atmel-isc.h
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@@ -67,17 +67,21 @@ struct isc_format {
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};
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/* Pipeline bitmap */
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-#define WB_ENABLE BIT(0)
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-#define CFA_ENABLE BIT(1)
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-#define CC_ENABLE BIT(2)
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-#define GAM_ENABLE BIT(3)
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-#define GAM_BENABLE BIT(4)
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-#define GAM_GENABLE BIT(5)
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-#define GAM_RENABLE BIT(6)
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-#define CSC_ENABLE BIT(7)
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-#define CBC_ENABLE BIT(8)
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-#define SUB422_ENABLE BIT(9)
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-#define SUB420_ENABLE BIT(10)
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+#define DPC_DPCENABLE BIT(0)
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+#define DPC_GDCENABLE BIT(1)
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+#define DPC_BLCENABLE BIT(2)
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+#define WB_ENABLE BIT(3)
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+#define CFA_ENABLE BIT(4)
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+#define CC_ENABLE BIT(5)
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+#define GAM_ENABLE BIT(6)
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+#define GAM_BENABLE BIT(7)
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+#define GAM_GENABLE BIT(8)
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+#define GAM_RENABLE BIT(9)
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+#define VHXS_ENABLE BIT(10)
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+#define CSC_ENABLE BIT(11)
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+#define CBC_ENABLE BIT(12)
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+#define SUB422_ENABLE BIT(13)
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+#define SUB420_ENABLE BIT(14)
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#define GAM_ENABLES (GAM_RENABLE | GAM_GENABLE | GAM_BENABLE | GAM_ENABLE)
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@@ -141,7 +145,7 @@ struct isc_ctrls {
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u32 hist_minmax[HIST_BAYER][2];
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};
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-#define ISC_PIPE_LINE_NODE_NUM 11
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+#define ISC_PIPE_LINE_NODE_NUM 15
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/*
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* struct isc_reg_offsets - ISC device register offsets
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