openwrt/target/linux/ramips/patches-5.15/850-awake-rt305x-dwc2-controller.patch

--- a/drivers/usb/dwc2/platform.c
+++ b/drivers/usb/dwc2/platform.c
@@ -498,6 +498,12 @@ static int dwc2_driver_probe(struct plat
 	if (retval)
 		return retval;
 
+	/* Enable USB port before any regs access */
+	if (readl(hsotg->regs + PCGCTL) & 0x0f) {
+		writel(0x00, hsotg->regs + PCGCTL);
+		/* TODO: mdelay(25) here? vendor driver don't use it */
+	}
+
 	hsotg->needs_byte_swap = dwc2_check_core_endianness(hsotg);
 
 	retval = dwc2_get_dr_mode(hsotg);
ramips: add linux 5.15 support for mt7621 Signed-off-by: Felix Fietkau <nbd@nbd.name> 2022-03-27 21:26:31 +02:00			`--- a/drivers/usb/dwc2/platform.c`
			`+++ b/drivers/usb/dwc2/platform.c`
kernel: bump 5.15 to 5.15.105 Manually rebased: Removed upstreamed: backport-5.15/743-v6.3-0005-net-dsa-b53-mmap-fix-device-tree-support.patch[1] backport-5.15/743-v6.3-0006-net-dsa-tag_brcm-legacy-fix-daisy-chained-switches.patch[2] All other patches automatically rebased. 1. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.15.105&id=9bbb3d3f218f1cf51f57a43cf8fd63b05be1b821 2. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.15.105&id=48f52431af9980582b6faa32ff8b581edb10486c Build system: x86_64 Build-tested: bcm2711/RPi4B, ramips/tplink_archer-a6-v3, filogic/xiaomi_redmi-router-ax6000-ubootmod Run-tested: bcm2711/RPi4B, ramips/tplink_archer-a6-v3, filogic/xiaomi_redmi-router-ax6000-ubootmod Signed-off-by: John Audia <therealgraysky@proton.me> 2023-03-30 11:39:17 -04:00			`@@ -498,6 +498,12 @@ static int dwc2_driver_probe(struct plat`
ramips: add linux 5.15 support for mt7621 Signed-off-by: Felix Fietkau <nbd@nbd.name> 2022-03-27 21:26:31 +02:00			`if (retval)`
			`return retval;`

			`+ /* Enable USB port before any regs access */`
			`+ if (readl(hsotg->regs + PCGCTL) & 0x0f) {`
			`+ writel(0x00, hsotg->regs + PCGCTL);`
			`+ /* TODO: mdelay(25) here? vendor driver don't use it */`
			`+ }`
			`+`
			`hsotg->needs_byte_swap = dwc2_check_core_endianness(hsotg);`

			`retval = dwc2_get_dr_mode(hsotg);`