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66 lines
2.2 KiB
Diff
66 lines
2.2 KiB
Diff
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From 81480a89c72d811376e9e040729721705b2a984d Mon Sep 17 00:00:00 2001
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From: "Ivan T. Ivanov" <iivanov@mm-sol.com>
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Date: Thu, 13 Mar 2014 19:07:42 -0700
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Subject: [PATCH 061/182] i2c: qup: Add device tree bindings information
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The Qualcomm Universal Peripherial (QUP) wraps I2C mini-core and
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provide input and output FIFO's for it. I2C controller can operate
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as master with supported bus speeds of 100Kbps and 400Kbps.
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Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
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[bjorn: reformulated part of binding description
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added version to compatible
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cleaned up example]
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Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
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Acked-by: Rob Herring <robh@kernel.org>
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[wsa: removed the dummy child node which was a confusing example]
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Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
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---
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.../devicetree/bindings/i2c/qcom,i2c-qup.txt | 40 ++++++++++++++++++++
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1 file changed, 40 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/i2c/qcom,i2c-qup.txt
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-qup.txt
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@@ -0,0 +1,40 @@
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+Qualcomm Universal Peripheral (QUP) I2C controller
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+
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+Required properties:
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+ - compatible: Should be:
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+ * "qcom,i2c-qup-v1.1.1" for 8660, 8960 and 8064.
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+ * "qcom,i2c-qup-v2.1.1" for 8974 v1.
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+ * "qcom,i2c-qup-v2.2.1" for 8974 v2 and later.
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+ - reg: Should contain QUP register address and length.
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+ - interrupts: Should contain I2C interrupt.
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+
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+ - clocks: A list of phandles + clock-specifiers, one for each entry in
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+ clock-names.
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+ - clock-names: Should contain:
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+ * "core" for the core clock
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+ * "iface" for the AHB clock
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+
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+ - #address-cells: Should be <1> Address cells for i2c device address
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+ - #size-cells: Should be <0> as i2c addresses have no size component
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+
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+Optional properties:
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+ - clock-frequency: Should specify the desired i2c bus clock frequency in Hz,
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+ defaults to 100kHz if omitted.
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+
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+Child nodes should conform to i2c bus binding.
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+
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+Example:
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+
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+ i2c@f9924000 {
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+ compatible = "qcom,i2c-qup-v2.2.1";
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+ reg = <0xf9924000 0x1000>;
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+ interrupts = <0 96 0>;
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+
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+ clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
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+ clock-names = "core", "iface";
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+
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+ clock-frequency = <355000>;
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+
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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