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54 lines
1.8 KiB
Diff
54 lines
1.8 KiB
Diff
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From b9185c75f7ec2b600ebe0d49281e216a2456b764 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
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Date: Thu, 13 May 2021 15:11:06 +0200
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Subject: [PATCH] fix(plat/marvell/a3720/uart): fix configuring UART clock
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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When configuring the UART_BAUD_REG register, the function
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console_a3700_core_init() currently only changes the baud divisor field,
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leaving other fields to their previous value.
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This is incorrect, because the baud divisor is computed with the
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assumption that the parent clock rate is 25 MHz, and since the other
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fields in this register configure the parent clock, which could have
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been changed by U-Boot or Linux.
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Fix this function to also configure the other fields so that the UART
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parent clock is selected to be the xtal clock.
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For example without this change TF-A prints only
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ERROR: a3700_system_off needs to be implemented
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followed by garbage after plat_crash_console_init() is called.
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After applying this change instead of garbage it also print crash info:
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PANIC at PC : 0x0000000004023800
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Signed-off-by: Pali Rohár <pali@kernel.org>
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Change-Id: I72f338355cc60d939b8bb978d9c7fdd576416b81
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---
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drivers/marvell/uart/a3700_console.S | 7 ++-----
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1 file changed, 2 insertions(+), 5 deletions(-)
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--- a/drivers/marvell/uart/a3700_console.S
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+++ b/drivers/marvell/uart/a3700_console.S
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@@ -49,12 +49,9 @@ func console_a3700_core_init
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lsl w2, w2, #4
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add w1, w1, w2, lsr #1
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udiv w2, w1, w2
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- and w2, w2, #0x3ff
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+ and w2, w2, #0x3ff /* clear all other bits to use default clock */
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- ldr w3, [x0, #UART_BAUD_REG]
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- bic w3, w3, 0x3ff
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- orr w3, w3, w2
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- str w3, [x0, #UART_BAUD_REG]/* set baud rate divisor */
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+ str w2, [x0, #UART_BAUD_REG]/* set baud rate divisor */
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/* Set UART to default 16X scheme */
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mov w3, #0
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