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57 lines
1.8 KiB
Diff
57 lines
1.8 KiB
Diff
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From 83f865d7e32e40b4903b1f83537c63fc5cdf1eb8 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>
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Date: Wed, 17 Jun 2020 12:50:36 +0200
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Subject: [PATCH 4/9] mips: bmips: dts: add BCM6328 reset controller support
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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BCM6328 SoCs have a reset controller for certain components.
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Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
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Acked-by: Florian Fainelli <f.fainelli@gmail.com>
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Reviewed-by: Rob Herring <robh@kernel.org>
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Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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---
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arch/mips/boot/dts/brcm/bcm6328.dtsi | 6 ++++++
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include/dt-bindings/reset/bcm6328-reset.h | 18 ++++++++++++++++++
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2 files changed, 24 insertions(+)
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create mode 100644 include/dt-bindings/reset/bcm6328-reset.h
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--- a/arch/mips/boot/dts/brcm/bcm6328.dtsi
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+++ b/arch/mips/boot/dts/brcm/bcm6328.dtsi
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@@ -57,6 +57,12 @@
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#clock-cells = <1>;
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};
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+ periph_rst: reset-controller@10000010 {
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+ compatible = "brcm,bcm6345-reset";
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+ reg = <0x10000010 0x4>;
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+ #reset-cells = <1>;
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+ };
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+
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periph_intc: interrupt-controller@10000020 {
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compatible = "brcm,bcm6345-l1-intc";
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reg = <0x10000020 0x10>,
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--- /dev/null
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+++ b/include/dt-bindings/reset/bcm6328-reset.h
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@@ -0,0 +1,18 @@
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+/* SPDX-License-Identifier: GPL-2.0+ */
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+
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+#ifndef __DT_BINDINGS_RESET_BCM6328_H
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+#define __DT_BINDINGS_RESET_BCM6328_H
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+
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+#define BCM6328_RST_SPI 0
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+#define BCM6328_RST_EPHY 1
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+#define BCM6328_RST_SAR 2
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+#define BCM6328_RST_ENETSW 3
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+#define BCM6328_RST_USBS 4
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+#define BCM6328_RST_USBH 5
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+#define BCM6328_RST_PCM 6
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+#define BCM6328_RST_PCIE_CORE 7
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+#define BCM6328_RST_PCIE 8
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+#define BCM6328_RST_PCIE_EXT 9
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+#define BCM6328_RST_PCIE_HARD 10
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+
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+#endif /* __DT_BINDINGS_RESET_BCM6328_H */
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