openwrt/target/linux/bcm27xx/patches-6.1/950-1254-Add-pcie-32bit-dma-overlay-pi5-to-enable-32bit-DMA-o.patch

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From 1cdbd99f402b76c61632d09a49b20ce90af0cc72 Mon Sep 17 00:00:00 2001
From: Rodrigo Rosmaninho <quico.rosmaninho@gmail.com>
Date: Tue, 23 Jan 2024 18:50:19 +0000
Subject: [PATCH 1254/1295] Add pcie-32bit-dma-overlay-pi5 to enable 32bit DMA
on the Pi 5's external PCIe
Changes dma-ranges in the pcie1 component of the bcm2712 dts in order to ensure that the DMA addressing space is 32bits, at the expense of having to bounce buffers.
Signed-off-by: Rodrigo Rosmaninho <r.rosmaninho@ua.pt>
---
arch/arm/boot/dts/overlays/Makefile | 1 +
arch/arm/boot/dts/overlays/README | 6 +++++
arch/arm/boot/dts/overlays/overlay_map.dts | 5 ++++
.../overlays/pcie-32bit-dma-pi5-overlay.dts | 26 +++++++++++++++++++
4 files changed, 38 insertions(+)
create mode 100644 arch/arm/boot/dts/overlays/pcie-32bit-dma-pi5-overlay.dts
--- a/arch/arm/boot/dts/overlays/Makefile
+++ b/arch/arm/boot/dts/overlays/Makefile
@@ -182,6 +182,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \
pca953x.dtbo \
pcf857x.dtbo \
pcie-32bit-dma.dtbo \
+ pcie-32bit-dma-pi5.dtbo \
pibell.dtbo \
pifacedigital.dtbo \
pifi-40.dtbo \
--- a/arch/arm/boot/dts/overlays/README
+++ b/arch/arm/boot/dts/overlays/README
@@ -3388,6 +3388,12 @@ Load: dtoverlay=pcie-32bit-dma
Params: <None>
+Name: pcie-32bit-dma-pi5
+Info: Force PCIe config to support 32bit DMA addresses at the expense of
+ having to bounce buffers (on the Pi 5).
+Load: dtoverlay=pcie-32bit-dma-pi5
+Params: <None>
+
[ The pcf2127-rtc overlay has been deleted. See i2c-rtc. ]
--- a/arch/arm/boot/dts/overlays/overlay_map.dts
+++ b/arch/arm/boot/dts/overlays/overlay_map.dts
@@ -185,6 +185,11 @@
pcie-32bit-dma {
bcm2711;
+ bcm2712 = "pcie-32bit-dma-pi5";
+ };
+
+ pcie-32bit-dma-pi5 {
+ bcm2712;
};
pi3-act-led {
--- /dev/null
+++ b/arch/arm/boot/dts/overlays/pcie-32bit-dma-pi5-overlay.dts
@@ -0,0 +1,26 @@
+/*
+ * pcie-32bit-dma-pi5-overlay.dts
+ */
+
+/dts-v1/;
+/plugin/;
+
+/ {
+ compatible = "brcm,bcm2712";
+
+ fragment@0 {
+ target = <&pcie1>;
+ __overlay__ {
+ /*
+ * The size of the range is rounded up to a power of 2,
+ * so the range ends up being 0-4GB, and the MSI vector
+ * gets pushed beyond 4GB.
+ */
+ #address-cells = <3>;
+ #size-cells = <2>;
+ dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000
+ 0x0 0x80000000>;
+ };
+ };
+
+};