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82 lines
2.3 KiB
Diff
82 lines
2.3 KiB
Diff
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From b3b1177092d4d2ba6df74042d39aa42c5055f687 Mon Sep 17 00:00:00 2001
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From: Phil Elwell <phil@raspberrypi.com>
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Date: Mon, 3 Jul 2023 09:08:16 +0100
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Subject: [PATCH] ASoC: dwc: Add DMACR handling
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Add control of the DMACR register, which is required for paced DMA
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(i.e. DREQ) support.
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Signed-off-by: Phil Elwell <phil@raspberrypi.com>
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---
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sound/soc/dwc/dwc-i2s.c | 13 ++++++++++---
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sound/soc/dwc/local.h | 13 +++++++++++++
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2 files changed, 23 insertions(+), 3 deletions(-)
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--- a/sound/soc/dwc/dwc-i2s.c
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+++ b/sound/soc/dwc/dwc-i2s.c
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@@ -185,9 +185,9 @@ static void i2s_stop(struct dw_i2s_dev *
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static void dw_i2s_config(struct dw_i2s_dev *dev, int stream)
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{
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- u32 ch_reg;
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struct i2s_clk_config_data *config = &dev->config;
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-
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+ u32 ch_reg;
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+ u32 dmacr = 0;
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i2s_disable_channels(dev, stream);
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@@ -198,15 +198,22 @@ static void dw_i2s_config(struct dw_i2s_
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i2s_write_reg(dev->i2s_base, TFCR(ch_reg),
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dev->fifo_th - 1);
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i2s_write_reg(dev->i2s_base, TER(ch_reg), 1);
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+ dmacr |= (DMACR_DMAEN_TXCH0 << ch_reg);
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} else {
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i2s_write_reg(dev->i2s_base, RCR(ch_reg),
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dev->xfer_resolution);
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i2s_write_reg(dev->i2s_base, RFCR(ch_reg),
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dev->fifo_th - 1);
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i2s_write_reg(dev->i2s_base, RER(ch_reg), 1);
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+ dmacr |= (DMACR_DMAEN_RXCH0 << ch_reg);
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}
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-
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}
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+ if (stream == SNDRV_PCM_STREAM_PLAYBACK)
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+ dmacr |= DMACR_DMAEN_TX;
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+ else if (stream == SNDRV_PCM_STREAM_CAPTURE)
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+ dmacr |= DMACR_DMAEN_RX;
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+
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+ i2s_write_reg(dev->i2s_base, DMACR, dmacr);
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}
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static int dw_i2s_hw_params(struct snd_pcm_substream *substream,
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--- a/sound/soc/dwc/local.h
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+++ b/sound/soc/dwc/local.h
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@@ -25,6 +25,8 @@
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#define RXFFR 0x014
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#define TXFFR 0x018
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+#define DMACR 0x200
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+
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/* Interrupt status register fields */
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#define ISR_TXFO BIT(5)
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#define ISR_TXFE BIT(4)
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@@ -47,6 +49,17 @@
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#define RFF(x) (0x40 * x + 0x050)
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#define TFF(x) (0x40 * x + 0x054)
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+#define DMACR_DMAEN_TX BIT(17)
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+#define DMACR_DMAEN_RX BIT(16)
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+#define DMACR_DMAEN_TXCH3 BIT(11)
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+#define DMACR_DMAEN_TXCH2 BIT(10)
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+#define DMACR_DMAEN_TXCH1 BIT(9)
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+#define DMACR_DMAEN_TXCH0 BIT(8)
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+#define DMACR_DMAEN_RXCH3 BIT(3)
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+#define DMACR_DMAEN_RXCH2 BIT(2)
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+#define DMACR_DMAEN_RXCH1 BIT(1)
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+#define DMACR_DMAEN_RXCH0 BIT(0)
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+
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/* I2SCOMPRegisters */
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#define I2S_COMP_PARAM_2 0x01F0
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#define I2S_COMP_PARAM_1 0x01F4
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