From 1cacd0f7b0d35f8e3d3f8a69ecb3b5e436d6b9e8 Mon Sep 17 00:00:00 2001
From: Jonas Gorski <jogo@openwrt.org>
Date: Sun, 22 Dec 2013 13:25:25 +0100
Subject: [PATCH 52/56] MIPS: BCM63XX: fixup mapped SPI flash access on boot

Some bootloaders leave the flash access in an invalid state with dual
read enabled; fix it by disabling it and falling back to simple fast
reads.

Signed-off-by: Jonas Gorski <jogo@openwrt.org>
---
 arch/mips/bcm63xx/dev-flash.c | 36 ++++++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

--- a/arch/mips/bcm63xx/dev-flash.c
+++ b/arch/mips/bcm63xx/dev-flash.c
@@ -110,9 +110,46 @@ static int __init bcm63xx_detect_flash_t
 	}
 }
 
+#define HSSPI_FLASH_CTRL_REG		0x14
+#define FLASH_CTRL_READ_OPCODE_MASK	0xff
+#define FLASH_CTRL_ADDR_BYTES_MASK	(0x3 << 8)
+#define FLASH_CTRL_ADDR_BYTES_2		(0 << 8)
+#define FLASH_CTRL_ADDR_BYTES_3		(1 << 8)
+#define FLASH_CTRL_ADDR_BYTES_4		(2 << 8)
+#define FLASH_CTRL_MB_EN		(1 << 23)
+
 void __init bcm63xx_flash_detect(void)
 {
 	flash_type = bcm63xx_detect_flash_type();
+
+	/* reduce flash mapping to single i/o reads for safety */
+	if (flash_type == BCM63XX_FLASH_TYPE_SERIAL &&
+	    (BCMCPU_IS_6318() || BCMCPU_IS_6328() || BCMCPU_IS_6362() ||
+	     BCMCPU_IS_63268())) {
+		u32 val = bcm_rset_readl(RSET_HSSPI, HSSPI_FLASH_CTRL_REG);
+
+		if (!(val & FLASH_CTRL_MB_EN))
+			return;
+
+		val &= ~FLASH_CTRL_MB_EN;
+		val &= ~FLASH_CTRL_READ_OPCODE_MASK;
+
+		switch (val & FLASH_CTRL_ADDR_BYTES_MASK) {
+		case FLASH_CTRL_ADDR_BYTES_3:
+			val |= 0x0b; /* OPCODE_FAST_READ */
+			break;
+		case FLASH_CTRL_ADDR_BYTES_4:
+			val |= 0x0c; /* OPCODE_FAST_READ_4B */
+			break;
+		case FLASH_CTRL_ADDR_BYTES_2:
+		default:
+			pr_warn("unsupported address byte mode (%x), not fixing up\n",
+				val & FLASH_CTRL_ADDR_BYTES_MASK);
+			return;
+		}
+
+		bcm_rset_writel(RSET_HSSPI, val, HSSPI_FLASH_CTRL_REG);
+	}
 }
 
 int __init bcm63xx_flash_register(void)
