From d09357656ae3985095f562cf005fa94fd61ebfe6 Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Tue, 1 Feb 2022 21:50:16 -0600
Subject: [PATCH 038/117] crypto: sun8i-ce - Add TRNG clock to D1 variant

At least the D1 variant requires a separate clock for the TRNG.
Without this clock enabled, reading from /dev/hwrng reports:

   sun8i-ce 3040000.crypto: DMA timeout for TRNG (tm=96) on flow 3

Experimentation shows that the necessary clock is the SoC's internal
RC oscillator. This makes sense, as the oscillator's frequency
variations can be used as a source of randomness.

Since D1 does not yet have a device tree, we can update this variant
without breaking anything.

Series-changes: 2
 - New patch

Signed-off-by: Samuel Holland <samuel@sholland.org>
---
 drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c | 1 +
 drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h      | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

--- a/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
+++ b/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
@@ -118,6 +118,7 @@ static const struct ce_variant ce_d1_var
 		{ "bus", 0, 200000000 },
 		{ "mod", 300000000, 0 },
 		{ "ram", 0, 400000000 },
+		{ "trng", 0, 0 },
 		},
 	.esr = ESR_D1,
 	.prng = CE_ALG_PRNG,
--- a/drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h
+++ b/drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h
@@ -105,7 +105,7 @@
 
 #define MAX_SG 8
 
-#define CE_MAX_CLOCKS 3
+#define CE_MAX_CLOCKS 4
 
 #define MAXFLOW 4
 
