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253 lines
6.9 KiB
C
253 lines
6.9 KiB
C
/*
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* AD9361
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* SPDX-FileCopyrightText: Copyright 2013-2018 Analog Devices Inc
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* Modified by Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef IIO_FREQUENCY_AD9361_H_
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#define IIO_FREQUENCY_AD9361_H_
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#include "ad9361_regs.h"
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enum ad9361_clocks {
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BB_REFCLK,
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RX_REFCLK,
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TX_REFCLK,
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BBPLL_CLK,
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ADC_CLK,
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R2_CLK,
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R1_CLK,
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CLKRF_CLK,
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RX_SAMPL_CLK,
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DAC_CLK,
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T2_CLK,
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T1_CLK,
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CLKTF_CLK,
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TX_SAMPL_CLK,
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RX_RFPLL_INT,
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TX_RFPLL_INT,
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RX_RFPLL_DUMMY,
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TX_RFPLL_DUMMY,
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RX_RFPLL,
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TX_RFPLL,
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NUM_AD9361_CLKS,
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};
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enum debugfs_cmd {
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DBGFS_NONE,
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DBGFS_INIT,
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DBGFS_LOOPBACK,
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DBGFS_BIST_PRBS,
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DBGFS_BIST_TONE,
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DBGFS_BIST_DT_ANALYSIS,
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DBGFS_RXGAIN_1,
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DBGFS_RXGAIN_2,
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DBGFS_MCS,
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DBGFS_CAL_SW_CTRL,
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DBGFS_DIGITAL_TUNE,
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DBGFS_GPO_SET,
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};
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enum dig_tune_flags {
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BE_VERBOSE = 1,
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BE_MOREVERBOSE = 2,
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DO_IDELAY = 4,
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DO_ODELAY = 8,
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SKIP_STORE_RESULT = 16,
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RESTORE_DEFAULT = 32,
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};
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enum ad9361_bist_mode {
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BIST_DISABLE,
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BIST_INJ_TX,
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BIST_INJ_RX,
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};
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enum {
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ID_AD9361,
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ID_AD9364,
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ID_AD9361_2,
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ID_AD9363A,
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};
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enum rx_port_sel {
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RX_A_BALANCED, /* 0 = (RX1A_N & RX1A_P) and (RX2A_N & RX2A_P) enabled; balanced */
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RX_B_BALANCED, /* 1 = (RX1B_N & RX1B_P) and (RX2B_N & RX2B_P) enabled; balanced */
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RX_C_BALANCED, /* 2 = (RX1C_N & RX1C_P) and (RX2C_N & RX2C_P) enabled; balanced */
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RX_A_N, /* 3 = RX1A_N and RX2A_N enabled; unbalanced */
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RX_A_P, /* 4 = RX1A_P and RX2A_P enabled; unbalanced */
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RX_B_N, /* 5 = RX1B_N and RX2B_N enabled; unbalanced */
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RX_B_P, /* 6 = RX1B_P and RX2B_P enabled; unbalanced */
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RX_C_N, /* 7 = RX1C_N and RX2C_N enabled; unbalanced */
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RX_C_P, /* 8 = RX1C_P and RX2C_P enabled; unbalanced */
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TX_MON1, /* 9 = TX_MON1 enabled */
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TX_MON2, /* 10 = TX_MON2 enabled */
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TX_MON1_2, /* 11 = TX_MON1 & TX_MON2 enabled */
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};
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enum tx_port_sel {
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TX_A,
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TX_B,
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};
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enum digital_tune_skip_mode {
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TUNE_RX_TX,
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SKIP_TX,
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SKIP_ALL,
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};
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enum rssi_restart_mode {
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AGC_IN_FAST_ATTACK_MODE_LOCKS_THE_GAIN,
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EN_AGC_PIN_IS_PULLED_HIGH,
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ENTERS_RX_MODE,
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GAIN_CHANGE_OCCURS,
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SPI_WRITE_TO_REGISTER,
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GAIN_CHANGE_OCCURS_OR_EN_AGC_PIN_PULLED_HIGH,
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};
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struct ctrl_outs_control {
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u8 index;
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u8 en_mask;
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};
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struct rssi_control {
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enum rssi_restart_mode restart_mode;
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bool rssi_unit_is_rx_samples; /* default unit is time */
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u32 rssi_delay;
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u32 rssi_wait;
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u32 rssi_duration;
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};
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struct rf_rssi {
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u32 ant; /* Antenna number for which RSSI is reported */
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u32 symbol; /* Runtime RSSI */
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u32 preamble; /* Initial RSSI */
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s32 multiplier; /* Multiplier to convert reported RSSI */
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u8 duration; /* Duration to be considered for measuring */
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};
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struct ad9361_rf_phy;
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struct ad9361_debugfs_entry {
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struct ad9361_rf_phy *phy;
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const char *propname;
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void *out_value;
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u32 val;
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u8 size;
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u8 cmd;
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};
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struct ad9361_dig_tune_data {
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u32 bist_loopback_mode;
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u32 bist_config;
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u32 ensm_state;
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u8 skip_mode;
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};
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struct refclk_scale {
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struct clk_hw hw;
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struct spi_device *spi;
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struct ad9361_rf_phy *phy;
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unsigned long rate;
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u32 mult;
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u32 div;
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enum ad9361_clocks source;
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};
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struct ad9361_rf_phy_state;
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struct ad9361_ext_band_ctl;
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struct ad9361_rf_phy {
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struct spi_device *spi;
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struct clk *clk_refin;
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struct clk *clk_ext_lo_rx;
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struct clk *clk_ext_lo_tx;
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struct clk *clks[NUM_AD9361_CLKS];
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struct notifier_block clk_nb_tx;
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struct notifier_block clk_nb_rx;
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struct refclk_scale clk_priv[NUM_AD9361_CLKS];
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struct clk_onecell_data clk_data;
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struct ad9361_phy_platform_data *pdata;
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struct ad9361_debugfs_entry debugfs_entry[182];
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struct bin_attribute bin;
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struct bin_attribute bin_gt;
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struct iio_dev *indio_dev;
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struct work_struct work;
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struct completion complete;
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struct gain_table_info *gt_info;
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char *bin_attr_buf;
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u32 ad9361_debugfs_entry_index;
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struct ad9361_ext_band_ctl *ext_band_ctl;
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struct ad9361_rf_phy_state *state;
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};
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int ad9361_ctrl_outs_setup(struct ad9361_rf_phy *phy, struct ctrl_outs_control *ctrl);
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int ad9361_clk_set_rate(struct clk *clk, unsigned long rate);
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int ad9361_rssi_setup(struct ad9361_rf_phy *phy,
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struct rssi_control *ctrl,
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bool is_update);
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int ad9361_read_rssi(struct ad9361_rf_phy *phy, struct rf_rssi *rssi);
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int ad9361_update_rf_bandwidth(struct ad9361_rf_phy *phy,u32 rf_rx_bw, u32 rf_tx_bw);
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ssize_t ad9361_dig_interface_timing_analysis(struct ad9361_rf_phy *phy,
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char *buf, unsigned buflen);
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int ad9361_hdl_loopback(struct ad9361_rf_phy *phy, bool enable);
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int ad9361_register_axi_converter(struct ad9361_rf_phy *phy);
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struct ad9361_rf_phy* ad9361_spi_to_phy(struct spi_device *spi);
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int ad9361_spi_read(struct spi_device *spi, u32 reg);
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int ad9361_spi_write(struct spi_device *spi, u32 reg, u32 val);
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int ad9361_bist_loopback(struct ad9361_rf_phy *phy, unsigned mode);
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int ad9361_bist_prbs(struct ad9361_rf_phy *phy, enum ad9361_bist_mode mode);
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int ad9361_find_opt(u8 *field, u32 size, u32 *ret_start);
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int ad9361_ensm_mode_disable_pinctrl(struct ad9361_rf_phy *phy);
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int ad9361_ensm_mode_restore_pinctrl(struct ad9361_rf_phy *phy);
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void ad9361_ensm_force_state(struct ad9361_rf_phy *phy, u8 ensm_state);
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void ad9361_ensm_restore_state(struct ad9361_rf_phy *phy, u8 ensm_state);
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void ad9361_ensm_restore_prev_state(struct ad9361_rf_phy *phy);
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int ad9361_set_trx_clock_chain_freq(struct ad9361_rf_phy *phy,
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unsigned long freq);
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int ad9361_set_trx_clock_chain_default(struct ad9361_rf_phy *phy);
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int ad9361_dig_tune(struct ad9361_rf_phy *phy, unsigned long max_freq,
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enum dig_tune_flags flags);
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int ad9361_tx_mute(struct ad9361_rf_phy *phy, u32 state);
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int ad9361_get_tx_atten(struct ad9361_rf_phy *phy, u32 tx_num);
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int ad9361_set_tx_atten(struct ad9361_rf_phy *phy, u32 atten_mdb, bool tx1, bool tx2, bool immed);
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int ad9361_write_bist_reg(struct ad9361_rf_phy *phy, u32 val);
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bool ad9361_uses_rx2tx2(struct ad9361_rf_phy *phy);
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int ad9361_get_dig_tune_data(struct ad9361_rf_phy *phy,
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struct ad9361_dig_tune_data *data);
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int ad9361_read_clock_data_delays(struct ad9361_rf_phy *phy);
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int ad9361_write_clock_data_delays(struct ad9361_rf_phy *phy);
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bool ad9361_uses_lvds_mode(struct ad9361_rf_phy *phy);
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int ad9361_set_rx_port(struct ad9361_rf_phy *phy, enum rx_port_sel sel);
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int ad9361_set_tx_port(struct ad9361_rf_phy *phy, enum tx_port_sel sel);
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#ifdef CONFIG_AD9361_EXT_BAND_CONTROL
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int ad9361_register_ext_band_control(struct ad9361_rf_phy *phy);
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int ad9361_adjust_rx_ext_band_settings(struct ad9361_rf_phy *phy, u64 freq);
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int ad9361_adjust_tx_ext_band_settings(struct ad9361_rf_phy *phy, u64 freq);
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void ad9361_unregister_ext_band_control(struct ad9361_rf_phy *phy);
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#else
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static inline int ad9361_register_ext_band_control(struct ad9361_rf_phy *phy)
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{
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return 0;
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}
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static inline int ad9361_adjust_rx_ext_band_settings(
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struct ad9361_rf_phy *phy, u64 freq)
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{
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return 0;
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}
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static inline int ad9361_adjust_tx_ext_band_settings(
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struct ad9361_rf_phy *phy, u64 freq)
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{
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return 0;
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}
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static inline void ad9361_unregister_ext_band_control(
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struct ad9361_rf_phy *phy)
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{}
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#endif
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#endif
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