9 Commits

Author	SHA1	Message	Date
Jiao Xianjun	d0d5556d26	Add FPGA internal loopback inline.	2023-06-08 12:04:57 +02:00
Xianjun Jiao	ca63c39f0d	While changing fft_win_shift 1-->0 not touching bit [9:4]: ... They are for equalizer monitor auto-rst: small_eq_out_counter_th	2023-02-09 16:12:16 +01:00
Xianjun Jiao	7eea29887a	Update docs for ADI kuiper (our notter release)	2023-01-26 17:11:46 +01:00
Wei.Li	a066622e35	Sdrpi (#211) ... Add sdrpi support	2022-09-02 16:36:38 +02:00
Jiao Xianjun	c6dd9e71e5	Update packet-iq-self-loopback-test.md	2022-06-29 08:28:27 +02:00
redfast00	b6f9140315	Fix instructions for self-loopback	2022-06-24 16:43:27 +02:00
Jiao Xianjun	05506cbaa0	pre trigger length 0 (wh11d0) goes into some coner case. ... Change it to more safe value > 0. (At least 1!)	2022-06-21 11:26:04 +02:00
Jiao Xianjun	dbcf06d18f	Update packet-iq-self-loopback-test.md	2022-03-22 16:24:20 +01:00
Jiao Xianjun	529690b6c1	Create packet-iq-self-loopback-test.md	2022-03-22 15:52:35 +01:00