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157 Commits 8 Branches 6 Tags 27 MiB
22dd0cc486
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4 Commits

Author SHA1 Message Date
Xianjun Jiao
22dd0cc486 the side channel (timestamp, frequency offset, CSI, equalizer) feature 2020-10-08 15:07:57 +02:00
Xianjun Jiao
838a9007cf update source coed of: 4 fpga queues and better driver/fpga flow control to avoid crash. improved slice cfg and printing 2020-06-12 10:50:34 +02:00
Xianjun Jiao
e63d1ec300 Jetmir: add tsf set command to sdrctl 2020-03-05 08:50:41 +01:00
Xianjun Jiao
2ee6717882 initial commit 2019-12-10 14:03:47 +01:00