Jiao Xianjun
ed343c37f8
Update publications.md
2021-10-15 15:24:48 +02:00
Jiao Xianjun
1682b23bf4
Clarify the command in csi.md
2021-10-14 15:36:06 +02:00
Jiao Xianjun
72c90e5e32
Merge pull request #104 from open-sdr/fix_large_ping_delay_igent
...
Fix the issue of iGent env related big ping delay:
2021-10-13 09:32:21 +02:00
Jiao Xianjun
bab95fd73b
Merge pull request #102 from open-sdr/sdrctl_lbt_th
...
Use drv_xpu register 0 for LBT threshold setting.
2021-10-04 16:39:11 +02:00
Xianjun Jiao
b60e485eb5
Fix the possible wrong last_auto_fpga_lbt_th saving:
...
1. Remove the last_auto_fpga_lbt_th saving from sdrctl set reg command. Otherwise, repeated sdrctl set reg will save wrong value into last_auto_fpga_lbt_th
2. The last_auto_fpga_lbt_th is only set in ad9361_rf_set_channel, which is called at least once by Linux after NIC is up
2021-10-04 09:59:43 +02:00
Xianjun Jiao
109b1cfd3a
Fix the issue of iGent env related big ping delay:
...
1. The issue only happens at zcu102 side, when it is tested as AP together with zedboard
2. The issue does not happen when zcu102 is client and zedboard is AP
3. The issue (most likely) does not happen in places other than iGent (like Pablo home)
4. Sometimes it does happen at my home when I test zcu102 as AP together with COTS WiFi
5. Indeed seems like the environment related. Guess some quick small packets in the environment quickly flush/round-up/mess-up the rx dma cyclic buffer, and the rx interrupt internal static variable target_buf_idx_old loses track of the background automatic rx dma cyclic buffer
6. The fix is for all board types (zcu102, zedboard, 7035, etc)
7. The driver compiling make_all.sh script generates USE_NEW_RX_INTERRUPT macro to pre_def.h to enable the new code (while keeping the old code). You can use the script as before.
8. The logic of the fix is that exhaustive search all the rx dma cyclic buffer in rx interrupt to get packet to Linux in the first place.
2021-09-29 16:52:45 +02:00
Xianjun Jiao
8598d2949d
Use drv_xpu register 0 for LBT threshold setting. 0 will enable FPGA threshold auto setting by ad9361_rf_set_channel() in sdr.c. Other value will set static threshold (that value) to FPGA
2021-09-28 21:52:31 +02:00
mmehari
f286042926
72113-files.zip: use local copy instead of downloading from internet
2021-09-28 16:34:07 +02:00
Jiao Xianjun
9cc49242a2
Update ap-client-two-sdr.md
2021-09-23 10:30:37 +02:00
Jiao Xianjun
dceb00f0c0
Update publications.md
2021-09-18 12:49:41 +02:00
Jiao Xianjun
bdd4523a7e
Update ad-hoc-two-sdr.md
2021-09-12 20:16:01 +02:00
Jiao Xianjun
a4f70eb810
Update ap-client-two-sdr.md
2021-09-12 20:15:47 +02:00
Jiao Xianjun
8e232f265b
Update ap-client-two-sdr.md
2021-09-12 20:14:57 +02:00
Jiao Xianjun
0fae09a874
Update README.md
2021-09-12 20:14:40 +02:00
Jiao Xianjun
a83823a4ba
Update ad-hoc-two-sdr.md
2021-09-12 20:10:25 +02:00
Jiao Xianjun
b58ec5b67e
Update ap-client-two-sdr.md
2021-09-12 17:31:24 +02:00
Jiao Xianjun
61bd473364
Create wpa-openwifi.conf
2021-09-12 17:17:37 +02:00
Jiao Xianjun
8df4d41bd6
Update publications.md
2021-09-12 13:35:45 +02:00
Jiao Xianjun
e7c0ebb78a
Update publications.md
2021-09-11 11:16:24 +02:00
Jiao Xianjun
28385c4fd7
Update videos.md
2021-09-11 11:05:38 +02:00
Jiao Xianjun
38a4802eae
Update SD card image for antsdr in README
...
Add antsdr devicetree.dtb and BOOT.BIN to the SD card image.
2021-09-02 21:18:26 +02:00
Jiao Xianjun
1469efb619
Merge pull request #96 from open-sdr/antsdr
...
Antsdr test is OK.
2021-09-02 21:15:03 +02:00
Jiao Xianjun
1ee5906a27
Update README.md
2021-09-02 12:17:33 +02:00
Jiao Xianjun
9e51933acf
Merge pull request #95 from open-sdr/antsdr_readme
...
Antsdr readme
2021-08-27 20:12:19 +02:00
Xianjun Jiao
a348227f20
add antsdr notes.md
2021-08-27 16:07:40 +02:00
Jiao Xianjun
f65d9fc830
Update README.md
...
for antsdr
2021-08-27 16:05:06 +02:00
Jiao Xianjun
a932eaa5dc
Merge pull request #93 from MicroPhase/antsdr
...
pull request point to the antsdr branch
2021-08-24 11:54:20 +02:00
MicroPhase
96a72425e7
Update get_fpga.sh
2021-08-24 11:17:53 +08:00
black-pigeon
d45655f234
the submodule uri keep the same with upstream
2021-08-24 11:14:33 +08:00
black-pigeon
c96d387068
change the uboot file, edit devicetree to add a status led support
2021-08-24 11:08:14 +08:00
Jiao Xianjun
5ef6df29e7
Update videos.md
2021-08-23 16:55:33 +02:00
black-pigeon
f057dd806f
add README file for antsdr
2021-08-18 15:57:14 +08:00
black-pigeon
0530334c7a
get_fpga.h is switch to branch antsdr instead of master
2021-08-13 17:57:55 +08:00
black-pigeon
64ff0923d1
retargert openwifi-hw submodule to MicroPhase repo
2021-08-13 11:13:29 +08:00
black-pigeon
ad0b112aa3
change openwifi-hw submodule url, add new sdr hardware antsdr-e310, add necessary modifications
2021-08-13 11:07:44 +08:00
black-pigeon
ac994fd7dc
change openwifi-hw submodule url, add new sdr hardware antsdr-e310, add necessary modifications
2021-08-13 11:06:39 +08:00
Jiao Xianjun
2742c7205f
Update issue-description.md
2021-07-16 11:53:21 +02:00
Jiao Xianjun
ae5998ce77
Update issue-description.md
2021-07-12 09:12:37 +02:00
Xianjun Jiao
eaaa3bfcfe
Improve the IQ sample Matlab script
...
For displaying and saving I/Q sample captured by openwifi side channel feature
2021-07-08 18:10:34 +02:00
Xianjun Jiao
b68f51fb20
format the cite info in publications.md
2021-07-08 18:07:21 +02:00
Jiao Xianjun
93b8d1639e
Update publications.md
2021-07-06 12:13:51 +02:00
Jiao Xianjun
41bbe142fd
Create cite-openwifi-github-code.md
2021-07-06 12:11:41 +02:00
Jiao Xianjun
50c96272b3
Put ACM paper link to CSI fuzzer app note.
2021-07-06 12:08:43 +02:00
Jiao Xianjun
d8545c1261
Update publications
2021-07-06 12:06:57 +02:00
Jiao Xianjun
3bd1e9ee68
Update issue-description.md
2021-06-25 10:50:57 +02:00
Jiao Xianjun
295aaf5443
Delete report-issue.md
2021-06-25 10:47:55 +02:00
Jiao Xianjun
d6c460e8d2
Merge pull request #78 from open-sdr/JiaoXianjun-patch-1
...
Update issue templates
2021-06-25 10:46:58 +02:00
Jiao Xianjun
6418e0cf18
Update issue templates
2021-06-25 10:46:32 +02:00
Jiao Xianjun
035b3a0430
Update csi_fuzzer.md
2021-06-22 09:36:24 +02:00
Xianjun Jiao
a86b7d6e01
update csi fuzzer picture
2021-06-18 19:52:24 +02:00
