From 31955e7fc8a1c23ac4c9a5d2e16a4e51bf47947d Mon Sep 17 00:00:00 2001 From: Jiao Xianjun Date: Sat, 12 Nov 2022 08:50:47 +0100 Subject: [PATCH 001/104] Update publications.md --- doc/publications.md | 1 + 1 file changed, 1 insertion(+) diff --git a/doc/publications.md b/doc/publications.md index 68a9db6..b84c590 100644 --- a/doc/publications.md +++ b/doc/publications.md @@ -33,6 +33,7 @@ Publications in category: - [Pablo Avila-Campos, et al. Beacon-Based Wireless TSN Association. 2022 IEEE INFOCOM](https://imec-publications.be/bitstream/handle/20.500.12860/40111/8126_acc.pdf?sequence=2) - [Pablo Avila-Campos, et al. Impactless Beacon-Based Wireless TSN Association Procedure. 2022 IEEE 18th International Conference on Factory Communication Systems (WFCS)](https://ieeexplore.ieee.org/abstract/document/9779186) - [Jetmir Haxhibeqiri, et al. Safety-related Applications over Wireless Time-Sensitive Networks. IEEE ETFA 2022](https://biblio.ugent.be/publication/8770625/file/8770627.pdf) +- [Pablo Avila-Campos, et al. Removing the Wires in Time-Sensitive Networks. 2022 61st FITCE International Congress Future Telecommunications: Infrastructure and Sustainability (FITCE)](https://ieeexplore.ieee.org/abstract/document/9934268) ## CSI Channel State Information and Security - [Marco Cominelli, et al. CSI MURDER. ORCA project opencall 2019](https://ans.unibs.it/projects/csi-murder/) From b147dfd1528021e018580b2fbcf1c7ed43239962 Mon Sep 17 00:00:00 2001 From: Jiao Xianjun Date: Sat, 26 Nov 2022 10:17:20 +0100 Subject: [PATCH 002/104] Update publications.md --- doc/publications.md | 1 + 1 file changed, 1 insertion(+) diff --git a/doc/publications.md b/doc/publications.md index b84c590..3f29d9b 100644 --- a/doc/publications.md +++ b/doc/publications.md @@ -34,6 +34,7 @@ Publications in category: - [Pablo Avila-Campos, et al. Impactless Beacon-Based Wireless TSN Association Procedure. 2022 IEEE 18th International Conference on Factory Communication Systems (WFCS)](https://ieeexplore.ieee.org/abstract/document/9779186) - [Jetmir Haxhibeqiri, et al. Safety-related Applications over Wireless Time-Sensitive Networks. IEEE ETFA 2022](https://biblio.ugent.be/publication/8770625/file/8770627.pdf) - [Pablo Avila-Campos, et al. Removing the Wires in Time-Sensitive Networks. 2022 61st FITCE International Congress Future Telecommunications: Infrastructure and Sustainability (FITCE)](https://ieeexplore.ieee.org/abstract/document/9934268) +- [Pablo Avila-Campos, et al. Periodic Control Traffic Support in a Wireless Time-Sensitive Network. 2022 13th International Conference on Network of the Future (NoF)](https://ieeexplore.ieee.org/document/9942586) ## CSI Channel State Information and Security - [Marco Cominelli, et al. CSI MURDER. ORCA project opencall 2019](https://ans.unibs.it/projects/csi-murder/) From eaf0cb68bbeae3a7ec36643fd0339680b0c1d791 Mon Sep 17 00:00:00 2001 From: Jiao Xianjun Date: Thu, 8 Dec 2022 15:58:43 +0100 Subject: [PATCH 003/104] Update publications.md --- doc/publications.md | 1 + 1 file changed, 1 insertion(+) diff --git a/doc/publications.md b/doc/publications.md index 3f29d9b..bed0146 100644 --- a/doc/publications.md +++ b/doc/publications.md @@ -20,6 +20,7 @@ Publications in category: - [Luca Baldesi, et al. ChARM: NextG Spectrum Sharing Through Data-Driven Real-Time O-RAN Dynamic Control. INFOCOM 2022](https://ece.northeastern.edu/wineslab/papers/BaldesiInfocom22.pdf) - [Thijs Havinga, et al. WIP: Achieving Self-Interference-Free Operation on SDR Platform with Critical TDD Turnaround Time. accepted WoWMoM2022 paper](https://arxiv.org/abs/2204.07354) - [Yingshuo Xi, Baiming Zhang. High-Throughput Open Source Viterbi Decoder for OpenWiFi. 2022 KU Leuven master thesis](https://github.com/BaimingZhang26213/viterbi_decoder) +- [Merkebu Girmay, et al. Technology recognition and traffic characterization for wireless technologies in ITS band. Vehicular Communications Volume 39, February 2023, 100563](https://doi.org/10.1016/j.vehcom.2022.100563) ## TSN Time Sensitive Network and RT Real Time - [Jetmir Haxhibeqiri, et al. Enabling TSN over IEEE 802.11: Low-overhead Time Synchronization for Wi-Fi Clients. ICIT2021](https://biblio.ugent.be/publication/8700714/file/8700715.pdf) From 9d2c75f1e11871ddef09f5e01a445cb0c1efef56 Mon Sep 17 00:00:00 2001 From: Jiao Xianjun Date: Fri, 16 Dec 2022 13:10:38 +0100 Subject: [PATCH 004/104] Update publications.md --- doc/publications.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/publications.md b/doc/publications.md index bed0146..cae33d1 100644 --- a/doc/publications.md +++ b/doc/publications.md @@ -27,7 +27,7 @@ Publications in category: - [Ingrid Moerman, et al. Wireless Time-Sensitive Networks: When Every Microsecond Counts. Microwaves&RF, 2021](https://www.mwrf.com/technologies/systems/article/21164984/wireless-timesensitive-networks-when-every-microsecond-counts) - [Muhammad Aslam, et al. High precision time synchronization on Wi-Fi based multi-hop network. CNERT2021](https://biblio.ugent.be/publication/8709058/file/8709060.pdf) - [Ingrid Moerman, et al. Interoperable Time-Sensitive Networking Towards 6G (invited presentation)](https://biblio.ugent.be/publication/8719532/file/8719533.pdf) -- [Lihao Zhang, et al. A Just-In-Time Networking Framework for Minimizing Request-Response Latency of Wireless Time-Sensitive Applications. Arxiv 2021](https://arxiv.org/abs/2109.03032) +- [Lihao Zhang, et al. A Just-In-Time Networking Framework for Minimizing Request-Response Latency of Wireless Time-Sensitive Applications. Arxiv 2021. Accepted by IEEE IoT journal 2022.](https://arxiv.org/abs/2109.03032) - [Jetmir Haxhibeqiri, et al. Bringing Time-Sensitive Networking to Wireless Professional Private Networks. Wireless Personal Communications 2021](https://link.springer.com/article/10.1007/s11277-021-09056-0) - [Muhammad Aslam, et al. Hardware Efficient Clock Synchronization across Wi-Fi and Ethernet Based Network Using PTP. IEEE Transactions on Industrial Informatics 2021](https://ieeexplore.ieee.org/document/9573364) - [Zelin Yun, et al. RT-WiFi on Software-Defined Radio: Design and Implementation. accepted RTAS2022 paper and demo](https://arxiv.org/abs/2203.10390) From efa47b29f6d5d373a45064351dbcfb7ff5720ddb Mon Sep 17 00:00:00 2001 From: Xianjun Jiao Date: Tue, 10 Jan 2023 16:05:33 +0100 Subject: [PATCH 005/104] Update document and script for antsdr_e200 --- README.md | 1 + kernel_boot/build_boot_bin.sh | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/README.md b/README.md index 4510d0d..0945b63 100644 --- a/README.md +++ b/README.md @@ -55,6 +55,7 @@ adrv9364z7020|[ADRV9364-Z7020 + ADRV1CRR-BOB](https://www.analog.com/en/design-c adrv9361z7035|[ADRV9361-Z7035 + ADRV1CRR-BOB/FMC](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/ADRV9361-Z7035.html)|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.3.1-wilsele-1-32bit.img.xz)|Need zc702_fmcs2|[Xilinx ZC702 board](https://www.xilinx.com/products/boards-and-kits/ek-z7-zc702-g.html) + [FMCOMMS2/3/4](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad-fmcomms2.html)|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.3.1-wilsele-1-32bit.img.xz)|**NO** need antsdr|[MicroPhase](https://github.com/MicroPhase/) enhanced ADALM-PLUTO [Notes](kernel_boot/boards/antsdr/notes.md)|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.3.1-wilsele-1-32bit.img.xz)|**NO** need +antsdr_e200|[MicroPhase](https://github.com/MicroPhase/) enhanced ADALM-PLUTO [Notes](kernel_boot/boards/antsdr_e200/README.md)|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.3.1-wilsele-1-32bit.img.xz)|**NO** need sdrpi|[HexSDR](https://github.com/HexSDR/) Powerful SDR in Raspberry Pi size [Notes](kernel_boot/boards/sdrpi/notes.md)|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.3.1-wilsele-1-32bit.img.xz)|**NO** need zcu102_fmcs2|[Xilinx ZCU102 board](https://www.xilinx.com/products/boards-and-kits/ek-u1-zcu102-g.html) + [FMCOMMS2/3/4](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad-fmcomms2.html)|Done|[64bit img](https://users.ugent.be/~xjiao/openwifi-1.3.1-wilsele-64bit.img.xz)|Need zcu102_9371|[Xilinx ZCU102 board](https://www.xilinx.com/products/boards-and-kits/ek-u1-zcu102-g.html) + [ADRV9371](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-adrv9371.html)|Future|Future|Need diff --git a/kernel_boot/build_boot_bin.sh b/kernel_boot/build_boot_bin.sh index 4639167..9a9a581 100755 --- a/kernel_boot/build_boot_bin.sh +++ b/kernel_boot/build_boot_bin.sh @@ -7,7 +7,7 @@ if [ "$#" -ne 2 ]; then echo "You must enter the \$OPENWIFI_HW_DIR \$BOARD_NAME as argument" - echo "BOARD_NAME Like: sdrpi antsdr adrv9364z7020 adrv9361z7035 zc706_fmcs2 zed_fmcs2 zc702_fmcs2 zcu102_fmcs2 zcu102_9371" + echo "BOARD_NAME Like: sdrpi antsdr_e200 antsdr adrv9364z7020 adrv9361z7035 zc706_fmcs2 zed_fmcs2 zc702_fmcs2 zcu102_fmcs2 zcu102_9371" exit 1 fi From c0371e3594513c00c51dfbb073a9295564844441 Mon Sep 17 00:00:00 2001 From: thavinga Date: Tue, 10 Jan 2023 16:16:08 +0100 Subject: [PATCH 006/104] Add script to read RSSI from AD9361 --- user_space/rssi_show.sh | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100755 user_space/rssi_show.sh diff --git a/user_space/rssi_show.sh b/user_space/rssi_show.sh new file mode 100755 index 0000000..9d181fd --- /dev/null +++ b/user_space/rssi_show.sh @@ -0,0 +1,36 @@ +#!/bin/bash + +# Reads RSSI in dB from RX1, let's call it "r". +# Linear fit offset "o" depends on frequency (2.4GHz or 5GHz and FMCOMMS2/3). +# RSSI(dBm) = -r + o +# 2.4GHz FMCOMMS2: o = 16.74 +# 2.4GHz FMCOMMS3: o = 17.44 +# 5GHz FMCOMMS2: o = 25.41 +# 5GHz FMCOMMS3: o = 24.58 + +home_dir=$(pwd) + +set -x +if test -f "/sys/bus/iio/devices/iio:device0/in_voltage0_rssi"; then + cd /sys/bus/iio/devices/iio:device0/ +else if test -f "/sys/bus/iio/devices/iio:device1/in_voltage0_rssi"; then + cd /sys/bus/iio/devices/iio:device1/ + else if test -f "/sys/bus/iio/devices/iio:device2/in_voltage0_rssi"; then + cd /sys/bus/iio/devices/iio:device2/ + else if test -f "/sys/bus/iio/devices/iio:device3/in_voltage0_rssi"; then + cd /sys/bus/iio/devices/iio:device3/ + else if test -f "/sys/bus/iio/devices/iio:device4/in_voltage0_rssi"; then + cd /sys/bus/iio/devices/iio:device4/ + else + echo "Can not find in_voltage_rf_bandwidth!" + echo "Check log to make sure ad9361 driver is loaded!" + exit 1 + fi + fi + fi + fi +fi +set +x + +cat in_voltage0_rssi +cd $home_dir From 0410b1af1aecf038665d1003e93fa77e09aeb735 Mon Sep 17 00:00:00 2001 From: Xianjun Jiao Date: Wed, 19 Oct 2022 22:18:57 +0200 Subject: [PATCH 007/104] Add neptunesdr files --- kernel_boot/boards/neptunesdr/devicetree.dtb | Bin 0 -> 19680 bytes kernel_boot/boards/neptunesdr/devicetree.dts | 889 +++++++++++++++++++ kernel_boot/boards/neptunesdr/u-boot.elf | Bin 0 -> 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z&Y@kuN9_pTE>2hLh!VKpfcewz^lI+PDhLq>C516iSyha^I0izP$Ek;#v@MKaTQ)-M z<)d&OLOjNBU}(26H?|lw>f>~~RgKSw*%IzJ^omIyjxih}3OKA`JfZbal2p=KHtiS{ z_)5YZc^JToGRy>bM;*XzO7&+DYU9HdUQxxdg#p(;*96qLwMvP$iT2g zeTaml_4OLf*eNhr%z~!35^@faUVS@pw>J>^u^m4@xpEi}4=SNm(DGW}6 zYT~RE5WS>K=_wAtC8>+`3q-}yII`5Wu-TGYJ-Cb%*6gUnWy9MjlxA=thPps;N{2&! zl~w7c29#OD4%!LEq18{-*!buRpObh{1CBQhF-ptS6){RgTgRD1Y&0DYn^+QUyZF4S zQtEaTDx8~BmAJzYMnkCRGB~kFz%Eior&e1UTow0fa?oS{JPQO~6>? zqXLTuFLsg%ZgN15wK~^plfso{oD=}LE{HvJLI+>qyL!{YtPFja^|1+vSFq1P3nL87 zLU%iJaQV$Ou34zAP>k@pkEB_gxr?+8684!g_N4?*w^;J6?&-W40*i=G+f`9bx zMcw*iC##$$AcpREg1tpCQXc>m*g;`1#G=(g;-0|<)z6&pGYDaULsy=lVa*xjHkB!t m9Y@tpY$JTwonW2M_@ChaIE7j0mD)O=J1Di^R9gbsHvccrrHrfq literal 0 HcmV?d00001 diff --git a/kernel_boot/boards/neptunesdr/devicetree.dts b/kernel_boot/boards/neptunesdr/devicetree.dts new file mode 100644 index 0000000..7d14278 --- /dev/null +++ b/kernel_boot/boards/neptunesdr/devicetree.dts @@ -0,0 +1,889 @@ +/dts-v1/; + +/ { + #address-cells = <0x01>; + #size-cells = <0x01>; + compatible = "xlnx,zynq-7000"; + interrupt-parent = <0x01>; + model = "Analog Devices ADRV9364-Z7020 (Z7020/AD9364)"; + + cpus { + #address-cells = <0x01>; + #size-cells = <0x00>; + + cpu@0 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0x00>; + clocks = <0x02 0x03>; + clock-latency = <0x3e8>; + cpu0-supply = <0x03>; + operating-points = <0xa2c2b 0xf4240 0x51616 0xf4240>; + }; + + cpu@1 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0x01>; + clocks = <0x02 0x03>; + }; + }; + + fpga-full { + compatible = "fpga-region"; + fpga-mgr = <0x04>; + #address-cells = <0x01>; + #size-cells = <0x01>; + ranges; + }; + + pmu@f8891000 { + compatible = "arm,cortex-a9-pmu"; + interrupts = <0x00 0x05 0x04 0x00 0x06 0x04>; + interrupt-parent = <0x01>; + reg = <0xf8891000 0x1000 0xf8893000 0x1000>; + }; + + fixedregulator { + compatible = "regulator-fixed"; + regulator-name = "VCCPINT"; + regulator-min-microvolt = <0xf4240>; + regulator-max-microvolt = <0xf4240>; + regulator-boot-on; + regulator-always-on; + linux,phandle = <0x03>; + phandle = <0x03>; + }; + + amba { + u-boot,dm-pre-reloc; + compatible = "simple-bus"; + #address-cells = <0x01>; + #size-cells = <0x01>; + interrupt-parent = <0x01>; + ranges; + + adc@f8007100 { + compatible = "xlnx,zynq-xadc-1.00.a"; + reg = <0xf8007100 0x20>; + interrupts = <0x00 0x07 0x04>; + interrupt-parent = <0x01>; + clocks = <0x02 0x0c>; + }; + + can@e0008000 { + compatible = "xlnx,zynq-can-1.0"; + status = "disabled"; + clocks = <0x02 0x13 0x02 0x24>; + clock-names = "can_clk\0pclk"; + reg = <0xe0008000 0x1000>; + interrupts = <0x00 0x1c 0x04>; + interrupt-parent = <0x01>; + tx-fifo-depth = <0x40>; + rx-fifo-depth = <0x40>; + }; + + can@e0009000 { + compatible = "xlnx,zynq-can-1.0"; + status = "disabled"; + clocks = <0x02 0x14 0x02 0x25>; + clock-names = "can_clk\0pclk"; + reg = <0xe0009000 0x1000>; + interrupts = <0x00 0x33 0x04>; + interrupt-parent = <0x01>; + tx-fifo-depth = <0x40>; + rx-fifo-depth = <0x40>; + }; + + gpio@e000a000 { + compatible = "xlnx,zynq-gpio-1.0"; + #gpio-cells = <0x02>; + clocks = <0x02 0x2a>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <0x02>; + interrupt-parent = <0x01>; + interrupts = <0x00 0x14 0x04>; + reg = <0xe000a000 0x1000>; + linux,phandle = <0x06>; + phandle = <0x06>; + }; + + i2c@e0004000 { + compatible = "cdns,i2c-r1p10"; + status = "disabled"; + clocks = <0x02 0x26>; + interrupt-parent = <0x01>; + interrupts = <0x00 0x19 0x04>; + reg = <0xe0004000 0x1000>; + #address-cells = <0x01>; + #size-cells = <0x00>; + }; + + i2c@e0005000 { + compatible = "cdns,i2c-r1p10"; + status = "disabled"; + clocks = <0x02 0x27>; + interrupt-parent = <0x01>; + interrupts = <0x00 0x30 0x04>; + reg = <0xe0005000 0x1000>; + #address-cells = <0x01>; + #size-cells = <0x00>; + }; + + interrupt-controller@f8f01000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <0x03>; + interrupt-controller; + reg = <0xf8f01000 0x1000 0xf8f00100 0x100>; + linux,phandle = <0x01>; + phandle = <0x01>; + }; + + cache-controller@f8f02000 { + compatible = "arm,pl310-cache"; + reg = <0xf8f02000 0x1000>; + interrupts = <0x00 0x02 0x04>; + arm,data-latency = <0x03 0x02 0x02>; + arm,tag-latency = <0x02 0x02 0x02>; + cache-unified; + cache-level = <0x02>; + }; + + memory-controller@f8006000 { + compatible = "xlnx,zynq-ddrc-a05"; + reg = <0xf8006000 0x1000>; + }; + + ocmc@f800c000 { + compatible = "xlnx,zynq-ocmc-1.0"; + interrupt-parent = <0x01>; + interrupts = <0x00 0x03 0x04>; + reg = <0xf800c000 0x1000>; + }; + + serial@e0000000 { + compatible = "xlnx,xuartps\0cdns,uart-r1p8"; + status = "disabled"; + clocks = <0x02 0x17 0x02 0x28>; + clock-names = "uart_clk\0pclk"; + reg = <0xe0000000 0x1000>; + interrupts = <0x00 0x1b 0x04>; + }; + + serial@e0001000 { + compatible = "xlnx,xuartps\0cdns,uart-r1p8"; + status = "okay"; + clocks = <0x02 0x18 0x02 0x29>; + clock-names = "uart_clk\0pclk"; + reg = <0xe0001000 0x1000>; + interrupts = <0x00 0x32 0x04>; + }; + + spi@e0006000 { + compatible = "xlnx,zynq-spi-r1p6"; + reg = <0xe0006000 0x1000>; + status = "okay"; + interrupt-parent = <0x01>; + interrupts = <0x00 0x1a 0x04>; + clocks = <0x02 0x19 0x02 0x22>; + clock-names = "ref_clk\0pclk"; + #address-cells = <0x01>; + #size-cells = <0x00>; + + ad9361-phy@0 { + #address-cells = <0x01>; + #size-cells = <0x00>; + #clock-cells = <0x01>; + compatible = "adi,ad9361"; + reg = <0x00>; + spi-cpha; + spi-max-frequency = <0x989680>; + clocks = <0x05 0x00>; + clock-names = "ad9364_ext_refclk"; + clock-output-names = "rx_sampl_clk\0tx_sampl_clk"; + adi,digital-interface-tune-skip-mode = <0x00>; + adi,pp-tx-swap-enable; + adi,pp-rx-swap-enable; + adi,rx-frame-pulse-mode-enable; + adi,lvds-mode-enable; + adi,lvds-bias-mV = <0x96>; + adi,lvds-rx-onchip-termination-enable; + adi,rx-data-delay = <0x04>; + adi,tx-fb-clock-delay = <0x07>; + adi,xo-disable-use-ext-refclk-enable; + adi,2rx-2tx-mode-enable; + adi,frequency-division-duplex-mode-enable; + adi,rx-rf-port-input-select = <0x00>; + adi,tx-rf-port-input-select = <0x00>; + adi,tx-attenuation-mdB = <0x2710>; + adi,tx-lo-powerdown-managed-enable; + adi,rf-rx-bandwidth-hz = <0x112a880>; + adi,rf-tx-bandwidth-hz = <0x112a880>; + adi,rx-synthesizer-frequency-hz = <0x00 0x8f0d1800>; + adi,tx-synthesizer-frequency-hz = <0x00 0x92080880>; + adi,rx-path-clock-frequencies = <0x3a980000 0xea60000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>; + adi,tx-path-clock-frequencies = <0x3a980000 0x7530000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>; + adi,gc-rx1-mode = <0x02>; + adi,gc-rx2-mode = <0x02>; + adi,gc-adc-ovr-sample-size = <0x04>; + adi,gc-adc-small-overload-thresh = <0x2f>; + adi,gc-adc-large-overload-thresh = <0x3a>; + adi,gc-lmt-overload-high-thresh = <0x320>; + adi,gc-lmt-overload-low-thresh = <0x2c0>; + adi,gc-dec-pow-measurement-duration = <0x2000>; + adi,gc-low-power-thresh = <0x18>; + adi,mgc-inc-gain-step = <0x02>; + adi,mgc-dec-gain-step = <0x02>; + adi,mgc-split-table-ctrl-inp-gain-mode = <0x00>; + adi,agc-attack-delay-extra-margin-us = <0x01>; + adi,agc-outer-thresh-high = <0x05>; + adi,agc-outer-thresh-high-dec-steps = <0x02>; + adi,agc-inner-thresh-high = <0x0a>; + adi,agc-inner-thresh-high-dec-steps = <0x01>; + adi,agc-inner-thresh-low = <0x0c>; + adi,agc-inner-thresh-low-inc-steps = <0x01>; + adi,agc-outer-thresh-low = <0x12>; + adi,agc-outer-thresh-low-inc-steps = <0x02>; + adi,agc-adc-small-overload-exceed-counter = <0x0a>; + adi,agc-adc-large-overload-exceed-counter = <0x0a>; + adi,agc-adc-large-overload-inc-steps = <0x02>; + adi,agc-lmt-overload-large-exceed-counter = <0x0a>; + adi,agc-lmt-overload-small-exceed-counter = <0x0a>; + adi,agc-lmt-overload-large-inc-steps = <0x02>; + adi,agc-gain-update-interval-us = <0x3e8>; + adi,fagc-dec-pow-measurement-duration = <0x40>; + adi,fagc-lp-thresh-increment-steps = <0x01>; + adi,fagc-lp-thresh-increment-time = <0x05>; + adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <0x08>; + adi,fagc-final-overrange-count = <0x03>; + adi,fagc-gain-index-type-after-exit-rx-mode = <0x00>; + adi,fagc-lmt-final-settling-steps = <0x01>; + adi,fagc-lock-level = <0x0a>; + adi,fagc-lock-level-gain-increase-upper-limit = <0x05>; + adi,fagc-lock-level-lmt-gain-increase-enable; + adi,fagc-lpf-final-settling-steps = <0x01>; + adi,fagc-optimized-gain-offset = <0x05>; + adi,fagc-power-measurement-duration-in-state5 = <0x40>; + adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable; + adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <0x0a>; + adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable; + adi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0x00>; + adi,fagc-rst-gla-large-adc-overload-enable; + adi,fagc-rst-gla-large-lmt-overload-enable; + adi,fagc-rst-gla-stronger-sig-thresh-above-ll = <0x0a>; + adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable; + adi,fagc-state-wait-time-ns = <0x104>; + adi,fagc-use-last-lock-level-for-set-gain-enable; + adi,rssi-restart-mode = <0x03>; + adi,rssi-delay = <0x01>; + adi,rssi-wait = <0x01>; + adi,rssi-duration = <0x3e8>; + adi,ctrl-outs-index = <0x00>; + adi,ctrl-outs-enable-mask = <0xff>; + adi,temp-sense-measurement-interval-ms = <0x3e8>; + adi,temp-sense-offset-signed = <0xce>; + adi,temp-sense-periodic-measurement-enable; + adi,aux-dac-manual-mode-enable; + adi,aux-dac1-default-value-mV = <0x00>; + adi,aux-dac1-rx-delay-us = <0x00>; + adi,aux-dac1-tx-delay-us = <0x00>; + adi,aux-dac2-default-value-mV = <0x00>; + adi,aux-dac2-rx-delay-us = <0x00>; + adi,aux-dac2-tx-delay-us = <0x00>; + en_agc-gpios = <0x06 0x62 0x00>; + sync-gpios = <0x06 0x63 0x00>; + reset-gpios = <0x06 0x64 0x00>; + enable-gpios = <0x06 0x65 0x00>; + txnrx-gpios = <0x06 0x66 0x00>; + linux,phandle = <0x0b>; + phandle = <0x0b>; + }; + }; + + spi@e0007000 { + compatible = "xlnx,zynq-spi-r1p6"; + reg = <0xe0007000 0x1000>; + status = "disabled"; + interrupt-parent = <0x01>; + interrupts = <0x00 0x31 0x04>; + clocks = <0x02 0x1a 0x02 0x23>; + clock-names = "ref_clk\0pclk"; + #address-cells = <0x01>; + #size-cells = <0x00>; + }; + + spi@e000d000 { + clock-names = "ref_clk\0pclk"; + clocks = <0x02 0x0a 0x02 0x2b>; + compatible = "xlnx,zynq-qspi-1.0"; + status = "okay"; + interrupt-parent = <0x01>; + interrupts = <0x00 0x13 0x04>; + reg = <0xe000d000 0x1000>; + #address-cells = <0x01>; + #size-cells = <0x00>; + is-dual = <0x00>; + num-cs = <0x01>; + + ps7-qspi@0 { + #address-cells = <0x01>; + #size-cells = <0x01>; + spi-tx-bus-width = <0x01>; + spi-rx-bus-width = <0x04>; + compatible = "n25q256a\0jedec,spi-nor"; + reg = <0x00>; + spi-max-frequency = <0x2faf080>; + + partition@qspi-fsbl-uboot { + label = "qspi-fsbl-uboot"; + reg = <0x00 0xe0000>; + }; + + partition@qspi-uboot-env { + label = "qspi-uboot-env"; + reg = <0xe0000 0x20000>; + }; + + partition@qspi-linux { + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + + partition@qspi-device-tree { + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + + partition@qspi-rootfs { + label = "qspi-rootfs"; + reg = <0x620000 0xce0000>; + }; + + partition@qspi-bitstream { + label = "qspi-bitstream"; + reg = <0x1300000 0xd00000>; + }; + }; + }; + + memory-controller@e000e000 { + #address-cells = <0x01>; + #size-cells = <0x01>; + status = "disabled"; + clock-names = "memclk\0aclk"; + clocks = <0x02 0x0b 0x02 0x2c>; + compatible = "arm,pl353-smc-r2p1"; + interrupt-parent = <0x01>; + interrupts = <0x00 0x12 0x04>; + ranges; + reg = <0xe000e000 0x1000>; + + flash@e1000000 { + status = "disabled"; + compatible = "arm,pl353-nand-r2p1"; + reg = <0xe1000000 0x1000000>; + #address-cells = <0x01>; + #size-cells = <0x01>; + }; + + flash@e2000000 { + status = "disabled"; + compatible = "cfi-flash"; + reg = <0xe2000000 0x2000000>; + #address-cells = <0x01>; + #size-cells = <0x01>; + }; + }; + + ethernet@e000b000 { + compatible = "cdns,zynq-gem\0cdns,gem"; + reg = <0xe000b000 0x1000>; + status = "okay"; + interrupts = <0x00 0x16 0x04>; + clocks = <0x02 0x1e 0x02 0x1e 0x02 0x0d>; + clock-names = "pclk\0hclk\0tx_clk"; + #address-cells = <0x01>; + #size-cells = <0x00>; + phy-handle = <0x07>; + phy-mode = "rgmii-id"; + + phy@0 { + device_type = "ethernet-phy"; + reg = <0x00>; + marvell,reg-init = <0x03 0x10 0xff00 0x1e 0x03 0x11 0xfff0 0x00>; + linux,phandle = <0x07>; + phandle = <0x07>; + }; + }; + + ethernet@e000c000 { + compatible = "cdns,zynq-gem\0cdns,gem"; + reg = <0xe000c000 0x1000>; + status = "disabled"; + interrupts = <0x00 0x2d 0x04>; + clocks = <0x02 0x1f 0x02 0x1f 0x02 0x0e>; + clock-names = "pclk\0hclk\0tx_clk"; + #address-cells = <0x01>; + #size-cells = <0x00>; + }; + + mmc@e0100000 { + compatible = "arasan,sdhci-8.9a"; + status = "okay"; + clock-names = "clk_xin\0clk_ahb"; + clocks = <0x02 0x15 0x02 0x20>; + interrupt-parent = <0x01>; + interrupts = <0x00 0x18 0x04>; + reg = <0xe0100000 0x1000>; + disable-wp; + }; + + mmc@e0101000 { + compatible = "arasan,sdhci-8.9a"; + status = "disabled"; + clock-names = "clk_xin\0clk_ahb"; + clocks = <0x02 0x16 0x02 0x21>; + interrupt-parent = <0x01>; + interrupts = <0x00 0x2f 0x04>; + reg = <0xe0101000 0x1000>; + }; + + slcr@f8000000 { + u-boot,dm-pre-reloc; + #address-cells = <0x01>; + #size-cells = <0x01>; + compatible = "xlnx,zynq-slcr\0syscon\0simple-mfd"; + reg = <0xf8000000 0x1000>; + ranges; + linux,phandle = <0x08>; + phandle = <0x08>; + + clkc@100 { + u-boot,dm-pre-reloc; + #clock-cells = <0x01>; + compatible = "xlnx,ps7-clkc"; + fclk-enable = <0x0f>; + clock-output-names = "armpll\0ddrpll\0iopll\0cpu_6or4x\0cpu_3or2x\0cpu_2x\0cpu_1x\0ddr2x\0ddr3x\0dci\0lqspi\0smc\0pcap\0gem0\0gem1\0fclk0\0fclk1\0fclk2\0fclk3\0can0\0can1\0sdio0\0sdio1\0uart0\0uart1\0spi0\0spi1\0dma\0usb0_aper\0usb1_aper\0gem0_aper\0gem1_aper\0sdio0_aper\0sdio1_aper\0spi0_aper\0spi1_aper\0can0_aper\0can1_aper\0i2c0_aper\0i2c1_aper\0uart0_aper\0uart1_aper\0gpio_aper\0lqspi_aper\0smc_aper\0swdt\0dbg_trc\0dbg_apb"; + reg = <0x100 0x100>; + ps-clk-frequency = <0x1fca055>; + linux,phandle = <0x02>; + phandle = <0x02>; + }; + + rstc@200 { + compatible = "xlnx,zynq-reset"; + reg = <0x200 0x48>; + #reset-cells = <0x01>; + syscon = <0x08>; + }; + + pinctrl@700 { + compatible = "xlnx,pinctrl-zynq"; + reg = <0x700 0x200>; + syscon = <0x08>; + }; + }; + + dmac@f8003000 { + compatible = "arm,pl330\0arm,primecell"; + reg = <0xf8003000 0x1000>; + interrupt-parent = <0x01>; + interrupt-names = "abort\0dma0\0dma1\0dma2\0dma3\0dma4\0dma5\0dma6\0dma7"; + interrupts = <0x00 0x0d 0x04 0x00 0x0e 0x04 0x00 0x0f 0x04 0x00 0x10 0x04 0x00 0x11 0x04 0x00 0x28 0x04 0x00 0x29 0x04 0x00 0x2a 0x04 0x00 0x2b 0x04>; + #dma-cells = <0x01>; + #dma-channels = <0x08>; + #dma-requests = <0x04>; + clocks = <0x02 0x1b>; + clock-names = "apb_pclk"; + }; + + devcfg@f8007000 { + compatible = "xlnx,zynq-devcfg-1.0"; + interrupt-parent = <0x01>; + interrupts = <0x00 0x08 0x04>; + reg = <0xf8007000 0x100>; + clocks = <0x02 0x0c 0x02 0x0f 0x02 0x10 0x02 0x11 0x02 0x12>; + clock-names = "ref_clk\0fclk0\0fclk1\0fclk2\0fclk3"; + syscon = <0x08>; + linux,phandle = <0x04>; + phandle = <0x04>; + }; + + efuse@f800d000 { + compatible = "xlnx,zynq-efuse"; + reg = <0xf800d000 0x20>; + }; + + timer@f8f00200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0xf8f00200 0x20>; + interrupts = <0x01 0x0b 0x301>; + interrupt-parent = <0x01>; + clocks = <0x02 0x04>; + }; + + timer@f8001000 { + interrupt-parent = <0x01>; + interrupts = <0x00 0x0a 0x04 0x00 0x0b 0x04 0x00 0x0c 0x04>; + compatible = "cdns,ttc"; + clocks = <0x02 0x06>; + reg = <0xf8001000 0x1000>; + }; + + timer@f8002000 { + interrupt-parent = <0x01>; + interrupts = <0x00 0x25 0x04 0x00 0x26 0x04 0x00 0x27 0x04>; + compatible = "cdns,ttc"; + clocks = <0x02 0x06>; + reg = <0xf8002000 0x1000>; + }; + + timer@f8f00600 { + interrupt-parent = <0x01>; + interrupts = <0x01 0x0d 0x301>; + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xf8f00600 0x20>; + clocks = <0x02 0x04>; + }; + + usb@e0002000 { + compatible = "xlnx,zynq-usb-2.20a\0chipidea,usb2"; + status = "okay"; + clocks = <0x02 0x1c>; + interrupt-parent = <0x01>; + interrupts = <0x00 0x15 0x04>; + reg = <0xe0002000 0x1000>; + phy_type = "ulpi"; + dr_mode = "host"; + xlnx,phy-reset-gpio = <0x06 0x07 0x00>; + }; + + usb@e0003000 { + compatible = "xlnx,zynq-usb-2.20a\0chipidea,usb2"; + status = "disabled"; + clocks = <0x02 0x1d>; + interrupt-parent = <0x01>; + interrupts = <0x00 0x2c 0x04>; + reg = <0xe0003000 0x1000>; + phy_type = "ulpi"; + }; + + watchdog@f8005000 { + clocks = <0x02 0x2d>; + compatible = "cdns,wdt-r1p2"; + interrupt-parent = <0x01>; + interrupts = <0x00 0x09 0x01>; + reg = <0xf8005000 0x1000>; + timeout-sec = <0x0a>; + }; + }; + + aliases { + ethernet0 = "/amba/ethernet@e000b000"; + serial0 = "/amba/serial@e0001000"; + }; + + memory { + device_type = "memory"; + reg = <0x00 0x40000000>; + }; + + chosen { + linux,stdout-path = "/amba@0/uart@E0001000"; + }; + + clocks { + + clock@0 { + #clock-cells = <0x00>; + compatible = "adjustable-clock"; + clock-frequency = <0x2625a00>; + clock-accuracy = <0x30d40>; + clock-output-names = "ad9364_ext_refclk"; + linux,phandle = <0x05>; + phandle = <0x05>; + }; + + clock@1 { + #clock-cells = <0x00>; + compatible = "fixed-clock"; + clock-frequency = <0x16e3600>; + clock-output-names = "24MHz"; + linux,phandle = <0x09>; + phandle = <0x09>; + }; + }; + + usb-ulpi-gpio-gate@0 { + compatible = "gpio-gate-clock"; + clocks = <0x09>; + #clock-cells = <0x00>; + enable-gpios = <0x06 0x09 0x01>; + }; + + fpga-axi@0 { + compatible = "simple-bus"; + #address-cells = <0x01>; + #size-cells = <0x01>; + ranges; + + i2c@41600000 { + compatible = "xlnx,axi-iic-1.02.a\0xlnx,xps-iic-2.00.a"; + reg = <0x41600000 0x10000>; + interrupt-parent = <0x01>; + interrupts = <0x00 0x3a 0x04>; + clocks = <0x02 0x0f>; + clock-names = "pclk"; + #address-cells = <0x01>; + #size-cells = <0x00>; + + ad7291@20 { + compatible = "adi,ad7291"; + reg = <0x20>; + }; + + ad7291-bob@2C { + compatible = "adi,ad7291"; + reg = <0x2c>; + }; + + eeprom@50 { + compatible = "at24,24c32"; + reg = <0x50>; + }; + }; + + sdr { + compatible = "sdr,sdr"; + dmas = <0x0a 0x01 0x0c 0x00>; + dma-names = "rx_dma_s2mm\0tx_dma_mm2s"; + interrupt-names = "not_valid_anymore\0rx_pkt_intr\0tx_itrpt"; + interrupt-parent = <0x01>; + interrupts = <0x00 0x1d 0x01 0x00 0x1e 0x01 0x00 0x21 0x01 0x00 0x22 0x01>; + }; + + axidmatest@1 { + compatible = "xlnx,axi-dma-test-1.00.a"; + dmas = <0x0a 0x00 0x0a 0x01>; + dma-names = "axidma0\0axidma1"; + }; + + dma@80400000 { + #dma-cells = <0x01>; + clock-names = "s_axi_lite_aclk\0m_axi_sg_aclk\0m_axi_mm2s_aclk\0m_axi_s2mm_aclk"; + clocks = <0x02 0x11 0x02 0x11 0x02 0x11 0x02 0x11>; + compatible = "xlnx,axi-dma-1.00.a"; + interrupt-names = "mm2s_introut\0s2mm_introut"; + interrupt-parent = <0x01>; + interrupts = <0x00 0x23 0x04 0x00 0x24 0x04>; + reg = <0x80400000 0x10000>; + xlnx,addrwidth = <0x20>; + xlnx,include-sg; + xlnx,sg-length-width = <0x0e>; + phandle = <0x0c>; + + dma-channel@80400000 { + compatible = "xlnx,axi-dma-mm2s-channel"; + dma-channels = <0x01>; + interrupts = <0x00 0x23 0x04>; + xlnx,datawidth = <0x40>; + xlnx,device-id = <0x00>; + }; + + dma-channel@80400030 { + compatible = "xlnx,axi-dma-s2mm-channel"; + dma-channels = <0x01>; + interrupts = <0x00 0x24 0x04>; + xlnx,datawidth = <0x40>; + xlnx,device-id = <0x00>; + }; + }; + + dma@80410000 { + #dma-cells = <0x01>; + clock-names = "s_axi_lite_aclk\0m_axi_sg_aclk\0m_axi_mm2s_aclk\0m_axi_s2mm_aclk"; + clocks = <0x02 0x11 0x02 0x11 0x02 0x11 0x02 0x11>; + compatible = "xlnx,axi-dma-1.00.a"; + interrupt-names = "mm2s_introut\0s2mm_introut"; + interrupt-parent = <0x01>; + interrupts = <0x00 0x1f 0x04 0x00 0x20 0x04>; + reg = <0x80410000 0x10000>; + xlnx,addrwidth = <0x20>; + xlnx,include-sg; + xlnx,sg-length-width = <0x0e>; + phandle = <0x0a>; + + dma-channel@80410000 { + compatible = "xlnx,axi-dma-mm2s-channel"; + dma-channels = <0x01>; + interrupts = <0x00 0x1f 0x04>; + xlnx,datawidth = <0x40>; + xlnx,device-id = <0x01>; + }; + + dma-channel@80410030 { + compatible = "xlnx,axi-dma-s2mm-channel"; + dma-channels = <0x01>; + interrupts = <0x00 0x20 0x04>; + xlnx,datawidth = <0x40>; + xlnx,device-id = <0x01>; + }; + }; + + tx_intf@83c00000 { + clock-names = "s00_axi_aclk\0s00_axis_aclk"; + clocks = <0x02 0x11 0x02 0x11>; + compatible = "sdr,tx_intf"; + interrupt-names = "tx_itrpt"; + interrupt-parent = <0x01>; + interrupts = <0x00 0x22 0x01>; + reg = <0x83c00000 0x10000>; + xlnx,s00-axi-addr-width = <0x07>; + xlnx,s00-axi-data-width = <0x20>; + }; + + rx_intf@83c20000 { + clock-names = "s00_axi_aclk\0m00_axis_aclk"; + clocks = <0x02 0x11 0x02 0x11>; + compatible = "sdr,rx_intf"; + interrupt-names = "not_valid_anymore\0rx_pkt_intr"; + interrupt-parent = <0x01>; + interrupts = <0x00 0x1d 0x01 0x00 0x1e 0x01>; + reg = <0x83c20000 0x10000>; + xlnx,s00-axi-addr-width = <0x07>; + xlnx,s00-axi-data-width = <0x20>; + }; + + openofdm_tx@83c10000 { + clock-names = "clk"; + clocks = <0x02 0x11>; + compatible = "sdr,openofdm_tx"; + reg = <0x83c10000 0x10000>; + }; + + openofdm_rx@83c30000 { + clock-names = "clk"; + clocks = <0x02 0x11>; + compatible = "sdr,openofdm_rx"; + reg = <0x83c30000 0x10000>; + }; + + xpu@83c40000 { + clock-names = "s00_axi_aclk"; + clocks = <0x02 0x11>; + compatible = "sdr,xpu"; + reg = <0x83c40000 0x10000>; + }; + + side_ch@83c50000 { + clock-names = "s00_axi_aclk"; + clocks = <0x02 0x11>; + compatible = "sdr,side_ch"; + reg = <0x83c50000 0x10000>; + dmas = <0x0a 0x00 0x0c 0x01>; + dma-names = "rx_dma_mm2s\0tx_dma_s2mm"; + }; + + cf-ad9361-lpc@79020000 { + compatible = "adi,axi-ad9361-6.00.a"; + reg = <0x79020000 0x6000>; + spibus-connected = <0x0b>; + }; + + cf-ad9361-dds-core-lpc@79024000 { + compatible = "adi,axi-ad9361-dds-6.00.a"; + reg = <0x79024000 0x1000>; + clocks = <0x0b 0x0d>; + clock-names = "sampl_clk"; + }; + + mwipcore@43c00000 { + compatible = "mathworks,mwipcore-axi4lite-v1.00"; + reg = <0x43c00000 0xffff>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led0 { + label = "led0:green"; + gpios = <0x06 0x3a 0x00>; + }; + + led1 { + label = "led1:green"; + gpios = <0x06 0x3b 0x00>; + }; + + led2 { + label = "led2:green"; + gpios = <0x06 0x3c 0x00>; + }; + + led3 { + label = "led3:green"; + gpios = <0x06 0x3d 0x00>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <0x01>; + #size-cells = <0x00>; + autorepeat; + + pb0 { + label = "Left"; + linux,code = <0x69>; + gpios = <0x06 0x36 0x00>; + }; + + pb1 { + label = "Right"; + linux,code = <0x6a>; + gpios = <0x06 0x37 0x00>; + }; + + pb2 { + label = "Up"; + linux,code = <0x67>; + gpios = <0x06 0x38 0x00>; + }; + + pb3 { + label = "Down"; + linux,code = <0x6c>; + gpios = <0x06 0x39 0x00>; + }; + + sw0 { + label = "SW0"; + linux,input-type = <0x05>; + linux,code = <0x00>; + gpios = <0x06 0x3e 0x00>; + }; + + sw1 { + label = "SW1"; + linux,input-type = <0x05>; + linux,code = <0x01>; + gpios = <0x06 0x3f 0x00>; + }; + + sw2 { + label = "SW2"; + linux,input-type = <0x05>; + linux,code = <0x02>; + gpios = <0x06 0x40 0x00>; + }; + + sw3 { + label = "SW3"; + linux,input-type = <0x05>; + linux,code = <0x03>; + gpios = <0x06 0x41 0x00>; + }; + }; +}; diff --git a/kernel_boot/boards/neptunesdr/u-boot.elf b/kernel_boot/boards/neptunesdr/u-boot.elf new file mode 100644 index 0000000000000000000000000000000000000000..d07429340c6ed0986ab73a4e02e19d7421b2f4d3 GIT binary patch literal 1837207 zcmeFae|TI~wg11*%$a054ecpOX&fRwg$SWUol4aT6$YqSwaBzhON9yp6h+1B09AUi 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