diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md index b54a75f..cfdf747 100644 --- a/CONTRIBUTING.md +++ b/CONTRIBUTING.md @@ -4,6 +4,6 @@ SPDX-FileCopyrightText: 2019 UGent SPDX-License-Identifier: AGPL-3.0-or-later --> -CLA([Individual](https://users.ugent.be/~xjiao/openwifi-Individual.pdf), [Entity](https://users.ugent.be/~xjiao/openwifi-Entity.pdf)) needs to be signed and sent to Filip.Louagie@UGent.be before you contributing. +CLA([Individual](https://github.com/open-sdr/openwifi-hw-img/raw/master/doc_repo/openwifi-Individual.pdf), [Entity](https://github.com/open-sdr/openwifi-hw-img/raw/master/doc_repo/openwifi-Entity.pdf)) needs to be signed and sent to Filip.Louagie@UGent.be before you contributing. CLA is generated by the [Project Harmony](http://www.harmonyagreements.org/index.html). diff --git a/README.md b/README.md index 4510d0d..b187bc0 100644 --- a/README.md +++ b/README.md @@ -43,23 +43,25 @@ Openwifi code has dual licenses. [AGPLv3](https://github.com/open-sdr/openwifi/b **Performance (best case: aggregation/AMPDU on):** - iperf: TCP 40~50Mbps; UDP 50Mbps -- EVM -38dB; MCS0 sensitivity -87dBm; MCS7 -72dBm. (FMCOMMS2 2.4GHz; cable and OTA test) +- EVM -38dB; MCS0 sensitivity -92dBm; MCS7 -73dBm. (FMCOMMS2 2.4GHz; cable and OTA test) -**Supported SDR platforms:** (Check [Porting guide](#Porting-guide) for your new board if it isn't in the list) +**Supported SDR platforms:** -board_name|board combination|status|SD card img|Vivado license --------|-------|----|----|----- -zc706_fmcs2|[Xilinx ZC706 board](https://www.xilinx.com/products/boards-and-kits/ek-z7-zc706-g.html) + [FMCOMMS2/3/4](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad-fmcomms2.html)|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.3.1-wilsele-1-32bit.img.xz)|Need -zed_fmcs2|[Xilinx zed board](https://www.xilinx.com/products/boards-and-kits/1-8dyf-11.html) + [FMCOMMS2/3/4](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad-fmcomms2.html)|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.3.1-wilsele-1-32bit.img.xz)|**NO** need -adrv9364z7020|[ADRV9364-Z7020 + ADRV1CRR-BOB](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/adrv9364-z7020.html)|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.3.1-wilsele-1-32bit.img.xz)|**NO** need -adrv9361z7035|[ADRV9361-Z7035 + ADRV1CRR-BOB/FMC](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/ADRV9361-Z7035.html)|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.3.1-wilsele-1-32bit.img.xz)|Need -zc702_fmcs2|[Xilinx ZC702 board](https://www.xilinx.com/products/boards-and-kits/ek-z7-zc702-g.html) + [FMCOMMS2/3/4](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad-fmcomms2.html)|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.3.1-wilsele-1-32bit.img.xz)|**NO** need -antsdr|[MicroPhase](https://github.com/MicroPhase/) enhanced ADALM-PLUTO [Notes](kernel_boot/boards/antsdr/notes.md)|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.3.1-wilsele-1-32bit.img.xz)|**NO** need -sdrpi|[HexSDR](https://github.com/HexSDR/) Powerful SDR in Raspberry Pi size [Notes](kernel_boot/boards/sdrpi/notes.md)|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.3.1-wilsele-1-32bit.img.xz)|**NO** need -zcu102_fmcs2|[Xilinx ZCU102 board](https://www.xilinx.com/products/boards-and-kits/ek-u1-zcu102-g.html) + [FMCOMMS2/3/4](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad-fmcomms2.html)|Done|[64bit img](https://users.ugent.be/~xjiao/openwifi-1.3.1-wilsele-64bit.img.xz)|Need -zcu102_9371|[Xilinx ZCU102 board](https://www.xilinx.com/products/boards-and-kits/ek-u1-zcu102-g.html) + [ADRV9371](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-adrv9371.html)|Future|Future|Need +board_name|Description|Vivado license +----------|-----------|-------------- +zc706_fmcs2|[Xilinx ZC706 board](https://www.xilinx.com/products/boards-and-kits/ek-z7-zc706-g.html) + [FMCOMMS2/3/4](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad-fmcomms2.html)|Need +zed_fmcs2|[Xilinx zed board](https://www.xilinx.com/products/boards-and-kits/1-8dyf-11.html) + [FMCOMMS2/3/4](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad-fmcomms2.html)|**NO** need +adrv9364z7020|[ADRV9364-Z7020 + ADRV1CRR-BOB](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/adrv9364-z7020.html)|**NO** need +adrv9361z7035|[ADRV9361-Z7035 + ADRV1CRR-BOB/FMC](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/ADRV9361-Z7035.html)|Need +zc702_fmcs2|[Xilinx ZC702 board](https://www.xilinx.com/products/boards-and-kits/ek-z7-zc702-g.html) + [FMCOMMS2/3/4](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad-fmcomms2.html)|**NO** need +antsdr|[MicroPhase](https://github.com/MicroPhase/) enhanced ADALM-PLUTO [Notes](kernel_boot/boards/antsdr/notes.md)|**NO** need +antsdr_e200|[MicroPhase](https://github.com/MicroPhase/) enhanced ADALM-PLUTO (smaller/cheaper) [Notes](kernel_boot/boards/antsdr_e200/README.md)|**NO** need +sdrpi|[HexSDR](https://github.com/HexSDR/) SDR in Raspberry Pi size [Notes](kernel_boot/boards/sdrpi/notes.md)|**NO** need +zcu102_fmcs2|[Xilinx ZCU102 board](https://www.xilinx.com/products/boards-and-kits/ek-u1-zcu102-g.html) + [FMCOMMS2/3/4](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad-fmcomms2.html)|Need +neptunesdr|Low cost Zynq 7020 + AD9361 board|**NO** need -- board_name is used to identify FPGA design in openwifi-hw/boards/ +- Check [Porting guide](#Porting-guide) for your new board if it isn't in the list. +- board_name is used to identify FPGA design in openwifi-hw/boards/ and FPGA image in openwifi-hw-img/boards - Don't have any boards? Or you like JTAG boot instead of SD card? Check our test bed [w-iLab.t](https://doc.ilabt.imec.be/ilabt/wilab/tutorials/openwifi.html) tutorial. [[Quick start](#Quick-start)] @@ -76,16 +78,25 @@ zcu102_9371|[Xilinx ZCU102 board](https://www.xilinx.com/products/boards-and-kit [[Application notes](doc/app_notes/README.md)] ## Quick start -- Restore openwifi board specific img file (from the table) into a SD card. To do this, program "Disks" in Ubuntu can be used (Install: "sudo apt install gnome-disk-utility"). After restoring, the SD card should have two partitions: BOOT and rootfs. You need to config the **correct files in the BOOT partition** according to the **board you have** by operation on your computer: - - Copy files in **openwifi/board_name** to the base directory of BOOT partition. - - Copy **openwifi/zynqmp-common/Image** (zcu102 board) or **openwifi/zynq-common/uImage** (other boards) to the base directory of BOOT partition -- Connect two antennas to RXA/TXA ports. Config the board to SD card boot mode (check the board manual). Insert the SD card to the board. Power on. +- Download [openwifi img](https://drive.google.com/file/d/12egFLT9TclmY8m3vCMHmUuSne3qK0SWc/view?usp=sharing), unzip and burn it into a SD card (>=16GB). After this operation, the SD card should have two partitions: BOOT and rootfs. To flash the SD card, SD card tool software (such as Startup Disk Creator in Ubuntu) or dd command can be used: + ``` + sudo dd bs=512 count=31116288 if=openwifi-xyz.img of=/dev/your_sdcard_dev + (To have correct count value, better to check the .img file actual situation by "fdisk -l img_filename") + ``` +- Config the **correct files in the BOOT partition** according to the **board you have** by operation on your computer: + - Copy files in **BOOT/openwifi/board_name** to the base directory of BOOT partition. + - Delete the **rootfs/root/kernel_modules** directory (if exist). + - Delete the **rootfs/root/etc/network/interfaces.new** directory (if exist). +- Insert the SD card to the board. Configure the board in SD booting mode. Connect antennas. Power on. - Login to the board from your PC (PC Ethernet should have IP 192.168.10.1) with password **openwifi**. ``` ssh root@192.168.10.122 ``` +- If not successful, check [known issue](doc/known_issue/notter.md) - Then, run openwifi AP and the on board webserver ``` + raspi-config --expand-rootfs (Only needed when your SD card > 16GB. Run and reboot) + ./openwifi/setup_once.sh (Reboot the board. Only need to run once for new board) cd openwifi ./wgd.sh ./fosdem.sh @@ -93,9 +104,9 @@ zcu102_9371|[Xilinx ZCU102 board](https://www.xilinx.com/products/boards-and-kit (Use "./fosdem-11ag.sh" to force 11a/g mode) ``` **NOTE** adrv9361z7035 has ultra low TX power in 5GHz. Move **CLOSER** when you use that board in 5GHz!!! -- After you see the "openwifi" SSID on your device (Phone/Laptop/etc), connect it. Browser to 192.168.13.1 on your device, you should see the webpage hosted by the webserver on board. +- After you see the "openwifi" SSID on your device (Phone/Laptop/etc), connect it (password: openwifi). If not get 192.168.13.* IP automatically, check [known issue](doc/known_issue/notter.md). Browser to 192.168.13.1 on your device, you should see the webpage hosted by the webserver on board. - Note 1: If your device doesn't support 5GHz (ch44), please change the **hostapd-openwifi.conf** on board and re-run fosdem.sh. - - Note 2: After ~2 hours, the Viterbi decoder will halt (Xilinx Evaluation License). Just power cycle the board if it happens. (If output of "./sdrctl dev sdr0 get reg rx 20" is always the same, it means the decoder halts) + - Note 2: After ~2 hours, the Viterbi decoder will halt (Xilinx Evaluation License). Just reload FPGA ([method](doc/app_notes/drv_fpga_dynamic_loading.md)) or simply power cycle the board if it happens. (If output of "./sdrctl dev sdr0 get reg rx 20" is always the same, it means the decoder halts) - To give the Wi-Fi client internet access, configure routing/NAT **on the PC**: ``` sudo sysctl -w net.ipv4.ip_forward=1 @@ -127,55 +138,39 @@ The board actually is an Linux/Ubuntu computer which is running **hostapd** to o ## Update FPGA -(Check [Driver and FPGA dynamic reloading app note](./doc/app_notes/drv_fpga_dynamic_loading.md) for more convenient way of updating FPGA and driver files) +(Check [Driver and FPGA dynamic reloading app note](./doc/app_notes/drv_fpga_dynamic_loading.md) for more convenient way of updating FPGA and driver files without rebooting/power-cycle) Since the pre-built SD card image might not have the latest bug-fixes/updates, it is recommended to always copy the latest files in the [user_space](./user_space) directory on to the board. Then update the fpga bitstream and driver (see next section) on to the board. -- Install Vivado/SDK 2018.3 (Vivado Design Suite - HLx Editions - 2018.3 Full Product Installation. If you don't need to generate new FPGA bitstream, WebPack version without license is enough) +- Install Vivado 2021.1. Make sure install Vitis as well. You should have this directory: your_Xilinx_install_directory/Vitis (NOT Vitis_HLS!) + - If the Vitis is not installed, you can add it by running "Xilinx Design Tools --> Add Design Tools for Devices 2021.1" from Xilinx program group/menu in your OS start menu. - Setup environment variables (use absolute path): ``` export XILINX_DIR=your_Xilinx_install_directory - (Example: export XILINX_DIR=/opt/Xilinx. The Xilinx directory should include sth like: Downloads, SDK, Vivado, xic) - export OPENWIFI_HW_DIR=your_openwifi-hw_directory - (The directory where you store the open-sdr/openwifi-hw repo via git clone) + (Example: export XILINX_DIR=/opt/Xilinx. The Xilinx directory should include sth like: Downloads, Vitis, etc.) + export OPENWIFI_HW_IMG_DIR=your_openwifi-hw-img_directory + (The directory where you get the open-sdr/openwifi-hw-img repo via git clone) export BOARD_NAME=your_board_name ``` -- Pick the FPGA bitstream from openwifi-hw, and generate BOOT.BIN and transfer it on board via ssh channel: +- Pick the FPGA bitstream from openwifi-hw-img, generate system_top.bit.bin and transfer it on board via ssh channel: ``` - For Zynq 7000: - - cd openwifi/user_space; ./boot_bin_gen.sh $OPENWIFI_HW_DIR $XILINX_DIR $BOARD_NAME - - For Zynq MPSoC (like zcu102 board): - cd openwifi/user_space; ./boot_bin_gen_zynqmp.sh $OPENWIFI_HW_DIR $XILINX_DIR $BOARD_NAME - - cd openwifi/kernel_boot/boards/$BOARD_NAME/output_boot_bin; scp ./BOOT.BIN root@192.168.10.122: + cd openwifi/user_space; ./boot_bin_gen.sh $XILINX_DIR $BOARD_NAME $OPENWIFI_HW_IMG_DIR/boards/$BOARD_NAME/sdk/system_top.xsa + scp ./system_top.bit.bin root@192.168.10.122:openwifi/ ``` -- On board: Put the BOOT.BIN into the BOOT partition. - ``` - mount /dev/mmcblk0p1 /mnt - cp ~/BOOT.BIN /mnt - cd /mnt - sync - cd ~ - umount /mnt - ``` - **Power cycle** the board to load new FPGA bitstream. - - To load FPGA dynamically without rebooting/power-cycle, check [Driver and FPGA dynamic reloading app note](./doc/app_notes/drv_fpga_dynamic_loading.md). +- Now the system_top.bit.bin is onboard in /root/openwifi/ directory. When wgd.sh runs onboard from that directory, it will discover the FPGA img file system_top.bit.bin and load it before loading driver .ko files. ## Update Driver -(Check [Driver and FPGA dynamic reloading app note](./doc/app_notes/drv_fpga_dynamic_loading.md) for more convenient way of updating FPGA and driver files) +(Check [Driver and FPGA dynamic reloading app note](./doc/app_notes/drv_fpga_dynamic_loading.md) for more convenient way of updating FPGA and driver files without rebooting/power-cycle) Since the pre-built SD card image might not have the latest bug-fixes/updates, it is recommended to always copy the latest files in the [user_space](./user_space) directory on to the board. Then update the fpga bitstream (see previous section) and driver on to the board. - Prepare Analog Devices Linux kernel source code (only need to run once): ``` - cd openwifi/user_space; ./prepare_kernel.sh $XILINX_DIR ARCH_BIT build + sudo apt install flex bison libssl-dev device-tree-compiler u-boot-tools -y + cd openwifi/user_space; ./prepare_kernel.sh $XILINX_DIR ARCH_BIT (For Zynq 7000, ARCH_BIT should be 32, for Zynq MPSoC, ARCH_BIT should be 64) ``` - **Note**: In Ubuntu, gcc-10 might have issue ('yylloc' error), so use gcc-9 if you encounter error. - Compile the latest openwifi driver ``` cd openwifi/driver; ./make_all.sh $XILINX_DIR ARCH_BIT @@ -189,7 +184,7 @@ Since the pre-built SD card image might not have the latest bug-fixes/updates, i Now you can use **wgd.sh** on board to load the new openwifi driver. **wgd.sh** also tries to reload FPGA img if system_top.bit.bin presents in the same directory. Find more information in [Driver and FPGA dynamic reloading app note](./doc/app_notes/drv_fpga_dynamic_loading.md). - **Note**: If you have symbol or version error while loadng the driver, it could be because the kernel in the SD card image is too old. In this case, you need to follow [[Build openwifi Linux img from scratch](#Build-openwifi-Linux-img-from-scratch)] to generate your new SD card image. + **Note**: If you have symbol or version error while loadng the driver, it could be because the kernel in the SD card image is too old. In this case, you need put the linux kernel image generated by prepare_kernel.sh (check [[Update Driver](#Update-Driver)]) to the BOOT partition of SD card. The kernel image file name: adi-linux/arch/arm/boot/uImage (32bit); adi-linux-64/arch/arm64/boot/Image (64bit). ## Update sdrctl - Copy the sdrctl source files to the board via ssh channel @@ -198,11 +193,11 @@ Since the pre-built SD card image might not have the latest bug-fixes/updates, i ``` - Compile the sdrctl **on board**: ``` - cd ~/openwifi/sdrctl_src/ && make && cp sdrctl ../ && cd .. + cd ~/openwifi/sdrctl_src/ && make clean && make && cp sdrctl ../ && cd .. ``` ## Easy Access and etc -- Check [Driver and FPGA dynamic reloading app note](./doc/app_notes/drv_fpga_dynamic_loading.md) for more convenient way of updating FPGA and driver files. +- Check [Driver and FPGA dynamic reloading app note](./doc/app_notes/drv_fpga_dynamic_loading.md) for more convenient way of updating FPGA and driver files without rebooting/power-cycle. - FPGA and driver on board update scripts - Setup [ftp server](https://ubuntu.com/server/docs/service-ftp) on PC, allow anonymous and change ftp root directory to the openwifi directory. - On board: @@ -217,45 +212,7 @@ Since the pre-built SD card image might not have the latest bug-fixes/updates, i - Input password "openwifi" ## Build openwifi Linux img from scratch -- Install the devicetree compiler -- dtc. (For Ubuntu: sudo apt install device-tree-compiler) -- Install the mkimage tool. (For Ubuntu: sudo apt install u-boot-tools) -- Download [2019_R1-2020_06_22.img.xz](http://swdownloads.analog.com/cse/2019_R1-2020_06_22.img.xz) from [Analog Devices Wiki](https://wiki.analog.com/resources/tools-software/linux-software/zynq_images). Burn it to a SD card. -- Insert the SD card to your Linux PC. Find out the mount point (that has two sub directories BOOT and rootfs), and setup environment variables (use absolute path): - ``` - export SDCARD_DIR=sdcard_mount_point - export XILINX_DIR=your_Xilinx_install_directory - export OPENWIFI_HW_DIR=your_openwifi-hw_directory - export BOARD_NAME=your_board_name - ``` -- Run script to update SD card: - ``` - cd openwifi/user_space; ./update_sdcard.sh $OPENWIFI_HW_DIR $XILINX_DIR $BOARD_NAME $SDCARD_DIR - ``` -- Config your board to SD card boot mode (check the board manual). Insert the SD card to the board. Power on. -- Login to the board from your PC (PC Ethernet should have IP 192.168.10.1) with one time password **analog**. - ``` - ssh root@192.168.10.122 - ``` -- Setup routing/NAT **on the PC** for your board -- this internet connection is **important** for post installation/config. - ``` - sudo sysctl -w net.ipv4.ip_forward=1 - sudo iptables -t nat -A POSTROUTING -o NICY -j MASQUERADE - sudo ip route add 192.168.13.0/24 via 192.168.10.122 dev ethX - ``` - **ethX** is the PC NIC name connecting the board ethernet. **NICY** is the PC NIC name connecting internet (WiFi or another ethernet). - - If you want, uncommenting "net.ipv4.ip_forward=1" in /etc/sysctl.conf to make IP forwarding persistent on PC. -- Test the connectivity. Run on board (in the ssh session): - ``` - route add default gw 192.168.10.1 - ping IP_YOU_KNOW_ON_YOUR_NETWORK - ``` - If there is issue with the connectivity (ping can not reach the target), it needs to be solved before going to the next step. -- Run **one time** script on board to complete post installation/config (After this, password becomes **openwifi**) - ``` - cd ~/openwifi && ./post_config.sh - ``` -- Now you can start from [Quick start](#Quick-start) (Skip the image download and burn step) +- For the latest ADI Kuiper image, please check [kuiper.md](./doc/img_build_instruction/kuiper.md) ## Special note for 11b @@ -272,13 +229,13 @@ cd openwifi/user_space; ./build_wpa_supplicant_wo11b.sh ``` ## Porting guide -This section explains the porting work by showing the differences between openwifi and Analog Devices reference design. openwifi is based on 2019_R1 of [HDL Reference Designs](https://github.com/analogdevicesinc/hdl). +This section explains the porting work by showing the differences between openwifi and Analog Devices reference design. openwifi is based on 2021_r1 of [HDL Reference Designs](https://github.com/analogdevicesinc/hdl). - Open the fmcomms2 + zc706 reference design at hdl/projects/fmcomms2/zc706 (Please read Analog Devices help) - Open the openwifi design zc706_fmcs2 at openwifi-hw/boards/zc706_fmcs2 (Please read openwifi-hw repository) - "Open Block Design", you will see the differences between openwifi and the reference design. Both in "diagram" and in "Address Editor". - The address/interrupts of FPGA blocks hooked to the ARM bus should be put/aligned to the devicetree file openwifi/kernel_boot/boards/zc706_fmcs2/devicetree.dts. Linux will parse the devicetree.dtb when booting to know information of attached device (FPGA blocks in our case). - We use dtc command to get devicetree.dts converted from devicetree.dtb in [Analog Devices Linux image](https://wiki.analog.com/resources/tools-software/linux-software/zynq_images), then do modification according to what we have added/modified to the reference design. -- Please learn the script in [[Build openwifi Linux img from scratch](#Build-openwifi-Linux-img-from-scratch)] to understand how we generate devicetree.dtb, BOOT.BIN and Linux kernel uImage and put them together to build the full SD card image. +- Please learn the script in [[Build openwifi Linux img from scratch](#Build-openwifi-Linux-img-from-scratch)] to understand how we generate devicetree.dtb, BOOT.BIN, Linux kernel and put them together to build the full SD card image. ## License diff --git a/doc/README.md b/doc/README.md index 80686a6..b8b12c9 100644 --- a/doc/README.md +++ b/doc/README.md @@ -204,7 +204,7 @@ reg_idx|meaning|comment 8|RSSI threshold for CCA (channel idle/busy)|set by ad9361_rf_set_channel automatically. the unit is rssi_half_db, check rssi_half_db_to_rssi_dbm()/rssi_dbm_to_rssi_half_db() in sdr.c to see the relation to rssi dBm 9|some low MAC time setting|bit31 0:auto, 1:manual. When manual, bit6-0: PHY rx delay, bit13-7: SIFS, bit18-14: slot time, bit23-19: ofdm symbol time, bit30-24: preamble+SIG time. unit us. check xpu.v (search slv_reg9) 10|BB RF delay setting|unit 0.1us. bit7-0: BB RF delay, bit14-8: RF end extended time on top of the delay. bit22-16: delay between bb tx start to RF tx on (lo or port control via spi). bit30-24: delay between bb tx end to RF tx off. check xpu.v (search slv_reg10) -11|ACK control and max num retransmission|bit4: 0:normal ACK, 1:disable auto ACK reply in FPGA. bit3-0: if bit3==0, the number of retransmission is decided by Linux. if bit3==1, the max num retransmission is taken from bit2-0 +11|ACK control and max num retransmission|bit4: 0:normal ACK tx/reply, 1:disable auto ACK tx/reply in FPGA. bit5: 0:normal ACK rx from peer, 1:not expecting ACK rx from peer. bit3-0: if bit3==0, the number of retransmission is decided by Linux. if bit3==1, the max num retransmission is taken from bit2-0 12|AMPDU control|bit0: indicate low MAC start to receive AMPDU. bit4-1: tid. bit31: tid enable (by default, tid is not enabled and we decode AMPDU of all tid) 13|spi controller config|1: disable spi control and Tx RF is always on; 0: enable spi control and Tx RF only on (lo/port) when pkt sending 16|setting when wait for ACK in 2.4GHz|unit 0.1us. bit14-0: OFDM decoding timeout (after detect PHY header), bit30-16: timeout for PHY header detection, bit31: 0: FCS valid is not needed for ACK packet, 1: FCS valid is needed for ACK packet diff --git a/doc/app_notes/README.md b/doc/app_notes/README.md index 086f391..a5ed1fa 100644 --- a/doc/app_notes/README.md +++ b/doc/app_notes/README.md @@ -13,7 +13,7 @@ Application notes collect many small topics about using openwifi in different sc - [WiFi CSI radar via self CSI capturing](radar-self-csi.md) - [Capture IQ sample, AGC gain, RSSI with many types of trigger condition](iq.md) - [Capture dual antenna TX/RX IQ for multi-purpose (capture collision)](iq_2ant.md) -- [WiFi packet and IQ sample self loopback test (over-the-air and FPGA internal)](packet-iq-self-loopback-test.md) +- [WiFi packet, CSI and IQ sample self loopback test (over-the-air and FPGA internal)](packet-iq-self-loopback-test.md) - [IEEE 802.11n (Wi-Fi 4)](ieee80211n.md) - [802.11 packet injection and fuzzing](inject_80211.md) - [CSI fuzzer](csi_fuzzer.md) diff --git a/doc/app_notes/drv_fpga_dynamic_loading.md b/doc/app_notes/drv_fpga_dynamic_loading.md index e6dcea6..d60bf8f 100644 --- a/doc/app_notes/drv_fpga_dynamic_loading.md +++ b/doc/app_notes/drv_fpga_dynamic_loading.md @@ -20,7 +20,7 @@ present in the directory. If wgd.sh can not find the FPGA image, it will skip re - Generate the reloadable FPGA file **system_top.bit.bin**. In the Linux host computer: ``` cd openwifi/user_space - ./drv_and_fpga_package_gen.sh $OPENWIFI_HW_DIR $XILINX_DIR $BOARD_NAME + ./drv_and_fpga_package_gen.sh $OPENWIFI_HW_IMG_DIR $XILINX_DIR $BOARD_NAME ``` Then **system_top.bit.bin** will be generated in openwifi/user_space. diff --git a/doc/app_notes/frequent_trick.md b/doc/app_notes/frequent_trick.md index 352c979..5d93bbb 100644 --- a/doc/app_notes/frequent_trick.md +++ b/doc/app_notes/frequent_trick.md @@ -1,7 +1,7 @@ Some usual/frequent control trick over the openwifi FPGA. You need to do these controls on board in the openwifi directory. [[CCA LBT threshold and disable](#CCA-LBT-threshold-and-disable)] -[[Retransmission and ACK tx control](#Retransmission-and-ACK-tx-control)] +[[Retransmission and ACK control](#Retransmission-and-ACK-control)] [[NAV DIFS EIFS CW disable and enable](#NAV-DIFS-EIFS-CW-disable-and-enable)] [[CW max and min config](#CW-max-and-min-config)] @@ -20,26 +20,30 @@ Some usual/frequent control trick over the openwifi FPGA. You need to do these c In normal operation, different threshold is set to FPGA according to the different calibration of different frequency/channel by driver automatically. Show the current LBT threshold in FPGA: ``` ./set_lbt_th.sh +dmesg ``` -"reg val: 00000086" means the current threshold is 134 (86 in Hex). Its unit is rssi_half_db. Check rssi_half_db_to_rssi_dbm()/rssi_dbm_to_rssi_half_db() in sdr.c to see the relation to rssi dBm. +It shows: "sdr,sdr FPGA LBT threshold 166(-62dBm). The last_auto_fpga_lbt_th 166(-62dBm). rssi corr 145". Check rssi_half_db_to_rssi_dbm()/rssi_dbm_to_rssi_half_db() in sdr.c to see the relation to rssi dBm. Override a new threshold -NNdBm to FPGA, for example -70dBm: ``` ./set_lbt_th.sh 70 +dmesg ``` Above will disable the automatic CCA threshold setting from the openwifi driver. Recover the driver automatic control on the threshold: ``` ./set_lbt_th.sh 0 +dmesg ``` Disable the CCA by setting a very strong level as threshold, for example -1dBm: ``` ./set_lbt_th.sh 1 +dmesg ``` After above command, the CCA engine will always believe the channel is idle, because the rx signal strength not likely could exceed -1dBm. -## Retransmission and ACK tx control +## Retransmission and ACK control The best way of override the maximum number of re-transmission for a Tx packet is doing it in the driver openwifi_tx() function. ``` @@ -60,7 +64,7 @@ To override the maximum number of re-transmission, set bit3 to 1, and set the va 9 in binary form is 01001. -To disable the ACK TX after receive a packet, set bit4 to 1. (Assume we want to preserve the above re-transmission overriding setting) +To disable the ACK TX after receiving a packet, set bit4 to 1. (Assume we want to preserve the above re-transmission overriding setting) ``` ./sdrctl dev sdr0 set reg xpu 11 25 ``` @@ -68,6 +72,8 @@ To disable the ACK TX after receive a packet, set bit4 to 1. (Assume we want to 25 in binary form is 11001. the 1001 of bit3 to 1 is untouched. Disabling ACK TX might be useful for monitor mode and packet injection. + +To disable the ACK RX after sending a packet, set bit5 to 1. ## NAV DIFS EIFS CW disable and enable diff --git a/doc/app_notes/iq.md b/doc/app_notes/iq.md index 585194b..ab7e02a 100644 --- a/doc/app_notes/iq.md +++ b/doc/app_notes/iq.md @@ -84,7 +84,7 @@ We implement the **IQ sample capture** with interesting extensions: many **trigg 0 |receiver gives FCS checksum result. no matter pass/fail 1 |receiver gives FCS checksum result. pass 2 |receiver gives FCS checksum result. fail - 3 |receiver gives SIGNAL field checksum result. no matter pass/fail + 3 |the tx_intf_iq0 becomes non zero (the 1st I/Q out) 4 |receiver gives SIGNAL field checksum result. pass 5 |receiver gives SIGNAL field checksum result. fail 6 |receiver gives SIGNAL field checksum result. no matter pass/fail. HT packet diff --git a/doc/app_notes/openwifi-csi-fpga-loopback.jpg b/doc/app_notes/openwifi-csi-fpga-loopback.jpg new file mode 100644 index 0000000..299a909 Binary files /dev/null and b/doc/app_notes/openwifi-csi-fpga-loopback.jpg differ diff --git a/doc/app_notes/packet-iq-self-loopback-test.md b/doc/app_notes/packet-iq-self-loopback-test.md index 75ba222..b140b4c 100644 --- a/doc/app_notes/packet-iq-self-loopback-test.md +++ b/doc/app_notes/packet-iq-self-loopback-test.md @@ -5,13 +5,13 @@ SPDX-License-Identifier: AGPL-3.0-or-later --> One super power of the openwifi platform is "**Full Duplex**" which means that openwifi baseband can receive its own TX signal. -This makes the IQ sample and WiFi packet self loopback test possible. Reading the normal IQ sample capture [app note](iq.md) will help if you have issue or -want to understand openwifi side channel (for IQ and CSI) deeper. +This makes the IQ sample, WiFi packet and CSI self loopback test possible. Reading the normal [IQ sample capture app note](iq.md) and [CSI radar app note](radar-self-csi.md) will help if you have issue or want to understand openwifi side channel (for IQ and CSI) deeper. ![](./openwifi-loopback-principle.jpg) [[IQ self loopback quick start](#IQ-self-loopback-quick-start)] [[Check the packet loopback on board](#Check-the-packet-loopback-on-board)] -[[Self loopback config](#Self-loopback-config)] +[[IQ self loopback config](#IQ-self-loopback-config)] +[[CSI FPGA self loopback quick start](#CSI-FPGA-self-loopback-quick-start)] ## IQ self loopback quick start (Please replace the IQ length **8187** by **4095** if you use low end FPGA board: zedboard/adrv9464z7020/antsdr/zc702/sdrpi) @@ -112,7 +112,7 @@ to do further offline analysis, or feed the IQ sample to the openwifi receiver s ``` You should see the printk message of packet Tx and Rx from the openwifi driver (sdr.c). -## Self loopback config +## IQ self loopback config - By default, the loopback is via the air (from Tx antenna to Rx antenna). FPGA inernal loopback option is offered to have IQ sample and packet without any interference. To have FPGA internal loopback, replace the "./side_ch_ctl wh5h0" during setup (the very 1st ssh session) by: @@ -128,3 +128,34 @@ to do further offline analysis, or feed the IQ sample to the openwifi receiver s - To understand deeper of all above commands/settings, please refer to [Capture IQ sample, AGC gain, RSSI with many types of trigger condition](iq.md) and [Capture dual antenna TX/RX IQ for multi-purpose (capture collision)](iq_2ant.md) + +## CSI FPGA self loopback quick start + +This section will show how to connect the WiFi OFDM transmitter to the receiver directly inside FPGA, and show the ideal CSI/constellation/frequency-offset. (For CSI over the air loopback, please refer to [CSI radar app note](radar-self-csi.md)) + +Command sequence on board: +``` +cd openwifi +./wgd.sh +./monitor_ch.sh sdr0 6 +insmod side_ch.ko +./side_ch_ctl g +``` +Open another ssh session on board, then: +``` +cd openwifi +./sdrctl dev sdr0 set reg rx_intf 3 256 +(Above command let the FPGA Tx IQ come to receiver directly. Set 256 back to 0 to let receiver back connect to AD9361 RF frontend) +./sdrctl dev sdr0 set reg rx 5 768 +(Disable the receiver FFT window shift. By default it is 1 (768+1) -- good for multipath, overfitting for direct loopback) +./inject_80211/inject_80211 -m n -r 7 -n 99999 -s 1400 -d 1000000 sdr0 +(Transmit 802.11n MCS7 1400Byte packet every second) +``` + +Command on computer: +``` +cd openwifi/user_space/side_ch_ctl_src +python3 side_info_display.py +``` +Now you should see the following screenshot that shows the CSI/constellation/frequency-offset over this in-FPGA ideal channel. +![](./openwifi-csi-fpga-loopback.jpg) diff --git a/doc/app_notes/radar-self-csi.md b/doc/app_notes/radar-self-csi.md index 679bb09..ba9804c 100644 --- a/doc/app_notes/radar-self-csi.md +++ b/doc/app_notes/radar-self-csi.md @@ -14,6 +14,7 @@ One super power of the openwifi platform is "**Full Duplex**" which means that o ssh root@192.168.10.122 (password: openwifi) cd openwifi + ./wgd.sh ./fosdem.sh (After the AP started by above command, you can connect a WiFi client to this openwifi AP) (Or setup other scenario according to your requirement) diff --git a/doc/img_build_instruction/kuiper.md b/doc/img_build_instruction/kuiper.md new file mode 100644 index 0000000..384292f --- /dev/null +++ b/doc/img_build_instruction/kuiper.md @@ -0,0 +1,159 @@ +**IMPORTANT pre-conditions**: +- Install Vivado 2021.1. Make sure install Vitis as well. You should have this directory: your_Xilinx_install_directory/Vitis (NOT Vitis_HLS!) + - If the Vitis is not installed, you can add it by running "Xilinx Design Tools --> Add Design Tools for Devices 2021.1" from Xilinx program group/menu in your OS start menu, or Help menu of Vivado. +- SD card at least with 16GB +- Install packages: `sudo apt install flex bison libssl-dev device-tree-compiler u-boot-tools -y` + +[[Use openwifi prebuilt img](#Use-openwifi-prebuilt-img)] +[[Build SD card from scratch](#Build-SD-card-from-scratch)] +[[Use existing SD card on new board](#Use-existing-SD-card-on-new-board)] + +## Use openwifi prebuilt img + +Download openwifi pre-built img (see [Quick start](../../README.md#quick-start)), and extract it to .img file. + +Use dd command to flash the SD card. (Or other software like Startup Disk Creator in Ubuntu) +``` +sudo dd bs=512 count=31116288 if=openwifi-xyz.img of=/dev/your_sdcard_dev +``` +To have correct count value, better to check the .img file actual situation by "fdisk -l img_filename". + +Then start from the 2nd step of the [Quick start](../../README.md#quick-start) in README. + +## Build SD card from scratch + +Download image_2022-08-04-ADI-Kuiper-full.zip from https://wiki.analog.com/resources/tools-software/linux-software/kuiper-linux?redirect=1 + +Extract it to .img file. + +Use dd command to flash the SD card. (Or other software like Startup Disk Creator in Ubuntu) +``` +sudo dd bs=512 count=24018944 if=2022-08-04-ADI-Kuiper-full.img of=/dev/your_sdcard_dev +``` + +(To have correct count value, better to check the .img file actual situation by "fdisk -l img_filename". While making .img from SD card, check the SD card dev instead) + +Mount the BOOT and rootfs partition of SD card to your computer. + +Change the SD card file: Add following into rootfs/etc/network/interfaces +``` +# The loopback interface +auto lo +iface lo inet loopback +auto eth0 +iface eth0 inet static + +#your static IP +address 192.168.10.122 + +#your gateway IP +gateway 192.168.10.1 +netmask 255.255.255.0 + +#your network address "family" +network 192.168.10.0 +broadcast 192.168.10.255 +``` + +Change the SD card file: Add following into rootfs/etc/sysctl.conf +``` +net.ipv4.ip_forward=1 +``` + +Change the SD card file: Add following into rootfs/etc/systemd/system.conf +``` +DefaultTimeoutStopSec=2s +``` + +Put the openwifi/kernel_boot/10-network-device.rules into rootfs/etc/udev/rules.d/ + +Run **update_sdcard.sh** from openwifi/user_space directory to further prepare the SD card. The last argument $SDCARD_DIR of the script is the directory (mounting point) on your computer that has BOOT and rootfs directories/partitions. + +The script will build and put following things into the SD card: + - Linux kernel image file ([Update Driver](../../README.md#Update-Driver)): + - adi-linux-64/arch/arm64/boot/Image (64bit) + - adi-linux/arch/arm/boot/uImage (32bit) + - devicetree file: + - openwifi/kernel_boot/boards/zcu102_fmcs2/system.dtb (64bit) + - openwifi/kernel_boot/boards/$BOARD_NAME/devicetree.dtb (32bit) + - BOOT.BIN ([Update FPGA](../../README.md#Update-FPGA)): + - openwifi/kernel_boot/boards/$BOARD_NAME/output_boot_bin/BOOT.BIN + - openwifi driver ([Update Driver](../../README.md#Update-Driver)). + - openwifi/user_space files and openwifi/webserver files + +After **update_sdcard.sh** finishes, please do the 2nd step "Config the correct files ..." in [Quick start](../../README.md#quick-start). Then power on the board with the SD card, connect the board to your host PC (static IP 192.168.10.1) via ethernet, and ssh to the board with password **"analog"** +``` +ssh root@192.168.10.122 +``` + +Then change password to "openwifi" via "passwd" command onbard. + +Enlarge the onboard SD disk space, and reboot (https://github.com/analogdevicesinc/adi-kuiper-gen/releases) +``` +raspi-config --expand-rootfs +reboot now +``` +Setup routing/NAT **on the PC** for your board -- this internet connection is **important** for post installation/config. +``` +sudo sysctl -w net.ipv4.ip_forward=1 +sudo iptables -t nat -A POSTROUTING -o NICY -j MASQUERADE +sudo ip route add 192.168.13.0/24 via 192.168.10.122 dev ethX +``` +**ethX** is the PC NIC name connecting the board ethernet. **NICY** is the PC NIC name connecting internet (WiFi or another ethernet). + +If you want, uncommenting "net.ipv4.ip_forward=1" in /etc/sysctl.conf to make IP forwarding persistent on PC. + +Test the connectivity. Run on board (in the ssh session): +``` +route add default gw 192.168.10.1 +ping IP_YOU_KNOW_ON_YOUR_NETWORK +``` +If there is issue with the connectivity (ping can not reach the target), it needs to be solved before going to the next step. + +Do misc configurations/installations in the ssh session onboard: +``` +sudo apt update +chmod +x /root/openwifi/*.sh + +# install and setup dhcp server +sudo apt-get -y install isc-dhcp-server +cp /root/openwifi/dhcpd.conf /etc/dhcp/dhcpd.conf + +# install hostapd and other useful tools +sudo apt-get -y install hostapd +sudo apt-get -y install tcpdump +sudo apt-get -y install webfs +sudo apt-get -y install iperf +sudo apt-get -y install iperf3 +sudo apt-get -y install libpcap-dev +sudo apt-get -y install bridge-utils + +# build on board tools +sudo apt-get -y install libnl-3-dev +sudo apt-get -y install libnl-genl-3-dev +cd /root/openwifi/sdrctl_src +make clean +make +cp sdrctl ../ +cd /root/openwifi/side_ch_ctl_src/ +gcc -o side_ch_ctl side_ch_ctl.c +cp side_ch_ctl ../ +cd /root/openwifi/inject_80211/ +make clean +make +cd .. +``` + +Run openwifi in the ssh session onboard: +``` +/root/openwifi/setup_once.sh (Only need to run once for new board) +cd /root/openwifi +./wgd.sh +ifconfig sdr0 up +iwlist sdr0 scan +./fosdem.sh +``` + +## Use existing SD card on new board + +Just operate the existing/working SD card of the old board on your computer starting from the 2nd step of the [Quick start](../../README.md#quick-start) in README. Then start using the SD card on the new board. diff --git a/doc/known_issue/notter.md b/doc/known_issue/notter.md new file mode 100644 index 0000000..60bd910 --- /dev/null +++ b/doc/known_issue/notter.md @@ -0,0 +1,30 @@ +# Known issue + +- [Network issue in quick start](#Network-issue-in-quick-start) +- [EXT4 fs error rootfs issue](#EXT4-fs-error-rootfs-issue) +- [antsdr e200 UART console](#antsdr-e200-UART-console) +- [Client can not get IP](#Client-can-not-get-IP) + +## Network issue in quick star + +- OS: Ubuntu 22 LTS +- image: [openwifi img](https://drive.google.com/file/d/1fb8eJGJAntOciCiGFVLfQs7m7ucRtSWD/view?usp=share_link) + +If can't ssh to the board via Ethernet for the 1st time, you might need to delete /etc/network/interfaces.new on SD card (on your computer). + +If still can't ssh the board via Ethernet, you should use UART console (/dev/ttyUSBx, /dev/ttyCH341USBx, etc.) to monitor what happened during booting. + +## EXT4 fs error rootfs issue + +Sometimes, the 1st booting after flashing SD card might encounter "EXT4-fs error (device mmcblk0p2): ..." error on neptunesdr, changing SD card flashing tool might solve this issue. Some tool candidates: +- gnome-disks +- Startup Disk Creator +- win32diskimager + +## antsdr e200 UART console + +If can't see the UART console in Linux (/dev/ttyUSB0 or /dev/ttyCH341USB0), according to https://github.com/juliagoda/CH341SER, you might need to do `sudo apt remove brltty` + +## Client can not get IP + +If the client can not get IP from the openwifi AP, just re-run "service isc-dhcp-server restart" on board and do re-connect from the client. diff --git a/doc/publications.md b/doc/publications.md index 68a9db6..08c914c 100644 --- a/doc/publications.md +++ b/doc/publications.md @@ -15,33 +15,38 @@ Publications in category: ## Feature Functionality and System - [Xianjun Jiao, et al. openwifi: a free and open-source IEEE802.11 SDR implementation on SoC. VTC2020 spring Antwerp](https://www.orca-project.eu/wp-content/uploads/sites/4/2020/03/openwifi-vtc-antwerp-PID1249076.pdf) -- [Cedric Den Haese, The initial 802.11n 2*2 MIMO and diversity (CSD/Combining) work. UGent master thesis 2021](https://users.ugent.be/~xjiao/Cedric_Den_Haese_masterproef.pdf) +- [Cedric Den Haese, The initial 802.11n 2*2 MIMO and diversity (CSD/Combining) work. UGent master thesis 2021](https://github.com/open-sdr/openwifi-hw-img/raw/master/doc_repo/Cedric_Den_Haese_masterproef.pdf) - [Paul Zanna, et al. A novel method for utilizing RF information from IEEE 802.11 frames in Software Defined Networks. MethodsX 2021](https://www.sciencedirect.com/science/article/pii/S2215016121003368) - [Luca Baldesi, et al. ChARM: NextG Spectrum Sharing Through Data-Driven Real-Time O-RAN Dynamic Control. INFOCOM 2022](https://ece.northeastern.edu/wineslab/papers/BaldesiInfocom22.pdf) - [Thijs Havinga, et al. WIP: Achieving Self-Interference-Free Operation on SDR Platform with Critical TDD Turnaround Time. accepted WoWMoM2022 paper](https://arxiv.org/abs/2204.07354) - [Yingshuo Xi, Baiming Zhang. High-Throughput Open Source Viterbi Decoder for OpenWiFi. 2022 KU Leuven master thesis](https://github.com/BaimingZhang26213/viterbi_decoder) +- [Merkebu Girmay, et al. Technology recognition and traffic characterization for wireless technologies in ITS band. Vehicular Communications Volume 39, February 2023, 100563](https://doi.org/10.1016/j.vehcom.2022.100563) ## TSN Time Sensitive Network and RT Real Time - [Jetmir Haxhibeqiri, et al. Enabling TSN over IEEE 802.11: Low-overhead Time Synchronization for Wi-Fi Clients. ICIT2021](https://biblio.ugent.be/publication/8700714/file/8700715.pdf) - [Ingrid Moerman, et al. Wireless Time-Sensitive Networks: When Every Microsecond Counts. Microwaves&RF, 2021](https://www.mwrf.com/technologies/systems/article/21164984/wireless-timesensitive-networks-when-every-microsecond-counts) - [Muhammad Aslam, et al. High precision time synchronization on Wi-Fi based multi-hop network. CNERT2021](https://biblio.ugent.be/publication/8709058/file/8709060.pdf) - [Ingrid Moerman, et al. Interoperable Time-Sensitive Networking Towards 6G (invited presentation)](https://biblio.ugent.be/publication/8719532/file/8719533.pdf) -- [Lihao Zhang, et al. A Just-In-Time Networking Framework for Minimizing Request-Response Latency of Wireless Time-Sensitive Applications. Arxiv 2021](https://arxiv.org/abs/2109.03032) +- [Lihao Zhang, et al. A Just-In-Time Networking Framework for Minimizing Request-Response Latency of Wireless Time-Sensitive Applications. Arxiv 2021. Accepted by IEEE IoT journal 2022.](https://arxiv.org/abs/2109.03032) - [Jetmir Haxhibeqiri, et al. Bringing Time-Sensitive Networking to Wireless Professional Private Networks. Wireless Personal Communications 2021](https://link.springer.com/article/10.1007/s11277-021-09056-0) - [Muhammad Aslam, et al. Hardware Efficient Clock Synchronization across Wi-Fi and Ethernet Based Network Using PTP. IEEE Transactions on Industrial Informatics 2021](https://ieeexplore.ieee.org/document/9573364) - [Zelin Yun, et al. RT-WiFi on Software-Defined Radio: Design and Implementation. accepted RTAS2022 paper and demo](https://arxiv.org/abs/2203.10390) - [Pablo Avila-Campos, et al. Beacon-Based Wireless TSN Association. 2022 IEEE INFOCOM](https://imec-publications.be/bitstream/handle/20.500.12860/40111/8126_acc.pdf?sequence=2) - [Pablo Avila-Campos, et al. Impactless Beacon-Based Wireless TSN Association Procedure. 2022 IEEE 18th International Conference on Factory Communication Systems (WFCS)](https://ieeexplore.ieee.org/abstract/document/9779186) - [Jetmir Haxhibeqiri, et al. Safety-related Applications over Wireless Time-Sensitive Networks. IEEE ETFA 2022](https://biblio.ugent.be/publication/8770625/file/8770627.pdf) +- [Pablo Avila-Campos, et al. Removing the Wires in Time-Sensitive Networks. 2022 61st FITCE International Congress Future Telecommunications: Infrastructure and Sustainability (FITCE)](https://ieeexplore.ieee.org/abstract/document/9934268) +- [Pablo Avila-Campos, et al. Periodic Control Traffic Support in a Wireless Time-Sensitive Network. 2022 13th International Conference on Network of the Future (NoF)](https://ieeexplore.ieee.org/document/9942586) +- [Gilson Miranda, et al. The Quality-Aware and Vertical-Tailored Management of Wireless Time-Sensitive Networks. IEEE Internet of Things Magazine ( Volume: 5, Issue: 4, December 2022)](https://ieeexplore.ieee.org/abstract/document/10012491) ## CSI Channel State Information and Security - [Marco Cominelli, et al. CSI MURDER. ORCA project opencall 2019](https://ans.unibs.it/projects/csi-murder/) - [Marco Cominelli, et al. IEEE 802.11 CSI randomization to preserve location privacy: An empirical evaluation in different scenarios. ELSEVIER Computer Networks, 2021](https://www.sciencedirect.com/science/article/abs/pii/S138912862100102X) - [Xianjun Jiao, et al. Openwifi CSI fuzzer for authorized sensing and covert channels. ACM WiSec 2021](https://dl.acm.org/doi/pdf/10.1145/3448300.3468255) - [Hongjian Cao, et al. OWFuzz: WiFi Protocol Fuzzing Tool Based on OpenWiFi. Blackhat asia 2021](https://www.blackhat.com/asia-21/arsenal/schedule/#owfuzz-wifi-protocol-fuzzing-tool-based-on-openwifi-22569), [[**code**]](https://github.com/alipay/Owfuzz) -- [Steven Heijse, IEEE 802.11 Physical Layer Fuzzing Using OpenWifi. UGent master thesis 2021](https://users.ugent.be/~xjiao/Steven_Heijse_masterproef.pdf) -- [Jasper Devreker, Developing IEEE 802.11 PHY fuzzing capabilities using the open source Openwifi project. UGent master thesis 2022](https://users.ugent.be/~xjiao/Jasper_Devreker_masterproef.pdf) -- [Thomas Schuddinck, Cybersecurity: Breaking IEEE 802.11 Devices at the Physical Layer. UGent master thesis 2022](https://users.ugent.be/~xjiao/Thomas_Schuddinck_masterproef.pdf) -- [Seppe Dejonckheere, The design of a CSI sensing authorisation mechanism using the open source Openwifi project. UGnet master thesis 2022](https://users.ugent.be/~xjiao/Seppe_Dejonckheere_masterproef.pdf) +- [Steven Heijse, IEEE 802.11 Physical Layer Fuzzing Using OpenWifi. UGent master thesis 2021](https://github.com/open-sdr/openwifi-hw-img/raw/master/doc_repo/Steven_Heijse_masterproef.pdf) +- [Jasper Devreker, Developing IEEE 802.11 PHY fuzzing capabilities using the open source Openwifi project. UGent master thesis 2022](https://github.com/open-sdr/openwifi-hw-img/raw/master/doc_repo/Jasper_Devreker_masterproef.pdf) +- [Thomas Schuddinck, Cybersecurity: Breaking IEEE 802.11 Devices at the Physical Layer. UGent master thesis 2022](https://github.com/open-sdr/openwifi-hw-img/raw/master/doc_repo/Thomas_Schuddinck_masterproef.pdf) +- [Seppe Dejonckheere, The design of a CSI sensing authorisation mechanism using the open source Openwifi project. UGnet master thesis 2022](https://github.com/open-sdr/openwifi-hw-img/raw/master/doc_repo/Seppe_Dejonckheere_masterproef.pdf) +- [Mathy Vanhoef, et al. Testing and Improving the Correctness of Wi-Fi Frame Injection. ACM WiSec 2023](https://papers.mathyvanhoef.com/wisec2023-wifi-injection.pdf) **Openwifi was born in ORCA project (EU's Horizon2020 programme under agreement number 732174).** diff --git a/driver/Makefile b/driver/Makefile index 12efaf9..8fd1fb4 100644 --- a/driver/Makefile +++ b/driver/Makefile @@ -1,6 +1,6 @@ # Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be -obj-m += sdr.o +obj-m += sdr.o openofdm_rx/openofdm_rx.o openofdm_tx/openofdm_tx.o tx_intf/tx_intf.o rx_intf/rx_intf.o xpu/xpu.o all: make -C $(KDIR) M=$(PWD) modules diff --git a/driver/ad9361/README.md b/driver/ad9361/README.md deleted file mode 100644 index 0f3b2e5..0000000 --- a/driver/ad9361/README.md +++ /dev/null @@ -1,6 +0,0 @@ - -We don't maintain our own (modified) ad9361 driver anymore! The original ad9361 driver in the Linux kernel tree can be used with some extra EXPORT_SYMBOL. diff --git a/driver/ad9361/ad9361.c b/driver/ad9361/ad9361.c deleted file mode 100644 index e538a63..0000000 --- a/driver/ad9361/ad9361.c +++ /dev/null @@ -1,9541 +0,0 @@ -/* - * AD9361 Agile RF Transceiver - * - * Copyright 2013-2015 Analog Devices Inc. - * - * Licensed under the GPL-2. - */ -//#define DEBUG -//#define _DEBUG -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include - -#include -#include - -#include -#include -#include - -#define IIO_AD9361_USE_PRIVATE_H_ - -#include "ad9361.h" -#include "ad9361_private.h" - -static const struct SynthLUT SynthLUT_FDD[LUT_FTDD_ENT][SYNTH_LUT_SIZE] = { -{ - {12605, 13, 1, 4, 2, 15, 12, 7, 14, 6, 14, 5, 15}, /* 40 MHz */ - {12245, 13, 1, 4, 2, 15, 12, 7, 14, 6, 14, 5, 15}, - {11906, 13, 1, 4, 2, 15, 12, 7, 15, 6, 14, 5, 15}, - {11588, 13, 1, 4, 2, 15, 12, 8, 15, 6, 14, 5, 15}, - {11288, 13, 1, 4, 2, 15, 12, 8, 15, 6, 14, 5, 15}, - {11007, 13, 1, 4, 2, 15, 12, 9, 15, 6, 14, 5, 15}, - {10742, 13, 1, 4, 2, 15, 12, 9, 15, 6, 14, 5, 15}, - {10492, 13, 1, 6, 2, 15, 12, 10, 15, 6, 14, 5, 15}, - {10258, 13, 1, 6, 2, 15, 12, 10, 15, 6, 14, 5, 15}, - {10036, 13, 1, 6, 2, 15, 12, 11, 15, 6, 14, 5, 15}, - {9827, 13, 1, 6, 2, 14, 12, 11, 15, 6, 14, 5, 15}, - {9631, 13, 1, 6, 2, 13, 12, 12, 15, 6, 14, 5, 15}, - {9445, 13, 1, 6, 2, 12, 12, 12, 15, 6, 14, 5, 15}, - {9269, 13, 1, 6, 2, 12, 12, 13, 15, 6, 14, 5, 15}, - {9103, 13, 1, 6, 2, 12, 12, 13, 15, 6, 14, 5, 15}, - {8946, 13, 1, 6, 2, 12, 12, 14, 15, 6, 14, 5, 15}, - {8797, 12, 1, 7, 2, 12, 12, 13, 15, 6, 14, 5, 15}, - {8655, 12, 1, 7, 2, 12, 12, 14, 15, 6, 14, 5, 15}, - {8520, 12, 1, 7, 2, 12, 12, 14, 15, 6, 14, 5, 15}, - {8392, 12, 1, 7, 2, 12, 12, 15, 15, 6, 14, 5, 15}, - {8269, 12, 1, 7, 2, 12, 12, 15, 15, 6, 14, 5, 15}, - {8153, 12, 1, 7, 2, 12, 12, 16, 15, 6, 14, 5, 15}, - {8041, 12, 1, 7, 2, 13, 12, 16, 15, 6, 14, 5, 15}, - {7934, 11, 1, 7, 2, 12, 12, 16, 15, 6, 14, 5, 15}, - {7831, 11, 1, 7, 2, 12, 12, 16, 15, 6, 14, 5, 15}, - {7733, 10, 1, 7, 3, 13, 12, 16, 15, 6, 14, 5, 15}, - {7638, 10, 1, 7, 2, 12, 12, 16, 15, 6, 14, 5, 15}, - {7547, 10, 1, 7, 2, 12, 12, 17, 15, 6, 14, 5, 15}, - {7459, 10, 1, 7, 2, 12, 12, 17, 15, 6, 14, 5, 15}, - {7374, 10, 2, 7, 3, 14, 13, 14, 15, 6, 14, 5, 15}, - {7291, 10, 2, 7, 3, 14, 13, 14, 15, 6, 14, 5, 15}, - {7212, 10, 2, 7, 3, 14, 13, 14, 15, 6, 14, 5, 15}, - {7135, 10, 2, 7, 3, 14, 13, 15, 15, 7, 14, 5, 15}, - {7061, 10, 2, 7, 3, 14, 13, 15, 15, 6, 14, 5, 15}, - {6988, 10, 1, 7, 3, 12, 14, 20, 15, 6, 14, 5, 15}, - {6918, 9, 2, 7, 3, 14, 13, 15, 15, 6, 14, 5, 15}, - {6850, 9, 2, 7, 3, 14, 13, 15, 15, 6, 14, 5, 15}, - {6784, 9, 2, 7, 2, 13, 13, 15, 15, 6, 14, 5, 15}, - {6720, 9, 2, 7, 2, 13, 13, 16, 15, 6, 14, 5, 15}, - {6658, 8, 2, 7, 3, 14, 13, 15, 15, 6, 14, 5, 15}, - {6597, 8, 2, 7, 2, 13, 13, 15, 15, 6, 14, 5, 15}, - {6539, 8, 2, 7, 2, 13, 13, 15, 15, 6, 14, 5, 15}, - {6482, 8, 2, 7, 2, 13, 13, 16, 15, 6, 14, 5, 15}, - {6427, 7, 2, 7, 3, 14, 13, 15, 15, 6, 14, 5, 15}, - {6373, 7, 2, 7, 3, 15, 13, 15, 15, 6, 14, 5, 15}, - {6321, 7, 2, 7, 3, 15, 13, 15, 15, 6, 14, 5, 15}, - {6270, 7, 2, 7, 3, 15, 13, 16, 15, 6, 14, 5, 15}, - {6222, 7, 2, 7, 3, 15, 13, 16, 15, 6, 14, 5, 15}, - {6174, 6, 2, 7, 3, 15, 13, 15, 15, 6, 14, 5, 15}, - {6128, 6, 2, 7, 3, 15, 13, 15, 15, 6, 14, 5, 15}, - {6083, 6, 2, 7, 3, 15, 13, 16, 15, 6, 14, 5, 15}, - {6040, 6, 2, 7, 3, 15, 13, 16, 15, 6, 14, 5, 15}, - {5997, 6, 2, 7, 3, 15, 13, 16, 15, 6, 14, 5, 15}, -}, { - {12605, 13, 1, 4, 2, 15, 12, 13, 15, 12, 12, 5, 14}, /* 60 MHz */ - {12245, 13, 1, 4, 2, 15, 12, 13, 15, 12, 12, 5, 14}, - {11906, 13, 1, 4, 2, 15, 12, 13, 15, 13, 12, 5, 13}, - {11588, 13, 1, 4, 2, 15, 12, 14, 15, 13, 12, 5, 13}, - {11288, 13, 1, 5, 2, 15, 12, 15, 15, 13, 12, 5, 13}, - {11007, 13, 1, 5, 2, 15, 12, 16, 15, 13, 12, 5, 13}, - {10742, 13, 1, 5, 2, 15, 12, 16, 15, 12, 12, 5, 14}, - {10492, 13, 1, 6, 2, 15, 12, 17, 15, 12, 12, 5, 14}, - {10258, 13, 1, 6, 2, 15, 12, 18, 15, 13, 12, 5, 13}, - {10036, 13, 1, 6, 2, 15, 12, 19, 15, 13, 12, 5, 13}, - {9827, 13, 1, 6, 2, 14, 12, 20, 15, 13, 12, 5, 13}, - {9631, 13, 1, 6, 2, 13, 12, 21, 15, 13, 12, 5, 13}, - {9445, 13, 1, 6, 2, 12, 12, 22, 15, 13, 12, 5, 13}, - {9269, 13, 1, 6, 2, 12, 12, 22, 15, 12, 12, 5, 14}, - {9103, 13, 1, 6, 2, 12, 12, 23, 15, 13, 12, 5, 13}, - {8946, 13, 1, 6, 2, 12, 12, 24, 15, 13, 12, 5, 13}, - {8797, 12, 1, 7, 2, 12, 12, 24, 15, 13, 12, 5, 13}, - {8655, 12, 1, 7, 2, 12, 12, 25, 15, 13, 12, 5, 13}, - {8520, 12, 1, 7, 2, 12, 12, 25, 15, 13, 12, 5, 13}, - {8392, 12, 1, 7, 2, 12, 12, 26, 15, 13, 12, 5, 13}, - {8269, 12, 1, 7, 2, 12, 12, 27, 15, 13, 12, 5, 13}, - {8153, 12, 1, 7, 2, 12, 12, 28, 15, 13, 12, 5, 13}, - {8041, 12, 1, 7, 2, 13, 12, 29, 15, 13, 12, 5, 13}, - {7934, 11, 1, 7, 2, 12, 12, 28, 15, 13, 12, 5, 13}, - {7831, 11, 1, 7, 2, 12, 12, 29, 15, 13, 12, 5, 13}, - {7733, 10, 1, 7, 3, 13, 12, 28, 15, 13, 12, 5, 13}, - {7638, 10, 1, 7, 2, 12, 12, 29, 15, 13, 12, 5, 13}, - {7547, 10, 1, 7, 2, 12, 12, 29, 15, 13, 12, 5, 13}, - {7459, 10, 1, 7, 2, 12, 12, 30, 15, 13, 12, 5, 13}, - {7374, 10, 2, 7, 3, 14, 13, 24, 15, 13, 12, 5, 13}, - {7291, 10, 2, 7, 3, 14, 13, 25, 15, 13, 12, 5, 13}, - {7212, 10, 2, 7, 3, 14, 13, 25, 15, 13, 12, 5, 13}, - {7135, 10, 2, 7, 3, 14, 13, 26, 15, 13, 12, 5, 13}, - {7061, 10, 2, 7, 3, 14, 13, 26, 15, 13, 12, 5, 13}, - {6988, 10, 1, 7, 3, 12, 14, 35, 15, 13, 12, 5, 13}, - {6918, 9, 1, 7, 3, 12, 14, 33, 15, 13, 12, 5, 13}, - {6850, 9, 1, 7, 3, 12, 14, 34, 15, 13, 12, 5, 13}, - {6784, 9, 1, 7, 2, 11, 14, 35, 15, 13, 12, 5, 13}, - {6720, 9, 1, 7, 2, 11, 14, 35, 15, 13, 12, 5, 13}, - {6658, 8, 2, 7, 3, 15, 13, 26, 15, 13, 12, 5, 13}, - {6597, 8, 2, 7, 2, 15, 13, 27, 15, 13, 12, 5, 13}, - {6539, 8, 2, 7, 2, 15, 13, 27, 15, 13, 12, 5, 13}, - {6482, 8, 2, 7, 2, 15, 13, 28, 15, 13, 12, 5, 13}, - {6427, 7, 2, 7, 3, 14, 13, 27, 15, 13, 12, 5, 13}, - {6373, 7, 2, 7, 3, 15, 13, 27, 15, 13, 12, 5, 13}, - {6321, 7, 2, 7, 3, 15, 13, 27, 15, 13, 12, 5, 13}, - {6270, 7, 2, 7, 3, 15, 13, 28, 15, 13, 12, 5, 13}, - {6222, 7, 2, 7, 3, 15, 13, 28, 15, 13, 12, 5, 13}, - {6174, 6, 2, 7, 3, 15, 13, 27, 15, 13, 12, 5, 13}, - {6128, 6, 2, 7, 3, 15, 13, 27, 15, 13, 12, 5, 13}, - {6083, 6, 2, 7, 3, 15, 13, 28, 15, 13, 12, 5, 13}, - {6040, 6, 2, 7, 3, 15, 13, 28, 15, 13, 12, 5, 13}, - {5997, 6, 2, 7, 3, 15, 13, 29, 15, 13, 12, 5, 13}, -}, { - {12605, 13, 1, 4, 2, 15, 12, 7, 15, 6, 13, 5, 14}, /* 80 MHz */ - {12245, 13, 1, 4, 2, 15, 12, 7, 15, 6, 13, 5, 14}, - {11906, 13, 1, 4, 2, 15, 12, 7, 15, 6, 13, 5, 14}, - {11588, 13, 1, 4, 2, 15, 12, 7, 14, 6, 14, 4, 14}, - {11288, 13, 1, 4, 2, 15, 12, 8, 15, 6, 13, 5, 14}, - {11007, 13, 1, 4, 2, 15, 12, 8, 14, 6, 13, 5, 14}, - {10742, 13, 1, 4, 2, 15, 12, 9, 15, 6, 13, 5, 14}, - {10492, 13, 1, 6, 2, 15, 12, 9, 14, 6, 13, 5, 14}, - {10258, 13, 1, 6, 2, 15, 12, 10, 15, 6, 13, 5, 14}, - {10036, 13, 1, 6, 2, 15, 12, 10, 15, 6, 13, 5, 14}, - {9827, 13, 1, 6, 2, 14, 12, 11, 15, 6, 13, 5, 14}, - {9631, 13, 1, 6, 2, 13, 12, 11, 15, 6, 13, 5, 14}, - {9445, 13, 1, 6, 2, 12, 12, 12, 15, 6, 13, 5, 14}, - {9269, 13, 1, 6, 2, 12, 12, 12, 15, 6, 13, 5, 14}, - {9103, 13, 1, 6, 2, 12, 12, 13, 15, 6, 13, 5, 14}, - {8946, 13, 1, 6, 2, 12, 12, 13, 15, 6, 13, 5, 14}, - {8797, 12, 1, 7, 2, 12, 12, 13, 15, 6, 13, 5, 14}, - {8655, 12, 1, 7, 2, 12, 12, 14, 15, 6, 13, 5, 14}, - {8520, 12, 1, 7, 2, 12, 12, 14, 15, 6, 13, 5, 14}, - {8392, 12, 1, 7, 2, 12, 12, 15, 15, 7, 13, 5, 14}, - {8269, 12, 1, 7, 2, 12, 12, 15, 15, 6, 13, 5, 14}, - {8153, 12, 1, 7, 2, 12, 12, 15, 15, 6, 13, 5, 14}, - {8041, 12, 1, 7, 2, 13, 12, 16, 15, 6, 13, 5, 14}, - {7934, 11, 1, 7, 2, 12, 12, 15, 15, 6, 13, 5, 14}, - {7831, 11, 1, 7, 2, 12, 12, 16, 15, 6, 13, 5, 14}, - {7733, 10, 1, 7, 3, 13, 12, 15, 15, 6, 13, 5, 14}, - {7638, 10, 1, 7, 2, 12, 12, 16, 15, 6, 13, 5, 14}, - {7547, 10, 1, 7, 2, 12, 12, 16, 15, 6, 13, 5, 14}, - {7459, 10, 1, 7, 2, 12, 12, 17, 15, 6, 13, 5, 14}, - {7374, 10, 2, 7, 3, 14, 13, 13, 15, 6, 13, 5, 14}, - {7291, 10, 2, 7, 3, 14, 13, 14, 15, 6, 13, 5, 14}, - {7212, 10, 2, 7, 3, 14, 13, 14, 15, 6, 13, 5, 14}, - {7135, 10, 2, 7, 3, 14, 13, 14, 15, 6, 13, 5, 14}, - {7061, 10, 2, 7, 3, 14, 13, 15, 15, 6, 13, 5, 14}, - {6988, 10, 1, 7, 3, 12, 14, 19, 15, 6, 13, 5, 14}, - {6918, 9, 2, 7, 3, 14, 13, 14, 15, 6, 13, 5, 14}, - {6850, 9, 2, 7, 3, 14, 13, 15, 15, 6, 13, 5, 14}, - {6784, 9, 2, 7, 2, 13, 13, 15, 15, 6, 13, 5, 14}, - {6720, 9, 2, 7, 2, 13, 13, 15, 15, 6, 13, 5, 14}, - {6658, 8, 2, 7, 3, 14, 13, 15, 15, 6, 13, 5, 14}, - {6597, 8, 2, 7, 2, 13, 13, 15, 15, 6, 13, 5, 14}, - {6539, 8, 2, 7, 2, 13, 13, 15, 15, 6, 13, 5, 14}, - {6482, 8, 2, 7, 2, 13, 13, 15, 15, 6, 13, 5, 14}, - {6427, 7, 2, 7, 3, 14, 13, 15, 15, 6, 13, 5, 14}, - {6373, 7, 2, 7, 3, 15, 13, 15, 15, 6, 13, 5, 14}, - {6321, 7, 2, 7, 3, 15, 13, 15, 15, 6, 13, 5, 14}, - {6270, 7, 2, 7, 3, 15, 13, 15, 15, 6, 13, 5, 14}, - {6222, 7, 2, 7, 3, 15, 13, 16, 15, 6, 13, 5, 14}, - {6174, 6, 2, 7, 3, 15, 13, 15, 15, 6, 13, 5, 14}, - {6128, 6, 2, 7, 3, 15, 13, 15, 15, 6, 13, 5, 14}, - {6083, 6, 2, 7, 3, 15, 13, 15, 15, 6, 13, 5, 14}, - {6040, 6, 2, 7, 3, 15, 13, 16, 15, 6, 13, 5, 14}, - {5997, 6, 2, 7, 3, 15, 13, 16, 15, 6, 13, 5, 14}, -}}; - -static struct SynthLUT SynthLUT_TDD[LUT_FTDD_ENT][SYNTH_LUT_SIZE] = { -{ - {12605, 13, 1, 4, 2, 15, 12, 27, 12, 15, 12, 4, 13}, /* 40 MHz */ - {12245, 13, 1, 4, 2, 15, 12, 27, 12, 15, 12, 4, 13}, - {11906, 13, 1, 4, 2, 15, 12, 26, 11, 15, 12, 4, 13}, - {11588, 13, 1, 4, 2, 15, 12, 28, 12, 15, 12, 4, 13}, - {11288, 13, 1, 4, 2, 15, 12, 30, 12, 15, 12, 4, 13}, - {11007, 13, 1, 4, 2, 15, 12, 32, 12, 15, 12, 4, 13}, - {10742, 13, 1, 4, 2, 15, 12, 33, 12, 15, 12, 4, 13}, - {10492, 13, 1, 6, 2, 15, 12, 35, 12, 15, 12, 4, 13}, - {10258, 13, 1, 6, 2, 15, 12, 37, 12, 15, 12, 4, 13}, - {10036, 13, 1, 6, 2, 15, 12, 38, 12, 15, 12, 4, 13}, - {9827, 13, 1, 6, 2, 14, 12, 40, 12, 15, 12, 4, 13}, - {9631, 13, 1, 6, 2, 13, 12, 42, 12, 15, 12, 4, 13}, - {9445, 13, 1, 6, 2, 12, 12, 44, 12, 15, 12, 4, 13}, - {9269, 13, 1, 6, 2, 12, 12, 45, 12, 15, 12, 4, 13}, - {9103, 13, 1, 6, 2, 12, 12, 47, 12, 15, 12, 4, 13}, - {8946, 13, 1, 6, 2, 12, 12, 49, 12, 15, 12, 4, 13}, - {8797, 12, 1, 7, 2, 12, 12, 48, 12, 15, 12, 4, 13}, - {8655, 12, 1, 7, 2, 12, 12, 50, 12, 15, 12, 4, 13}, - {8520, 12, 1, 7, 2, 12, 12, 51, 12, 15, 12, 4, 13}, - {8392, 12, 1, 7, 2, 12, 12, 53, 12, 15, 12, 4, 13}, - {8269, 12, 1, 7, 2, 12, 12, 55, 12, 15, 12, 4, 13}, - {8153, 12, 1, 7, 2, 12, 12, 56, 12, 15, 12, 4, 13}, - {8041, 12, 1, 7, 2, 13, 12, 58, 12, 15, 12, 4, 13}, - {7934, 11, 1, 7, 2, 12, 12, 57, 12, 15, 12, 4, 13}, - {7831, 11, 1, 7, 2, 12, 12, 58, 12, 15, 12, 4, 13}, - {7733, 10, 1, 7, 3, 13, 12, 56, 12, 15, 12, 4, 13}, - {7638, 10, 1, 7, 2, 12, 12, 58, 12, 15, 12, 4, 13}, - {7547, 10, 1, 7, 2, 12, 12, 59, 12, 15, 12, 4, 13}, - {7459, 10, 1, 7, 2, 12, 12, 61, 12, 15, 12, 4, 13}, - {7374, 10, 2, 7, 3, 14, 13, 49, 12, 15, 12, 4, 13}, - {7291, 10, 2, 7, 3, 14, 13, 50, 12, 15, 12, 4, 13}, - {7212, 10, 2, 7, 3, 14, 13, 51, 12, 15, 12, 4, 13}, - {7135, 10, 2, 7, 3, 14, 13, 52, 12, 15, 12, 4, 13}, - {7061, 10, 2, 7, 3, 14, 13, 53, 12, 15, 12, 4, 13}, - {6988, 10, 1, 7, 3, 12, 14, 63, 11, 14, 12, 3, 13}, - {6918, 9, 2, 7, 3, 14, 13, 52, 12, 15, 12, 4, 13}, - {6850, 9, 2, 7, 3, 14, 13, 53, 12, 15, 12, 4, 13}, - {6784, 9, 2, 7, 2, 13, 13, 54, 12, 15, 12, 4, 13}, - {6720, 9, 2, 7, 2, 13, 13, 56, 12, 15, 12, 4, 13}, - {6658, 8, 2, 7, 3, 14, 13, 53, 12, 15, 12, 4, 13}, - {6597, 8, 2, 7, 2, 13, 13, 54, 12, 15, 12, 4, 13}, - {6539, 8, 2, 7, 2, 13, 13, 55, 12, 15, 12, 4, 13}, - {6482, 8, 2, 7, 2, 13, 13, 56, 12, 15, 12, 4, 13}, - {6427, 7, 2, 7, 3, 14, 13, 54, 12, 15, 12, 4, 13}, - {6373, 7, 2, 7, 3, 15, 13, 54, 12, 15, 12, 4, 13}, - {6321, 7, 2, 7, 3, 15, 13, 55, 12, 15, 12, 4, 13}, - {6270, 7, 2, 7, 3, 15, 13, 56, 12, 15, 12, 4, 13}, - {6222, 7, 2, 7, 3, 15, 13, 57, 12, 15, 12, 4, 13}, - {6174, 6, 2, 7, 3, 15, 13, 54, 12, 15, 12, 4, 13}, - {6128, 6, 2, 7, 3, 15, 13, 55, 12, 15, 12, 4, 13}, - {6083, 6, 2, 7, 3, 15, 13, 56, 12, 15, 12, 4, 13}, - {6040, 6, 2, 7, 3, 15, 13, 57, 12, 15, 12, 4, 13}, - {5997, 6, 2, 7, 3, 15, 13, 58, 12, 15, 12, 4, 13}, -}, { - {12605, 13, 1, 4, 2, 15, 12, 26, 11, 15, 11, 4, 13}, /* 60 MHz */ - {12245, 13, 1, 4, 2, 15, 12, 26, 11, 15, 11, 4, 13}, - {11906, 13, 1, 4, 2, 15, 12, 26, 12, 15, 11, 4, 12}, - {11588, 13, 1, 4, 2, 15, 12, 30, 12, 15, 11, 4, 12}, - {11288, 13, 1, 4, 2, 15, 12, 32, 12, 15, 10, 4, 12}, - {11007, 13, 1, 4, 2, 15, 12, 31, 12, 15, 11, 4, 12}, - {10742, 13, 1, 4, 2, 15, 12, 33, 12, 15, 10, 4, 12}, - {10492, 13, 1, 6, 2, 15, 12, 37, 12, 15, 10, 4, 12}, - {10258, 13, 1, 6, 2, 15, 12, 38, 12, 15, 11, 4, 13}, - {10036, 13, 1, 6, 2, 15, 12, 38, 12, 15, 10, 4, 12}, - {9827, 13, 1, 6, 2, 14, 12, 42, 12, 15, 11, 4, 12}, - {9631, 13, 1, 6, 2, 13, 12, 41, 12, 15, 11, 4, 12}, - {9445, 13, 1, 6, 2, 12, 12, 45, 12, 15, 11, 4, 12}, - {9269, 13, 1, 6, 2, 12, 12, 47, 12, 15, 11, 4, 12}, - {9103, 13, 1, 6, 2, 12, 12, 46, 12, 15, 11, 4, 12}, - {8946, 13, 1, 6, 2, 12, 12, 48, 12, 15, 10, 4, 12}, - {8797, 12, 1, 7, 2, 12, 12, 49, 12, 15, 11, 4, 13}, - {8655, 12, 1, 7, 2, 12, 12, 51, 12, 15, 11, 4, 12}, - {8520, 12, 1, 7, 2, 12, 12, 50, 12, 15, 11, 4, 12}, - {8392, 12, 1, 7, 2, 12, 12, 52, 12, 15, 10, 4, 12}, - {8269, 12, 1, 7, 2, 12, 12, 56, 12, 15, 10, 4, 12}, - {8153, 12, 1, 7, 2, 12, 12, 55, 12, 15, 11, 4, 12}, - {8041, 12, 1, 7, 2, 13, 12, 57, 12, 15, 10, 4, 12}, - {7934, 11, 1, 7, 2, 12, 12, 55, 12, 15, 11, 4, 12}, - {7831, 11, 1, 7, 2, 12, 12, 57, 12, 15, 10, 4, 12}, - {7733, 10, 1, 7, 3, 13, 12, 55, 12, 15, 11, 4, 12}, - {7638, 10, 1, 7, 2, 12, 12, 59, 12, 15, 10, 4, 12}, - {7547, 10, 1, 7, 2, 12, 12, 60, 12, 15, 11, 4, 12}, - {7459, 10, 1, 7, 2, 12, 12, 48, 12, 15, 11, 4, 12}, - {7374, 10, 2, 7, 3, 14, 13, 47, 12, 15, 11, 4, 13}, - {7291, 10, 2, 7, 3, 14, 13, 49, 12, 15, 10, 4, 12}, - {7212, 10, 2, 7, 3, 14, 13, 50, 12, 15, 10, 4, 12}, - {7135, 10, 2, 7, 3, 14, 13, 52, 12, 15, 11, 4, 13}, - {7061, 10, 2, 7, 3, 14, 13, 52, 12, 15, 11, 4, 12}, - {6988, 10, 1, 7, 3, 12, 14, 63, 11, 15, 11, 4, 13}, - {6918, 9, 1, 7, 3, 12, 14, 63, 11, 15, 11, 4, 13}, - {6850, 9, 1, 7, 3, 12, 14, 63, 11, 15, 11, 4, 13}, - {6784, 9, 1, 7, 2, 11, 14, 63, 11, 15, 11, 4, 13}, - {6720, 9, 1, 7, 2, 11, 14, 63, 11, 14, 11, 3, 13}, - {6658, 8, 1, 7, 3, 12, 14, 63, 11, 15, 11, 4, 13}, - {6597, 8, 1, 7, 2, 11, 14, 63, 11, 14, 11, 3, 13}, - {6539, 8, 1, 7, 2, 11, 14, 63, 10, 14, 11, 3, 13}, - {6482, 8, 1, 7, 2, 11, 14, 63, 10, 14, 11, 3, 13}, - {6427, 7, 2, 7, 3, 14, 13, 54, 12, 15, 10, 4, 12}, - {6373, 7, 2, 7, 3, 15, 13, 53, 12, 15, 11, 4, 12}, - {6321, 7, 2, 7, 3, 15, 13, 54, 12, 15, 11, 4, 12}, - {6270, 7, 2, 7, 3, 15, 13, 55, 12, 15, 11, 4, 12}, - {6222, 7, 2, 7, 3, 15, 13, 56, 12, 15, 11, 4, 12}, - {6174, 6, 2, 7, 3, 15, 13, 53, 12, 15, 11, 4, 12}, - {6128, 6, 2, 7, 3, 15, 13, 55, 12, 15, 11, 4, 12}, - {6083, 6, 2, 7, 3, 15, 13, 55, 12, 15, 10, 4, 12}, - {6040, 6, 2, 7, 3, 15, 13, 56, 12, 15, 10, 4, 12}, - {5997, 6, 2, 7, 3, 15, 13, 57, 12, 15, 10, 4, 12}, -}, { - {12605, 13, 1, 4, 2, 15, 12, 21, 12, 15, 11, 4, 13}, /* 80 MHz */ - {12245, 13, 1, 4, 2, 15, 12, 21, 12, 15, 11, 4, 13}, - {11906, 13, 1, 4, 2, 15, 12, 20, 11, 15, 11, 4, 13}, - {11588, 13, 1, 4, 2, 15, 12, 22, 12, 15, 11, 4, 12}, - {11288, 13, 1, 5, 2, 15, 12, 23, 12, 15, 11, 4, 13}, - {11007, 13, 1, 5, 2, 15, 12, 25, 12, 15, 10, 4, 12}, - {10742, 13, 1, 5, 2, 15, 12, 26, 12, 15, 11, 4, 13}, - {10492, 13, 1, 6, 2, 15, 12, 27, 11, 15, 11, 4, 13}, - {10258, 13, 1, 6, 2, 15, 12, 29, 12, 15, 10, 4, 12}, - {10036, 13, 1, 6, 2, 15, 12, 30, 12, 15, 11, 4, 12}, - {9827, 13, 1, 6, 2, 14, 12, 31, 12, 15, 11, 4, 13}, - {9631, 13, 1, 6, 2, 13, 12, 33, 12, 15, 10, 4, 12}, - {9445, 13, 1, 6, 2, 12, 12, 34, 12, 15, 11, 4, 12}, - {9269, 13, 1, 6, 2, 12, 12, 35, 12, 15, 11, 4, 13}, - {9103, 13, 1, 6, 2, 12, 12, 37, 12, 15, 10, 4, 12}, - {8946, 13, 1, 6, 2, 12, 12, 38, 12, 15, 11, 4, 12}, - {8797, 12, 1, 7, 2, 12, 12, 37, 12, 15, 11, 4, 13}, - {8655, 12, 1, 7, 2, 12, 12, 39, 12, 15, 11, 4, 12}, - {8520, 12, 1, 7, 2, 12, 12, 40, 12, 15, 11, 4, 12}, - {8392, 12, 1, 7, 2, 12, 12, 41, 12, 15, 11, 4, 13}, - {8269, 12, 1, 7, 2, 12, 12, 43, 12, 15, 10, 4, 12}, - {8153, 12, 1, 7, 2, 12, 12, 44, 12, 15, 11, 4, 12}, - {8041, 12, 1, 7, 2, 13, 12, 45, 12, 15, 11, 4, 12}, - {7934, 11, 1, 7, 2, 12, 12, 44, 12, 15, 11, 4, 12}, - {7831, 11, 1, 7, 2, 12, 12, 45, 12, 15, 11, 4, 13}, - {7733, 10, 1, 7, 3, 13, 12, 44, 12, 15, 11, 4, 12}, - {7638, 10, 1, 7, 2, 12, 12, 45, 12, 15, 11, 4, 12}, - {7547, 10, 1, 7, 2, 12, 12, 46, 12, 15, 11, 4, 12}, - {7459, 10, 1, 7, 2, 12, 12, 47, 12, 15, 11, 4, 13}, - {7374, 10, 2, 7, 3, 14, 13, 38, 12, 15, 11, 4, 12}, - {7291, 10, 2, 7, 3, 14, 13, 39, 12, 15, 10, 4, 12}, - {7212, 10, 2, 7, 3, 14, 13, 40, 12, 15, 10, 4, 12}, - {7135, 10, 2, 7, 3, 14, 13, 41, 12, 15, 10, 4, 12}, - {7061, 10, 2, 7, 3, 14, 13, 41, 12, 15, 11, 4, 13}, - {6988, 10, 1, 7, 3, 12, 14, 54, 12, 15, 11, 4, 12}, - {6918, 9, 2, 7, 3, 14, 13, 41, 12, 15, 10, 4, 12}, - {6850, 9, 2, 7, 3, 14, 13, 42, 12, 15, 10, 4, 12}, - {6784, 9, 2, 7, 2, 13, 13, 42, 12, 15, 11, 4, 13}, - {6720, 9, 2, 7, 2, 13, 13, 43, 12, 15, 11, 4, 13}, - {6658, 8, 2, 7, 3, 14, 13, 41, 12, 15, 11, 4, 13}, - {6597, 8, 2, 7, 2, 13, 13, 42, 12, 15, 11, 4, 12}, - {6539, 8, 2, 7, 2, 13, 13, 43, 12, 15, 11, 4, 12}, - {6482, 8, 2, 7, 2, 13, 13, 44, 12, 15, 11, 4, 12}, - {6427, 7, 2, 7, 3, 14, 13, 42, 12, 15, 10, 4, 12}, - {6373, 7, 2, 7, 3, 15, 13, 42, 12, 15, 11, 4, 13}, - {6321, 7, 2, 7, 3, 15, 13, 43, 12, 15, 11, 4, 12}, - {6270, 7, 2, 7, 3, 15, 13, 44, 12, 15, 11, 4, 12}, - {6222, 7, 2, 7, 3, 15, 13, 45, 12, 15, 10, 4, 12}, - {6174, 6, 2, 7, 3, 15, 13, 42, 12, 15, 11, 4, 13}, - {6128, 6, 2, 7, 3, 15, 13, 43, 12, 15, 11, 4, 12}, - {6083, 6, 2, 7, 3, 15, 13, 44, 12, 15, 10, 4, 12}, - {6040, 6, 2, 7, 3, 15, 13, 44, 12, 15, 11, 4, 13}, - {5997, 6, 2, 7, 3, 15, 13, 45, 12, 15, 11, 4, 12}, -}}; - -/* Rx Gain Tables */ - -#define SIZE_FULL_TABLE 77 - -static const u8 full_gain_table[RXGAIN_TBLS_END][SIZE_FULL_TABLE][3] = -{{ /* 800 MHz */ - {0x00, 0x00, 0x20}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, - {0x00, 0x01, 0x00}, {0x00, 0x02, 0x00}, {0x00, 0x03, 0x00}, - {0x00, 0x04, 0x00}, {0x00, 0x05, 0x00}, {0x01, 0x03, 0x20}, - {0x01, 0x04, 0x00}, {0x01, 0x05, 0x00}, {0x01, 0x06, 0x00}, - {0x01, 0x07, 0x00}, {0x01, 0x08, 0x00}, {0x01, 0x09, 0x00}, - {0x01, 0x0A, 0x00}, {0x01, 0x0B, 0x00}, {0x01, 0x0C, 0x00}, - {0x01, 0x0D, 0x00}, {0x01, 0x0E, 0x00}, {0x02, 0x09, 0x20}, - {0x02, 0x0A, 0x00}, {0x02, 0x0B, 0x00}, {0x02, 0x0C, 0x00}, - {0x02, 0x0D, 0x00}, {0x02, 0x0E, 0x00}, {0x02, 0x0F, 0x00}, - {0x02, 0x10, 0x00}, {0x02, 0x2B, 0x20}, {0x02, 0x2C, 0x00}, - {0x04, 0x28, 0x20}, {0x04, 0x29, 0x00}, {0x04, 0x2A, 0x00}, - {0x04, 0x2B, 0x00}, {0x24, 0x20, 0x20}, {0x24, 0x21, 0x00}, - {0x44, 0x20, 0x20}, {0x44, 0x21, 0x00}, {0x44, 0x22, 0x00}, - {0x44, 0x23, 0x00}, {0x44, 0x24, 0x00}, {0x44, 0x25, 0x00}, - {0x44, 0x26, 0x00}, {0x44, 0x27, 0x00}, {0x44, 0x28, 0x00}, - {0x44, 0x29, 0x00}, {0x44, 0x2A, 0x00}, {0x44, 0x2B, 0x00}, - {0x44, 0x2C, 0x00}, {0x44, 0x2D, 0x00}, {0x44, 0x2E, 0x00}, - {0x44, 0x2F, 0x00}, {0x44, 0x30, 0x00}, {0x44, 0x31, 0x00}, - {0x44, 0x32, 0x00}, {0x64, 0x2E, 0x20}, {0x64, 0x2F, 0x00}, - {0x64, 0x30, 0x00}, {0x64, 0x31, 0x00}, {0x64, 0x32, 0x00}, - {0x64, 0x33, 0x00}, {0x64, 0x34, 0x00}, {0x64, 0x35, 0x00}, - {0x64, 0x36, 0x00}, {0x64, 0x37, 0x00}, {0x64, 0x38, 0x00}, - {0x65, 0x38, 0x20}, {0x66, 0x38, 0x20}, {0x67, 0x38, 0x20}, - {0x68, 0x38, 0x20}, {0x69, 0x38, 0x20}, {0x6A, 0x38, 0x20}, - {0x6B, 0x38, 0x20}, {0x6C, 0x38, 0x20}, {0x6D, 0x38, 0x20}, - {0x6E, 0x38, 0x20}, {0x6F, 0x38, 0x20} -},{ /* 2300 MHz */ - {0x00, 0x00, 0x20}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, - {0x00, 0x01, 0x00}, {0x00, 0x02, 0x00}, {0x00, 0x03, 0x00}, - {0x00, 0x04, 0x00}, {0x00, 0x05, 0x00}, {0x01, 0x03, 0x20}, - {0x01, 0x04, 0x00}, {0x01, 0x05, 0x00}, {0x01, 0x06, 0x00}, - {0x01, 0x07, 0x00}, {0x01, 0x08, 0x00}, {0x01, 0x09, 0x00}, - {0x01, 0x0A, 0x00}, {0x01, 0x0B, 0x00}, {0x01, 0x0C, 0x00}, - {0x01, 0x0D, 0x00}, {0x01, 0x0E, 0x00}, {0x02, 0x09, 0x20}, - {0x02, 0x0A, 0x00}, {0x02, 0x0B, 0x00}, {0x02, 0x0C, 0x00}, - {0x02, 0x0D, 0x00}, {0x02, 0x0E, 0x00}, {0x02, 0x0F, 0x00}, - {0x02, 0x10, 0x00}, {0x02, 0x2B, 0x20}, {0x02, 0x2C, 0x00}, - {0x04, 0x27, 0x20}, {0x04, 0x28, 0x00}, {0x04, 0x29, 0x00}, - {0x04, 0x2A, 0x00}, {0x04, 0x2B, 0x00}, {0x24, 0x21, 0x20}, - {0x24, 0x22, 0x00}, {0x44, 0x20, 0x20}, {0x44, 0x21, 0x00}, - {0x44, 0x22, 0x00}, {0x44, 0x23, 0x00}, {0x44, 0x24, 0x00}, - {0x44, 0x25, 0x00}, {0x44, 0x26, 0x00}, {0x44, 0x27, 0x00}, - {0x44, 0x28, 0x00}, {0x44, 0x29, 0x00}, {0x44, 0x2A, 0x00}, - {0x44, 0x2B, 0x00}, {0x44, 0x2C, 0x00}, {0x44, 0x2D, 0x00}, - {0x44, 0x2E, 0x00}, {0x44, 0x2F, 0x00}, {0x44, 0x30, 0x00}, - {0x44, 0x31, 0x00}, {0x64, 0x2E, 0x20}, {0x64, 0x2F, 0x00}, - {0x64, 0x30, 0x00}, {0x64, 0x31, 0x00}, {0x64, 0x32, 0x00}, - {0x64, 0x33, 0x00}, {0x64, 0x34, 0x00}, {0x64, 0x35, 0x00}, - {0x64, 0x36, 0x00}, {0x64, 0x37, 0x00}, {0x64, 0x38, 0x00}, - {0x65, 0x38, 0x20}, {0x66, 0x38, 0x20}, {0x67, 0x38, 0x20}, - {0x68, 0x38, 0x20}, {0x69, 0x38, 0x20}, {0x6A, 0x38, 0x20}, - {0x6B, 0x38, 0x20}, {0x6C, 0x38, 0x20}, {0x6D, 0x38, 0x20}, - {0x6E, 0x38, 0x20}, {0x6F, 0x38, 0x20}, -},{ /* 5500 MHz */ - {0x00, 0x00, 0x20}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, - {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x01, 0x00}, - {0x00, 0x02, 0x00}, {0x00, 0x03, 0x00}, {0x01, 0x01, 0x20}, - {0x01, 0x02, 0x00}, {0x01, 0x03, 0x00}, {0x01, 0x04, 0x20}, - {0x01, 0x05, 0x00}, {0x01, 0x06, 0x00}, {0x01, 0x07, 0x00}, - {0x01, 0x08, 0x00}, {0x01, 0x09, 0x00}, {0x01, 0x0A, 0x00}, - {0x01, 0x0B, 0x00}, {0x01, 0x0C, 0x00}, {0x02, 0x08, 0x20}, - {0x02, 0x09, 0x00}, {0x02, 0x0A, 0x00}, {0x02, 0x0B, 0x20}, - {0x02, 0x0C, 0x00}, {0x02, 0x0D, 0x00}, {0x02, 0x0E, 0x00}, - {0x02, 0x0F, 0x00}, {0x02, 0x2A, 0x20}, {0x02, 0x2B, 0x00}, - {0x04, 0x27, 0x20}, {0x04, 0x28, 0x00}, {0x04, 0x29, 0x00}, - {0x04, 0x2A, 0x00}, {0x04, 0x2B, 0x00}, {0x04, 0x2C, 0x00}, - {0x04, 0x2D, 0x00}, {0x24, 0x20, 0x20}, {0x24, 0x21, 0x00}, - {0x24, 0x22, 0x00}, {0x44, 0x20, 0x20}, {0x44, 0x21, 0x00}, - {0x44, 0x22, 0x00}, {0x44, 0x23, 0x00}, {0x44, 0x24, 0x00}, - {0x44, 0x25, 0x00}, {0x44, 0x26, 0x00}, {0x44, 0x27, 0x00}, - {0x44, 0x28, 0x00}, {0x44, 0x29, 0x00}, {0x44, 0x2A, 0x00}, - {0x44, 0x2B, 0x00}, {0x44, 0x2C, 0x00}, {0x44, 0x2D, 0x00}, - {0x44, 0x2E, 0x00}, {0x64, 0x2E, 0x20}, {0x64, 0x2F, 0x00}, - {0x64, 0x30, 0x00}, {0x64, 0x31, 0x00}, {0x64, 0x32, 0x00}, - {0x64, 0x33, 0x00}, {0x64, 0x34, 0x00}, {0x64, 0x35, 0x00}, - {0x64, 0x36, 0x00}, {0x64, 0x37, 0x00}, {0x64, 0x38, 0x00}, - {0x65, 0x38, 0x20}, {0x66, 0x38, 0x20}, {0x67, 0x38, 0x20}, - {0x68, 0x38, 0x20}, {0x69, 0x38, 0x20}, {0x6A, 0x38, 0x20}, - {0x6B, 0x38, 0x20}, {0x6C, 0x38, 0x20}, {0x6D, 0x38, 0x20}, - {0x6E, 0x38, 0x20}, {0x6F, 0x38, 0x20} -}}; - -static const s8 full_gain_table_abs_gain[RXGAIN_TBLS_END][SIZE_FULL_TABLE] = -{{ /* 800 MHz */ - -1, -1, -1, 0, 1, 2, 3, 4, - 5, 6, 7, 8, 9, 10, 11, 12, - 13, 14, 15, 16, 17, 18, 19, 20, - 21, 22, 23, 24, 25, 26, 27, 28, - 29, 30, 31, 32, 33, 34, 35, 36, - 37, 38, 39, 40, 41, 42, 43, 44, - 45, 46, 47, 48, 49, 50, 51, 52, - 53, 54, 55, 56, 57, 58, 59, 60, - 61, 62, 63, 64, 65, 66, 67, 68, - 69, 70, 71, 72, 73 -}, { /* 2300 MHz */ - -3, -3, -3, -2, -1, 0, 1, 2, - 3, 4, 5, 6, 7, 8, 9, 10, - 11, 12, 13, 14, 15, 16, 17, 18, - 19, 20, 21, 22, 23, 24, 25, 26, - 27, 28, 29, 30, 31, 32, 33, 34, - 35, 36, 37, 38, 39, 40, 41, 42, - 43, 44, 45, 46, 47, 48, 49, 50, - 51, 52, 53, 54, 55, 56, 57, 58, - 59, 60, 61, 62, 63, 64, 65, 66, - 67, 68, 69, 70, 71 -}, { /* 5500 MHz */ - -10, -10, -10, -10, -10, -9, -8, -7, - -6, -5, -4, -3, -2, -1, 0, 1, - 2, 3, 4, 5, 6, 7, 8, 9, - 10, 11, 12, 13, 14, 15, 16, 17, - 18, 19, 20, 21, 22, 23, 24, 25, - 26, 27, 28, 29, 30, 31, 32, 33, - 34, 35, 36, 37, 38, 39, 40, 41, - 42, 43, 44, 45, 46, 47, 48, 49, - 50, 51, 52, 53, 54, 55, 56, 57, - 58, 59, 60, 61, 62 -}}; - -#define SIZE_SPLIT_TABLE 41 - -static const u8 split_gain_table[RXGAIN_TBLS_END][SIZE_SPLIT_TABLE][3] = -{{ /* 800 MHz */ - {0x00, 0x18, 0x20}, {0x00, 0x18, 0x00}, {0x00, 0x18, 0x00}, - {0x00, 0x18, 0x00}, {0x00, 0x18, 0x00}, {0x00, 0x18, 0x00}, - {0x00, 0x18, 0x20}, {0x01, 0x18, 0x20}, {0x02, 0x18, 0x20}, - {0x04, 0x18, 0x20}, {0x04, 0x38, 0x20}, {0x05, 0x38, 0x20}, - {0x06, 0x38, 0x20}, {0x07, 0x38, 0x20}, {0x08, 0x38, 0x20}, - {0x09, 0x38, 0x20}, {0x0A, 0x38, 0x20}, {0x0B, 0x38, 0x20}, - {0x0C, 0x38, 0x20}, {0x0D, 0x38, 0x20}, {0x0E, 0x38, 0x20}, - {0x0F, 0x38, 0x20}, {0x24, 0x38, 0x20}, {0x25, 0x38, 0x20}, - {0x44, 0x38, 0x20}, {0x45, 0x38, 0x20}, {0x46, 0x38, 0x20}, - {0x47, 0x38, 0x20}, {0x48, 0x38, 0x20}, {0x64, 0x38, 0x20}, - {0x65, 0x38, 0x20}, {0x66, 0x38, 0x20}, {0x67, 0x38, 0x20}, - {0x68, 0x38, 0x20}, {0x69, 0x38, 0x20}, {0x6A, 0x38, 0x20}, - {0x6B, 0x38, 0x20}, {0x6C, 0x38, 0x20}, {0x6D, 0x38, 0x20}, - {0x6E, 0x38, 0x20}, {0x6F, 0x38, 0x20}, -},{ /* 2300 MHz */ - {0x00, 0x18, 0x20}, {0x00, 0x18, 0x00}, {0x00, 0x18, 0x00}, - {0x00, 0x18, 0x00}, {0x00, 0x18, 0x00}, {0x00, 0x18, 0x00}, - {0x00, 0x18, 0x00}, {0x00, 0x18, 0x20}, {0x01, 0x18, 0x20}, - {0x02, 0x18, 0x20}, {0x04, 0x18, 0x20}, {0x04, 0x38, 0x20}, - {0x05, 0x38, 0x20}, {0x06, 0x38, 0x20}, {0x07, 0x38, 0x20}, - {0x08, 0x38, 0x20}, {0x09, 0x38, 0x20}, {0x0A, 0x38, 0x20}, - {0x0B, 0x38, 0x20}, {0x0C, 0x38, 0x20}, {0x0D, 0x38, 0x20}, - {0x0E, 0x38, 0x20}, {0x0F, 0x38, 0x20}, {0x25, 0x38, 0x20}, - {0x26, 0x38, 0x20}, {0x44, 0x38, 0x20}, {0x45, 0x38, 0x20}, - {0x46, 0x38, 0x20}, {0x47, 0x38, 0x20}, {0x64, 0x38, 0x20}, - {0x65, 0x38, 0x20}, {0x66, 0x38, 0x20}, {0x67, 0x38, 0x20}, - {0x68, 0x38, 0x20}, {0x69, 0x38, 0x20}, {0x6A, 0x38, 0x20}, - {0x6B, 0x38, 0x20}, {0x6C, 0x38, 0x20}, {0x6D, 0x38, 0x20}, - {0x6E, 0x38, 0x20}, {0x6F, 0x38, 0x20}, -},{ /* 5500 MHz */ - {0x00, 0x18, 0x20}, {0x00, 0x18, 0x00}, {0x00, 0x18, 0x00}, - {0x00, 0x18, 0x00}, {0x00, 0x18, 0x00}, {0x00, 0x18, 0x00}, - {0x00, 0x18, 0x00}, {0x00, 0x18, 0x00}, {0x00, 0x18, 0x00}, - {0x00, 0x18, 0x00}, {0x01, 0x18, 0x20}, {0x02, 0x18, 0x20}, - {0x04, 0x18, 0x20}, {0x04, 0x38, 0x20}, {0x05, 0x38, 0x20}, - {0x06, 0x38, 0x20}, {0x07, 0x38, 0x20}, {0x08, 0x38, 0x20}, - {0x09, 0x38, 0x20}, {0x0A, 0x38, 0x20}, {0x0B, 0x38, 0x20}, - {0x0C, 0x38, 0x20}, {0x0D, 0x38, 0x20}, {0x0E, 0x38, 0x20}, - {0x0F, 0x38, 0x20}, {0x62, 0x38, 0x20}, {0x25, 0x38, 0x20}, - {0x26, 0x38, 0x20}, {0x44, 0x38, 0x20}, {0x64, 0x38, 0x20}, - {0x65, 0x38, 0x20}, {0x66, 0x38, 0x20}, {0x67, 0x38, 0x20}, - {0x68, 0x38, 0x20}, {0x69, 0x38, 0x20}, {0x6A, 0x38, 0x20}, - {0x6B, 0x38, 0x20}, {0x6C, 0x38, 0x20}, {0x6D, 0x38, 0x20}, - {0x6E, 0x38, 0x20}, {0x6F, 0x38, 0x20}, -}}; - - -static const u8 split_gain_table_abs_gain[RXGAIN_TBLS_END][SIZE_SPLIT_TABLE] = -{{ /* 800 MHz */ - -1, -1, -1, -1, -1, -1, -1, 2, - 8, 13, 19, 20, 21, 22, 23, 24, - 25, 26, 27, 28, 29, 30, 31, 32, - 33, 34, 35, 36, 37, 38, 39, 40, - 41, 42, 43, 44, 45, 46, 47, 48, - 49 -}, { /* 2300 MHz */ - -3, -3, -3, -3, -3, -3, -3, -3, - 0, 6, 12, 18, 19, 20, 21, 22, - 23, 24, 25, 26, 27, 28, 29, 30, - 31, 32, 33, 34, 35, 36, 37, 38, - 39, 40, 41, 42, 43, 44, 45, 46, - 47 -}, { /* 5500 MHz */ - -10, -10, -10, -10, -10, -10, -10, -10, - -10, -10, -7, -2, 3, 9, 10, 11, - 12, 13, 14, 15, 16, 17, 18, 19, - 20, 22, 24, 25, 26, 27, 28, 29, - 30, 31, 32, 33, 34, 35, 36, 37, - 38 -}}; - -struct gain_table_info { - u64 start; - u64 end; - u8 max_index; - u8 split_table; - s8 *abs_gain_tbl; - u8 (*tab)[3]; -}; - -static struct gain_table_info ad9361_adi_gt_info[] = { -{ - .start = 0, - .end = 1300000000ULL, - .max_index = SIZE_FULL_TABLE, - .abs_gain_tbl = (s8 *) &full_gain_table_abs_gain[TBL_200_1300_MHZ], - .tab = (u8 (*)[3]) full_gain_table[TBL_200_1300_MHZ], -},{ - .start = 1300000000ULL, - .end = 4000000000ULL, - .max_index = SIZE_FULL_TABLE, - .abs_gain_tbl = (s8 *) &full_gain_table_abs_gain[TBL_1300_4000_MHZ], - .tab = (u8 (*)[3]) full_gain_table[TBL_1300_4000_MHZ], -},{ - .start = 4000000000ULL, - .end = 6000000000ULL, - .max_index = SIZE_FULL_TABLE, - .abs_gain_tbl = (s8 *) &full_gain_table_abs_gain[TBL_4000_6000_MHZ], - .tab = (u8 (*)[3]) full_gain_table[TBL_4000_6000_MHZ], -},{ - .start = 0, - .end = 1300000000ULL, - .max_index = SIZE_SPLIT_TABLE, - .split_table = 1, - .abs_gain_tbl = (s8 *) &split_gain_table_abs_gain[TBL_200_1300_MHZ], - .tab = (u8 (*)[3]) split_gain_table[TBL_200_1300_MHZ], -},{ - .start = 1300000000ULL, - .end = 4000000000ULL, - .max_index = SIZE_SPLIT_TABLE, - .split_table = 1, - .abs_gain_tbl = (s8 *) &split_gain_table_abs_gain[TBL_1300_4000_MHZ], - .tab = (u8 (*)[3]) split_gain_table[TBL_1300_4000_MHZ], -},{ - .start = 4000000000ULL, - .end = 6000000000ULL, - .max_index = SIZE_SPLIT_TABLE, - .split_table = 1, - .abs_gain_tbl = (s8 *) &split_gain_table_abs_gain[TBL_4000_6000_MHZ], - .tab = (u8 (*)[3]) split_gain_table[TBL_4000_6000_MHZ], -},{ }, /* Don't Remove */ -}; - - -/* Mixer GM Sub-table */ - -static const u8 gm_st_gain[16]= {0x78, 0x74, 0x70, 0x6C, 0x68, 0x64, 0x60, - 0x5C, 0x58, 0x54, 0x50, 0x4C, 0x48, 0x30, 0x18, 0x0}; -static const u8 gm_st_ctrl[16]= {0x0, 0xD, 0x15, 0x1B, 0x21, 0x25, 0x29, - 0x2C, 0x2F, 0x31, 0x33, 0x34, 0x35, 0x3A, 0x3D, 0x3E}; - - -static const s8 lna_table[RXGAIN_TBLS_END][4] = { - {5, 17, 19, 24}, {3, 14, 17, 21}, {-4, 10, 13, 14}}; -static const s8 tia_table[] = {-6, 0}; -static const s8 mixer_table[RXGAIN_TBLS_END][16] = { - {0, 3, 9, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25}, - {0, 3, 9, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26}, - {0, 3, 8, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24}}; - -static const u32 gain_step_calib_reg_val[4][5] = { - {0xC0, 0x2E, 0x10, 0x06, 0x00}, // LO Frequency Range: 600 to 1300 MHz - {0xC0, 0x2C, 0x10, 0x06, 0x00}, // LO Frequency Range: 1300 to 3300 MHz - {0xB8, 0x2C, 0x10, 0x06, 0x00}, // LO Frequency Range: 2700 to 4100 MHz - {0xA0, 0x24, 0x10, 0x06, 0x00}, // LO Frequency Range: 4000 to 6000 MHz -}; - -#ifdef _DEBUG -struct ad9361_trace { - s64 time; - unsigned reg; - unsigned read; -}; - -static struct ad9361_trace timestamps[5000]; -static int timestamp_cnt = 0; -static bool timestamp_en = 0; - -static inline void ad9361_timestamp_en(void) -{ - timestamp_en = true; -} - -static inline void ad9361_timestamp_dis(void) -{ - timestamp_en = false; -} - -static inline void ad9361_add_timestamp(struct iio_dev *indio_dev, unsigned reg, unsigned read) -{ - if (timestamp_en && (timestamp_cnt < 5000)) { - timestamps[timestamp_cnt].time = iio_get_time_ns(indio_dev); - timestamps[timestamp_cnt].reg = reg; - timestamps[timestamp_cnt].read = read; - - timestamp_cnt++; - } -} - -static inline void ad9361_print_timestamp(void) -{ - int i; - - pr_debug("\n--- TRACE START / Points (%d) --- \n", timestamp_cnt); - - for (i = 0; i < timestamp_cnt; i++) { - if (i == 0) - pr_debug("[%lld] [%lld] \t%s\t 0x%X\n", - timestamps[i].time, - 0LL, - timestamps[i].read ? "REG_RD" : "REG_WR", - timestamps[i].reg); - else - pr_debug("[%lld] [%12lld] \t%s\t 0x%X\n", - timestamps[i].time, - timestamps[i].time - timestamps[i - 1].time, - timestamps[i].read ? "REG_RD" : "REG_WR", - timestamps[i].reg); - - } - - pr_debug("\n--- TRACE END / Time %lld ns --- \n", - timestamps[timestamp_cnt - 1].time - timestamps[0].time); - - timestamp_cnt = 0; -} -#endif - -static const char *ad9361_ensm_states[] = { - "sleep", NULL, NULL, NULL, NULL, "alert", "tx", "tx flush", - "rx", "rx_flush", "fdd", "fdd_flush" -}; - -static int ad9361_spi_readm(struct spi_device *spi, u32 reg, - u8 *rbuf, u32 num) -{ - u8 buf[2]; - int ret; - u16 cmd; - - if (num > MAX_MBYTE_SPI) - return -EINVAL; - - cmd = AD_READ | AD_CNT(num) | AD_ADDR(reg); - buf[0] = cmd >> 8; - buf[1] = cmd & 0xFF; - - ret = spi_write_then_read(spi, &buf[0], 2, rbuf, num); - if (ret < 0) { - dev_err(&spi->dev, "Read Error %d", ret); - return ret; - } -#ifdef _DEBUG - { - int i; - for (i = 0; i < num; i++) - dev_dbg(&spi->dev, "%s: reg 0x%X val 0x%X\n", - __func__, reg--, rbuf[i]); - } -#endif - - return 0; -} - -int ad9361_spi_read(struct spi_device *spi, u32 reg) -{ - u8 buf; - int ret; - - ret = ad9361_spi_readm(spi, reg, &buf, 1); - if (ret < 0) - return ret; - - return buf; -} -EXPORT_SYMBOL(ad9361_spi_read); - -static int __ad9361_spi_readf(struct spi_device *spi, u32 reg, - u32 mask, u32 offset) -{ - u8 buf; - int ret; - - if (!mask) - return -EINVAL; - - ret = ad9361_spi_readm(spi, reg, &buf, 1); - if (ret < 0) - return ret; - - buf &= mask; - buf >>= offset; - - return buf; -} - -#define ad9361_spi_readf(spi, reg, mask) \ - __ad9361_spi_readf(spi, reg, mask, __ffs(mask)) - -int ad9361_spi_write(struct spi_device *spi, - u32 reg, u32 val) -{ - u8 buf[3]; - int ret; - u16 cmd; - - cmd = AD_WRITE | AD_CNT(1) | AD_ADDR(reg); - buf[0] = cmd >> 8; - buf[1] = cmd & 0xFF; - buf[2] = val; - - ret = spi_write_then_read(spi, buf, 3, NULL, 0); - if (ret < 0) { - dev_err(&spi->dev, "Write Error %d", ret); - return ret; - } - -#ifdef _DEBUG - dev_dbg(&spi->dev, "%s: reg 0x%X val 0x%X\n", __func__, reg, buf[2]); -#endif - - return 0; -} -EXPORT_SYMBOL(ad9361_spi_write); - -static int __ad9361_spi_writef(struct spi_device *spi, u32 reg, - u32 mask, u32 offset, u32 val) -{ - u8 buf; - int ret; - - if (!mask) - return -EINVAL; - - ret = ad9361_spi_readm(spi, reg, &buf, 1); - if (ret < 0) - return ret; - - buf &= ~mask; - buf |= ((val << offset) & mask); - - return ad9361_spi_write(spi, reg, buf); -} - -#define ad9361_spi_writef(spi, reg, mask, val) \ - __ad9361_spi_writef(spi,reg, mask, __ffs(mask), val) - -static int ad9361_spi_writem(struct spi_device *spi, - u32 reg, u8 *tbuf, u32 num) -{ - u8 buf[10]; - int ret; - u16 cmd; - - if (num > MAX_MBYTE_SPI) - return -EINVAL; - - cmd = AD_WRITE | AD_CNT(num) | AD_ADDR(reg); - buf[0] = cmd >> 8; - buf[1] = cmd & 0xFF; - - memcpy(&buf[2], tbuf, num); - - ret = spi_write_then_read(spi, buf, num + 2, NULL, 0); - if (ret < 0) { - dev_err(&spi->dev, "Write Error %d", ret); - return ret; - } - -#ifdef _DEBUG - { - int i; - for (i = 0; i < num; i++) - pr_err("%s: reg 0x%X val 0x%X\n", __func__, reg--, tbuf[i]); - } -#endif - - return 0; -} - -u32 ad9361_validate_rf_bw(struct ad9361_rf_phy *phy, u32 bw) -{ - switch(spi_get_device_id(phy->spi)->driver_data) { - case ID_AD9363A: - return clamp_t(u32, bw, 200000UL, 20000000UL); - default: - return clamp_t(u32, bw, 200000UL, 56000000UL); - } -} - -int ad9361_validate_rfpll(struct ad9361_rf_phy *phy, bool is_tx, u64 freq) -{ - switch(spi_get_device_id(phy->spi)->driver_data) { - case ID_AD9363A: - if (freq > AD9363A_MAX_CARRIER_FREQ_HZ || - freq < AD9363A_MIN_CARRIER_FREQ_HZ) - return -EINVAL; - break; - default: - if (freq > MAX_CARRIER_FREQ_HZ || freq < (is_tx ? - MIN_TX_CARRIER_FREQ_HZ : MIN_RX_CARRIER_FREQ_HZ)) - return -EINVAL; - } - - return 0; -} - -int ad9361_find_opt(u8 *field, u32 size, u32 *ret_start) -{ - int i, cnt = 0, max_cnt = 0, start, max_start = 0; - - for(i = 0, start = -1; i < size; i++) { - if (field[i] == 0) { - if (start == -1) - start = i; - cnt++; - } else { - if (cnt > max_cnt) { - max_cnt = cnt; - max_start = start; - } - start = -1; - cnt = 0; - } - } - - if (cnt > max_cnt) { - max_cnt = cnt; - max_start = start; - } - - *ret_start = max_start; - - return max_cnt; -} -EXPORT_SYMBOL(ad9361_find_opt); - -static int ad9361_1rx1tx_channel_map(struct ad9361_rf_phy *phy, bool tx, int channel) -{ - u32 map; - - if (phy->pdata->rx2tx2) - return channel; - - if (tx) - map = phy->pdata->rx1tx1_mode_use_tx_num; - else - map = phy->pdata->rx1tx1_mode_use_rx_num; - - if (map == 2) - return channel + 1; - - return channel; -} - -static int ad9361_reset(struct ad9361_rf_phy *phy) -{ - if (phy->pdata->reset_gpio) { - gpiod_set_value_cansleep(phy->pdata->reset_gpio, 0); - mdelay(1); - gpiod_set_value_cansleep(phy->pdata->reset_gpio, 1); - mdelay(1); - dev_dbg(&phy->spi->dev, "%s: by GPIO", __func__); - return 0; - } - - /* SPI Soft Reset was removed from the register map, since it doesn't - * work reliably. Without a prober HW reset randomness may happen. - * Please specify a RESET GPIO. - */ - - ad9361_spi_write(phy->spi, REG_SPI_CONF, SOFT_RESET | _SOFT_RESET); - ad9361_spi_write(phy->spi, REG_SPI_CONF, 0x0); - dev_err(&phy->spi->dev, - "%s: by SPI, this may cause unpredicted behavior!", __func__); - - return -ENODEV; -} - -static int ad9361_en_dis_tx(struct ad9361_rf_phy *phy, u32 tx_if, u32 enable) -{ - if ((tx_if & enable) > 1 && spi_get_device_id(phy->spi)->driver_data == - ID_AD9364 && enable) - return -EINVAL; - - return ad9361_spi_writef(phy->spi, REG_TX_ENABLE_FILTER_CTRL, - TX_CHANNEL_ENABLE(tx_if), enable); -} - -static int ad9361_en_dis_rx(struct ad9361_rf_phy *phy, u32 rx_if, u32 enable) -{ - if ((rx_if & enable) > 1 && spi_get_device_id(phy->spi)->driver_data == - ID_AD9364 && enable) - return -EINVAL; - - return ad9361_spi_writef(phy->spi, REG_RX_ENABLE_FILTER_CTRL, - RX_CHANNEL_ENABLE(rx_if), enable); -} - -static int ad9361_int_loopback_fix_ch_cross(struct ad9361_rf_phy *phy, bool enable) -{ - /* Loopback works only TX1->RX1 or RX2->RX2 */ - if (!phy->pdata->rx2tx2 && phy->pdata->rx1tx1_mode_use_rx_num != - phy->pdata->rx1tx1_mode_use_tx_num) - return ad9361_en_dis_tx(phy, TX_1 | TX_2, - enable ? phy->pdata->rx1tx1_mode_use_rx_num : - phy->pdata->rx1tx1_mode_use_tx_num); - - return 0; -} - -int ad9361_bist_loopback(struct ad9361_rf_phy *phy, unsigned mode) -{ - struct ad9361_rf_phy_state *st = phy->state; - u32 sp_hd, reg; - - dev_dbg(&phy->spi->dev, "%s: mode %d", __func__, mode); - - reg = ad9361_spi_read(phy->spi, REG_OBSERVE_CONFIG); - - st->bist_loopback_mode = mode; - - switch (mode) { - case 0: - ad9361_hdl_loopback(phy, false); - ad9361_int_loopback_fix_ch_cross(phy, false); - reg &= ~(DATA_PORT_SP_HD_LOOP_TEST_OE | - DATA_PORT_LOOP_TEST_ENABLE); - return ad9361_spi_write(phy->spi, REG_OBSERVE_CONFIG, reg); - case 1: - /* loopback (AD9361 internal) TX->RX */ - ad9361_hdl_loopback(phy, false); - ad9361_int_loopback_fix_ch_cross(phy, true); - sp_hd = ad9361_spi_read(phy->spi, REG_PARALLEL_PORT_CONF_3); - if ((sp_hd & SINGLE_PORT_MODE) && (sp_hd & HALF_DUPLEX_MODE)) - reg |= DATA_PORT_SP_HD_LOOP_TEST_OE; - else - reg &= ~DATA_PORT_SP_HD_LOOP_TEST_OE; - - reg |= DATA_PORT_LOOP_TEST_ENABLE; - - return ad9361_spi_write(phy->spi, REG_OBSERVE_CONFIG, reg); - case 2: - /* loopback (FPGA internal) RX->TX */ - ad9361_hdl_loopback(phy, true); - ad9361_int_loopback_fix_ch_cross(phy, false); - reg &= ~(DATA_PORT_SP_HD_LOOP_TEST_OE | - DATA_PORT_LOOP_TEST_ENABLE); - return ad9361_spi_write(phy->spi, REG_OBSERVE_CONFIG, reg); - default: - return -EINVAL; - } -} -EXPORT_SYMBOL(ad9361_bist_loopback); - -int ad9361_write_bist_reg(struct ad9361_rf_phy *phy, u32 val) -{ - if (!phy || !phy->state) - return -EINVAL; - phy->state->bist_config = val; - return ad9361_spi_write(phy->spi, REG_BIST_CONFIG, val); -} -EXPORT_SYMBOL(ad9361_write_bist_reg); - -int ad9361_bist_prbs(struct ad9361_rf_phy *phy, enum ad9361_bist_mode mode) -{ - u32 reg = 0; - - dev_dbg(&phy->spi->dev, "%s: mode %d", __func__, mode); - - switch (mode) { - case BIST_DISABLE: - reg = 0; - break; - case BIST_INJ_TX: - reg = BIST_CTRL_POINT(0) | BIST_ENABLE; - break; - case BIST_INJ_RX: - reg = BIST_CTRL_POINT(2) | BIST_ENABLE; - break; - }; - - return ad9361_write_bist_reg(phy, reg); -} -EXPORT_SYMBOL(ad9361_bist_prbs); - -static int ad9361_bist_tone(struct ad9361_rf_phy *phy, - enum ad9361_bist_mode mode, u32 freq_Hz, - u32 level_dB, u32 mask) -{ - unsigned long clk = 0; - u32 reg = 0, reg1, reg_mask; - - dev_dbg(&phy->spi->dev, "%s: mode %d", __func__, mode); - - switch (mode) { - case BIST_DISABLE: - reg = 0; - break; - case BIST_INJ_TX: - clk = clk_get_rate(phy->clks[TX_SAMPL_CLK]); - reg = BIST_CTRL_POINT(0) | BIST_ENABLE; - break; - case BIST_INJ_RX: - clk = clk_get_rate(phy->clks[RX_SAMPL_CLK]); - reg = BIST_CTRL_POINT(2) | BIST_ENABLE; - break; - }; - - reg |= TONE_PRBS; - reg |= TONE_LEVEL(level_dB / 6); - - if (freq_Hz < 4) { - reg |= TONE_FREQ(freq_Hz); - } else { - if (clk) - reg |= TONE_FREQ(DIV_ROUND_CLOSEST(freq_Hz * 32, clk) - 1); - } - - reg_mask = BIST_MASK_CHANNEL_1_I_DATA | BIST_MASK_CHANNEL_1_Q_DATA | - BIST_MASK_CHANNEL_2_I_DATA | BIST_MASK_CHANNEL_2_Q_DATA; - - reg1 = ((mask << 2) & reg_mask); - ad9361_spi_write(phy->spi, REG_BIST_AND_DATA_PORT_TEST_CONFIG, reg1); - - return ad9361_write_bist_reg(phy, reg); -} - -static int ad9361_check_cal_done(struct ad9361_rf_phy *phy, u32 reg, - u32 mask, u32 done_state) -{ - u32 timeout = 5000; /* RFDC_CAL can take long */ - u32 state; - - do { - state = ad9361_spi_readf(phy->spi, reg, mask); - if (state == done_state) - return 0; - - if (reg == REG_CALIBRATION_CTRL) - usleep_range(800, 1200); - else - usleep_range(80, 120); - - } while (timeout--); - - dev_err(&phy->spi->dev, "Calibration TIMEOUT (0x%X, 0x%X)", reg, mask); - - return -ETIMEDOUT; -} - -static int ad9361_run_calibration(struct ad9361_rf_phy *phy, u32 mask) -{ - int ret = ad9361_spi_write(phy->spi, REG_CALIBRATION_CTRL, mask); - if (ret < 0) - return ret; - - dev_dbg(&phy->spi->dev, "%s: CAL Mask 0x%X", __func__, mask); - - return ad9361_check_cal_done(phy, REG_CALIBRATION_CTRL, mask, 0); -} - -static int ad9361_gt_tableindex(struct ad9361_rf_phy *phy, u64 freq) -{ - int i; - - for (i = 0; phy->gt_info[i].tab != NULL; i++) { - if ((phy->pdata->split_gt == phy->gt_info[i].split_table) && - (phy->gt_info[i].start < freq) && - (freq <= phy->gt_info[i].end)) { - return i; - } - } - - dev_err(&phy->spi->dev, - "%s: Failed to find suitable gain table (%llu)", __func__, freq); - - return 0; -} - -static int ad9361_gt(struct ad9361_rf_phy *phy) -{ - struct ad9361_rf_phy_state *st = phy->state; - - if (st->current_table == -1) { - dev_err(&phy->spi->dev, "%s: ERROR", __func__); - return 0; - } - - return st->current_table; -} - -/* PLL operates between 47 .. 6000 MHz which is > 2^32 */ - -static unsigned long ad9361_to_clk(u64 freq) -{ - return (unsigned long) min(freq >> 1, (u64) ULONG_MAX); -} - -static u64 ad9361_from_clk(unsigned long freq) -{ - return ((u64)freq << 1); -} - -static int ad9361_setup_ext_lna(struct ad9361_rf_phy *phy, - struct elna_control *ctrl) -{ - ad9361_spi_writef(phy->spi, REG_EXTERNAL_LNA_CTRL, EXTERNAL_LNA1_CTRL, - ctrl->elna_1_control_en); - - ad9361_spi_writef(phy->spi, REG_EXTERNAL_LNA_CTRL, EXTERNAL_LNA2_CTRL, - ctrl->elna_2_control_en); - - ad9361_spi_write(phy->spi, REG_EXT_LNA_HIGH_GAIN, - EXT_LNA_HIGH_GAIN(ctrl->gain_mdB / 500)); - - return ad9361_spi_write(phy->spi, REG_EXT_LNA_LOW_GAIN, - EXT_LNA_LOW_GAIN(ctrl->bypass_loss_mdB / 500)); -} - -static int ad9361_clkout_control(struct ad9361_rf_phy *phy, - enum ad9361_clkout mode) -{ - if (mode == CLKOUT_DISABLE) - return ad9361_spi_writef(phy->spi, REG_BBPLL, CLKOUT_ENABLE, 0); - - return ad9361_spi_writef(phy->spi, REG_BBPLL, - CLKOUT_ENABLE | CLKOUT_SELECT(~0), - ((mode - 1) << 1) | 0x1); -} - -static int ad9361_load_mixer_gm_subtable(struct ad9361_rf_phy *phy) -{ - int i, addr; - dev_dbg(&phy->spi->dev, "%s", __func__); - - ad9361_spi_write(phy->spi, REG_GM_SUB_TABLE_CONFIG, - START_GM_SUB_TABLE_CLOCK); /* Start Clock */ - - for (i = 0, addr = ARRAY_SIZE(gm_st_ctrl); i < ARRAY_SIZE(gm_st_ctrl); i++) { - ad9361_spi_write(phy->spi, REG_GM_SUB_TABLE_ADDRESS, --addr); /* Gain Table Index */ - ad9361_spi_write(phy->spi, REG_GM_SUB_TABLE_BIAS_WRITE, 0); /* Bias */ - ad9361_spi_write(phy->spi, REG_GM_SUB_TABLE_GAIN_WRITE, gm_st_gain[i]); /* Gain */ - ad9361_spi_write(phy->spi, REG_GM_SUB_TABLE_CTRL_WRITE, gm_st_ctrl[i]); /* Control */ - ad9361_spi_write(phy->spi, REG_GM_SUB_TABLE_CONFIG, - WRITE_GM_SUB_TABLE | START_GM_SUB_TABLE_CLOCK); /* Write Words */ - ad9361_spi_write(phy->spi, REG_GM_SUB_TABLE_GAIN_READ, 0); /* Dummy Delay */ - ad9361_spi_write(phy->spi, REG_GM_SUB_TABLE_GAIN_READ, 0); /* Dummy Delay */ - } - - ad9361_spi_write(phy->spi, REG_GM_SUB_TABLE_CONFIG, START_GM_SUB_TABLE_CLOCK); /* Clear Write */ - ad9361_spi_write(phy->spi, REG_GM_SUB_TABLE_GAIN_READ, 0); /* Dummy Delay */ - ad9361_spi_write(phy->spi, REG_GM_SUB_TABLE_GAIN_READ, 0); /* Dummy Delay */ - ad9361_spi_write(phy->spi, REG_GM_SUB_TABLE_CONFIG, 0); /* Stop Clock */ - - return 0; -} - -int ad9361_set_tx_atten(struct ad9361_rf_phy *phy, u32 atten_mdb, - bool tx1, bool tx2, bool immed) -{ - u8 buf[2]; - int ret = 0; - - dev_dbg(&phy->spi->dev, "%s : attenuation %u mdB tx1=%d tx2=%d", - __func__, atten_mdb, tx1, tx2); - - if (atten_mdb > MAX_TX_ATTENUATION_DB) /* 89.75 dB */ - return -EINVAL; - - atten_mdb /= 250; /* Scale to 0.25dB / LSB */ - - buf[0] = atten_mdb >> 8; - buf[1] = atten_mdb & 0xFF; - - ad9361_spi_writef(phy->spi, REG_TX2_DIG_ATTEN, - IMMEDIATELY_UPDATE_TPC_ATTEN, 0); - - if (tx1) - ret = ad9361_spi_writem(phy->spi, REG_TX1_ATTEN_1, buf, 2); - - if (tx2) - ret = ad9361_spi_writem(phy->spi, REG_TX2_ATTEN_1, buf, 2); - - if (immed) - ad9361_spi_writef(phy->spi, REG_TX2_DIG_ATTEN, - IMMEDIATELY_UPDATE_TPC_ATTEN, 1); - - return ret; -} -EXPORT_SYMBOL(ad9361_set_tx_atten); - -int ad9361_get_tx_atten(struct ad9361_rf_phy *phy, u32 tx_num) -{ - u8 buf[2]; - int ret = 0; - u32 code; - - ret = ad9361_spi_readm(phy->spi, (tx_num == 1) ? - REG_TX1_ATTEN_1 : REG_TX2_ATTEN_1, buf, 2); - - if (ret < 0) - return ret; - - code = (buf[0] << 8) | buf[1]; - - code *= 250; - - return code; -} -EXPORT_SYMBOL(ad9361_get_tx_atten); - -int ad9361_tx_mute(struct ad9361_rf_phy *phy, u32 state) -{ - struct ad9361_rf_phy_state *st = phy->state; - int ret; - - if (state) { - st->tx1_atten_cached = ad9361_get_tx_atten(phy, 1); - st->tx2_atten_cached = ad9361_get_tx_atten(phy, 2); - - return ad9361_set_tx_atten(phy, 89750, true, true, true); - } else { - if (st->tx1_atten_cached == st->tx2_atten_cached) - return ad9361_set_tx_atten(phy, st->tx1_atten_cached, - true, true, true); - - ret = ad9361_set_tx_atten(phy, st->tx1_atten_cached, - true, false, true); - ret |= ad9361_set_tx_atten(phy, st->tx2_atten_cached, - false, true, true); - - return ret; - } -} -EXPORT_SYMBOL(ad9361_tx_mute); - -static int ad9361_trx_ext_lo_control(struct ad9361_rf_phy *phy, - bool tx, bool enable) -{ - struct ad9361_rf_phy_state *st = phy->state; - u32 val = enable ? ~0 : 0; - int ret; - - /* REVIST: - * POWER_DOWN_TRX_SYNTH and MCS_RF_ENABLE somehow conflict - */ - - bool mcs_rf_enable = ad9361_spi_readf(phy->spi, - REG_MULTICHIP_SYNC_AND_TX_MON_CTRL, - MCS_RF_ENABLE); - - dev_dbg(&phy->spi->dev, "%s : %s state %d", __func__, - tx ? "TX" : "RX", enable); - - if (tx) { - ret = ad9361_spi_writef(phy->spi, REG_ENSM_CONFIG_2, - POWER_DOWN_TX_SYNTH, mcs_rf_enable ? 0 : enable); - - ret = ad9361_spi_writef(phy->spi, REG_ENSM_CONFIG_2, - TX_SYNTH_READY_MASK, enable); - - ret |= ad9361_spi_writef(phy->spi, REG_RFPLL_DIVIDERS, - TX_VCO_DIVIDER(~0), enable ? 7 : - st->cached_tx_rfpll_div); - - if (enable) - st->cached_synth_pd[0] |= TX_SYNTH_VCO_ALC_POWER_DOWN | - TX_SYNTH_PTAT_POWER_DOWN | - TX_SYNTH_VCO_POWER_DOWN; - else - st->cached_synth_pd[0] &= ~(TX_SYNTH_VCO_ALC_POWER_DOWN | - TX_SYNTH_PTAT_POWER_DOWN | - TX_SYNTH_VCO_POWER_DOWN); - - - ret |= ad9361_spi_write(phy->spi, REG_TX_SYNTH_POWER_DOWN_OVERRIDE, - st->cached_synth_pd[0]); - - ret |= ad9361_spi_writef(phy->spi, REG_ANALOG_POWER_DOWN_OVERRIDE, - TX_EXT_VCO_BUFFER_POWER_DOWN, !enable); - - ret |= ad9361_spi_write(phy->spi, REG_TX_LO_GEN_POWER_MODE, - TX_LO_GEN_POWER_MODE(val)); - } else { - ret = ad9361_spi_writef(phy->spi, REG_ENSM_CONFIG_2, - POWER_DOWN_RX_SYNTH, mcs_rf_enable ? 0 : enable); - - ret = ad9361_spi_writef(phy->spi, REG_ENSM_CONFIG_2, - RX_SYNTH_READY_MASK, enable); - - ret |= ad9361_spi_writef(phy->spi, REG_RFPLL_DIVIDERS, - RX_VCO_DIVIDER(~0), enable ? 7 : - st->cached_rx_rfpll_div); - - if (enable) - st->cached_synth_pd[1] |= RX_SYNTH_VCO_ALC_POWER_DOWN | - RX_SYNTH_PTAT_POWER_DOWN | - RX_SYNTH_VCO_POWER_DOWN; - else - st->cached_synth_pd[1] &= ~(TX_SYNTH_VCO_ALC_POWER_DOWN | - RX_SYNTH_PTAT_POWER_DOWN | - RX_SYNTH_VCO_POWER_DOWN); - - ret |= ad9361_spi_write(phy->spi, REG_RX_SYNTH_POWER_DOWN_OVERRIDE, - st->cached_synth_pd[1]); - - ret |= ad9361_spi_writef(phy->spi, REG_ANALOG_POWER_DOWN_OVERRIDE, - RX_EXT_VCO_BUFFER_POWER_DOWN, !enable); - - ret |= ad9361_spi_write(phy->spi, REG_RX_LO_GEN_POWER_MODE, - RX_LO_GEN_POWER_MODE(val)); - } - - return ret; -} - -static int ad9361_synth_lo_powerdown(struct ad9361_rf_phy *phy, - enum synth_pd_ctrl rx, - enum synth_pd_ctrl tx) -{ - struct ad9361_rf_phy_state *st = phy->state; - - dev_dbg(&phy->spi->dev, "%s : RX(%d) TX(%d)", __func__, rx, tx); - - switch (rx) { - case LO_OFF: - st->cached_synth_pd[1] |= RX_LO_POWER_DOWN; - break; - case LO_ON: - st->cached_synth_pd[1] &= ~RX_LO_POWER_DOWN; - break; - case LO_DONTCARE: - break; - } - - switch (tx) { - case LO_OFF: - st->cached_synth_pd[0] |= TX_LO_POWER_DOWN; - break; - case LO_ON: - st->cached_synth_pd[0] &= ~TX_LO_POWER_DOWN; - break; - case LO_DONTCARE: - break; - } - - return ad9361_spi_writem(phy->spi, REG_TX_SYNTH_POWER_DOWN_OVERRIDE, - st->cached_synth_pd, 2); -} - -static u32 ad9361_rfvco_tableindex(unsigned long freq) -{ - if (freq < 50000000UL) - return LUT_FTDD_40; - - if (freq <= 70000000UL) - return LUT_FTDD_60; - - return LUT_FTDD_80; -} - -static int ad9361_rfpll_vco_init(struct ad9361_rf_phy *phy, - bool tx, u64 vco_freq, - unsigned long ref_clk) -{ - struct ad9361_rf_phy_state *st = phy->state; - struct spi_device *spi = phy->spi; - const struct SynthLUT (*tab); - int i = 0; - u32 range, offs = 0; - - range = ad9361_rfvco_tableindex(ref_clk); - - dev_dbg(&phy->spi->dev, "%s : vco_freq %llu : ref_clk %lu : range %d", - __func__, vco_freq, ref_clk, range); - - do_div(vco_freq, 1000000UL); /* vco_freq in MHz */ - - if ((phy->pdata->fdd && !phy->pdata->fdd_independent_mode) - && (st->current_tx_lo_freq != st->current_rx_lo_freq)) { - tab = &SynthLUT_FDD[range][0]; - if (tx) - st->current_tx_use_tdd_table = false; - else - st->current_rx_use_tdd_table = false; - } else { - tab = &SynthLUT_TDD[range][0]; - if (tx) - st->current_tx_use_tdd_table = true; - else - st->current_rx_use_tdd_table = true; - } - - if (tx) - offs = REG_TX_VCO_OUTPUT - REG_RX_VCO_OUTPUT; - - while (i < SYNTH_LUT_SIZE && tab[i].VCO_MHz > vco_freq) - i++; - - dev_dbg(&phy->spi->dev, "%s : freq %d MHz : index %d", - __func__, tab[i].VCO_MHz, i); - - ad9361_spi_write(spi, REG_RX_VCO_OUTPUT + offs, - VCO_OUTPUT_LEVEL(tab[i].VCO_Output_Level) | - PORB_VCO_LOGIC); - ad9361_spi_writef(spi, REG_RX_ALC_VARACTOR + offs, - VCO_VARACTOR(~0), tab[i].VCO_Varactor); - ad9361_spi_write(spi, REG_RX_VCO_BIAS_1 + offs, - VCO_BIAS_REF(tab[i].VCO_Bias_Ref) | - VCO_BIAS_TCF(tab[i].VCO_Bias_Tcf)); - - ad9361_spi_write(spi, REG_RX_FORCE_VCO_TUNE_1 + offs, - VCO_CAL_OFFSET(tab[i].VCO_Cal_Offset)); - ad9361_spi_write(spi, REG_RX_VCO_VARACTOR_CTRL_1 + offs, - VCO_VARACTOR_REFERENCE( - tab[i].VCO_Varactor_Reference)); - - ad9361_spi_write(spi, REG_RX_VCO_CAL_REF + offs, VCO_CAL_REF_TCF(0)); - - ad9361_spi_write(spi, REG_RX_VCO_VARACTOR_CTRL_0 + offs, - VCO_VARACTOR_OFFSET(0) | - VCO_VARACTOR_REFERENCE_TCF(7)); - - ad9361_spi_writef(spi, REG_RX_CP_CURRENT + offs, CHARGE_PUMP_CURRENT(~0), - tab[i].Charge_Pump_Current); - ad9361_spi_write(spi, REG_RX_LOOP_FILTER_1 + offs, - LOOP_FILTER_C2(tab[i].LF_C2) | - LOOP_FILTER_C1(tab[i].LF_C1)); - ad9361_spi_write(spi, REG_RX_LOOP_FILTER_2 + offs, - LOOP_FILTER_R1(tab[i].LF_R1) | - LOOP_FILTER_C3(tab[i].LF_C3)); - ad9361_spi_write(spi, REG_RX_LOOP_FILTER_3 + offs, - LOOP_FILTER_R3(tab[i].LF_R3)); - - return 0; -} - -static int ad9361_get_split_table_gain(struct ad9361_rf_phy *phy, u32 idx_reg, - struct rf_rx_gain *rx_gain) -{ - struct spi_device *spi = phy->spi; - u32 val, tbl_addr; - int rc = 0; - - rx_gain->fgt_lmt_index = ad9361_spi_readf(spi, idx_reg, - FULL_TABLE_GAIN_INDEX(~0)); - tbl_addr = ad9361_spi_read(spi, REG_GAIN_TABLE_ADDRESS); - - ad9361_spi_write(spi, REG_GAIN_TABLE_ADDRESS, rx_gain->fgt_lmt_index); - - val = ad9361_spi_read(spi, REG_GAIN_TABLE_READ_DATA1); - rx_gain->lna_index = TO_LNA_GAIN(val); - rx_gain->mixer_index = TO_MIXER_GM_GAIN(val); - - rx_gain->tia_index = ad9361_spi_readf(spi, REG_GAIN_TABLE_READ_DATA2, TIA_GAIN); - - rx_gain->lmt_gain = lna_table[ad9361_gt(phy)][rx_gain->lna_index] + - mixer_table[ad9361_gt(phy)][rx_gain->mixer_index] + - tia_table[rx_gain->tia_index]; - - ad9361_spi_write(spi, REG_GAIN_TABLE_ADDRESS, tbl_addr); - - /* Read LPF Index */ - rx_gain->lpf_gain = ad9361_spi_readf(spi, idx_reg + 1, LPF_GAIN_RX(~0)); - - /* Read Digital Gain */ - rx_gain->digital_gain = ad9361_spi_readf(spi, idx_reg + 2, - DIGITAL_GAIN_RX(~0)); - - rx_gain->gain_db = rx_gain->lmt_gain + rx_gain->lpf_gain + - rx_gain->digital_gain; - return rc; -} - -static int ad9361_get_full_table_gain(struct ad9361_rf_phy *phy, u32 idx_reg, - struct rf_rx_gain *rx_gain) -{ - struct spi_device *spi = phy->spi; - u32 val; - - rx_gain->fgt_lmt_index = val = ad9361_spi_readf(spi, idx_reg, - FULL_TABLE_GAIN_INDEX(~0)); - /* Read Digital Gain */ - rx_gain->digital_gain = ad9361_spi_readf(spi, idx_reg + 2, - DIGITAL_GAIN_RX(~0)); - - rx_gain->gain_db = phy->gt_info[ad9361_gt(phy)].abs_gain_tbl[val]; - - return 0; -} - -static int ad9361_get_rx_gain(struct ad9361_rf_phy *phy, - u32 rx_id, struct rf_rx_gain *rx_gain) -{ - struct device *dev = &phy->spi->dev; - struct spi_device *spi = phy->spi; - u32 val, idx_reg; - u8 gain_ctl_shift, rx_enable_mask; - u8 fast_atk_shift; - int rc = 0; - - if (rx_id == 1) { - gain_ctl_shift = RX1_GAIN_CTRL_SHIFT; - idx_reg = REG_GAIN_RX1; - rx_enable_mask = RX_CHANNEL_ENABLE(RX_1); - fast_atk_shift = RX1_FAST_ATK_SHIFT; - - } else if (rx_id == 2) { - gain_ctl_shift = RX2_GAIN_CTRL_SHIFT; - idx_reg = REG_GAIN_RX2; - rx_enable_mask = RX_CHANNEL_ENABLE(RX_2); - fast_atk_shift = RX2_FAST_ATK_SHIFT; - } else { - dev_err(dev, "Unknown Rx path %d\n", rx_id); - rc = -EINVAL; - goto out; - } - - val = ad9361_spi_readf(spi, REG_RX_ENABLE_FILTER_CTRL, rx_enable_mask); - - if (!val) { - dev_dbg(dev, "Rx%d is not enabled\n", rx_gain->ant); - rc = -EAGAIN; - goto out; - } - - val = ad9361_spi_read(spi, REG_AGC_CONFIG_1); - - val = (val >> gain_ctl_shift) & RX_GAIN_CTL_MASK; - - if (val == RX_GAIN_CTL_AGC_FAST_ATK) { - /* In fast attack mode check whether Fast attack state machine - * has locked gain, if not then we can not read gain. - */ - val = ad9361_spi_read(spi, REG_FAST_ATTACK_STATE); - val = (val >> fast_atk_shift) & FAST_ATK_MASK; - if (val != FAST_ATK_GAIN_LOCKED) { - dev_warn(dev, "Failed to read gain, state m/c at %x\n", - val); - rc = -EAGAIN; - goto out; - } - } - - if (phy->pdata->split_gt) - rc = ad9361_get_split_table_gain(phy, idx_reg, rx_gain); - else - rc = ad9361_get_full_table_gain(phy, idx_reg, rx_gain); - -out: - return rc; -} - -static u8 ad9361_ensm_get_state(struct ad9361_rf_phy *phy) -{ - return ad9361_spi_readf(phy->spi, REG_STATE, ENSM_STATE(~0)); -} - -void ad9361_ensm_force_state(struct ad9361_rf_phy *phy, u8 ensm_state) -{ - struct ad9361_rf_phy_state *st = phy->state; - struct spi_device *spi = phy->spi; - struct device *dev = &phy->spi->dev; - u8 dev_ensm_state; - int rc; - u32 val; - - dev_ensm_state = ad9361_spi_readf(spi, REG_STATE, ENSM_STATE(~0)); - - st->prev_ensm_state = dev_ensm_state; - - if (dev_ensm_state == ensm_state) { - dev_dbg(dev, "Nothing to do, device is already in %d state\n", - ensm_state); - goto out; - } - - dev_dbg(dev, "Device is in %x state, forcing to %x\n", dev_ensm_state, - ensm_state); - - val = ad9361_spi_read(spi, REG_ENSM_CONFIG_1); - - /* Enable control through SPI writes, and take out from - * Alert - */ - if (val & ENABLE_ENSM_PIN_CTRL) { - val &= ~ENABLE_ENSM_PIN_CTRL; - st->ensm_pin_ctl_en = true; - } else { - st->ensm_pin_ctl_en = false; - } - - if (dev_ensm_state) - val &= ~(TO_ALERT); - - switch (ensm_state) { - - case ENSM_STATE_TX: - case ENSM_STATE_FDD: - val |= FORCE_TX_ON; - break; - case ENSM_STATE_RX: - val |= FORCE_RX_ON; - break; - case ENSM_STATE_ALERT: - val &= ~(FORCE_TX_ON | FORCE_RX_ON); - val |= TO_ALERT | FORCE_ALERT_STATE; - break; - default: - dev_err(dev, "No handling for forcing %d ensm state\n", - ensm_state); - goto out; - } - - ad9361_spi_write(spi, REG_ENSM_CONFIG_1, TO_ALERT | FORCE_ALERT_STATE); - - rc = ad9361_spi_write(spi, REG_ENSM_CONFIG_1, val); - if (rc) - dev_err(dev, "Failed to restore state\n"); - -out: - return; - -} -EXPORT_SYMBOL(ad9361_ensm_force_state); - -void ad9361_ensm_restore_state(struct ad9361_rf_phy *phy, u8 ensm_state) -{ - struct ad9361_rf_phy_state *st = phy->state; - struct spi_device *spi = phy->spi; - struct device *dev = &phy->spi->dev; - int rc; - u32 val; - - val = ad9361_spi_read(spi, REG_ENSM_CONFIG_1); - - /* We are restoring state only, so clear State bits first - * which might have set while forcing a particular state - */ - val &= ~(FORCE_TX_ON | FORCE_RX_ON | FORCE_ALERT_STATE); - val |= TO_ALERT; - - switch (ensm_state) { - case ENSM_STATE_TX: - case ENSM_STATE_FDD: - val |= FORCE_TX_ON; - break; - case ENSM_STATE_RX: - val |= FORCE_RX_ON; - break; - case ENSM_STATE_ALERT: - val |= TO_ALERT; - break; - case ENSM_STATE_INVALID: - dev_dbg(dev, "No need to restore, ENSM state wasn't saved\n"); - return; - default: - dev_dbg(dev, "Could not restore to %d ENSM state\n", - ensm_state); - return; - } - - ad9361_spi_write(spi, REG_ENSM_CONFIG_1, TO_ALERT | FORCE_ALERT_STATE); - - rc = ad9361_spi_write(spi, REG_ENSM_CONFIG_1, val); - if (rc) { - dev_err(dev, "Failed to write ENSM_CONFIG_1"); - return; - } - - if (st->ensm_pin_ctl_en) { - val |= ENABLE_ENSM_PIN_CTRL; - rc = ad9361_spi_write(spi, REG_ENSM_CONFIG_1, val); - if (rc) - dev_err(dev, "Failed to write ENSM_CONFIG_1"); - } -} -EXPORT_SYMBOL(ad9361_ensm_restore_state); - -void ad9361_ensm_restore_prev_state(struct ad9361_rf_phy *phy) -{ - return ad9361_ensm_restore_state(phy, phy->state->prev_ensm_state); -} -EXPORT_SYMBOL(ad9361_ensm_restore_prev_state); - -static int find_table_index(struct ad9361_rf_phy *phy, int gain) -{ - u32 i, nm1, n; - - for (i = 0; i < phy->gt_info[ad9361_gt(phy)].max_index; i++) { - if (phy->gt_info[ad9361_gt(phy)].abs_gain_tbl[i] >= gain) { - nm1 = abs(phy->gt_info[ad9361_gt(phy)].abs_gain_tbl[ - (i > 0) ? i - 1 : i] - gain); - n = abs(phy->gt_info[ad9361_gt(phy)].abs_gain_tbl[i] - - gain); - if (nm1 < n) - return (i > 0) ? i - 1 : i; - else - return i; - } - } - - return -EINVAL; -} - -static int ad9361_load_gt(struct ad9361_rf_phy *phy, u64 freq, u32 dest) -{ - struct ad9361_rf_phy_state *st = phy->state; - struct spi_device *spi = phy->spi; - u8 (*tab)[3]; - u32 band, index_max, i, lna, lpf_tia_mask, set_gain; - int ret, rx1_gain, rx2_gain; - - dev_dbg(&phy->spi->dev, "%s: frequency %llu", __func__, freq); - - band = ad9361_gt_tableindex(phy, freq); - - dev_dbg(&phy->spi->dev, "%s: frequency %llu (band %d)", - __func__, freq, band); - - /* check if table is present */ - if (st->current_table == band) - return 0; - - tab = phy->gt_info[band].tab; - index_max = phy->gt_info[band].max_index; - - ad9361_spi_writef(spi, REG_AGC_CONFIG_2, - AGC_USE_FULL_GAIN_TABLE, !phy->pdata->split_gt); - - ad9361_spi_write(spi, REG_MAX_LMT_FULL_GAIN, index_max - 1); /* Max Full/LMT Gain Table Index */ - - set_gain = ad9361_spi_readf(spi, REG_RX1_MANUAL_LMT_FULL_GAIN, - RX_FULL_TBL_IDX_MASK); - - if (st->current_table >= 0) { - rx1_gain = phy->gt_info[st->current_table].abs_gain_tbl[set_gain]; - } else { - if (set_gain > (index_max - 1)) - set_gain = index_max - 1; - - rx1_gain = phy->gt_info[band].abs_gain_tbl[set_gain]; - } - - set_gain = ad9361_spi_readf(spi, REG_RX2_MANUAL_LMT_FULL_GAIN, - RX_FULL_TBL_IDX_MASK); - - if (st->current_table >= 0) { - rx2_gain = phy->gt_info[st->current_table].abs_gain_tbl[set_gain]; - } else { - if (set_gain > (index_max - 1)) - set_gain = index_max - 1; - - rx2_gain = phy->gt_info[band].abs_gain_tbl[set_gain]; - } - - lna = phy->pdata->elna_ctrl.elna_in_gaintable_all_index_en ? - EXT_LNA_CTRL : 0; - - ad9361_spi_write(spi, REG_GAIN_TABLE_CONFIG, START_GAIN_TABLE_CLOCK | - RECEIVER_SELECT(dest)); /* Start Gain Table Clock */ - - /* TX QUAD Calibration */ - if (phy->pdata->split_gt) - lpf_tia_mask = 0x20; - else - lpf_tia_mask = 0x3F; - - st->tx_quad_lpf_tia_match = -EINVAL; - - for (i = 0; i < index_max; i++) { - ad9361_spi_write(spi, REG_GAIN_TABLE_ADDRESS, i); /* Gain Table Index */ - ad9361_spi_write(spi, REG_GAIN_TABLE_WRITE_DATA1, tab[i][0] | lna); /* Ext LNA, Int LNA, & Mixer Gain Word */ - ad9361_spi_write(spi, REG_GAIN_TABLE_WRITE_DATA2, tab[i][1]); /* TIA & LPF Word */ - ad9361_spi_write(spi, REG_GAIN_TABLE_WRITE_DATA3, tab[i][2]); /* DC Cal bit & Dig Gain Word */ - ad9361_spi_write(spi, REG_GAIN_TABLE_CONFIG, - START_GAIN_TABLE_CLOCK | - WRITE_GAIN_TABLE | - RECEIVER_SELECT(dest)); /* Gain Table Index */ - ad9361_spi_write(spi, REG_GAIN_TABLE_READ_DATA1, 0); /* Dummy Write to delay 3 ADCCLK/16 cycles */ - ad9361_spi_write(spi, REG_GAIN_TABLE_READ_DATA1, 0); /* Dummy Write to delay ~1u */ - - if ((tab[i][1] & lpf_tia_mask) == 0x20) - st->tx_quad_lpf_tia_match = i; - - } - - ad9361_spi_write(spi, REG_GAIN_TABLE_CONFIG, START_GAIN_TABLE_CLOCK | - RECEIVER_SELECT(dest)); /* Clear Write Bit */ - ad9361_spi_write(spi, REG_GAIN_TABLE_READ_DATA1, 0); /* Dummy Write to delay ~1u */ - ad9361_spi_write(spi, REG_GAIN_TABLE_READ_DATA1, 0); /* Dummy Write to delay ~1u */ - ad9361_spi_write(spi, REG_GAIN_TABLE_CONFIG, 0); /* Stop Gain Table Clock */ - - st->current_table = band; - - ret = find_table_index(phy, rx1_gain); - if (ret < 0) - ret = phy->gt_info[band].max_index - 1; - - ad9361_spi_writef(spi, REG_RX1_MANUAL_LMT_FULL_GAIN, - RX_FULL_TBL_IDX_MASK, ret); /* Rx1 Full/LMT Gain Index */ - - ret = find_table_index(phy, rx2_gain); - if (ret < 0) - ret = phy->gt_info[band].max_index - 1; - - ad9361_spi_write(spi, REG_RX2_MANUAL_LMT_FULL_GAIN, ret); /* Rx2 Full/LMT Gain Index */ - - return 0; -} - -static int set_split_table_gain(struct ad9361_rf_phy *phy, u32 idx_reg, - struct rf_rx_gain *rx_gain) -{ - struct device *dev = &phy->spi->dev; - struct spi_device *spi = phy->spi; - int rc = 0; - - if ((rx_gain->fgt_lmt_index > MAX_LMT_INDEX) || - (rx_gain->lpf_gain > MAX_LPF_GAIN) || - (rx_gain->digital_gain > MAX_DIG_GAIN)) { - dev_err(dev, "LMT_INDEX missing or greater than max value %d", - MAX_LMT_INDEX); - dev_err(dev, "LPF_GAIN missing or greater than max value %d", - MAX_LPF_GAIN); - dev_err(dev, "DIGITAL_GAIN cannot be more than %d", - MAX_DIG_GAIN); - rc = -EINVAL; - goto out; - } - - rc = find_table_index(phy, rx_gain->gain_db); - if (rc < 0) { - dev_err(dev, "Invalid gain %d, supported range [%d - %d]\n", - rx_gain->gain_db, phy->gt_info[ad9361_gt(phy)]. - abs_gain_tbl[0], - phy->gt_info[ad9361_gt(phy)].abs_gain_tbl - [phy->gt_info[ad9361_gt(phy)].max_index - 1]); - goto out; - } - - rx_gain->fgt_lmt_index = rc; - - ad9361_spi_writef(spi, idx_reg, RX_FULL_TBL_IDX_MASK, rx_gain->fgt_lmt_index); - ad9361_spi_writef(spi, idx_reg + 1, RX_LPF_IDX_MASK, rx_gain->lpf_gain); - - if (phy->pdata->gain_ctrl.dig_gain_en) { - ad9361_spi_writef(spi, idx_reg + 2, RX_DIGITAL_IDX_MASK, rx_gain->digital_gain); - - } else if (rx_gain->digital_gain > 0) { - dev_err(dev, "Digital gain is disabled and cannot be set"); - } -out: - return 0; -} - -static int set_full_table_gain(struct ad9361_rf_phy *phy, u32 idx_reg, - struct rf_rx_gain *rx_gain) -{ - struct spi_device *spi = phy->spi; - struct device *dev = &phy->spi->dev; - int rc = 0; - - if (rx_gain->fgt_lmt_index != ~0 || rx_gain->lpf_gain != ~0 || - rx_gain->digital_gain > 0) - dev_dbg(dev, - "Ignoring lmt/lpf/digital gains in Single Table mode"); - - rc = find_table_index(phy, rx_gain->gain_db); - if (rc < 0) { - dev_err(dev, "Invalid gain %d, supported range [%d - %d]\n", - rx_gain->gain_db, phy->gt_info[ad9361_gt(phy)]. - abs_gain_tbl[0], - phy->gt_info[ad9361_gt(phy)].abs_gain_tbl - [phy->gt_info[ad9361_gt(phy)].max_index - 1]); - goto out; - } - - rc = ad9361_spi_writef(spi, idx_reg, RX_FULL_TBL_IDX_MASK, rc); -out: - return rc; -} - -static int ad9361_set_rx_gain(struct ad9361_rf_phy *phy, - u32 rx_id, struct rf_rx_gain *rx_gain) -{ - struct spi_device *spi = phy->spi; - struct device *dev = &phy->spi->dev; - u32 val, idx_reg; - u8 gain_ctl_shift; - int rc = 0; - - if (rx_id == 1) { - gain_ctl_shift = RX1_GAIN_CTRL_SHIFT; - idx_reg = REG_RX1_MANUAL_LMT_FULL_GAIN; - - } else if (rx_id == 2) { - gain_ctl_shift = RX2_GAIN_CTRL_SHIFT; - idx_reg = REG_RX2_MANUAL_LMT_FULL_GAIN; - } else { - dev_err(dev, "Unknown Rx path %d\n", rx_id); - rc = -EINVAL; - goto out; - - } - - val = ad9361_spi_read(spi, REG_AGC_CONFIG_1); - val = (val >> gain_ctl_shift) & RX_GAIN_CTL_MASK; - - if (val != RX_GAIN_CTL_MGC) { - dev_dbg(dev, "Rx gain can be set in MGC mode only\n"); - rc = -EOPNOTSUPP; - goto out; - } - - if (phy->pdata->split_gt) - rc = set_split_table_gain(phy, idx_reg, rx_gain); - else - rc = set_full_table_gain(phy, idx_reg, rx_gain); - - if (rc) { - dev_err(dev, "Unable to write gain tbl idx reg: %d\n", idx_reg); - goto out; - } - -out: - return rc; - -} - -static int ad9361_gc_update(struct ad9361_rf_phy *phy) -{ - struct ad9361_rf_phy_state *st = phy->state; - struct spi_device *spi = phy->spi; - unsigned long clkrf; - u32 reg, delay_lna, settling_delay, dec_pow_meas_dur; - int ret; - - clkrf = clk_get_rate(phy->clks[CLKRF_CLK]); - delay_lna = phy->pdata->elna_ctrl.settling_delay_ns; - - /* - * AGC Attack Delay (us)=ceiling((((0.2+Delay_LNA)*ClkRF+14))/(2*ClkRF))+1 - * ClkRF in MHz, delay in us - */ - - reg = (200 + delay_lna) / 2 + (14000000UL / (clkrf / 500U)); - reg = DIV_ROUND_UP(reg, 1000UL) + - phy->pdata->gain_ctrl.agc_attack_delay_extra_margin_us; - reg = clamp_t(u8, reg, 0U, 31U); - ret = ad9361_spi_writef(spi, REG_AGC_ATTACK_DELAY, - AGC_ATTACK_DELAY(~0), reg); - - /* - * Peak Overload Wait Time (ClkRF cycles)=ceiling((0.1+Delay_LNA) *clkRF+1) - */ - - reg = (delay_lna + 100UL) * (clkrf / 1000UL); - reg = DIV_ROUND_UP(reg, 1000000UL) + 1; - reg = clamp_t(u8, reg, 0U, 31U); - ret |= ad9361_spi_writef(spi, REG_PEAK_WAIT_TIME, - PEAK_OVERLOAD_WAIT_TIME(~0), reg); - - /* - * Settling Delay in 0x111. Applies to all gain control modes: - * 0x111[D4:D0]= ceiling(((0.2+Delay_LNA)*clkRF - dodebug = false;+14)/2) - */ - - reg = (delay_lna + 200UL) * (clkrf / 2000UL); - reg = DIV_ROUND_UP(reg, 1000000UL) + 7; - reg = settling_delay = clamp_t(u8, reg, 0U, 31U); - ret |= ad9361_spi_writef(spi, REG_FAST_CONFIG_2_SETTLING_DELAY, - SETTLING_DELAY(~0), reg); - - /* - * Gain Update Counter [15:0]= round((((time*ClkRF-0x111[D4:D0]*2)-2))/2) - */ - reg = phy->pdata->gain_ctrl.gain_update_interval_us * (clkrf / 1000UL) - - settling_delay * 2000UL - 2000UL; - - reg = DIV_ROUND_CLOSEST(reg, 2000UL); - reg = clamp_t(u32, reg, 0U, 131071UL); - - if (st->agc_mode[0] == RF_GAIN_FASTATTACK_AGC || - st->agc_mode[1] == RF_GAIN_FASTATTACK_AGC) { - dec_pow_meas_dur = - phy->pdata->gain_ctrl.f_agc_dec_pow_measuremnt_duration; - } else { - u32 fir_div = DIV_ROUND_CLOSEST(clkrf, clk_get_rate(phy->clks[RX_SAMPL_CLK])); - dec_pow_meas_dur = phy->pdata->gain_ctrl.dec_pow_measuremnt_duration; - - if (((reg * 2 / fir_div) / dec_pow_meas_dur) < 2) { - dec_pow_meas_dur = reg / fir_div; - } - } - - - /* Power Measurement Duration */ - ad9361_spi_writef(spi, REG_DEC_POWER_MEASURE_DURATION_0, - DEC_POWER_MEASUREMENT_DURATION(~0), - ilog2(dec_pow_meas_dur / 16)); - - - ret |= ad9361_spi_writef(spi, REG_DIGITAL_SAT_COUNTER, - DOUBLE_GAIN_COUNTER, reg > 65535); - - if (reg > 65535) - reg /= 2; - - ret |= ad9361_spi_write(spi, REG_GAIN_UPDATE_COUNTER1, reg & 0xFF); - ret |= ad9361_spi_write(spi, REG_GAIN_UPDATE_COUNTER2, reg >> 8); - - /* - * Fast AGC State Wait Time - Energy Detect Count - */ - - reg = DIV_ROUND_CLOSEST(phy->pdata->gain_ctrl.f_agc_state_wait_time_ns * - (clkrf / 1000UL), 1000000UL); - reg = clamp_t(u32, reg, 0U, 31U); - ret |= ad9361_spi_writef(spi, REG_FAST_ENERGY_DETECT_COUNT, - ENERGY_DETECT_COUNT(~0), reg); - - return ret; -} - -static int ad9361_set_gain_ctrl_mode(struct ad9361_rf_phy *phy, - struct rf_gain_ctrl *gain_ctrl) -{ - struct spi_device *spi = phy->spi; - struct device *dev = &phy->spi->dev; - int rc = 0; - u32 gain_ctl_shift, mode; - u8 val; - - rc = ad9361_spi_readm(spi, REG_AGC_CONFIG_1, &val, 1); - if (rc) { - dev_err(dev, "Unable to read AGC config1 register: %x\n", - REG_AGC_CONFIG_1); - goto out; - } - - switch (gain_ctrl->mode) { - case RF_GAIN_MGC: - mode = RX_GAIN_CTL_MGC; - break; - case RF_GAIN_FASTATTACK_AGC: - mode = RX_GAIN_CTL_AGC_FAST_ATK; - break; - case RF_GAIN_SLOWATTACK_AGC: - mode = RX_GAIN_CTL_AGC_SLOW_ATK; - break; - case RF_GAIN_HYBRID_AGC: - mode = RX_GAIN_CTL_AGC_SLOW_ATK_HYBD; - break; - default: - rc = -EINVAL; - goto out; - } - - if (gain_ctrl->ant == 1) { - gain_ctl_shift = RX1_GAIN_CTRL_SHIFT; - } else if (gain_ctrl->ant == 2) { - gain_ctl_shift = RX2_GAIN_CTRL_SHIFT; - } else { - dev_err(dev, "Unknown Rx path %d\n", gain_ctrl->ant); - rc = -EINVAL; - goto out; - } - - rc = ad9361_en_dis_rx(phy, gain_ctrl->ant, RX_DISABLE); - if (rc) { - dev_err(dev, "Unable to disable rx%d\n", gain_ctrl->ant); - goto out; - } - - val &= ~(RX_GAIN_CTL_MASK << gain_ctl_shift); - val |= mode << gain_ctl_shift; - if (mode == RX_GAIN_CTL_AGC_SLOW_ATK_HYBD) - val |= SLOW_ATTACK_HYBRID_MODE; - else - val &= ~SLOW_ATTACK_HYBRID_MODE; - - rc = ad9361_spi_write(spi, REG_AGC_CONFIG_1, val); - if (rc) { - dev_err(dev, "Unable to write AGC config1 register: %x\n", - REG_AGC_CONFIG_1); - goto out; - } - - - ad9361_en_dis_rx(phy, gain_ctrl->ant, RX_ENABLE); - rc = ad9361_gc_update(phy); -out: - return rc; -} - -static int ad9361_read_rssi(struct ad9361_rf_phy *phy, struct rf_rssi *rssi) -{ - struct spi_device *spi = phy->spi; - u8 reg_val_buf[6]; - int rc; - - rc = ad9361_spi_readm(spi, REG_PREAMBLE_LSB, - reg_val_buf, ARRAY_SIZE(reg_val_buf)); - if (rssi->ant == 1) { - rssi->symbol = RSSI_RESOLUTION * - ((reg_val_buf[5] << RSSI_LSB_SHIFT) + - (reg_val_buf[1] & RSSI_LSB_MASK1)); - rssi->preamble = RSSI_RESOLUTION * - ((reg_val_buf[4] << RSSI_LSB_SHIFT) + - (reg_val_buf[0] & RSSI_LSB_MASK1)); - } else if (rssi->ant == 2) { - rssi->symbol = RSSI_RESOLUTION * - ((reg_val_buf[3] << RSSI_LSB_SHIFT) + - ((reg_val_buf[1] & RSSI_LSB_MASK2) >> 1)); - rssi->preamble = RSSI_RESOLUTION * - ((reg_val_buf[2] << RSSI_LSB_SHIFT) + - ((reg_val_buf[0] & RSSI_LSB_MASK2) >> 1)); - } else - rc = -EFAULT; - - rssi->multiplier = RSSI_MULTIPLIER; - - return rc; -} - -static int ad9361_rx_adc_setup(struct ad9361_rf_phy *phy, unsigned long bbpll_freq, - unsigned long adc_sampl_freq_Hz) -{ - struct ad9361_rf_phy_state *st = phy->state; - unsigned long scale_snr_1e3, maxsnr, sqrt_inv_rc_tconst_1e3, tmp_1e3, - scaled_adc_clk_1e6, inv_scaled_adc_clk_1e3, sqrt_term_1e3, - min_sqrt_term_1e3, bb_bw_Hz; - u64 tmp, invrc_tconst_1e6; - u8 data[40]; - u32 i; - int ret; - - /* Following registers are set implicitly by the RX BB analog filter calibration */ - - u8 c3_msb = ad9361_spi_read(phy->spi, REG_RX_BBF_C3_MSB); - u8 c3_lsb = ad9361_spi_read(phy->spi, REG_RX_BBF_C3_LSB); - u8 r2346 = ad9361_spi_read(phy->spi, REG_RX_BBF_R2346); - - /* - * BBBW = (BBPLL / RxTuneDiv) * ln(2) / (1.4 * 2PI ) - * We assume ad9361_rx_bb_analog_filter_calib() is always run prior - */ - - tmp = bbpll_freq * 10000ULL; - do_div(tmp, 126906UL * st->rxbbf_div); - bb_bw_Hz = tmp; - - dev_dbg(&phy->spi->dev, "%s : BBBW %lu : ADCfreq %lu", - __func__, bb_bw_Hz, adc_sampl_freq_Hz); - - dev_dbg(&phy->spi->dev, "c3_msb 0x%X : c3_lsb 0x%X : r2346 0x%X : ", - c3_msb, c3_lsb, r2346); - - bb_bw_Hz = clamp(bb_bw_Hz, 200000UL, 28000000UL); - - if (adc_sampl_freq_Hz < 80000000) - scale_snr_1e3 = 1000; - else - scale_snr_1e3 = 1585; /* pow(10, scale_snr_dB/10); */ - - if (bb_bw_Hz >= 18000000) { - invrc_tconst_1e6 = (160975ULL * r2346 * - (160 * c3_msb + 10 * c3_lsb + 140) * - (bb_bw_Hz) * (1000 + (10 * (bb_bw_Hz - 18000000) / 1000000))); - - do_div(invrc_tconst_1e6, 1000UL); - - } else { - invrc_tconst_1e6 = (160975ULL * r2346 * - (160 * c3_msb + 10 * c3_lsb + 140) * - (bb_bw_Hz)); - } - - do_div(invrc_tconst_1e6, 1000000000UL); - - if (invrc_tconst_1e6 > 0xFFFFFFFF) - dev_err(&phy->spi->dev, "invrc_tconst_1e6 > ULONG_MAX"); - - sqrt_inv_rc_tconst_1e3 = int_sqrt((u32)invrc_tconst_1e6); - maxsnr = 640/160; - scaled_adc_clk_1e6 = DIV_ROUND_CLOSEST(adc_sampl_freq_Hz, 640); - inv_scaled_adc_clk_1e3 = DIV_ROUND_CLOSEST(640000000, - DIV_ROUND_CLOSEST(adc_sampl_freq_Hz, 1000)); - tmp_1e3 = DIV_ROUND_CLOSEST(980000 + 20 * max_t(u32, 1000U, - DIV_ROUND_CLOSEST(inv_scaled_adc_clk_1e3, maxsnr)), 1000); - sqrt_term_1e3 = int_sqrt(scaled_adc_clk_1e6); - min_sqrt_term_1e3 = min_t(u32, 1000U, - int_sqrt(maxsnr * scaled_adc_clk_1e6)); - - dev_dbg(&phy->spi->dev, "invrc_tconst_1e6 %llu, sqrt_inv_rc_tconst_1e3 %lu\n", - invrc_tconst_1e6, sqrt_inv_rc_tconst_1e3); - dev_dbg(&phy->spi->dev, "scaled_adc_clk_1e6 %lu, inv_scaled_adc_clk_1e3 %lu\n", - scaled_adc_clk_1e6, inv_scaled_adc_clk_1e3); - dev_dbg(&phy->spi->dev, "tmp_1e3 %lu, sqrt_term_1e3 %lu, min_sqrt_term_1e3 %lu\n", - tmp_1e3, sqrt_term_1e3, min_sqrt_term_1e3); - - data[0] = 0; - data[1] = 0; - data[2] = 0; - data[3] = 0x24; - data[4] = 0x24; - data[5] = 0; - data[6] = 0; - - tmp = -50000000 + 8ULL * scale_snr_1e3 * sqrt_inv_rc_tconst_1e3 * - min_sqrt_term_1e3; - do_div(tmp, 100000000UL); - data[7] = min_t(u64, 124U, tmp); - - tmp = (invrc_tconst_1e6 >> 1) + 20 * inv_scaled_adc_clk_1e3 * - data[7] / 80 * 1000ULL; - do_div(tmp, invrc_tconst_1e6); - data[8] = min_t(u64, 255U, tmp); - - tmp = (-500000 + 77ULL * sqrt_inv_rc_tconst_1e3 * min_sqrt_term_1e3); - do_div(tmp, 1000000UL); - data[10] = min_t(u64, 127U, tmp); - - data[9] = min_t(u32, 127U, ((800 * data[10]) / 1000)); - tmp = ((invrc_tconst_1e6 >> 1) + (20 * inv_scaled_adc_clk_1e3 * - data[10] * 1000ULL)); - do_div(tmp, invrc_tconst_1e6 * 77); - data[11] = min_t(u64, 255U, tmp); - data[12] = min_t(u32, 127U, (-500000 + 80 * sqrt_inv_rc_tconst_1e3 * - min_sqrt_term_1e3) / 1000000UL); - - tmp = -3*(long)(invrc_tconst_1e6 >> 1) + inv_scaled_adc_clk_1e3 * - data[12] * (1000ULL * 20 / 80); - do_div(tmp, invrc_tconst_1e6); - data[13] = min_t(u64, 255, tmp); - - data[14] = 21 * (inv_scaled_adc_clk_1e3 / 10000); - data[15] = min_t(u32, 127U, (500 + 1025 * data[7]) / 1000); - data[16] = min_t(u32, 127U, (data[15] * tmp_1e3) / 1000); - data[17] = data[15]; - data[18] = min_t(u32, 127U, (500 + 975 * data[10]) / 1000); - data[19] = min_t(u32, 127U, (data[18] * tmp_1e3) / 1000); - data[20] = data[18]; - data[21] = min_t(u32, 127U, (500 + 975 * data[12]) / 1000); - data[22] = min_t(u32, 127, (data[21] * tmp_1e3) / 1000); - data[23] = data[21]; - data[24] = 0x2E; - data[25] = (128 + min_t(u32, 63000U, DIV_ROUND_CLOSEST(63 * - scaled_adc_clk_1e6, 1000)) / 1000); - data[26] = min_t(u32, 63U,63 * scaled_adc_clk_1e6 / 1000000 * - (920 + 80 * inv_scaled_adc_clk_1e3 / 1000) / 1000); - data[27] = min_t(u32, 63,(32 * sqrt_term_1e3) / 1000); - data[28] = data[25]; - data[29] = data[26]; - data[30] = data[27]; - data[31] = data[25]; - data[32] = data[26]; - data[33] = min_t(u32, 63U, 63 * sqrt_term_1e3 / 1000); - data[34] = min_t(u32, 127U, 64 * sqrt_term_1e3 / 1000); - data[35] = 0x40; - data[36] = 0x40; - data[37] = 0x2C; - data[38] = 0x00; - data[39] = 0x00; - - for (i = 0; i < 40; i++) { - ret = ad9361_spi_write(phy->spi, 0x200 + i, data[i]); - if (ret < 0) - return ret; - } - - return 0; -} - -static int ad9361_rx_tia_calib(struct ad9361_rf_phy *phy, unsigned long bb_bw_Hz) -{ - unsigned long Cbbf, R2346; - u64 CTIA_fF; - - /* Following registers are set implicitly by the RX BB analog filter calibration */ - - u8 reg1EB = ad9361_spi_read(phy->spi, REG_RX_BBF_C3_MSB); - u8 reg1EC = ad9361_spi_read(phy->spi, REG_RX_BBF_C3_LSB); - u8 reg1E6 = ad9361_spi_read(phy->spi, REG_RX_BBF_R2346); - u8 reg1DB, reg1DF, reg1DD, reg1DC, reg1DE, temp; - - dev_dbg(&phy->spi->dev, "%s : bb_bw_Hz %lu", - __func__, bb_bw_Hz); - - bb_bw_Hz = clamp(bb_bw_Hz, 200000UL, 20000000UL); - - Cbbf = (reg1EB * 160) + (reg1EC * 10) + 140; /* fF */ - R2346 = 18300 * RX_BBF_R2346(reg1E6); - - CTIA_fF = Cbbf * R2346 * 560ULL; - do_div(CTIA_fF, 3500000UL); - - if (bb_bw_Hz <= 3000000UL) - reg1DB = 0xE0; - else if (bb_bw_Hz <= 10000000UL) - reg1DB = 0x60; - else - reg1DB = 0x20; - - if (CTIA_fF > 2920ULL) { - reg1DC = 0x40; - reg1DE = 0x40; - temp = min(127U, DIV_ROUND_CLOSEST((u32)CTIA_fF - 400, 320U)); - reg1DD = temp; - reg1DF = temp; - } else { - temp = DIV_ROUND_CLOSEST((u32)CTIA_fF - 400, 40U) + 0x40; - reg1DC = temp; - reg1DE = temp; - reg1DD = 0; - reg1DF = 0; - } - - ad9361_spi_write(phy->spi, REG_RX_TIA_CONFIG, reg1DB); - ad9361_spi_write(phy->spi, REG_TIA1_C_LSB, reg1DC); - ad9361_spi_write(phy->spi, REG_TIA1_C_MSB, reg1DD); - ad9361_spi_write(phy->spi, REG_TIA2_C_LSB, reg1DE); - ad9361_spi_write(phy->spi, REG_TIA2_C_MSB, reg1DF); - - return 0; -} - -/* BASEBAND RX ANALOG FILTER CALIBRATION */ - -static int ad9361_rx_bb_analog_filter_calib(struct ad9361_rf_phy *phy, - unsigned long rx_bb_bw, - unsigned long bbpll_freq) -{ - struct ad9361_rf_phy_state *st = phy->state; - unsigned long target; - u8 tmp; - int ret; - - dev_dbg(&phy->spi->dev, "%s : rx_bb_bw %lu bbpll_freq %lu", - __func__, rx_bb_bw, bbpll_freq); - - rx_bb_bw = clamp(rx_bb_bw, 200000UL, 28000000UL); - - /* 1.4 * BBBW * 2PI / ln(2) */ - target = 126906UL * (rx_bb_bw / 10000UL); - st->rxbbf_div = min_t(unsigned long, 511UL, DIV_ROUND_UP(bbpll_freq, target)); - - /* Set RX baseband filter divide value */ - ad9361_spi_write(phy->spi, REG_RX_BBF_TUNE_DIVIDE, st->rxbbf_div); - ad9361_spi_writef(phy->spi, REG_RX_BBF_TUNE_CONFIG, BIT(0), st->rxbbf_div >> 8); - - /* Write the BBBW into registers 0x1FB and 0x1FC */ - ad9361_spi_write(phy->spi, REG_RX_BBBW_MHZ, rx_bb_bw / 1000000UL); - - tmp = DIV_ROUND_CLOSEST((rx_bb_bw % 1000000UL) * 128, 1000000UL); - ad9361_spi_write(phy->spi, REG_RX_BBBW_KHZ, min_t(u8, 127, tmp)); - - ad9361_spi_write(phy->spi, REG_RX_MIX_LO_CM, RX_MIX_LO_CM(0x3F)); /* Set Rx Mix LO CM */ - ad9361_spi_write(phy->spi, REG_RX_MIX_GM_CONFIG, RX_MIX_GM_PLOAD(3)); /* Set GM common mode */ - - /* Enable the RX BBF tune circuit by writing 0x1E2=0x02 and 0x1E3=0x02 */ - ad9361_spi_write(phy->spi, REG_RX1_TUNE_CTRL, RX1_TUNE_RESAMPLE); - ad9361_spi_write(phy->spi, REG_RX2_TUNE_CTRL, RX2_TUNE_RESAMPLE); - - /* Start the RX Baseband Filter calibration in register 0x016[7] */ - /* Calibration is complete when register 0x016[7] self clears */ - ret = ad9361_run_calibration(phy, RX_BB_TUNE_CAL); - - /* Disable the RX baseband filter tune circuit, write 0x1E2=3, 0x1E3=3 */ - ad9361_spi_write(phy->spi, REG_RX1_TUNE_CTRL, - RX1_TUNE_RESAMPLE | RX1_PD_TUNE); - ad9361_spi_write(phy->spi, REG_RX2_TUNE_CTRL, - RX2_TUNE_RESAMPLE | RX2_PD_TUNE); - - return ret; -} - -/* BASEBAND TX ANALOG FILTER CALIBRATION */ - -static int ad9361_tx_bb_analog_filter_calib(struct ad9361_rf_phy *phy, - unsigned long tx_bb_bw, - unsigned long bbpll_freq) -{ - unsigned long target, txbbf_div; - int ret; - - dev_dbg(&phy->spi->dev, "%s : tx_bb_bw %lu bbpll_freq %lu", - __func__, tx_bb_bw, bbpll_freq); - - tx_bb_bw = clamp(tx_bb_bw, 625000UL, 20000000UL); - - /* 1.6 * BBBW * 2PI / ln(2) */ - target = 145036 * (tx_bb_bw / 10000UL); - txbbf_div = min_t(unsigned long, 511UL, DIV_ROUND_UP(bbpll_freq, target)); - - /* Set TX baseband filter divide value */ - ad9361_spi_write(phy->spi, REG_TX_BBF_TUNE_DIVIDER, txbbf_div); - ad9361_spi_writef(phy->spi, REG_TX_BBF_TUNE_MODE, - TX_BBF_TUNE_DIVIDER, txbbf_div >> 8); - - /* Enable the TX baseband filter tune circuit by setting 0x0CA=0x22. */ - ad9361_spi_write(phy->spi, REG_TX_TUNE_CTRL, TUNER_RESAMPLE | TUNE_CTRL(1)); - - /* Start the TX Baseband Filter calibration in register 0x016[6] */ - /* Calibration is complete when register 0x016[] self clears */ - ret = ad9361_run_calibration(phy, TX_BB_TUNE_CAL); - - /* Disable the TX baseband filter tune circuit by writing 0x0CA=0x26. */ - ad9361_spi_write(phy->spi, REG_TX_TUNE_CTRL, - TUNER_RESAMPLE | TUNE_CTRL(1) | PD_TUNE); - - return ret; -} - -/* BASEBAND TX SECONDARY FILTER */ - -static int ad9361_tx_bb_second_filter_calib(struct ad9361_rf_phy *phy, - unsigned long tx_bb_bw) -{ - u64 cap; - unsigned long corner, res, div; - u32 reg_conf, reg_res; - int ret, i; - - dev_dbg(&phy->spi->dev, "%s : tx_bb_bw %lu", - __func__, tx_bb_bw); - - tx_bb_bw = clamp(tx_bb_bw, 530000UL, 20000000UL); - - /* BBBW * 5PI */ - corner = 15708 * (tx_bb_bw / 10000UL); - - for (i = 0, res = 1; i < 4; i++) { - div = corner * res; - cap = (500000000ULL) + (div >> 1); - do_div(cap, div); - cap -= 12ULL; - if (cap < 64ULL) - break; - - res <<= 1; - } - - if (cap > 63ULL) - cap = 63ULL; - - if(tx_bb_bw <= 4500000UL ) - reg_conf = 0x59; - else if (tx_bb_bw <= 12000000UL) - reg_conf = 0x56; - else - reg_conf = 0x57; - - switch (res) { - case 1: - reg_res = 0x0C; - break; - case 2: - reg_res = 0x04; - break; - case 4: - reg_res = 0x03; - break; - case 8: - reg_res = 0x01; - break; - default: - reg_res = 0x01; - } - - ret = ad9361_spi_write(phy->spi, REG_CONFIG0, reg_conf); - ret |= ad9361_spi_write(phy->spi, REG_RESISTOR, reg_res); - ret |= ad9361_spi_write(phy->spi, REG_CAPACITOR, (u8)cap); - - return ret; -} - -/* RF SYNTHESIZER CHARGE PUMP CALIBRATION */ - -static int ad9361_txrx_synth_cp_calib(struct ad9361_rf_phy *phy, - unsigned long ref_clk_hz, bool tx) -{ - u32 offs = tx ? 0x40 : 0; - u32 vco_cal_cnt; - dev_dbg(&phy->spi->dev, "%s : ref_clk_hz %lu : is_tx %d", - __func__, ref_clk_hz, tx); - - /* REVIST:*/ - ad9361_spi_write(phy->spi, REG_RX_CP_LEVEL_DETECT + offs, 0x17); - - ad9361_spi_write(phy->spi, REG_RX_DSM_SETUP_1 + offs, 0x0); - - ad9361_spi_write(phy->spi, REG_RX_LO_GEN_POWER_MODE + offs, 0x00); - ad9361_spi_write(phy->spi, REG_RX_VCO_LDO + offs, 0x0B); - ad9361_spi_write(phy->spi, REG_RX_VCO_PD_OVERRIDES + offs, 0x02); - ad9361_spi_write(phy->spi, REG_RX_CP_CURRENT + offs, 0x80); - ad9361_spi_write(phy->spi, REG_RX_CP_CONFIG + offs, CP_OFFSET_OFF); - - /* see Table 70 Example Calibration Times for RF VCO Cal */ - if (phy->pdata->fdd) { - vco_cal_cnt = VCO_CAL_EN | VCO_CAL_COUNT(3) | FB_CLOCK_ADV(2); - } else { - if (ref_clk_hz > 40000000UL) - vco_cal_cnt = VCO_CAL_EN | VCO_CAL_COUNT(1) | - FB_CLOCK_ADV(2); - else - vco_cal_cnt = VCO_CAL_EN | VCO_CAL_COUNT(0) | - FB_CLOCK_ADV(2); - } - - ad9361_spi_write(phy->spi, REG_RX_VCO_CAL + offs, vco_cal_cnt); - - /* Enable FDD mode during calibrations */ - - if (!phy->pdata->fdd) { - ad9361_spi_writef(phy->spi, REG_PARALLEL_PORT_CONF_3, - HALF_DUPLEX_MODE, 0); - } - - ad9361_spi_write(phy->spi, REG_ENSM_CONFIG_2, DUAL_SYNTH_MODE); - ad9361_spi_write(phy->spi, REG_ENSM_CONFIG_1, - FORCE_ALERT_STATE | - TO_ALERT); - ad9361_spi_write(phy->spi, REG_ENSM_MODE, FDD_MODE); - - ad9361_spi_write(phy->spi, REG_RX_CP_CONFIG + offs, - CP_OFFSET_OFF | CP_CAL_ENABLE); - - return ad9361_check_cal_done(phy, REG_RX_CAL_STATUS + offs, - CP_CAL_VALID, 1); -} - -/* BASEBAND DC OFFSET CALIBRATION */ -static int ad9361_bb_dc_offset_calib(struct ad9361_rf_phy *phy) -{ - dev_dbg(&phy->spi->dev, "%s", __func__); - - ad9361_spi_write(phy->spi, REG_BB_DC_OFFSET_COUNT, 0x3F); - ad9361_spi_write(phy->spi, REG_BB_DC_OFFSET_SHIFT, BB_DC_M_SHIFT(0xF)); - ad9361_spi_write(phy->spi, REG_BB_DC_OFFSET_ATTEN, BB_DC_OFFSET_ATTEN(1)); - - return ad9361_run_calibration(phy, BBDC_CAL); -} - -/* RF DC OFFSET CALIBRATION */ - -static int ad9361_rf_dc_offset_calib(struct ad9361_rf_phy *phy, - u64 rx_freq) -{ - struct spi_device *spi = phy->spi; - - dev_dbg(&phy->spi->dev, "%s : rx_freq %llu", - __func__, rx_freq); - - ad9361_spi_write(spi, REG_WAIT_COUNT, 0x20); - - if(rx_freq <= 4000000000ULL) { - ad9361_spi_write(spi, REG_RF_DC_OFFSET_COUNT, - phy->pdata->rf_dc_offset_count_low); - ad9361_spi_write(spi, REG_RF_DC_OFFSET_CONFIG_1, - RF_DC_CALIBRATION_COUNT(4) | DAC_FS(2)); - ad9361_spi_write(spi, REG_RF_DC_OFFSET_ATTEN, - RF_DC_OFFSET_ATTEN( - phy->pdata->dc_offset_attenuation_low)); - } else { - ad9361_spi_write(spi, REG_RF_DC_OFFSET_COUNT, - phy->pdata->rf_dc_offset_count_high); - ad9361_spi_write(spi, REG_RF_DC_OFFSET_CONFIG_1, - RF_DC_CALIBRATION_COUNT(4) | DAC_FS(3)); - ad9361_spi_write(spi, REG_RF_DC_OFFSET_ATTEN, - RF_DC_OFFSET_ATTEN( - phy->pdata->dc_offset_attenuation_high)); - } - - ad9361_spi_write(spi, REG_DC_OFFSET_CONFIG2, - USE_WAIT_COUNTER_FOR_RF_DC_INIT_CAL | - DC_OFFSET_UPDATE(3)); - - - if (phy->pdata->rx1rx2_phase_inversion_en || - (phy->pdata->port_ctrl.pp_conf[1] & INVERT_RX2)) { - ad9361_spi_write(spi, REG_INVERT_BITS, - INVERT_RX1_RF_DC_CGOUT_WORD); - } else { - ad9361_spi_write(spi, REG_INVERT_BITS, - INVERT_RX1_RF_DC_CGOUT_WORD | - INVERT_RX2_RF_DC_CGOUT_WORD); - } - - return ad9361_run_calibration(phy, RFDC_CAL); -} - -static int __ad9361_update_rf_bandwidth(struct ad9361_rf_phy *phy, - u32 rf_rx_bw, u32 rf_tx_bw) -{ - u32 real_rx_bandwidth = rf_rx_bw / 2; - u32 real_tx_bandwidth = rf_tx_bw / 2; - unsigned long bbpll_freq; - int ret; - - dev_dbg(&phy->spi->dev, "%s: %d %d", - __func__, rf_rx_bw, rf_tx_bw); - - bbpll_freq = clk_get_rate(phy->clks[BBPLL_CLK]); - - ret = ad9361_rx_bb_analog_filter_calib(phy, - real_rx_bandwidth, - bbpll_freq); - if (ret < 0) - return ret; - - ret = ad9361_tx_bb_analog_filter_calib(phy, - real_tx_bandwidth, - bbpll_freq); - if (ret < 0) - return ret; - - ret = ad9361_rx_tia_calib(phy, real_rx_bandwidth); - if (ret < 0) - return ret; - - ret = ad9361_tx_bb_second_filter_calib(phy, real_tx_bandwidth); - if (ret < 0) - return ret; - - ret = ad9361_rx_adc_setup(phy, - bbpll_freq, - clk_get_rate(phy->clks[ADC_CLK])); - if (ret < 0) - return ret; - - return 0; -} - -/* TX QUADRATURE CALIBRATION */ - -static int __ad9361_tx_quad_calib(struct ad9361_rf_phy *phy, u32 phase, - u32 rxnco_word, u32 decim, u8 *res) -{ - int ret; - - ad9361_spi_write(phy->spi, REG_QUAD_CAL_NCO_FREQ_PHASE_OFFSET, - RX_NCO_FREQ(rxnco_word) | RX_NCO_PHASE_OFFSET(phase)); - ad9361_spi_write(phy->spi, REG_QUAD_CAL_CTRL, - SETTLE_MAIN_ENABLE | DC_OFFSET_ENABLE | QUAD_CAL_SOFT_RESET | - GAIN_ENABLE | PHASE_ENABLE | M_DECIM(decim)); - ad9361_spi_write(phy->spi, REG_QUAD_CAL_CTRL, - SETTLE_MAIN_ENABLE | DC_OFFSET_ENABLE | - GAIN_ENABLE | PHASE_ENABLE | M_DECIM(decim)); - - ret = ad9361_run_calibration(phy, TX_QUAD_CAL); - if (ret < 0) - return ret; - - if (res) - *res = ad9361_spi_read(phy->spi, - (phy->pdata->rx1tx1_mode_use_tx_num == 2) ? - REG_QUAD_CAL_STATUS_TX2 : REG_QUAD_CAL_STATUS_TX1) & - (TX1_LO_CONV | TX1_SSB_CONV); - - return 0; -} - -static int ad9361_tx_quad_phase_search(struct ad9361_rf_phy *phy, u32 rxnco_word, u8 decim) -{ - struct ad9361_rf_phy_state *st = phy->state; - int i, ret; - u8 field[64], val; - u32 start; - - dev_dbg(&phy->spi->dev, "%s", __func__); - - for (i = 0; i < (ARRAY_SIZE(field) / 2); i++) { - ret = __ad9361_tx_quad_calib(phy, i, rxnco_word, decim, &val); - if (ret < 0) - return ret; - - /* Handle 360/0 wrap around */ - field[i] = field[i + 32] = !((val & TX1_LO_CONV) && (val & TX1_SSB_CONV)); - } - - ret = ad9361_find_opt(field, ARRAY_SIZE(field), &start); - - st->last_tx_quad_cal_phase = (start + ret / 2) & 0x1F; - -#ifdef _DEBUG - for (i = 0; i < 64; i++) { - pr_err("%c", (field[i] ? '#' : 'o')); - } - pr_err(" RX_NCO_PHASE_OFFSET(%d, 0x%X)\n", st->last_tx_quad_cal_phase, - st->last_tx_quad_cal_phase); -#endif - - ret = __ad9361_tx_quad_calib(phy, st->last_tx_quad_cal_phase, rxnco_word, decim, NULL); - if (ret < 0) - return ret; - - return 0; -} - -static int ad9361_tx_quad_calib(struct ad9361_rf_phy *phy, - unsigned long bw_rx, unsigned long bw_tx, - int rx_phase) -{ - struct ad9361_rf_phy_state *st = phy->state; - struct device *dev = &phy->spi->dev; - struct spi_device *spi = phy->spi; - unsigned long clktf, clkrf; - int txnco_word, rxnco_word, txnco_freq, ret; - u8 __rx_phase = 0, reg_inv_bits, val, decim; - bool phase_inversion_en; - - if (st->cached_synth_pd[0] & TX_LO_POWER_DOWN) { - if (phy->pdata->lo_powerdown_managed_en) { - ad9361_spi_writef(spi, REG_TX_SYNTH_POWER_DOWN_OVERRIDE, - TX_LO_POWER_DOWN, 0); - } else { - dev_err(dev, - "%s : Tx QUAD Cal abort due to TX LO in powerdown\n", - __func__); - return -EFAULT; - } - } - /* - * Find NCO frequency that matches this equation: - * BW / 4 = Rx NCO freq = Tx NCO freq: - * Rx NCO = ClkRF * (rxNCO <1:0> + 1) / 32 - * Tx NCO = ClkTF * (txNCO <1:0> + 1) / 32 - */ - - clkrf = clk_get_rate(phy->clks[CLKRF_CLK]); - clktf = clk_get_rate(phy->clks[CLKTF_CLK]); - - dev_dbg(&phy->spi->dev, "%s : bw_tx %lu clkrf %lu clktf %lu", - __func__, bw_tx, clkrf, clktf); - - txnco_word = DIV_ROUND_CLOSEST(bw_tx * 8, clktf) - 1; - txnco_word = clamp_t(int, txnco_word, 0, 3); - rxnco_word = txnco_word; - - dev_dbg(dev, "Tx NCO frequency: %lu (BW/4: %lu) txnco_word %d\n", - clktf * (txnco_word + 1) / 32, bw_tx / 4, txnco_word); - - if (clktf <= 4000000UL) - decim = 2; - else - decim = 3; - - if (clkrf == (2 * clktf)) { - __rx_phase = 0x0E; - switch (txnco_word) { - case 0: - txnco_word++; - break; - case 1: - rxnco_word--; - break; - case 2: - rxnco_word-=2; - txnco_word--; - break; - case 3: - rxnco_word-=2; /* REVISIT */ - __rx_phase = 0x08; - break; - } - } else if (clkrf == clktf) { - switch (txnco_word) { - case 0: - case 3: - __rx_phase = 0x15; - break; - case 2: - __rx_phase = 0x1F; - break; - case 1: - if (ad9361_spi_readf(spi, - REG_TX_ENABLE_FILTER_CTRL, 0x3F) == 0x22) - __rx_phase = 0x15; /* REVISIT */ - else - __rx_phase = 0x1A; - break; - } - } else - dev_err(dev, "Unhandled case in %s line %d clkrf %lu clktf %lu\n", - __func__, __LINE__, clkrf, clktf); - - if (rx_phase >= 0) - __rx_phase = rx_phase; - - txnco_freq = clktf * (txnco_word + 1) / 32; - - if (txnco_freq > (bw_rx / 4) || txnco_freq > (bw_tx / 4)) { - /* Make sure the BW during calibration is wide enough */ - ret = __ad9361_update_rf_bandwidth(phy, txnco_freq * 8, txnco_freq * 8); - if (ret < 0) - goto out_restore; - } - - phase_inversion_en = phy->pdata->rx1rx2_phase_inversion_en || - (phy->pdata->port_ctrl.pp_conf[1] & INVERT_RX2); - - if (phase_inversion_en) { - ad9361_spi_writef(spi, REG_PARALLEL_PORT_CONF_2, INVERT_RX2, 0); - - reg_inv_bits = ad9361_spi_read(spi, REG_INVERT_BITS); - - ad9361_spi_write(spi, REG_INVERT_BITS, - INVERT_RX1_RF_DC_CGOUT_WORD | - INVERT_RX2_RF_DC_CGOUT_WORD); - } - - ad9361_spi_writef(spi, REG_KEXP_2, TX_NCO_FREQ(~0), txnco_word); - ad9361_spi_write(spi, REG_QUAD_CAL_COUNT, 0xFF); - ad9361_spi_write(spi, REG_KEXP_1, KEXP_TX(1) | KEXP_TX_COMP(3) | - KEXP_DC_I(3) | KEXP_DC_Q(3)); - ad9361_spi_write(spi, REG_MAG_FTEST_THRESH, 0x01); - ad9361_spi_write(spi, REG_MAG_FTEST_THRESH_2, 0x01); - - if (st->tx_quad_lpf_tia_match < 0) /* set in ad9361_load_gt() */ - dev_err(dev, "failed to find suitable LPF TIA value in gain table\n"); - else - ad9361_spi_write(spi, REG_TX_QUAD_FULL_LMT_GAIN, - st->tx_quad_lpf_tia_match); - - ad9361_spi_write(spi, REG_QUAD_SETTLE_COUNT, 0xF0); - ad9361_spi_write(spi, REG_TX_QUAD_LPF_GAIN, 0x00); - - if (rx_phase != -2) { - ret = __ad9361_tx_quad_calib(phy, __rx_phase, rxnco_word, decim, &val); - - dev_dbg(dev, "LO leakage: %d Quadrature Calibration: %d : rx_phase %d\n", - !!(val & TX1_LO_CONV), !!(val & TX1_SSB_CONV), __rx_phase); - - /* Calibration failed -> try last phase offset */ - if (val != (TX1_LO_CONV | TX1_SSB_CONV)) { - if (st->last_tx_quad_cal_phase < 31) - ret = __ad9361_tx_quad_calib(phy, st->last_tx_quad_cal_phase, - rxnco_word, decim, &val); - } else { - st->last_tx_quad_cal_phase = __rx_phase; - } - } else { - /* force phase search */ - val = 0; - } - /* Calibration failed -> loop through all 32 phase offsets */ - if (val != (TX1_LO_CONV | TX1_SSB_CONV)) - ret = ad9361_tx_quad_phase_search(phy, rxnco_word, decim); - - if (phase_inversion_en) { - ad9361_spi_writef(spi, REG_PARALLEL_PORT_CONF_2, INVERT_RX2, 1); - ad9361_spi_write(spi, REG_INVERT_BITS, reg_inv_bits); - } - - if (txnco_freq > (bw_rx / 4) || txnco_freq > (bw_tx / 4)) { - __ad9361_update_rf_bandwidth(phy, - st->current_rx_bw_Hz, - st->current_tx_bw_Hz); - } - -out_restore: - /* Restore synthesizer powerdown configuration */ - if (phy->pdata->lo_powerdown_managed_en && - (st->cached_synth_pd[0] & TX_LO_POWER_DOWN)) - ad9361_synth_lo_powerdown(phy, LO_DONTCARE, LO_DONTCARE); - - return ret; -} - -static int ad9361_tracking_control(struct ad9361_rf_phy *phy, bool bbdc_track, - bool rfdc_track, bool rxquad_track) -{ - struct spi_device *spi = phy->spi; - u32 qtrack = 0; - - dev_dbg(&spi->dev, "%s : bbdc_track=%d, rfdc_track=%d, rxquad_track=%d", - __func__, bbdc_track, rfdc_track, rxquad_track); - - ad9361_spi_write(spi, REG_CALIBRATION_CONFIG_2, - CALIBRATION_CONFIG2_DFLT | K_EXP_PHASE(0x15)); - ad9361_spi_write(spi, REG_CALIBRATION_CONFIG_3, - PREVENT_POS_LOOP_GAIN | K_EXP_AMPLITUDE(0x15)); - - ad9361_spi_write(spi, REG_DC_OFFSET_CONFIG2, - USE_WAIT_COUNTER_FOR_RF_DC_INIT_CAL | - DC_OFFSET_UPDATE(phy->pdata->dc_offset_update_events) | - (bbdc_track ? ENABLE_BB_DC_OFFSET_TRACKING : 0) | - (rfdc_track ? ENABLE_RF_OFFSET_TRACKING : 0)); - - ad9361_spi_writef(spi, REG_RX_QUAD_GAIN2, - CORRECTION_WORD_DECIMATION_M(~0), - phy->pdata->qec_tracking_slow_mode_en ? 4 : 0); - - if (rxquad_track) { - if (phy->pdata->rx2tx2) - qtrack = ENABLE_TRACKING_MODE_CH1 | ENABLE_TRACKING_MODE_CH2; - else - qtrack = (phy->pdata->rx1tx1_mode_use_rx_num == 1) ? - ENABLE_TRACKING_MODE_CH1 : ENABLE_TRACKING_MODE_CH2; - } - - ad9361_spi_write(spi, REG_CALIBRATION_CONFIG_1, - ENABLE_PHASE_CORR | ENABLE_GAIN_CORR | - FREE_RUN_MODE | ENABLE_CORR_WORD_DECIMATION | - qtrack); - - return 0; -} - -static int ad9361_trx_vco_cal_control(struct ad9361_rf_phy *phy, - bool tx, bool enable) -{ - dev_dbg(&phy->spi->dev, "%s : state %d", - __func__, enable); - - return ad9361_spi_writef(phy->spi, - tx ? REG_TX_PFD_CONFIG : REG_RX_PFD_CONFIG, - BYPASS_LD_SYNTH, !enable); -} - -/* REFERENCE CLOCK DELAY UNIT COUNTER REGISTER */ -static int ad9361_set_ref_clk_cycles(struct ad9361_rf_phy *phy, - unsigned long ref_clk_hz) -{ - dev_dbg(&phy->spi->dev, "%s : ref_clk_hz %lu", - __func__, ref_clk_hz); - - return ad9361_spi_write(phy->spi, REG_REFERENCE_CLOCK_CYCLES, - REFERENCE_CLOCK_CYCLES_PER_US((ref_clk_hz / 1000000UL) - 1)); -} - -static int ad9361_set_dcxo_tune(struct ad9361_rf_phy *phy, - u32 coarse, u32 fine) -{ - dev_dbg(&phy->spi->dev, "%s : coarse %u fine %u", - __func__, coarse, fine); - - if (phy->pdata->use_extclk) - return -ENODEV; - - ad9361_spi_write(phy->spi, REG_DCXO_COARSE_TUNE, - DCXO_TUNE_COARSE(coarse)); - ad9361_spi_write(phy->spi, REG_DCXO_FINE_TUNE_LOW, - DCXO_TUNE_FINE_LOW(fine)); - return ad9361_spi_write(phy->spi, REG_DCXO_FINE_TUNE_HIGH, - DCXO_TUNE_FINE_HIGH(fine)); -} - - -static int ad9361_txmon_setup(struct ad9361_rf_phy *phy, - struct tx_monitor_control *ctrl) -{ - struct spi_device *spi = phy->spi; - - dev_dbg(&phy->spi->dev, "%s", __func__); - - ad9361_spi_write(spi, REG_TPM_MODE_ENABLE, - (ctrl->one_shot_mode_en ? ONE_SHOT_MODE : 0) | - TX_MON_DURATION(ilog2(ctrl->tx_mon_duration / 16))); - - ad9361_spi_write(spi, REG_TX_MON_DELAY, ctrl->tx_mon_delay & 0xFF); - ad9361_spi_writef(spi, REG_TX_LEVEL_THRESH, - TX_MON_DELAY_COUNTER(~0), ctrl->tx_mon_delay >> 8); - - ad9361_spi_write(spi, REG_TX_MON_1_CONFIG, - TX_MON_1_LO_CM(ctrl->tx1_mon_lo_cm) | - TX_MON_1_GAIN(ctrl->tx1_mon_front_end_gain)); - ad9361_spi_write(spi, REG_TX_MON_2_CONFIG, - TX_MON_2_LO_CM(ctrl->tx2_mon_lo_cm) | - TX_MON_2_GAIN(ctrl->tx2_mon_front_end_gain)); - - ad9361_spi_write(spi, REG_TX_ATTEN_THRESH, - ctrl->low_high_gain_threshold_mdB / 250); - - ad9361_spi_write(spi, REG_TX_MON_HIGH_GAIN, - TX_MON_HIGH_GAIN(ctrl->high_gain_dB)); - - ad9361_spi_write(spi, REG_TX_MON_LOW_GAIN, - (ctrl->tx_mon_track_en ? TX_MON_TRACK : 0) | - TX_MON_LOW_GAIN(ctrl->low_gain_dB)); - - return 0; -} - -static int ad9361_txmon_control(struct ad9361_rf_phy *phy, - unsigned en_mask) -{ - dev_dbg(&phy->spi->dev, "%s: mask 0x%X", __func__, en_mask); - -#if 0 - if (!phy->pdata->fdd && en_mask) { - ad9361_spi_writef(phy->spi, REG_ENSM_CONFIG_1, - ENABLE_RX_DATA_PORT_FOR_CAL, 1); - st->txmon_tdd_en = true; - } else { - ad9361_spi_writef(phy->spi, REG_ENSM_CONFIG_1, - ENABLE_RX_DATA_PORT_FOR_CAL, 0); - st->txmon_tdd_en = false; - } -#endif - - ad9361_spi_writef(phy->spi, REG_ANALOG_POWER_DOWN_OVERRIDE, - TX_MONITOR_POWER_DOWN(~0), ~en_mask); - - ad9361_spi_writef(phy->spi, REG_TPM_MODE_ENABLE, - TX1_MON_ENABLE, !!(en_mask & TX_1)); - - return ad9361_spi_writef(phy->spi, REG_TPM_MODE_ENABLE, - TX2_MON_ENABLE, !!(en_mask & TX_2)); - -} - -/* val - * 0 (RX1A_N & RX1A_P) and (RX2A_N & RX2A_P) enabled; balanced - * 1 (RX1B_N & RX1B_P) and (RX2B_N & RX2B_P) enabled; balanced - * 2 (RX1C_N & RX1C_P) and (RX2C_N & RX2C_P) enabled; balanced - * - * 3 RX1A_N and RX2A_N enabled; unbalanced - * 4 RX1A_P and RX2A_P enabled; unbalanced - * 5 RX1B_N and RX2B_N enabled; unbalanced - * 6 RX1B_P and RX2B_P enabled; unbalanced - * 7 RX1C_N and RX2C_N enabled; unbalanced - * 8 RX1C_P and RX2C_P enabled; unbalanced - * 9 TX_MON1 - * 10 TX_MON2 - * 11 TX_MON1 & TX_MON2 - */ - -static int ad9361_rf_port_setup(struct ad9361_rf_phy *phy, bool is_out, - u32 rx_inputs, u32 txb) -{ - u32 val; - - if (rx_inputs > 11) - return -EINVAL; - - if (!is_out) { - if (rx_inputs > 8) - return ad9361_txmon_control(phy, rx_inputs & (TX_1 | TX_2)); - else - ad9361_txmon_control(phy, 0); - } - - if (rx_inputs < 3) - val = 3 << (rx_inputs * 2); - else - val = 1 << (rx_inputs - 3); - - if (txb) - val |= TX_OUTPUT; /* Select TX1B, TX2B */ - - dev_dbg(&phy->spi->dev, "%s : INPUT_SELECT 0x%X", - __func__, val); - - return ad9361_spi_write(phy->spi, REG_INPUT_SELECT, val); -} - -int ad9361_set_rx_port(struct ad9361_rf_phy *phy, enum rx_port_sel sel) -{ - struct ad9361_rf_phy_state *st; - - if (!phy) - return -EINVAL; - switch (sel) { - case RX_A_BALANCED: /* FALLTHROUGH */ - case RX_B_BALANCED: /* FALLTHROUGH */ - case RX_C_BALANCED: /* FALLTHROUGH */ - case RX_A_N: /* FALLTHROUGH */ - case RX_A_P: /* FALLTHROUGH */ - case RX_B_N: /* FALLTHROUGH */ - case RX_B_P: /* FALLTHROUGH */ - case RX_C_N: /* FALLTHROUGH */ - case RX_C_P: /* FALLTHROUGH */ - case TX_MON1: /* FALLTHROUGH */ - case TX_MON2: /* FALLTHROUGH */ - case TX_MON1_2: - st = phy->state; - if (st->rf_rx_input_sel == sel) - return 0; - st->rf_rx_input_sel = sel; - return ad9361_rf_port_setup(phy, false, sel, - st->rf_tx_output_sel); - default: - return -EINVAL; - } -} -EXPORT_SYMBOL(ad9361_set_rx_port); - -int ad9361_set_tx_port(struct ad9361_rf_phy *phy, enum tx_port_sel sel) -{ - struct ad9361_rf_phy_state *st; - - if (!phy) - return -EINVAL; - switch (sel) { - case (TX_A): /* FALLTHROUGH */ - case (TX_B): - st = phy->state; - if (st->rf_tx_output_sel == sel) - return 0; - st->rf_tx_output_sel = sel; - return ad9361_rf_port_setup(phy, true, st->rf_rx_input_sel, - sel); - default: - return -EINVAL; - } -} -EXPORT_SYMBOL(ad9361_set_tx_port); - -/* - * Setup the Parallel Port (Digital Data Interface) - */ -static int ad9361_pp_port_setup(struct ad9361_rf_phy *phy, bool restore_c3) -{ - struct spi_device *spi = phy->spi; - struct ad9361_phy_platform_data *pd = phy->pdata; - - dev_dbg(&phy->spi->dev, "%s", __func__); - - if (restore_c3) { - return ad9361_spi_write(spi, REG_PARALLEL_PORT_CONF_3, - pd->port_ctrl.pp_conf[2]); - } - - /* Sanity check */ - if (pd->port_ctrl.pp_conf[2] & LVDS_MODE) - pd->port_ctrl.pp_conf[2] &= - ~(HALF_DUPLEX_MODE | SINGLE_DATA_RATE | SINGLE_PORT_MODE); - - if (pd->port_ctrl.pp_conf[2] & FULL_PORT) - pd->port_ctrl.pp_conf[2] &= ~(HALF_DUPLEX_MODE | SINGLE_PORT_MODE); - - ad9361_spi_write(spi, REG_PARALLEL_PORT_CONF_1, pd->port_ctrl.pp_conf[0]); - ad9361_spi_write(spi, REG_PARALLEL_PORT_CONF_2, pd->port_ctrl.pp_conf[1]); - ad9361_spi_write(spi, REG_PARALLEL_PORT_CONF_3, pd->port_ctrl.pp_conf[2]); - ad9361_write_clock_data_delays(phy); - - ad9361_spi_write(spi, REG_LVDS_BIAS_CTRL, pd->port_ctrl.lvds_bias_ctrl); -// ad9361_spi_write(spi, REG_DIGITAL_IO_CTRL, pd->port_ctrl.digital_io_ctrl); - ad9361_spi_write(spi, REG_LVDS_INVERT_CTRL1, pd->port_ctrl.lvds_invert[0]); - ad9361_spi_write(spi, REG_LVDS_INVERT_CTRL2, pd->port_ctrl.lvds_invert[1]); - - if (pd->rx1rx2_phase_inversion_en || - (pd->port_ctrl.pp_conf[1] & INVERT_RX2)) { - - ad9361_spi_writef(spi, REG_PARALLEL_PORT_CONF_2, INVERT_RX2, 1); - ad9361_spi_writef(spi, REG_INVERT_BITS, - INVERT_RX2_RF_DC_CGOUT_WORD, 0); - } - - - return 0; -} - -static int ad9361_gc_setup(struct ad9361_rf_phy *phy, struct gain_control *ctrl) -{ - struct ad9361_rf_phy_state *st = phy->state; - struct spi_device *spi = phy->spi; - u32 reg, tmp1, tmp2; - - dev_dbg(&phy->spi->dev, "%s", __func__); - - reg = DEC_PWR_FOR_GAIN_LOCK_EXIT | DEC_PWR_FOR_LOCK_LEVEL | - DEC_PWR_FOR_LOW_PWR; - - if (ctrl->rx1_mode == RF_GAIN_HYBRID_AGC || - ctrl->rx2_mode == RF_GAIN_HYBRID_AGC) - reg |= SLOW_ATTACK_HYBRID_MODE; - - reg |= RX1_GAIN_CTRL_SETUP(ctrl->rx1_mode) | - RX2_GAIN_CTRL_SETUP(ctrl->rx2_mode); - - st->agc_mode[0] = ctrl->rx1_mode; - st->agc_mode[1] = ctrl->rx2_mode; - - ad9361_spi_write(spi, REG_AGC_CONFIG_1, reg); // Gain Control Mode Select - - /* AGC_USE_FULL_GAIN_TABLE handled in ad9361_load_gt() */ - ad9361_spi_writef(spi, REG_AGC_CONFIG_2, MAN_GAIN_CTRL_RX1, - ctrl->mgc_rx1_ctrl_inp_en); - ad9361_spi_writef(spi, REG_AGC_CONFIG_2, MAN_GAIN_CTRL_RX2, - ctrl->mgc_rx2_ctrl_inp_en); - ad9361_spi_writef(spi, REG_AGC_CONFIG_2, DIG_GAIN_EN, - ctrl->dig_gain_en); - - ctrl->adc_ovr_sample_size = clamp_t(u8, ctrl->adc_ovr_sample_size, 1U, 8U); - reg = ADC_OVERRANGE_SAMPLE_SIZE(ctrl->adc_ovr_sample_size - 1); - - if (phy->pdata->split_gt && - (ctrl->mgc_rx1_ctrl_inp_en || ctrl->mgc_rx2_ctrl_inp_en)) { - switch (ctrl->mgc_split_table_ctrl_inp_gain_mode) { - case 1: - reg &= ~INCDEC_LMT_GAIN; - break; - case 2: - reg |= INCDEC_LMT_GAIN; - break; - default: - case 0: - reg |= USE_AGC_FOR_LMTLPF_GAIN; - break; - } - } - - ctrl->mgc_inc_gain_step = clamp_t(u8, ctrl->mgc_inc_gain_step, 1U, 8U); - reg |= MANUAL_INCR_STEP_SIZE(ctrl->mgc_inc_gain_step - 1); - ad9361_spi_write(spi, REG_AGC_CONFIG_3, reg); // Incr Step Size, ADC Overrange Size - - ctrl->mgc_dec_gain_step = clamp_t(u8, ctrl->mgc_dec_gain_step, 1U, 8U); - reg = MANUAL_CTRL_IN_DECR_GAIN_STP_SIZE(ctrl->mgc_dec_gain_step - 1); - ad9361_spi_write(spi, REG_PEAK_WAIT_TIME, reg); // Decr Step Size, Peak Overload Time - - if (ctrl->dig_gain_en) - ad9361_spi_write(spi, REG_DIGITAL_GAIN, - MAXIMUM_DIGITAL_GAIN(ctrl->max_dig_gain) | - DIG_GAIN_STP_SIZE(ctrl->dig_gain_step_size)); - - if (ctrl->adc_large_overload_thresh >= ctrl->adc_small_overload_thresh) { - ad9361_spi_write(spi, REG_ADC_SMALL_OVERLOAD_THRESH, - ctrl->adc_small_overload_thresh); // ADC Small Overload Threshold - ad9361_spi_write(spi, REG_ADC_LARGE_OVERLOAD_THRESH, - ctrl->adc_large_overload_thresh); // ADC Large Overload Threshold - } else { - ad9361_spi_write(spi, REG_ADC_SMALL_OVERLOAD_THRESH, - ctrl->adc_large_overload_thresh); // ADC Small Overload Threshold - ad9361_spi_write(spi, REG_ADC_LARGE_OVERLOAD_THRESH, - ctrl->adc_small_overload_thresh); // ADC Large Overload Threshold - } - - reg = (ctrl->lmt_overload_high_thresh / 16) - 1; - reg = clamp(reg, 0U, 63U); - ad9361_spi_write(spi, REG_LARGE_LMT_OVERLOAD_THRESH, reg); - reg = (ctrl->lmt_overload_low_thresh / 16) - 1; - reg = clamp(reg, 0U, 63U); - ad9361_spi_writef(spi, REG_SMALL_LMT_OVERLOAD_THRESH, - SMALL_LMT_OVERLOAD_THRESH(~0), reg); - - if (phy->pdata->split_gt) { - /* REVIST */ - ad9361_spi_write(spi, REG_RX1_MANUAL_LPF_GAIN, 0x58); // Rx1 LPF Gain Index - ad9361_spi_write(spi, REG_RX2_MANUAL_LPF_GAIN, 0x18); // Rx2 LPF Gain Index - ad9361_spi_write(spi, REG_FAST_INITIAL_LMT_GAIN_LIMIT, 0x27); // Initial LMT Gain Limit - } - - ad9361_spi_write(spi, REG_RX1_MANUAL_DIGITALFORCED_GAIN, 0x00); // Rx1 Digital Gain Index - ad9361_spi_write(spi, REG_RX2_MANUAL_DIGITALFORCED_GAIN, 0x00); // Rx2 Digital Gain Index - - reg = clamp_t(u8, ctrl->low_power_thresh, 0U, 64U) * 2; - ad9361_spi_write(spi, REG_FAST_LOW_POWER_THRESH, reg); // Low Power Threshold - ad9361_spi_write(spi, REG_TX_SYMBOL_ATTEN_CONFIG, 0x00); // Tx Symbol Gain Control - - ad9361_spi_writef(spi, REG_DEC_POWER_MEASURE_DURATION_0, - USE_HB1_OUT_FOR_DEC_PWR_MEAS, - !ctrl->use_rx_fir_out_for_dec_pwr_meas); // USE HB1 or FIR output for power measurements - - ad9361_spi_writef(spi, REG_DEC_POWER_MEASURE_DURATION_0, - ENABLE_DEC_PWR_MEAS, 1); // Power Measurement Duration - - if (ctrl->rx1_mode == RF_GAIN_FASTATTACK_AGC || - ctrl->rx2_mode == RF_GAIN_FASTATTACK_AGC) - reg = ilog2(ctrl->f_agc_dec_pow_measuremnt_duration / 16); - else - reg = ilog2(ctrl->dec_pow_measuremnt_duration / 16); - - ad9361_spi_writef(spi, REG_DEC_POWER_MEASURE_DURATION_0, - DEC_POWER_MEASUREMENT_DURATION(~0), reg); // Power Measurement Duration - - /* AGC */ - - tmp1 = reg = clamp_t(u8, ctrl->agc_inner_thresh_high, 0U, 127U); - ad9361_spi_writef(spi, REG_AGC_LOCK_LEVEL, - AGC_LOCK_LEVEL_FAST_AGC_INNER_HIGH_THRESH_SLOW(~0), - reg); - - tmp2 = reg = clamp_t(u8, ctrl->agc_inner_thresh_low, 0U, 127U); - reg |= (ctrl->adc_lmt_small_overload_prevent_gain_inc ? - PREVENT_GAIN_INC : 0); - ad9361_spi_write(spi, REG_AGC_INNER_LOW_THRESH, reg); - - reg = AGC_OUTER_HIGH_THRESH(tmp1 - ctrl->agc_outer_thresh_high) | - AGC_OUTER_LOW_THRESH(ctrl->agc_outer_thresh_low - tmp2); - ad9361_spi_write(spi, REG_OUTER_POWER_THRESHS, reg); - - reg = AGC_OUTER_HIGH_THRESH_EXED_STP_SIZE(ctrl->agc_outer_thresh_high_dec_steps) | - AGC_OUTER_LOW_THRESH_EXED_STP_SIZE(ctrl->agc_outer_thresh_low_inc_steps); - ad9361_spi_write(spi, REG_GAIN_STP_2, reg); - - reg = ((ctrl->immed_gain_change_if_large_adc_overload) ? - IMMED_GAIN_CHANGE_IF_LG_ADC_OVERLOAD : 0) | - ((ctrl->immed_gain_change_if_large_lmt_overload) ? - IMMED_GAIN_CHANGE_IF_LG_LMT_OVERLOAD : 0) | - AGC_INNER_HIGH_THRESH_EXED_STP_SIZE(ctrl->agc_inner_thresh_high_dec_steps) | - AGC_INNER_LOW_THRESH_EXED_STP_SIZE(ctrl->agc_inner_thresh_low_inc_steps); - ad9361_spi_write(spi, REG_GAIN_STP1, reg); - - reg = LARGE_ADC_OVERLOAD_EXED_COUNTER(ctrl->adc_large_overload_exceed_counter) | - SMALL_ADC_OVERLOAD_EXED_COUNTER(ctrl->adc_small_overload_exceed_counter); - ad9361_spi_write(spi, REG_ADC_OVERLOAD_COUNTERS, reg); - - reg = DECREMENT_STP_SIZE_FOR_SMALL_LPF_GAIN_CHANGE(ctrl->f_agc_large_overload_inc_steps) | - LARGE_LPF_GAIN_STEP(ctrl->adc_large_overload_inc_steps); - ad9361_spi_write(spi, REG_GAIN_STP_CONFIG_2, reg); - - reg = LARGE_LMT_OVERLOAD_EXED_COUNTER(ctrl->lmt_overload_large_exceed_counter) | - SMALL_LMT_OVERLOAD_EXED_COUNTER(ctrl->lmt_overload_small_exceed_counter); - ad9361_spi_write(spi, REG_LMT_OVERLOAD_COUNTERS, reg); - - ad9361_spi_writef(spi, REG_GAIN_STP_CONFIG1, - DEC_STP_SIZE_FOR_LARGE_LMT_OVERLOAD(~0), - ctrl->lmt_overload_large_inc_steps); - - reg = DIG_SATURATION_EXED_COUNTER(ctrl->dig_saturation_exceed_counter) | - (ctrl->sync_for_gain_counter_en ? - ENABLE_SYNC_FOR_GAIN_COUNTER : 0); - ad9361_spi_write(spi, REG_DIGITAL_SAT_COUNTER, reg); - - /* - * Fast AGC - */ - - /* Fast AGC - Low Power */ - ad9361_spi_writef(spi, REG_FAST_CONFIG_1, - ENABLE_INCR_GAIN, - ctrl->f_agc_allow_agc_gain_increase); - - ad9361_spi_write(spi, REG_FAST_INCREMENT_TIME, - ctrl->f_agc_lp_thresh_increment_time); - - reg = ctrl->f_agc_lp_thresh_increment_steps - 1; - reg = clamp_t(u32, reg, 0U, 7U); - ad9361_spi_writef(spi, REG_FAST_ENERGY_DETECT_COUNT, - INCREMENT_GAIN_STP_LPFLMT(~0), reg); - - /* Fast AGC - Lock Level */ - /* Dual use see also agc_inner_thresh_high */ - ad9361_spi_writef(spi, REG_FAST_CONFIG_2_SETTLING_DELAY, - ENABLE_LMT_GAIN_INC_FOR_LOCK_LEVEL, - ctrl->f_agc_lock_level_lmt_gain_increase_en); - - reg = ctrl->f_agc_lock_level_gain_increase_upper_limit; - reg = clamp_t(u32, reg, 0U, 63U); - ad9361_spi_writef(spi, REG_FAST_AGCLL_UPPER_LIMIT, - AGCLL_MAX_INCREASE(~0), reg); - - /* Fast AGC - Peak Detectors and Final Settling */ - reg = ctrl->f_agc_lpf_final_settling_steps; - reg = clamp_t(u32, reg, 0U, 3U); - ad9361_spi_writef(spi, REG_FAST_ENERGY_LOST_THRESH, - POST_LOCK_LEVEL_STP_SIZE_FOR_LPF_TABLE_FULL_TABLE(~0), - reg); - - reg = ctrl->f_agc_lmt_final_settling_steps; - reg = clamp_t(u32, reg, 0U, 3U); - ad9361_spi_writef(spi, REG_FAST_STRONGER_SIGNAL_THRESH, - POST_LOCK_LEVEL_STP_FOR_LMT_TABLE(~0), reg); - - reg = ctrl->f_agc_final_overrange_count; - reg = clamp_t(u32, reg, 0U, 7U); - ad9361_spi_writef(spi, REG_FAST_FINAL_OVER_RANGE_AND_OPT_GAIN, - FINAL_OVER_RANGE_COUNT(~0), reg); - - /* Fast AGC - Final Power Test */ - ad9361_spi_writef(spi, REG_FAST_CONFIG_1, - ENABLE_GAIN_INC_AFTER_GAIN_LOCK, - ctrl->f_agc_gain_increase_after_gain_lock_en); - - /* Fast AGC - Unlocking the Gain */ - /* 0 = MAX Gain, 1 = Optimized Gain, 2 = Set Gain */ - - reg = ctrl->f_agc_gain_index_type_after_exit_rx_mode; - ad9361_spi_writef(spi, REG_FAST_CONFIG_1, - GOTO_SET_GAIN_IF_EXIT_RX_STATE, reg == SET_GAIN); - ad9361_spi_writef(spi, REG_FAST_CONFIG_1, - GOTO_OPTIMIZED_GAIN_IF_EXIT_RX_STATE, - reg == OPTIMIZED_GAIN); - - ad9361_spi_writef(spi, REG_FAST_CONFIG_2_SETTLING_DELAY, - USE_LAST_LOCK_LEVEL_FOR_SET_GAIN, - ctrl->f_agc_use_last_lock_level_for_set_gain_en); - - reg = ctrl->f_agc_optimized_gain_offset; - reg = clamp_t(u32, reg, 0U, 15U); - ad9361_spi_writef(spi, REG_FAST_FINAL_OVER_RANGE_AND_OPT_GAIN, - OPTIMIZE_GAIN_OFFSET(~0), reg); - - tmp1 = !ctrl->f_agc_rst_gla_stronger_sig_thresh_exceeded_en || - !ctrl->f_agc_rst_gla_engergy_lost_sig_thresh_exceeded_en || - !ctrl->f_agc_rst_gla_large_adc_overload_en || - !ctrl->f_agc_rst_gla_large_lmt_overload_en || - ctrl->f_agc_rst_gla_en_agc_pulled_high_en; - - ad9361_spi_writef(spi, REG_AGC_CONFIG_2, - AGC_GAIN_UNLOCK_CTRL, tmp1); - - reg = !ctrl->f_agc_rst_gla_stronger_sig_thresh_exceeded_en; - ad9361_spi_writef(spi, REG_FAST_STRONG_SIGNAL_FREEZE, - DONT_UNLOCK_GAIN_IF_STRONGER_SIGNAL, reg); - - reg = ctrl->f_agc_rst_gla_stronger_sig_thresh_above_ll; - reg = clamp_t(u32, reg, 0U, 63U); - ad9361_spi_writef(spi, REG_FAST_STRONGER_SIGNAL_THRESH, - STRONGER_SIGNAL_THRESH(~0), reg); - - reg = ctrl->f_agc_rst_gla_engergy_lost_sig_thresh_below_ll; - reg = clamp_t(u32, reg, 0U, 63U); - ad9361_spi_writef(spi, REG_FAST_ENERGY_LOST_THRESH, - ENERGY_LOST_THRESH(~0), reg); - - reg = ctrl->f_agc_rst_gla_engergy_lost_goto_optim_gain_en; - ad9361_spi_writef(spi, REG_FAST_CONFIG_1, - GOTO_OPT_GAIN_IF_ENERGY_LOST_OR_EN_AGC_HIGH, reg); - - reg = !ctrl->f_agc_rst_gla_engergy_lost_sig_thresh_exceeded_en; - ad9361_spi_writef(spi, REG_FAST_CONFIG_1, - DONT_UNLOCK_GAIN_IF_ENERGY_LOST, reg); - - reg = ctrl->f_agc_energy_lost_stronger_sig_gain_lock_exit_cnt; - reg = clamp_t(u32, reg, 0U, 63U); - ad9361_spi_writef(spi, REG_FAST_GAIN_LOCK_EXIT_COUNT, - GAIN_LOCK_EXIT_COUNT(~0), reg); - - reg = !ctrl->f_agc_rst_gla_large_adc_overload_en || - !ctrl->f_agc_rst_gla_large_lmt_overload_en; - ad9361_spi_writef(spi, REG_FAST_CONFIG_1, - DONT_UNLOCK_GAIN_IF_LG_ADC_OR_LMT_OVRG, reg); - - reg = !ctrl->f_agc_rst_gla_large_adc_overload_en; - ad9361_spi_writef(spi, REG_FAST_LOW_POWER_THRESH, - DONT_UNLOCK_GAIN_IF_ADC_OVRG, reg); - - /* 0 = Max Gain, 1 = Set Gain, 2 = Optimized Gain, 3 = No Gain Change */ - - if (ctrl->f_agc_rst_gla_en_agc_pulled_high_en) { - switch (ctrl->f_agc_rst_gla_if_en_agc_pulled_high_mode) { - case MAX_GAIN: - ad9361_spi_writef(spi, REG_FAST_CONFIG_2_SETTLING_DELAY, - GOTO_MAX_GAIN_OR_OPT_GAIN_IF_EN_AGC_HIGH, 1); - - ad9361_spi_writef(spi, REG_FAST_CONFIG_1, - GOTO_SET_GAIN_IF_EN_AGC_HIGH, 0); - - ad9361_spi_writef(spi, REG_FAST_CONFIG_1, - GOTO_OPT_GAIN_IF_ENERGY_LOST_OR_EN_AGC_HIGH, 0); - break; - case SET_GAIN: - ad9361_spi_writef(spi, REG_FAST_CONFIG_2_SETTLING_DELAY, - GOTO_MAX_GAIN_OR_OPT_GAIN_IF_EN_AGC_HIGH, 0); - - ad9361_spi_writef(spi, REG_FAST_CONFIG_1, - GOTO_SET_GAIN_IF_EN_AGC_HIGH, 1); - break; - case OPTIMIZED_GAIN: - ad9361_spi_writef(spi, REG_FAST_CONFIG_2_SETTLING_DELAY, - GOTO_MAX_GAIN_OR_OPT_GAIN_IF_EN_AGC_HIGH, 1); - - ad9361_spi_writef(spi, REG_FAST_CONFIG_1, - GOTO_SET_GAIN_IF_EN_AGC_HIGH, 0); - - ad9361_spi_writef(spi, REG_FAST_CONFIG_1, - GOTO_OPT_GAIN_IF_ENERGY_LOST_OR_EN_AGC_HIGH, 1); - break; - case NO_GAIN_CHANGE: - ad9361_spi_writef(spi, REG_FAST_CONFIG_1, - GOTO_SET_GAIN_IF_EN_AGC_HIGH, 0); - ad9361_spi_writef(spi, REG_FAST_CONFIG_2_SETTLING_DELAY, - GOTO_MAX_GAIN_OR_OPT_GAIN_IF_EN_AGC_HIGH, 0); - break; - } - } else { - ad9361_spi_writef(spi, REG_FAST_CONFIG_1, - GOTO_SET_GAIN_IF_EN_AGC_HIGH, 0); - ad9361_spi_writef(spi, REG_FAST_CONFIG_2_SETTLING_DELAY, - GOTO_MAX_GAIN_OR_OPT_GAIN_IF_EN_AGC_HIGH, 0); - } - - reg = ilog2(ctrl->f_agc_power_measurement_duration_in_state5 / 16); - reg = clamp_t(u32, reg, 0U, 15U); - ad9361_spi_writef(spi, REG_RX1_MANUAL_LPF_GAIN, - POWER_MEAS_IN_STATE_5(~0), reg); - ad9361_spi_writef(spi, REG_RX1_MANUAL_LMT_FULL_GAIN, - POWER_MEAS_IN_STATE_5_MSB, reg >> 3); - - return ad9361_gc_update(phy); -} - -static int ad9361_auxdac_set(struct ad9361_rf_phy *phy, unsigned dac, - unsigned val_mV) -{ - struct ad9361_rf_phy_state *st = phy->state; - struct spi_device *spi = phy->spi; - u32 val, tmp; - - dev_dbg(&phy->spi->dev, "%s DAC%d = %d mV", __func__, dac, val_mV); - - /* Disable DAC if val == 0, Ignored in ENSM Auto Mode */ - ad9361_spi_writef(spi, REG_AUXDAC_ENABLE_CTRL, - AUXDAC_MANUAL_BAR(dac), val_mV ? 0 : 1); - - if (val_mV < 306) - val_mV = 306; - - if (val_mV < 1888) { - val = ((val_mV - 306) * 1000) / 1469; /* Vref = 1V, Step = 2 */ - tmp = AUXDAC_1_VREF(0); - } else { - val = ((val_mV - 1761) * 1000) / 1512; /* Vref = 2.5V, Step = 2 */ - tmp = AUXDAC_1_VREF(3); - } - - val = clamp_t(u32, val, 0, 1023); - - switch (dac) { - case 1: - ad9361_spi_write(spi, REG_AUXDAC_1_WORD, val >> 2); - ad9361_spi_write(spi, REG_AUXDAC_1_CONFIG, AUXDAC_1_WORD_LSB(val) | tmp); - st->auxdac1_value = val_mV; - break; - case 2: - ad9361_spi_write(spi, REG_AUXDAC_2_WORD, val >> 2); - ad9361_spi_write(spi, REG_AUXDAC_2_CONFIG, AUXDAC_2_WORD_LSB(val) | tmp); - st->auxdac2_value = val_mV; - break; - default: - return -EINVAL; - } - - return 0; -} - -static int ad9361_auxdac_get(struct ad9361_rf_phy *phy, unsigned dac) -{ - struct ad9361_rf_phy_state *st = phy->state; - - switch (dac) { - case 1: - return st->auxdac1_value; - case 2: - return st->auxdac2_value; - default: - return -EINVAL; - } - - return 0; -} - - //************************************************************ - // Setup AuxDAC - //************************************************************ -static int ad9361_auxdac_setup(struct ad9361_rf_phy *phy, - struct auxdac_control *ctrl) -{ - struct spi_device *spi = phy->spi; - u8 tmp; - - dev_dbg(&phy->spi->dev, "%s", __func__); - - ad9361_auxdac_set(phy, 1, ctrl->dac1_default_value); - ad9361_auxdac_set(phy, 2, ctrl->dac2_default_value); - - tmp = ~(AUXDAC_AUTO_TX_BAR(ctrl->dac2_in_tx_en << 1 | ctrl->dac1_in_tx_en) | - AUXDAC_AUTO_RX_BAR(ctrl->dac2_in_rx_en << 1 | ctrl->dac1_in_rx_en) | - AUXDAC_INIT_BAR(ctrl->dac2_in_alert_en << 1 | ctrl->dac1_in_alert_en)); - - ad9361_spi_writef(spi, REG_AUXDAC_ENABLE_CTRL, - AUXDAC_AUTO_TX_BAR(~0) | - AUXDAC_AUTO_RX_BAR(~0) | - AUXDAC_INIT_BAR(~0), - tmp); /* Auto Control */ - - ad9361_spi_writef(spi, REG_EXTERNAL_LNA_CTRL, - AUXDAC_MANUAL_SELECT, ctrl->auxdac_manual_mode_en); - ad9361_spi_write(spi, REG_AUXDAC1_RX_DELAY, ctrl->dac1_rx_delay_us); - ad9361_spi_write(spi, REG_AUXDAC1_TX_DELAY, ctrl->dac1_tx_delay_us); - ad9361_spi_write(spi, REG_AUXDAC2_RX_DELAY, ctrl->dac2_rx_delay_us); - ad9361_spi_write(spi, REG_AUXDAC2_TX_DELAY, ctrl->dac2_tx_delay_us); - - return 0; -} - - //************************************************************ - // Setup AuxADC - //************************************************************ - -static int ad9361_auxadc_setup(struct ad9361_rf_phy *phy, - struct auxadc_control *ctrl, - unsigned long bbpll_freq) -{ - struct spi_device *spi = phy->spi; - u32 val; - - dev_dbg(&phy->spi->dev, "%s", __func__); - - val = DIV_ROUND_CLOSEST(ctrl->temp_time_inteval_ms * - (bbpll_freq / 1000UL), (1 << 29)); - - ad9361_spi_write(spi, REG_TEMP_OFFSET, ctrl->offset); - ad9361_spi_write(spi, REG_START_TEMP_READING, 0x00); - ad9361_spi_write(spi, REG_TEMP_SENSE2, - MEASUREMENT_TIME_INTERVAL(val) | - (ctrl->periodic_temp_measuremnt ? - TEMP_SENSE_PERIODIC_ENABLE : 0)); - ad9361_spi_write(spi, REG_TEMP_SENSOR_CONFIG, - TEMP_SENSOR_DECIMATION( - ilog2(ctrl->temp_sensor_decimation) - 8)); - ad9361_spi_write(spi, REG_AUXADC_CLOCK_DIVIDER, - bbpll_freq / ctrl->auxadc_clock_rate); - ad9361_spi_write(spi, REG_AUXADC_CONFIG, - AUX_ADC_DECIMATION( - ilog2(ctrl->auxadc_decimation) - 8)); - - return 0; -} - -static int ad9361_get_temp(struct ad9361_rf_phy *phy) -{ - s32 val; - - ad9361_spi_writef(phy->spi, REG_AUXADC_CONFIG, AUXADC_POWER_DOWN, 1); - val = (s8) ad9361_spi_read(phy->spi, REG_TEMPERATURE); - ad9361_spi_writef(phy->spi, REG_AUXADC_CONFIG, AUXADC_POWER_DOWN, 0); - - return DIV_ROUND_CLOSEST(val * 1000000, 1140); -} - -static int ad9361_get_auxadc(struct ad9361_rf_phy *phy) -{ - u32 val; - u8 buf[2]; - - ad9361_spi_writef(phy->spi, REG_AUXADC_CONFIG, AUXADC_POWER_DOWN, 1); - val = ad9361_spi_readm(phy->spi, REG_AUXADC_LSB, buf, 2); - ad9361_spi_writef(phy->spi, REG_AUXADC_CONFIG, AUXADC_POWER_DOWN, 0); - - return (buf[1] << 4) | AUXADC_WORD_LSB(buf[0]); -} - - //************************************************************ - // Setup Control Outs - //************************************************************ - -int ad9361_ctrl_outs_setup(struct ad9361_rf_phy *phy, - struct ctrl_outs_control *ctrl) -{ - struct spi_device *spi = phy->spi; - - dev_dbg(&phy->spi->dev, "%s", __func__); - - ad9361_spi_write(spi, REG_CTRL_OUTPUT_POINTER, ctrl->index); // Ctrl Out index - return ad9361_spi_write(spi, REG_CTRL_OUTPUT_ENABLE, ctrl->en_mask); // Ctrl Out [7:0] output enable -} -EXPORT_SYMBOL(ad9361_ctrl_outs_setup); - //************************************************************ - // Setup GPO - //************************************************************ - -static int ad9361_gpo_setup(struct ad9361_rf_phy *phy, struct gpo_control *ctrl) -{ - struct spi_device *spi = phy->spi; - - dev_dbg(&phy->spi->dev, "%s", __func__); - - ad9361_spi_write(spi, REG_AUTO_GPO, - GPO_ENABLE_AUTO_RX(ctrl->gpo0_slave_rx_en | - (ctrl->gpo1_slave_rx_en << 1) | - (ctrl->gpo2_slave_rx_en << 2) | - (ctrl->gpo3_slave_rx_en << 3)) | - GPO_ENABLE_AUTO_TX(ctrl->gpo0_slave_tx_en | - (ctrl->gpo1_slave_tx_en << 1) | - (ctrl->gpo2_slave_tx_en << 2) | - (ctrl->gpo3_slave_tx_en << 3))); - - ad9361_spi_write(spi, REG_GPO_FORCE_AND_INIT, - GPO_MANUAL_CTRL(ctrl->gpo_manual_mode_enable_mask) | - GPO_INIT_STATE(ctrl->gpo0_inactive_state_high_en | - (ctrl->gpo1_inactive_state_high_en << 1) | - (ctrl->gpo2_inactive_state_high_en << 2) | - (ctrl->gpo3_inactive_state_high_en << 3))); - - ad9361_spi_write(spi, REG_GPO0_RX_DELAY, ctrl->gpo0_rx_delay_us); - ad9361_spi_write(spi, REG_GPO0_TX_DELAY, ctrl->gpo0_tx_delay_us); - ad9361_spi_write(spi, REG_GPO1_RX_DELAY, ctrl->gpo1_rx_delay_us); - ad9361_spi_write(spi, REG_GPO1_TX_DELAY, ctrl->gpo1_tx_delay_us); - ad9361_spi_write(spi, REG_GPO2_RX_DELAY, ctrl->gpo2_rx_delay_us); - ad9361_spi_write(spi, REG_GPO2_TX_DELAY, ctrl->gpo2_tx_delay_us); - ad9361_spi_write(spi, REG_GPO3_RX_DELAY, ctrl->gpo3_rx_delay_us); - ad9361_spi_write(spi, REG_GPO3_TX_DELAY, ctrl->gpo3_tx_delay_us); - - /* - * GPO manual mode conflicts with automatic ENSM slave and eLNA mode - */ - ad9361_spi_writef(phy->spi, REG_EXTERNAL_LNA_CTRL, GPO_MANUAL_SELECT, - ctrl->gpo_manual_mode_en); - - return 0; -} - -static int ad9361_rssi_setup(struct ad9361_rf_phy *phy, - struct rssi_control *ctrl, - bool is_update) -{ - struct spi_device *spi = phy->spi; - u32 total_weight, weight[4], total_dur = 0, temp; - u8 dur_buf[4] = {0}; - int val, ret, i, j = 0; - u32 rssi_delay; - u32 rssi_wait; - s32 rssi_duration; - unsigned long rate; - - dev_dbg(&phy->spi->dev, "%s", __func__); - - if (ctrl->rssi_unit_is_rx_samples) { - if (is_update) - return 0; /* no update required */ - - rssi_delay = ctrl->rssi_delay; - rssi_wait = ctrl->rssi_wait; - rssi_duration = ctrl->rssi_duration; - } else { - /* update sample based on RX rate */ - rate = DIV_ROUND_CLOSEST( - clk_get_rate(phy->clks[RX_SAMPL_CLK]), 1000); - /* units are in us */ - rssi_delay = DIV_ROUND_CLOSEST(ctrl->rssi_delay * rate, 1000); - rssi_wait = DIV_ROUND_CLOSEST(ctrl->rssi_wait * rate, 1000); - rssi_duration = DIV_ROUND_CLOSEST( - ctrl->rssi_duration * rate, 1000); - } - - if (ctrl->restart_mode == EN_AGC_PIN_IS_PULLED_HIGH) - rssi_delay = 0; - - rssi_delay = clamp(rssi_delay / 8, 0U, 255U); - rssi_wait = clamp(rssi_wait / 4, 0U, 255U); - - do { - for (i = 14; rssi_duration > 0 && i >= 0 ; i--) { - val = 1 << i; - - if (rssi_duration >= val) { - dur_buf[j++] = i; - total_dur += val; - rssi_duration -= val; - break; - } - } - - } while (j < 4 && rssi_duration > 0); - - for (i = 0, total_weight = 0; i < 4; i++) { - if (i < j) - total_weight += weight[i] = - DIV_ROUND_CLOSEST(RSSI_MAX_WEIGHT * - (1 << dur_buf[i]), total_dur); - else - total_weight += weight[i] = 0; - } - - /* total of all weights must be 0xFF */ - val = total_weight - 0xFF; - weight[j - 1] -= val; - - ad9361_spi_write(spi, REG_MEASURE_DURATION_01, - (dur_buf[1] << 4) | dur_buf[0]); // RSSI Measurement Duration 0, 1 - ad9361_spi_write(spi, REG_MEASURE_DURATION_23, - (dur_buf[3] << 4) | dur_buf[2]); // RSSI Measurement Duration 2, 3 - ad9361_spi_write(spi, REG_RSSI_WEIGHT_0, weight[0]); // RSSI Weighted Multiplier 0 - ad9361_spi_write(spi, REG_RSSI_WEIGHT_1, weight[1]); // RSSI Weighted Multiplier 1 - ad9361_spi_write(spi, REG_RSSI_WEIGHT_2, weight[2]); // RSSI Weighted Multiplier 2 - ad9361_spi_write(spi, REG_RSSI_WEIGHT_3, weight[3]); // RSSI Weighted Multiplier 3 - ad9361_spi_write(spi, REG_RSSI_DELAY, rssi_delay); // RSSI Delay - ad9361_spi_write(spi, REG_RSSI_WAIT_TIME, rssi_wait); // RSSI Wait - - temp = RSSI_MODE_SELECT(ctrl->restart_mode); - if (ctrl->restart_mode == SPI_WRITE_TO_REGISTER) - temp |= START_RSSI_MEAS; - - if (rssi_duration == 0 && j == 1) /* Power of two */ - temp |= DEFAULT_RSSI_MEAS_MODE; - - ret = ad9361_spi_write(spi, REG_RSSI_CONFIG, temp); // RSSI Mode Select - - if (ret < 0) - dev_err(&phy->spi->dev, "Unable to write rssi config\n"); - - return 0; -} - -static int ad9361_bb_clk_change_handler(struct ad9361_rf_phy *phy) -{ - int ret; - - ret = ad9361_gc_update(phy); - ret |= ad9361_rssi_setup(phy, &phy->pdata->rssi_ctrl, true); - ret |= ad9361_auxadc_setup(phy, &phy->pdata->auxadc_ctrl, - clk_get_rate(phy->clks[BBPLL_CLK])); - - return ret; -} - -static int ad9361_ensm_set_state(struct ad9361_rf_phy *phy, u8 ensm_state, - bool pinctrl) -{ - struct ad9361_rf_phy_state *st = phy->state; - struct spi_device *spi = phy->spi; - struct device *dev = &phy->spi->dev; - int rc = 0; - u32 val; - - dev_dbg(dev, "Device is in %x state, moving to %x\n", st->curr_ensm_state, - ensm_state); - - - if (st->curr_ensm_state == ENSM_STATE_SLEEP) { - ad9361_spi_write(spi, REG_CLOCK_ENABLE, - DIGITAL_POWER_UP | CLOCK_ENABLE_DFLT | BBPLL_ENABLE | - (phy->pdata->use_extclk ? XO_BYPASS : 0)); /* Enable Clocks */ - udelay(20); - ad9361_spi_write(spi, REG_ENSM_CONFIG_1, TO_ALERT | FORCE_ALERT_STATE); - ad9361_trx_vco_cal_control(phy, false, true); /* Enable VCO Cal */ - ad9361_trx_vco_cal_control(phy, true, true); - } - - val = (phy->pdata->ensm_pin_pulse_mode ? 0 : LEVEL_MODE) | - (pinctrl ? ENABLE_ENSM_PIN_CTRL : 0) | - (st->txmon_tdd_en ? ENABLE_RX_DATA_PORT_FOR_CAL : 0) | - TO_ALERT; - - switch (ensm_state) { - case ENSM_STATE_TX: - val |= FORCE_TX_ON; - if (phy->pdata->fdd) - rc = -EINVAL; - else if (st->curr_ensm_state != ENSM_STATE_ALERT) - rc = -EINVAL; - break; - case ENSM_STATE_RX: - val |= FORCE_RX_ON; - if (phy->pdata->fdd) - rc = -EINVAL; - else if (st->curr_ensm_state != ENSM_STATE_ALERT) - rc = -EINVAL; - break; - case ENSM_STATE_FDD: - val |= FORCE_TX_ON; - if (!phy->pdata->fdd) - rc = -EINVAL; - break; - case ENSM_STATE_ALERT: - val &= ~(FORCE_TX_ON | FORCE_RX_ON); - val |= TO_ALERT | FORCE_ALERT_STATE; - break; - case ENSM_STATE_SLEEP_WAIT: - break; - case ENSM_STATE_SLEEP: - ad9361_trx_vco_cal_control(phy, false, false); /* Disable VCO Cal */ - ad9361_trx_vco_cal_control(phy, true, false); - ad9361_spi_write(spi, REG_ENSM_CONFIG_1, 0); /* Clear To Alert */ - ad9361_spi_write(spi, REG_ENSM_CONFIG_1, - phy->pdata->fdd ? FORCE_TX_ON : FORCE_RX_ON); - /* Delay Flush Time 384 ADC clock cycles */ - udelay(384000000UL / clk_get_rate(phy->clks[ADC_CLK])); - ad9361_spi_write(spi, REG_ENSM_CONFIG_1, 0); /* Move to Wait*/ - udelay(1); /* Wait for ENSM settle */ - ad9361_spi_write(spi, REG_CLOCK_ENABLE, - (phy->pdata->use_extclk ? XO_BYPASS : 0)); /* Turn off all clocks */ - st->curr_ensm_state = ensm_state; - return 0; - - default: - dev_err(dev, "No handling for forcing %d ensm state\n", - ensm_state); - goto out; - } - - if (rc) { - if ((st->curr_ensm_state != ENSM_STATE_ALERT) && (val & (FORCE_RX_ON | FORCE_TX_ON))) { - u32 val2 = val; - - val2 &= ~(FORCE_TX_ON | FORCE_RX_ON); - val2 |= TO_ALERT | FORCE_ALERT_STATE; - ad9361_spi_write(spi, REG_ENSM_CONFIG_1, val2); - - ad9361_check_cal_done(phy, REG_STATE, ENSM_STATE(~0), ENSM_STATE_ALERT); - } else { - dev_err(dev, "Invalid ENSM state transition in %s mode\n", - phy->pdata->fdd ? "FDD" : "TDD"); - goto out; - } - } - - if (!phy->pdata->fdd && !pinctrl && !phy->pdata->tdd_use_dual_synth && - (ensm_state == ENSM_STATE_TX || ensm_state == ENSM_STATE_RX)) { - u32 reg, check; - - if (ensm_state == ENSM_STATE_TX) { - reg = REG_TX_CP_OVERRANGE_VCO_LOCK; - check = !(st->cached_synth_pd[0] & - TX_SYNTH_VCO_POWER_DOWN); - } else { - reg = REG_RX_CP_OVERRANGE_VCO_LOCK; - check = !(st->cached_synth_pd[1] & - RX_SYNTH_VCO_POWER_DOWN); - } - - ad9361_spi_writef(phy->spi, REG_ENSM_CONFIG_2, - TXNRX_SPI_CTRL, ensm_state == ENSM_STATE_TX); - if (check) - ad9361_check_cal_done(phy, reg, VCO_LOCK, 1); - } - - rc = ad9361_spi_write(spi, REG_ENSM_CONFIG_1, val); - if (rc) - dev_err(dev, "Failed to restore state\n"); - - if ((val & FORCE_RX_ON) && - (st->agc_mode[0] == RF_GAIN_MGC || - st->agc_mode[1] == RF_GAIN_MGC)) { - u32 tmp = ad9361_spi_read(spi, REG_SMALL_LMT_OVERLOAD_THRESH); - ad9361_spi_write(spi, REG_SMALL_LMT_OVERLOAD_THRESH, - (tmp & SMALL_LMT_OVERLOAD_THRESH(~0)) | - (st->agc_mode[0] == RF_GAIN_MGC ? FORCE_PD_RESET_RX1 : 0) | - (st->agc_mode[1] == RF_GAIN_MGC ? FORCE_PD_RESET_RX2 : 0)); - ad9361_spi_write(spi, REG_SMALL_LMT_OVERLOAD_THRESH, - tmp & SMALL_LMT_OVERLOAD_THRESH(~0)); - } - - st->curr_ensm_state = ensm_state; - -out: - return rc; - -} - -static int ad9361_validate_trx_clock_chain(struct ad9361_rf_phy *phy, - unsigned long *rx_path_clks, - unsigned long *tx_path_clks) -{ - static const unsigned long max_rx_rates[] = {MAX_BBPLL_FREQ, MAX_ADC_CLK, - MAX_RX_HB3, MAX_RX_HB2, MAX_RX_HB1, MAX_BASEBAND_RATE}; - static const unsigned long max_tx_rates[] = {MAX_BBPLL_FREQ, MAX_DAC_CLK, - MAX_TX_HB3, MAX_TX_HB2, MAX_TX_HB1, MAX_BASEBAND_RATE}; - int i, data_clk; - - data_clk = (phy->pdata->rx2tx2 ? 4 : 2) / - ((phy->pdata->port_ctrl.pp_conf[2] & LVDS_MODE) ? 1 : 2) * - rx_path_clks[RX_SAMPL_FREQ]; - - /* CMOS Mode */ - if (!(phy->pdata->port_ctrl.pp_conf[2] & LVDS_MODE) && - (data_clk > MAX_BASEBAND_RATE)) { - dev_err(&phy->spi->dev, - "%s: Failed CMOS MODE DATA_CLK > 61.44MSPS", __func__); - return -EINVAL; - } - - /* Validate MAX PLL, ADC, DAC and HB filter rates */ - for (i = 0; i < ARRAY_SIZE(max_rx_rates); i++) { - if (rx_path_clks[i] > max_rx_rates[i]) { - dev_err(&phy->spi->dev, - "%s: Failed RX max rate check (%lu > %lu)", - __func__, rx_path_clks[i], max_rx_rates[i]); - return -EINVAL; - } - - if (tx_path_clks[i] > max_tx_rates[i]) { - dev_err(&phy->spi->dev, - "%s: Failed TX max rate check (%lu > %lu)", - __func__, tx_path_clks[i], max_tx_rates[i]); - return -EINVAL; - } - } - - /* Validate that DATA_CLK exist within the clock chain */ - for (i = 1; i <= 3; i++) { - if (abs(rx_path_clks[ADC_FREQ] / i - data_clk) < 4) - return 0; - } - - for (i = 1; i <= 4; i++) { - if (abs((rx_path_clks[R2_FREQ] >> i) - data_clk) < 4) - return 0; - } - - dev_err(&phy->spi->dev, "%s: Failed - at least one of the clock rates" - " must be equal to the DATA_CLK (lvds) rate", __func__); - - return -EINVAL; -} - -static int ad9361_set_trx_clock_chain(struct ad9361_rf_phy *phy, - unsigned long *rx_path_clks, - unsigned long *tx_path_clks) -{ - struct device *dev = &phy->spi->dev; - struct ad9361_rf_phy_state *st = phy->state; - int ret, i, j, n; - - dev_dbg(&phy->spi->dev, "%s", __func__); - - if (!rx_path_clks || !tx_path_clks) - return -EINVAL; - - dev_dbg(&phy->spi->dev, "%s: %lu %lu %lu %lu %lu %lu", - __func__, rx_path_clks[BBPLL_FREQ], rx_path_clks[ADC_FREQ], - rx_path_clks[R2_FREQ], rx_path_clks[R1_FREQ], - rx_path_clks[CLKRF_FREQ], rx_path_clks[RX_SAMPL_FREQ]); - - dev_dbg(&phy->spi->dev, "%s: %lu %lu %lu %lu %lu %lu", - __func__, tx_path_clks[BBPLL_FREQ], tx_path_clks[ADC_FREQ], - tx_path_clks[R2_FREQ], tx_path_clks[R1_FREQ], - tx_path_clks[CLKRF_FREQ], tx_path_clks[RX_SAMPL_FREQ]); - - ret = ad9361_validate_trx_clock_chain(phy, rx_path_clks, tx_path_clks); - if (ret < 0) - return ret; - - ret = clk_set_rate(phy->clks[BBPLL_CLK], rx_path_clks[BBPLL_FREQ]); - if (ret < 0) - return ret; - - st->current_rx_path_clks[BBPLL_FREQ] = rx_path_clks[BBPLL_FREQ]; - - for (i = ADC_CLK, j = DAC_CLK, n = ADC_FREQ; - i <= RX_SAMPL_CLK; i++, j++, n++) { - ret = clk_set_rate(phy->clks[i], rx_path_clks[n]); - if (ret < 0) { - dev_err(dev, "Failed to set BB ref clock rate (%d)\n", - ret); - return ret; - } - st->current_rx_path_clks[n] = rx_path_clks[n]; - ret = clk_set_rate(phy->clks[j], tx_path_clks[n]); - if (ret < 0) { - dev_err(dev, "Failed to set BB ref clock rate (%d)\n", - ret); - return ret; - } - st->current_tx_path_clks[n] = tx_path_clks[n]; - } - - /* - * Workaround for clock framework since clocks don't change we - * manually need to enable the filter - */ - - if (st->rx_fir_dec == 1 || st->bypass_rx_fir) { - ad9361_spi_writef(phy->spi, REG_RX_ENABLE_FILTER_CTRL, - RX_FIR_ENABLE_DECIMATION(~0), !st->bypass_rx_fir); - } - - if (st->tx_fir_int == 1 || st->bypass_tx_fir) { - ad9361_spi_writef(phy->spi, REG_TX_ENABLE_FILTER_CTRL, - TX_FIR_ENABLE_INTERPOLATION(~0), !st->bypass_tx_fir); - } - - /* The FIR filter once enabled causes the interface timing to change. - * It's typically not a problem if the timing margin is big enough. - * However at 61.44 MSPS it causes problems on some systems. - * So we always run the digital tune in case the filter is enabled. - * If it is disabled we restore the values from the initial calibration. - */ - - if (!phy->pdata->dig_interface_tune_fir_disable && - !(st->bypass_tx_fir && st->bypass_rx_fir)) - ret = ad9361_dig_tune(phy, 0, SKIP_STORE_RESULT); - - return ad9361_bb_clk_change_handler(phy); -} - -int ad9361_set_trx_clock_chain_default(struct ad9361_rf_phy *phy) -{ - return ad9361_set_trx_clock_chain(phy, - phy->pdata->rx_path_clks, - phy->pdata->tx_path_clks); -} -EXPORT_SYMBOL(ad9361_set_trx_clock_chain_default); - -bool ad9361_uses_rx2tx2(struct ad9361_rf_phy *phy) -{ - return phy && phy->pdata && phy->pdata->rx2tx2; -} -EXPORT_SYMBOL(ad9361_uses_rx2tx2); - -int ad9361_get_dig_tune_data(struct ad9361_rf_phy *phy, - struct ad9361_dig_tune_data *data) -{ - struct ad9361_rf_phy_state *st; - if (!phy || !data) - return -EINVAL; - st = phy->state; - data->ensm_state = ad9361_ensm_get_state(phy); - data->bist_loopback_mode = st->bist_loopback_mode; - data->skip_mode = phy->pdata->dig_interface_tune_skipmode; - data->bist_config = st->bist_config; - return 0; -} -EXPORT_SYMBOL(ad9361_get_dig_tune_data); - -bool ad9361_uses_lvds_mode(struct ad9361_rf_phy *phy) -{ - return (phy && phy->pdata && - !!(phy->pdata->port_ctrl.pp_conf[2] & LVDS_MODE)); -} -EXPORT_SYMBOL(ad9361_uses_lvds_mode); - -int ad9361_write_clock_data_delays(struct ad9361_rf_phy *phy) -{ - if (!phy || !phy->pdata) - return -EINVAL; - ad9361_spi_write(phy->spi, REG_RX_CLOCK_DATA_DELAY, - phy->pdata->port_ctrl.rx_clk_data_delay); - ad9361_spi_write(phy->spi, REG_TX_CLOCK_DATA_DELAY, - phy->pdata->port_ctrl.tx_clk_data_delay); - return 0; -} -EXPORT_SYMBOL(ad9361_write_clock_data_delays); - -int ad9361_read_clock_data_delays(struct ad9361_rf_phy *phy) -{ - if (!phy || !phy->pdata) - return -EINVAL; - phy->pdata->port_ctrl.rx_clk_data_delay = - ad9361_spi_read(phy->spi, REG_RX_CLOCK_DATA_DELAY); - phy->pdata->port_ctrl.tx_clk_data_delay = - ad9361_spi_read(phy->spi, REG_TX_CLOCK_DATA_DELAY); - return 0; -} -EXPORT_SYMBOL(ad9361_read_clock_data_delays); - -static int ad9361_get_trx_clock_chain(struct ad9361_rf_phy *phy, unsigned long *rx_path_clks, - unsigned long *tx_path_clks) -{ - int i, j, n; - unsigned long bbpll_freq; - - if (!rx_path_clks && !tx_path_clks) - return -EINVAL; - - bbpll_freq = clk_get_rate(phy->clks[BBPLL_CLK]); - - if (rx_path_clks) - rx_path_clks[BBPLL_FREQ] = bbpll_freq; - - if (tx_path_clks) - tx_path_clks[BBPLL_FREQ] = bbpll_freq; - - for (i = ADC_CLK, j = DAC_CLK, n = ADC_FREQ; - i <= RX_SAMPL_CLK; i++, j++, n++) { - if (rx_path_clks) - rx_path_clks[n] = clk_get_rate(phy->clks[i]); - if (tx_path_clks) - tx_path_clks[n] = clk_get_rate(phy->clks[j]); - } - - return 0; -} - -static int ad9361_calculate_rf_clock_chain(struct ad9361_rf_phy *phy, - unsigned long tx_sample_rate, - u32 rate_gov, - unsigned long *rx_path_clks, - unsigned long *tx_path_clks) -{ - struct ad9361_rf_phy_state *st = phy->state; - unsigned long clktf, clkrf, adc_rate = 0, dac_rate = 0; - u64 bbpll_rate; - int i, index_rx = -1, index_tx = -1, tmp; - u32 div, tx_intdec, rx_intdec, recursion = 1; - const char clk_dividers[][4] = { - {12,3,2,2}, - {8,2,2,2}, - {6,3,1,2}, - {4,2,2,1}, - {3,3,1,1}, - {2,2,1,1}, - {1,1,1,1}, - }; - - if (st->bypass_rx_fir) - rx_intdec = 1; - else - rx_intdec = st->rx_fir_dec; - - if (st->bypass_tx_fir) - tx_intdec = 1; - else - tx_intdec = st->tx_fir_int; - - if ((rate_gov == 1) && ((rx_intdec * tx_sample_rate * 8) < MIN_ADC_CLK)) { - recursion = 0; - rate_gov = 0; - } - - dev_dbg(&phy->spi->dev, "%s: requested rate %lu TXFIR int %d RXFIR dec %d mode %s", - __func__, tx_sample_rate, tx_intdec, rx_intdec, - rate_gov ? "Nominal" : "Highest OSR"); - - if (tx_sample_rate > MAX_BASEBAND_RATE) - return -EINVAL; - - clktf = tx_sample_rate * tx_intdec; - clkrf = tx_sample_rate * rx_intdec * (st->rx_eq_2tx ? 2 : 1); - - for (i = rate_gov; i < 7; i++) { - adc_rate = clkrf * clk_dividers[i][0]; - dac_rate = clktf * clk_dividers[i][0]; - - if ((adc_rate <= MAX_ADC_CLK) && (adc_rate >= MIN_ADC_CLK)) { - - - if (dac_rate > adc_rate) - tmp = (dac_rate / adc_rate) * -1; - else - tmp = adc_rate / dac_rate; - - if (adc_rate <= MAX_DAC_CLK) { - index_rx = i; - index_tx = i - ((tmp == 1) ? 0 : tmp); - dac_rate = adc_rate; /* ADC_CLK */ - break; - } else { - dac_rate = adc_rate / 2; /* ADC_CLK/2 */ - index_rx = i; - - if (i == 4 && tmp >= 0) - index_tx = 7; /* STOP: 3/2 != 1 */ - else - index_tx = i + ((i == 5 && tmp >= 0) ? 1 : 2) - - ((tmp == 1) ? 0 : tmp); - - break; - } - } - } - - if ((index_tx < 0 || index_tx > 6 || index_rx < 0 || index_rx > 6) && rate_gov < 7 && recursion) { - return ad9361_calculate_rf_clock_chain(phy, tx_sample_rate, - ++rate_gov, rx_path_clks, tx_path_clks); - } else if ((index_tx < 0 || index_tx > 6 || index_rx < 0 || index_rx > 6)) { - dev_err(&phy->spi->dev, "%s: Failed to find suitable dividers: %s", - __func__, (adc_rate < MIN_ADC_CLK) ? "ADC clock below limit" : "BBPLL rate above limit"); - - return -EINVAL; - } - - /* Calculate target BBPLL rate */ - div = MAX_BBPLL_DIV; - - do { - bbpll_rate = (u64)adc_rate * div; - div >>= 1; - - } while ((bbpll_rate > MAX_BBPLL_FREQ) && (div >= MIN_BBPLL_DIV)); - - rx_path_clks[BBPLL_FREQ] = bbpll_rate; - rx_path_clks[ADC_FREQ] = adc_rate; - rx_path_clks[R2_FREQ] = rx_path_clks[ADC_FREQ] / clk_dividers[index_rx][1]; - rx_path_clks[R1_FREQ] = rx_path_clks[R2_FREQ] / clk_dividers[index_rx][2]; - rx_path_clks[CLKRF_FREQ] = rx_path_clks[R1_FREQ] / clk_dividers[index_rx][3]; - rx_path_clks[RX_SAMPL_FREQ] = rx_path_clks[CLKRF_FREQ] / rx_intdec; - - tx_path_clks[BBPLL_FREQ] = bbpll_rate; - tx_path_clks[DAC_FREQ] = dac_rate; - tx_path_clks[T2_FREQ] = tx_path_clks[DAC_FREQ] / clk_dividers[index_tx][1]; - tx_path_clks[T1_FREQ] =tx_path_clks[T2_FREQ] / clk_dividers[index_tx][2]; - tx_path_clks[CLKTF_FREQ] = tx_path_clks[T1_FREQ] / clk_dividers[index_tx][3]; - tx_path_clks[TX_SAMPL_FREQ] = tx_path_clks[CLKTF_FREQ] / tx_intdec; - - return 0; -} - -int ad9361_set_trx_clock_chain_freq(struct ad9361_rf_phy *phy, - unsigned long freq) -{ - struct ad9361_rf_phy_state *st = phy->state; - unsigned long rx[6], tx[6]; - int ret; - - ret = ad9361_calculate_rf_clock_chain(phy, freq, - st->rate_governor, rx, tx); - if (ret < 0) - return ret; - return ad9361_set_trx_clock_chain(phy, rx, tx); -} -EXPORT_SYMBOL(ad9361_set_trx_clock_chain_freq); - -static int ad9361_set_ensm_mode(struct ad9361_rf_phy *phy, bool fdd, bool pinctrl) -{ - struct ad9361_phy_platform_data *pd = phy->pdata; - int ret; - u32 val = 0; - - ad9361_spi_write(phy->spi, REG_ENSM_MODE, fdd ? FDD_MODE : 0); - - val = ad9361_spi_read(phy->spi, REG_ENSM_CONFIG_2); - val &= POWER_DOWN_RX_SYNTH | POWER_DOWN_TX_SYNTH | - RX_SYNTH_READY_MASK | TX_SYNTH_READY_MASK; - - if (fdd) - ret = ad9361_spi_write(phy->spi, REG_ENSM_CONFIG_2, - val | DUAL_SYNTH_MODE | - (pd->fdd_independent_mode ? FDD_EXTERNAL_CTRL_ENABLE : 0)); - else - ret = ad9361_spi_write(phy->spi, REG_ENSM_CONFIG_2, val | - (pd->tdd_use_dual_synth ? DUAL_SYNTH_MODE : 0) | - (pd->tdd_use_dual_synth ? 0 : - (pinctrl ? SYNTH_ENABLE_PIN_CTRL_MODE : 0))); - - return ret; -} - -int ad9361_ensm_mode_disable_pinctrl(struct ad9361_rf_phy *phy) -{ - if (!phy->pdata->fdd) - return ad9361_set_ensm_mode(phy, true, false); - return 0; -} -EXPORT_SYMBOL(ad9361_ensm_mode_disable_pinctrl); - -int ad9361_ensm_mode_restore_pinctrl(struct ad9361_rf_phy *phy) -{ - if (!phy->pdata->fdd) - return ad9361_set_ensm_mode(phy, - phy->pdata->fdd, - phy->pdata->ensm_pin_ctrl); - return 0; -} -EXPORT_SYMBOL(ad9361_ensm_mode_restore_pinctrl); - -/* Fast Lock */ - -static int ad9361_fastlock_readval(struct spi_device *spi, bool tx, - u32 profile, u32 word) -{ - u32 offs = 0; - - if (tx) - offs = REG_TX_FAST_LOCK_SETUP - REG_RX_FAST_LOCK_SETUP; - - ad9361_spi_write(spi, REG_RX_FAST_LOCK_PROGRAM_ADDR + offs, - RX_FAST_LOCK_PROFILE_ADDR(profile) | - RX_FAST_LOCK_PROFILE_WORD(word)); - - return ad9361_spi_read(spi, REG_RX_FAST_LOCK_PROGRAM_READ + offs); -} - -static int ad9361_fastlock_writeval(struct spi_device *spi, bool tx, - u32 profile, u32 word, u8 val, bool last) -{ - u32 offs = 0; - int ret; - - if (tx) - offs = REG_TX_FAST_LOCK_SETUP - REG_RX_FAST_LOCK_SETUP; - - ret = ad9361_spi_write(spi, REG_RX_FAST_LOCK_PROGRAM_ADDR + offs, - RX_FAST_LOCK_PROFILE_ADDR(profile) | - RX_FAST_LOCK_PROFILE_WORD(word)); - ret |= ad9361_spi_write(spi, REG_RX_FAST_LOCK_PROGRAM_DATA + offs, val); - ret |= ad9361_spi_write(spi, REG_RX_FAST_LOCK_PROGRAM_CTRL + offs, - RX_FAST_LOCK_PROGRAM_WRITE | - RX_FAST_LOCK_PROGRAM_CLOCK_ENABLE); - - if (last) /* Stop Clocks */ - ret |= ad9361_spi_write(spi, - REG_RX_FAST_LOCK_PROGRAM_CTRL + offs, 0); - - return ret; -} - -static int ad9361_fastlock_load(struct ad9361_rf_phy *phy, bool tx, - u32 profile, u8 *values) -{ - struct ad9361_rf_phy_state *st = phy->state; - u32 offs = 0; - int i, ret = 0; - u8 buf[4]; - - dev_dbg(&phy->spi->dev, "%s: %s Profile %d:", - __func__, tx ? "TX" : "RX", profile); - - if (tx) - offs = REG_TX_FAST_LOCK_SETUP - REG_RX_FAST_LOCK_SETUP; - - buf[0] = values[0]; - buf[1] = RX_FAST_LOCK_PROFILE_ADDR(profile) | RX_FAST_LOCK_PROFILE_WORD(0); - ad9361_spi_writem(phy->spi, REG_RX_FAST_LOCK_PROGRAM_DATA + offs, buf, 2); - - for (i = 1; i < RX_FAST_LOCK_CONFIG_WORD_NUM; i++) { - buf[0] = RX_FAST_LOCK_PROGRAM_WRITE | RX_FAST_LOCK_PROGRAM_CLOCK_ENABLE; - buf[1] = 0; - buf[2] = values[i]; - buf[3] = RX_FAST_LOCK_PROFILE_ADDR(profile) | RX_FAST_LOCK_PROFILE_WORD(i); - ad9361_spi_writem(phy->spi, REG_RX_FAST_LOCK_PROGRAM_CTRL + offs, buf, 4); - } - - ad9361_spi_write(phy->spi, REG_RX_FAST_LOCK_PROGRAM_CTRL + offs, - RX_FAST_LOCK_PROGRAM_WRITE | RX_FAST_LOCK_PROGRAM_CLOCK_ENABLE); - ad9361_spi_write(phy->spi, REG_RX_FAST_LOCK_PROGRAM_CTRL + offs, 0); - - st->fastlock.entry[tx][profile].flags = FASTLOOK_INIT; - st->fastlock.entry[tx][profile].alc_orig = values[15]; - st->fastlock.entry[tx][profile].alc_written = values[15]; - - return ret; -} - -static int ad9361_fastlock_store(struct ad9361_rf_phy *phy, bool tx, u32 profile) -{ - struct spi_device *spi = phy->spi; - u8 val[16]; - u32 offs = 0, x, y; - - dev_dbg(&phy->spi->dev, "%s: %s Profile %d:", - __func__, tx ? "TX" : "RX", profile); - - if (tx) - offs = REG_TX_FAST_LOCK_SETUP - REG_RX_FAST_LOCK_SETUP; - - val[0] = ad9361_spi_read(spi, REG_RX_INTEGER_BYTE_0 + offs); - val[1] = ad9361_spi_read(spi, REG_RX_INTEGER_BYTE_1 + offs); - val[2] = ad9361_spi_read(spi, REG_RX_FRACT_BYTE_0 + offs); - val[3] = ad9361_spi_read(spi, REG_RX_FRACT_BYTE_1 + offs); - val[4] = ad9361_spi_read(spi, REG_RX_FRACT_BYTE_2 + offs); - - x = ad9361_spi_readf(spi, REG_RX_VCO_BIAS_1 + offs, VCO_BIAS_REF(~0)); - y = ad9361_spi_readf(spi, REG_RX_ALC_VARACTOR + offs, VCO_VARACTOR(~0)); - val[5] = (x << 4) | y; - - x = ad9361_spi_readf(spi, REG_RX_VCO_BIAS_1 + offs, VCO_BIAS_TCF(~0)); - y = ad9361_spi_readf(spi, REG_RX_CP_CURRENT + offs, CHARGE_PUMP_CURRENT(~0)); - /* Wide BW option: N = 1 - * Set init and steady state values to the same - let user space handle it - */ - val[6] = (x << 3) | y; - val[7] = y; - - x = ad9361_spi_readf(spi, REG_RX_LOOP_FILTER_3 + offs, LOOP_FILTER_R3(~0)); - val[8] = (x << 4) | x; - - x = ad9361_spi_readf(spi, REG_RX_LOOP_FILTER_2 + offs, LOOP_FILTER_C3(~0)); - val[9] = (x << 4) | x; - - x = ad9361_spi_readf(spi, REG_RX_LOOP_FILTER_1 + offs, LOOP_FILTER_C1(~0)); - y = ad9361_spi_readf(spi, REG_RX_LOOP_FILTER_1 + offs, LOOP_FILTER_C2(~0)); - val[10] = (x << 4) | y; - - x = ad9361_spi_readf(spi, REG_RX_LOOP_FILTER_2 + offs, LOOP_FILTER_R1(~0)); - val[11] = (x << 4) | x; - - x = ad9361_spi_readf(spi, REG_RX_VCO_VARACTOR_CTRL_0 + offs, - VCO_VARACTOR_REFERENCE_TCF(~0)); - y = ad9361_spi_readf(spi, REG_RFPLL_DIVIDERS, - tx ? TX_VCO_DIVIDER(~0) : RX_VCO_DIVIDER(~0)); - val[12] = (x << 4) | y; - - x = ad9361_spi_readf(spi, REG_RX_FORCE_VCO_TUNE_1 + offs, VCO_CAL_OFFSET(~0)); - y = ad9361_spi_readf(spi, REG_RX_VCO_VARACTOR_CTRL_1 + offs, VCO_VARACTOR_REFERENCE(~0)); - val[13] = (x << 4) | y; - - val[14] = ad9361_spi_read(spi, REG_RX_FORCE_VCO_TUNE_0 + offs); - - x = ad9361_spi_readf(spi, REG_RX_FORCE_ALC + offs, FORCE_ALC_WORD(~0)); - y = ad9361_spi_readf(spi, REG_RX_FORCE_VCO_TUNE_1 + offs, FORCE_VCO_TUNE); - val[15] = (x << 1) | y; - - return ad9361_fastlock_load(phy, tx, profile, val); -} - -static int ad9361_fastlock_prepare(struct ad9361_rf_phy *phy, bool tx, - u32 profile, bool prepare) -{ - struct ad9361_rf_phy_state *st = phy->state; - u32 offs, ready_mask; - bool is_prepared; - - dev_dbg(&phy->spi->dev, "%s: %s Profile %d: %s", - __func__, tx ? "TX" : "RX", profile, - prepare ? "Prepare" : "Un-Prepare"); - - if (tx) { - offs = REG_TX_FAST_LOCK_SETUP - REG_RX_FAST_LOCK_SETUP; - ready_mask = TX_SYNTH_READY_MASK; - } else { - offs = 0; - ready_mask = RX_SYNTH_READY_MASK; - } - - is_prepared = !!st->fastlock.current_profile[tx]; - - if (prepare && !is_prepared) { - ad9361_spi_write(phy->spi, - REG_RX_FAST_LOCK_SETUP_INIT_DELAY + offs, - (tx ? phy->pdata->tx_fastlock_delay_ns : - phy->pdata->rx_fastlock_delay_ns) / 250); - ad9361_spi_write(phy->spi, REG_RX_FAST_LOCK_SETUP + offs, - RX_FAST_LOCK_PROFILE(profile) | - RX_FAST_LOCK_MODE_ENABLE); - ad9361_spi_write(phy->spi, REG_RX_FAST_LOCK_PROGRAM_CTRL + offs, - 0); - - ad9361_spi_writef(phy->spi, REG_ENSM_CONFIG_2, ready_mask, 1); - ad9361_trx_vco_cal_control(phy, tx, false); - } else if (!prepare && is_prepared) { - ad9361_spi_write(phy->spi, REG_RX_FAST_LOCK_SETUP + offs, 0); - - /* Workaround: Exiting Fastlock Mode */ - ad9361_spi_writef(phy->spi, REG_RX_FORCE_ALC + offs, FORCE_ALC_ENABLE, 1); - ad9361_spi_writef(phy->spi, REG_RX_FORCE_VCO_TUNE_1 + offs, FORCE_VCO_TUNE, 1); - ad9361_spi_writef(phy->spi, REG_RX_FORCE_ALC + offs, FORCE_ALC_ENABLE, 0); - ad9361_spi_writef(phy->spi, REG_RX_FORCE_VCO_TUNE_1 + offs, FORCE_VCO_TUNE, 0); - - ad9361_trx_vco_cal_control(phy, tx, true); - ad9361_spi_writef(phy->spi, REG_ENSM_CONFIG_2, ready_mask, 0); - - st->fastlock.current_profile[tx] = 0; - } - - return 0; -} - -static int ad9361_fastlock_recall(struct ad9361_rf_phy *phy, bool tx, u32 profile) -{ - struct ad9361_rf_phy_state *st = phy->state; - u32 offs = 0; - u8 curr, new, orig, current_profile; - - dev_dbg(&phy->spi->dev, "%s: %s Profile %d:", - __func__, tx ? "TX" : "RX", profile); - - if (tx) - offs = REG_TX_FAST_LOCK_SETUP - REG_RX_FAST_LOCK_SETUP; - - if (st->fastlock.entry[tx][profile].flags != FASTLOOK_INIT) - return -EINVAL; - - /* Workaround: Lock problem with same ALC word */ - - current_profile = st->fastlock.current_profile[tx]; - new = st->fastlock.entry[tx][profile].alc_written; - - if (current_profile == 0) - curr = ad9361_spi_readf(phy->spi, REG_RX_FORCE_ALC + offs, - FORCE_ALC_WORD(~0)) << 1; - else - curr = st->fastlock.entry[tx][current_profile - 1].alc_written; - - if ((curr >> 1) == (new >> 1)) { - orig = st->fastlock.entry[tx][profile].alc_orig; - - if ((orig >> 1) == (new >> 1)) - st->fastlock.entry[tx][profile].alc_written += 2; - else - st->fastlock.entry[tx][profile].alc_written = orig; - - ad9361_fastlock_writeval(phy->spi, tx, profile, 0xF, - st->fastlock.entry[tx][profile].alc_written, true); - } - - ad9361_fastlock_prepare(phy, tx, profile, true); - st->fastlock.current_profile[tx] = profile + 1; - - return ad9361_spi_write(phy->spi, REG_RX_FAST_LOCK_SETUP + offs, - RX_FAST_LOCK_PROFILE(profile) | - (phy->pdata->trx_fastlock_pinctrl_en[tx] ? - RX_FAST_LOCK_PROFILE_PIN_SELECT : 0) | - RX_FAST_LOCK_MODE_ENABLE); -} - -static int ad9361_fastlock_save(struct ad9361_rf_phy *phy, bool tx, - u32 profile, u8 *values) -{ - int i; - - dev_dbg(&phy->spi->dev, "%s: %s Profile %d:", - __func__, tx ? "TX" : "RX", profile); - - for (i = 0; i < RX_FAST_LOCK_CONFIG_WORD_NUM; i++) - values[i] = ad9361_fastlock_readval(phy->spi, tx, profile, i); - - - return 0; -} - -static int ad9361_mcs(struct ad9361_rf_phy *phy, unsigned step) -{ - unsigned mcs_mask = MCS_RF_ENABLE | MCS_BBPLL_ENABLE | - MCS_DIGITAL_CLK_ENABLE | MCS_BB_ENABLE; - - dev_dbg(&phy->spi->dev, "%s: MCS step %d", __func__, step); - - switch(spi_get_device_id(phy->spi)->driver_data) { - case ID_AD9363A: - return -ENODEV; - } - - switch (step) { - case 1: - /* REVIST: - * POWER_DOWN_TRX_SYNTH and MCS_RF_ENABLE somehow conflict - */ - ad9361_spi_writef(phy->spi, REG_ENSM_CONFIG_2, - POWER_DOWN_TX_SYNTH | POWER_DOWN_RX_SYNTH, 0); - - ad9361_spi_writef(phy->spi, REG_MULTICHIP_SYNC_AND_TX_MON_CTRL, - mcs_mask, MCS_BB_ENABLE | MCS_BBPLL_ENABLE | MCS_RF_ENABLE); - ad9361_spi_writef(phy->spi, REG_CP_BLEED_CURRENT, - MCS_REFCLK_SCALE_EN, 1); - break; - case 2: - if (!phy->pdata->sync_gpio) - break; - /* - * NOTE: This is not a regular GPIO - - * HDL ensures Multi-chip Synchronization SYNC_IN Pulse Timing - * relative to rising and falling edge of REF_CLK - */ - gpiod_set_value(phy->pdata->sync_gpio, 1); - gpiod_set_value(phy->pdata->sync_gpio, 0); - break; - case 3: - ad9361_spi_writef(phy->spi, REG_MULTICHIP_SYNC_AND_TX_MON_CTRL, - mcs_mask, MCS_BB_ENABLE | MCS_DIGITAL_CLK_ENABLE | MCS_RF_ENABLE); - break; - case 4: - if (!phy->pdata->sync_gpio) - break; - gpiod_set_value(phy->pdata->sync_gpio, 1); - gpiod_set_value(phy->pdata->sync_gpio, 0); - break; - case 5: - ad9361_spi_writef(phy->spi, REG_MULTICHIP_SYNC_AND_TX_MON_CTRL, - mcs_mask, MCS_RF_ENABLE); - break; - } - - return 0; -} - -static int ad9361_rssi_write_err_tbl(struct ad9361_rf_phy *phy) -{ - u8 i; - - ad9361_spi_write(phy->spi, - REG_CONFIG, CALIB_TABLE_SELECT(0x3) | START_CALIB_TABLE_CLOCK); - for(i = 0; i < 4; i++) { - ad9361_spi_write(phy->spi, REG_WORD_ADDRESS, i); - ad9361_spi_write(phy->spi, REG_GAIN_DIFF_WORDERROR_WRITE, - phy->pdata->rssi_lna_err_tbl[i]); - ad9361_spi_write(phy->spi, REG_CONFIG, - CALIB_TABLE_SELECT(0x3) | WRITE_LNA_ERROR_TABLE | START_CALIB_TABLE_CLOCK); - } - ad9361_spi_write(phy->spi, REG_CONFIG, - CALIB_TABLE_SELECT(0x3) | START_CALIB_TABLE_CLOCK); - for(i = 0; i < 16; i++) { - ad9361_spi_write(phy->spi, REG_WORD_ADDRESS, i); - ad9361_spi_write(phy->spi, REG_GAIN_DIFF_WORDERROR_WRITE, - phy->pdata->rssi_mixer_err_tbl[i]); - ad9361_spi_write(phy->spi, REG_CONFIG, - CALIB_TABLE_SELECT(0x3) | WRITE_MIXER_ERROR_TABLE | START_CALIB_TABLE_CLOCK); - } - ad9361_spi_write(phy->spi, REG_CONFIG, 0x00); - - return 0; -} - -static int ad9361_rssi_program_lna_gain(struct ad9361_rf_phy *phy) -{ - u8 i; - - ad9361_spi_write(phy->spi, REG_LNA_GAIN, - phy->pdata->rssi_gain_step_calib_reg_val[0]); - - /* Program the LNA gain step words into the internal table. */ - ad9361_spi_write(phy->spi, REG_CONFIG, - CALIB_TABLE_SELECT(0x3) | START_CALIB_TABLE_CLOCK); - for(i = 0; i < 4; i++) { - ad9361_spi_write(phy->spi, REG_WORD_ADDRESS, i); - ad9361_spi_write(phy->spi, REG_GAIN_DIFF_WORDERROR_WRITE, - phy->pdata->rssi_gain_step_calib_reg_val[i+1]); - ad9361_spi_write(phy->spi, REG_CONFIG, - CALIB_TABLE_SELECT(0x3) | WRITE_LNA_GAIN_DIFF | - START_CALIB_TABLE_CLOCK); - udelay(3); //Wait for data to fully write to internal table - } - - return 0; -} - -static int ad9361_rssi_gain_step_calib(struct ad9361_rf_phy *phy) -{ - /* - * Before running the function, provide a single tone within the channel - * bandwidth and monitor the received data. Adjust the tone amplitude until - * the received data is within a few dB of full scale but not overloading. - */ - u64 lo_freq_hz; - u8 lo_index; - u8 i; - int ret; - - lo_freq_hz = ad9361_from_clk(clk_get_rate(phy->clks[RX_RFPLL])); - if (lo_freq_hz < 1300000000ULL) - lo_index = 0; - else - if (lo_freq_hz < 3300000000ULL) - lo_index = 1; - else - if (lo_freq_hz < 4100000000ULL) - lo_index = 2; - else - lo_index = 3; - - for(i = 0; i < 4; i++) - phy->pdata->rssi_gain_step_calib_reg_val[i] = - gain_step_calib_reg_val[lo_index][i]; - - /* Put the AD9361 into the Alert state. */ - ad9361_ensm_force_state(phy, ENSM_STATE_ALERT); - - /* Program the directly-addressable register values. */ - ad9361_spi_write(phy->spi, REG_MAX_MIXER_CALIBRATION_GAIN_INDEX, - MAX_MIXER_CALIBRATION_GAIN_INDEX(0x0F)); - ad9361_spi_write(phy->spi, REG_MEASURE_DURATION, - GAIN_CAL_MEAS_DURATION(0x0E)); - ad9361_spi_write(phy->spi, REG_SETTLE_TIME, - SETTLE_TIME(0x3F)); - ad9361_spi_write(phy->spi, REG_RSSI_CONFIG, - RSSI_MODE_SELECT(0x3) | DEFAULT_RSSI_MEAS_MODE); - ad9361_spi_write(phy->spi, REG_MEASURE_DURATION_01, - MEASUREMENT_DURATION_0(0x0E)); - - ad9361_rssi_program_lna_gain(phy); - - ad9361_spi_write(phy->spi, REG_CONFIG, START_CALIB_TABLE_CLOCK); - ad9361_spi_write(phy->spi, REG_CONFIG, 0x00); - - /* Run and wait until the calibration completes. */ - ret = ad9361_run_calibration(phy, RX_GAIN_STEP_CAL); - - /* Read the LNA and Mixer error terms into nonvolatile memory. */ - ad9361_spi_write(phy->spi, REG_CONFIG, CALIB_TABLE_SELECT(0x1) | READ_SELECT); - for(i = 0; i < 4; i++) { - ad9361_spi_write(phy->spi, REG_WORD_ADDRESS, i); - phy->pdata->rssi_lna_err_tbl[i] = - ad9361_spi_read(phy->spi, REG_GAIN_ERROR_READ); - } - ad9361_spi_write(phy->spi, REG_CONFIG, CALIB_TABLE_SELECT(0x1)); - for(i = 0; i < 16; i++) { - ad9361_spi_write(phy->spi, REG_WORD_ADDRESS, i); - phy->pdata->rssi_mixer_err_tbl[i] = - ad9361_spi_read(phy->spi, REG_GAIN_ERROR_READ); - } - ad9361_spi_write(phy->spi, REG_CONFIG, 0x00); - - /* Programming gain step errors into the AD9361 in the field */ - ad9361_rssi_write_err_tbl(phy); - - ad9361_spi_write(phy->spi, REG_SETTLE_TIME, - ENABLE_DIG_GAIN_CORR | SETTLE_TIME(0x10)); - - ad9361_ensm_restore_prev_state(phy); - - return ret; -} - -static void ad9361_init_state(struct ad9361_rf_phy *phy) -{ - struct ad9361_rf_phy_state *st = phy->state; - - st->current_table = -1; - st->bypass_tx_fir = true; - st->bypass_rx_fir = true; - st->rate_governor = 1; - st->rfdc_track_en = true; - st->bbdc_track_en = true; - st->quad_track_en = true; -} - -static void ad9361_clear_state(struct ad9361_rf_phy *phy) -{ - struct ad9361_rf_phy_state *st = phy->state; - - memset(st, 0, sizeof(*st)); - ad9361_init_state(phy); -} - -static unsigned long ad9361_ref_div_sel(unsigned long refin_Hz, unsigned long max) -{ - if (refin_Hz <= (max / 2)) - return 2 * refin_Hz; - else if (refin_Hz <= max) - return refin_Hz; - else if (refin_Hz <= (max * 2)) - return refin_Hz / 2; - else if (refin_Hz <= (max * 4)) - return refin_Hz / 4; - else - return 0; -} - -static int ad9361_setup(struct ad9361_rf_phy *phy) -{ - struct ad9361_rf_phy_state *st = phy->state; - unsigned long refin_Hz, ref_freq, bbpll_freq; - struct device *dev = &phy->spi->dev; - struct spi_device *spi = phy->spi; - struct ad9361_phy_platform_data *pd = phy->pdata; - u32 real_rx_bandwidth, real_tx_bandwidth; - int ret; - - pd->rf_rx_bandwidth_Hz = ad9361_validate_rf_bw(phy, pd->rf_rx_bandwidth_Hz); - pd->rf_tx_bandwidth_Hz = ad9361_validate_rf_bw(phy, pd->rf_tx_bandwidth_Hz); - - real_rx_bandwidth = pd->rf_rx_bandwidth_Hz / 2; - real_tx_bandwidth = pd->rf_tx_bandwidth_Hz / 2; - - dev_dbg(dev, "%s", __func__); - - if (pd->fdd) { - pd->tdd_skip_vco_cal = false; - if (pd->ensm_pin_ctrl && pd->fdd_independent_mode) { - dev_warn(dev, - "%s: Either set ENSM PINCTRL or FDD Independent Mode", - __func__); - pd->ensm_pin_ctrl = false; - } - } - - ret = ad9361_auxdac_setup(phy, &pd->auxdac_ctrl); - if (ret < 0) - return ret; - - ret = ad9361_gpo_setup(phy, &pd->gpo_ctrl); - if (ret < 0) - return ret; - - if (pd->port_ctrl.pp_conf[2] & FDD_RX_RATE_2TX_RATE) - st->rx_eq_2tx = true; - - ad9361_spi_write(spi, REG_CTRL, CTRL_ENABLE); - ad9361_spi_write(spi, REG_BANDGAP_CONFIG0, MASTER_BIAS_TRIM(0x0E)); /* Enable Master Bias */ - ad9361_spi_write(spi, REG_BANDGAP_CONFIG1, BANDGAP_TEMP_TRIM(0x0E)); /* Set Bandgap Trim */ - - ad9361_set_dcxo_tune(phy, pd->dcxo_coarse, pd->dcxo_fine); - - refin_Hz = clk_get_rate(phy->clk_refin); - - ref_freq = ad9361_ref_div_sel(refin_Hz, MAX_BBPLL_FREF); - if (!ref_freq) - return -EINVAL; - - ad9361_spi_writef(spi, REG_REF_DIVIDE_CONFIG_1, RX_REF_RESET_BAR, 1); - ad9361_spi_writef(spi, REG_REF_DIVIDE_CONFIG_2, TX_REF_RESET_BAR, 1); - ad9361_spi_writef(spi, REG_REF_DIVIDE_CONFIG_2, - TX_REF_DOUBLER_FB_DELAY(~0), 3); /* FB DELAY */ - ad9361_spi_writef(spi, REG_REF_DIVIDE_CONFIG_2, - RX_REF_DOUBLER_FB_DELAY(~0), 3); /* FB DELAY */ - - ad9361_spi_write(spi, REG_CLOCK_ENABLE, - DIGITAL_POWER_UP | CLOCK_ENABLE_DFLT | BBPLL_ENABLE | - (pd->use_extclk ? XO_BYPASS : 0)); /* Enable Clocks */ - - ret = clk_prepare_enable(phy->clk_refin); - if (ret < 0) - return ret; - - ret = clk_set_rate(phy->clks[BB_REFCLK], ref_freq); - if (ret < 0) { - dev_err(dev, "Failed to set BB ref clock rate (%d)\n", - ret); - return ret; - } - - ad9361_spi_write(spi, REG_FRACT_BB_FREQ_WORD_2, 0x12); - ad9361_spi_write(spi, REG_FRACT_BB_FREQ_WORD_3, 0x34); - - ret = ad9361_set_trx_clock_chain_default(phy); - if (ret < 0) - return ret; - - if (!pd->rx2tx2) { - pd->rx1tx1_mode_use_tx_num = - clamp_t(u32, pd->rx1tx1_mode_use_tx_num, TX_1, TX_2); - pd->rx1tx1_mode_use_rx_num = - clamp_t(u32, pd->rx1tx1_mode_use_rx_num, RX_1, RX_2); - - ad9361_en_dis_tx(phy, TX_1 | TX_2, pd->rx1tx1_mode_use_tx_num); - ad9361_en_dis_rx(phy, TX_1 | TX_2, pd->rx1tx1_mode_use_rx_num); - } else { - ad9361_en_dis_tx(phy, TX_1 | TX_2, TX_1 | TX_2); - ad9361_en_dis_rx(phy, RX_1 | RX_2, RX_1 | RX_2); - } - - ret = ad9361_rf_port_setup(phy, true, st->rf_rx_input_sel, - st->rf_tx_output_sel); - if (ret < 0) - return ret; - - ret = ad9361_pp_port_setup(phy, false); - if (ret < 0) - return ret; - - bbpll_freq = clk_get_rate(phy->clks[BBPLL_CLK]); - - ret = ad9361_auxadc_setup(phy, &pd->auxadc_ctrl, bbpll_freq); - if (ret < 0) - return ret; - - ret = ad9361_ctrl_outs_setup(phy, &pd->ctrl_outs_ctrl); - if (ret < 0) - return ret; - - ret = ad9361_set_ref_clk_cycles(phy, refin_Hz); - if (ret < 0) - return ret; - - ret = ad9361_setup_ext_lna(phy, &pd->elna_ctrl); - if (ret < 0) - return ret; - - /* - * This allows forcing a lower F_REF window - * (worse phase noise, better fractional spurs) - */ - pd->trx_synth_max_fref = clamp_t(u32, pd->trx_synth_max_fref, - MIN_SYNTH_FREF, MAX_SYNTH_FREF); - - ref_freq = ad9361_ref_div_sel(refin_Hz, pd->trx_synth_max_fref); - if (!ref_freq) - return -EINVAL; - - clk_set_parent(phy->clks[TX_RFPLL], phy->clks[TX_RFPLL_INT]); - clk_set_parent(phy->clks[RX_RFPLL], phy->clks[RX_RFPLL_INT]); - - ret = clk_set_rate(phy->clks[RX_REFCLK], ref_freq); - if (ret < 0) { - dev_err(dev, "Failed to set RX Synth ref clock rate (%d)\n", ret); - return ret; - } - - ret = clk_set_rate(phy->clks[TX_REFCLK], ref_freq); - if (ret < 0) { - dev_err(dev, "Failed to set TX Synth ref clock rate (%d)\n", ret); - return ret; - } - - ret = ad9361_txrx_synth_cp_calib(phy, ref_freq, false); /* RXCP */ - if (ret < 0) - return ret; - - ret = ad9361_txrx_synth_cp_calib(phy, ref_freq, true); /* TXCP */ - if (ret < 0) - return ret; - - ret = clk_set_rate(phy->clks[RX_RFPLL], ad9361_to_clk(pd->rx_synth_freq)); - if (ret < 0) { - dev_err(dev, "Failed to set RX Synth rate (%d)\n", - ret); - return ret; - } - - ret = clk_prepare_enable(phy->clks[RX_RFPLL]); - if (ret < 0) - return ret; - - /* Skip quad cal here we do it later again */ - st->last_tx_quad_cal_freq = pd->tx_synth_freq; - ret = clk_set_rate(phy->clks[TX_RFPLL], ad9361_to_clk(pd->tx_synth_freq)); - if (ret < 0) { - dev_err(dev, "Failed to set TX Synth rate (%d)\n", - ret); - return ret; - } - - ret = clk_prepare_enable(phy->clks[TX_RFPLL]); - if (ret < 0) - return ret; - - clk_set_parent(phy->clks[RX_RFPLL], - pd->use_ext_rx_lo ? phy->clk_ext_lo_rx : - phy->clks[RX_RFPLL_INT]); - - clk_set_parent(phy->clks[TX_RFPLL], - pd->use_ext_tx_lo ? phy->clk_ext_lo_tx : - phy->clks[TX_RFPLL_INT]); - - ret = ad9361_load_mixer_gm_subtable(phy); - if (ret < 0) - return ret; - - ret = ad9361_gc_setup(phy, &pd->gain_ctrl); - if (ret < 0) - return ret; - - ret = ad9361_rx_bb_analog_filter_calib(phy, - real_rx_bandwidth, - bbpll_freq); - if (ret < 0) - return ret; - - ret = ad9361_tx_bb_analog_filter_calib(phy, - real_tx_bandwidth, - bbpll_freq); - if (ret < 0) - return ret; - - ret = ad9361_rx_tia_calib(phy, real_rx_bandwidth); - if (ret < 0) - return ret; - - ret = ad9361_tx_bb_second_filter_calib(phy, real_tx_bandwidth); - if (ret < 0) - return ret; - - ret = ad9361_rx_adc_setup(phy, - bbpll_freq, - clk_get_rate(phy->clks[ADC_CLK])); - if (ret < 0) - return ret; - - ret = ad9361_bb_dc_offset_calib(phy); - if (ret < 0) - return ret; - - ret = ad9361_rf_dc_offset_calib(phy, - ad9361_from_clk(clk_get_rate(phy->clks[RX_RFPLL]))); - if (ret < 0) - return ret; - - st->current_rx_bw_Hz = pd->rf_rx_bandwidth_Hz; - st->current_tx_bw_Hz = pd->rf_tx_bandwidth_Hz; - st->last_tx_quad_cal_phase = ~0; - ret = ad9361_tx_quad_calib(phy, real_rx_bandwidth, real_tx_bandwidth, -1); - if (ret < 0) - return ret; - - ret = ad9361_tracking_control(phy, st->bbdc_track_en, - st->rfdc_track_en, st->quad_track_en); - if (ret < 0) - return ret; - - ad9361_pp_port_setup(phy, true); - - ret = ad9361_set_ensm_mode(phy, pd->fdd, pd->ensm_pin_ctrl); - if (ret < 0) - return ret; - - ad9361_spi_writef(phy->spi, REG_TX_ATTEN_OFFSET, - MASK_CLR_ATTEN_UPDATE, 0); - - ret = ad9361_set_tx_atten(phy, pd->tx_atten, - pd->rx2tx2 ? true : pd->rx1tx1_mode_use_tx_num == 1, - pd->rx2tx2 ? true : pd->rx1tx1_mode_use_tx_num == 2, true); - if (ret < 0) - return ret; - - if (!pd->rx2tx2) { - ret = ad9361_set_tx_atten(phy, 89750, - pd->rx1tx1_mode_use_tx_num == 2, - pd->rx1tx1_mode_use_tx_num == 1, true); - if (ret < 0) - return ret; - } - - ret = ad9361_rssi_setup(phy, &pd->rssi_ctrl, false); - if (ret < 0) - return ret; - - ret = ad9361_clkout_control(phy, pd->ad9361_clkout_mode); - if (ret < 0) - return ret; - - ret = ad9361_txmon_setup(phy, &pd->txmon_ctrl); - if (ret < 0) - return ret; - - st->curr_ensm_state = ad9361_spi_readf(spi, REG_STATE, ENSM_STATE(~0)); - ad9361_ensm_set_state(phy, pd->fdd ? ENSM_STATE_FDD : ENSM_STATE_RX, - pd->ensm_pin_ctrl); - - st->auto_cal_en = true; - st->cal_threshold_freq = 100000000ULL; /* 100 MHz */ - - if (!pd->rssi_skip_calib) { - ad9361_ensm_force_state(phy, ENSM_STATE_ALERT); - ad9361_rssi_program_lna_gain(phy); - ad9361_rssi_write_err_tbl(phy); - ad9361_spi_write(phy->spi, REG_SETTLE_TIME, - ENABLE_DIG_GAIN_CORR | SETTLE_TIME(0x10)); - ad9361_ensm_restore_prev_state(phy); - } - - return 0; - -} - -int ad9361_do_calib_run(struct ad9361_rf_phy *phy, u32 cal, int arg) -{ - struct ad9361_rf_phy_state *st = phy->state; - int ret; - - dev_dbg(&phy->spi->dev, "%s: CAL %u ARG %d", __func__, cal, arg); - - ret = ad9361_tracking_control(phy, false, false, false); - if (ret < 0) - return ret; - - ad9361_ensm_force_state(phy, ENSM_STATE_ALERT); - - switch (cal) { - case TX_QUAD_CAL: - ret = ad9361_tx_quad_calib(phy, st->current_rx_bw_Hz / 2, - st->current_tx_bw_Hz / 2, arg); - break; - case RFDC_CAL: - ret = ad9361_rf_dc_offset_calib(phy, - ad9361_from_clk(clk_get_rate(phy->clks[RX_RFPLL]))); - break; - default: - ret = -EINVAL; - break; - } - - ret = ad9361_tracking_control(phy, st->bbdc_track_en, - st->rfdc_track_en, st->quad_track_en); - ad9361_ensm_restore_prev_state(phy); - - return ret; -} -EXPORT_SYMBOL(ad9361_do_calib_run); - -static int ad9361_update_rf_bandwidth(struct ad9361_rf_phy *phy, - u32 rf_rx_bw, u32 rf_tx_bw) -{ - struct ad9361_rf_phy_state *st = phy->state; - int ret; - - ret = ad9361_tracking_control(phy, false, false, false); - if (ret < 0) - return ret; - - ad9361_ensm_force_state(phy, ENSM_STATE_ALERT); - - ret = __ad9361_update_rf_bandwidth(phy, rf_rx_bw, rf_tx_bw); - if (ret < 0) - return ret; - - st->current_rx_bw_Hz = rf_rx_bw; - st->current_tx_bw_Hz = rf_tx_bw; - - if (st->manual_tx_quad_cal_en == false) { - ret = ad9361_tx_quad_calib(phy, rf_rx_bw / 2, rf_tx_bw / 2, -1); - if (ret < 0) - return ret; - } - - ret = ad9361_tracking_control(phy, st->bbdc_track_en, - st->rfdc_track_en, st->quad_track_en); - if (ret < 0) - return ret; - - ad9361_ensm_restore_prev_state(phy); - - return 0; -} - -static int ad9361_verify_fir_filter_coef(struct ad9361_rf_phy *phy, - enum fir_dest dest, - u32 ntaps, short *coef) -{ - struct spi_device *spi = phy->spi; - u32 val, offs = 0, gain = 0, conf, sel, cnt; - int ret = 0; - -#ifndef DEBUG - return 0; -#endif - dev_dbg(&phy->spi->dev, "%s: TAPS %d, dest %d", - __func__, ntaps, dest); - - if (dest & FIR_IS_RX) { - gain = ad9361_spi_read(spi, REG_RX_FILTER_GAIN); - offs = REG_RX_FILTER_COEF_ADDR - REG_TX_FILTER_COEF_ADDR; - ad9361_spi_write(spi, REG_RX_FILTER_GAIN, 0); - } - - conf = ad9361_spi_read(spi, REG_TX_FILTER_CONF + offs); - - if ((dest & 3) == 3) { - sel = 1; - cnt = 2; - } else { - sel = (dest & 3); - cnt = 1; - } - - for (; cnt > 0; cnt--, sel++) { - - ad9361_spi_write(spi, REG_TX_FILTER_CONF + offs, - FIR_NUM_TAPS(ntaps / 16 - 1) | - FIR_SELECT(sel) | FIR_START_CLK); - - for (val = 0; val < ntaps; val++) { - short tmp; - ad9361_spi_write(spi, REG_TX_FILTER_COEF_ADDR + offs, val); - - tmp = (ad9361_spi_read(spi, REG_TX_FILTER_COEF_READ_DATA_1 + offs) & 0xFF) | - (ad9361_spi_read(spi, REG_TX_FILTER_COEF_READ_DATA_2 + offs) << 8); - - if (tmp != coef[val]) { - dev_err(&phy->spi->dev,"%s%d read verify failed TAP%d %d =! %d \n", - (dest & FIR_IS_RX) ? "RX" : "TX", sel, - val, tmp, coef[val]); - ret = -EIO; - } - } - } - - if (dest & FIR_IS_RX) { - ad9361_spi_write(spi, REG_RX_FILTER_GAIN, gain); - } - - ad9361_spi_write(spi, REG_TX_FILTER_CONF + offs, conf); - - return ret; -} - -static int ad9361_load_fir_filter_coef(struct ad9361_rf_phy *phy, - enum fir_dest dest, int gain_dB, - u32 ntaps, short *coef) -{ - struct ad9361_rf_phy_state *st = phy->state; - struct spi_device *spi = phy->spi; - u32 val, offs = 0, fir_conf = 0, fir_enable = 0; - int ret; - - dev_dbg(&phy->spi->dev, "%s: TAPS %d, gain %d, dest %d", - __func__, ntaps, gain_dB, dest); - - if (coef == NULL || !ntaps || ntaps > 128 || ntaps % 16) { - dev_err(&phy->spi->dev, - "%s: Invalid parameters: TAPS %d, gain %d, dest 0x%X", - __func__, ntaps, gain_dB, dest); - - return -EINVAL; - } - - ad9361_ensm_force_state(phy, ENSM_STATE_ALERT); - - if (dest & FIR_IS_RX) { - val = 3 - (gain_dB + 12) / 6; - ad9361_spi_write(spi, REG_RX_FILTER_GAIN, val & 0x3); - offs = REG_RX_FILTER_COEF_ADDR - REG_TX_FILTER_COEF_ADDR; - st->rx_fir_ntaps = ntaps; - fir_enable = ad9361_spi_readf(phy->spi, - REG_RX_ENABLE_FILTER_CTRL, RX_FIR_ENABLE_DECIMATION(~0)); - ad9361_spi_writef(phy->spi, REG_RX_ENABLE_FILTER_CTRL, - RX_FIR_ENABLE_DECIMATION(~0), - (st->rx_fir_dec == 4) ? 3 : st->rx_fir_dec); - } else { - if (gain_dB == -6) - fir_conf = TX_FIR_GAIN_6DB; - st->tx_fir_ntaps = ntaps; - fir_enable = ad9361_spi_readf(phy->spi, - REG_TX_ENABLE_FILTER_CTRL, TX_FIR_ENABLE_INTERPOLATION(~0)); - ad9361_spi_writef(phy->spi, REG_TX_ENABLE_FILTER_CTRL, - TX_FIR_ENABLE_INTERPOLATION(~0), - (st->tx_fir_int == 4) ? 3 : st->tx_fir_int); - } - - val = ntaps / 16 - 1; - - fir_conf |= FIR_NUM_TAPS(val) | FIR_SELECT(dest) | FIR_START_CLK; - - ad9361_spi_write(spi, REG_TX_FILTER_CONF + offs, fir_conf); - - for (val = 0; val < ntaps; val++) { - ad9361_spi_write(spi, REG_TX_FILTER_COEF_ADDR + offs, val); - ad9361_spi_write(spi, REG_TX_FILTER_COEF_WRITE_DATA_1 + offs, - coef[val] & 0xFF); - ad9361_spi_write(spi, REG_TX_FILTER_COEF_WRITE_DATA_2 + offs, - coef[val] >> 8); - ad9361_spi_write(spi, REG_TX_FILTER_CONF + offs, - fir_conf | FIR_WRITE); - ad9361_spi_write(spi, REG_TX_FILTER_COEF_READ_DATA_2 + offs, 0); - ad9361_spi_write(spi, REG_TX_FILTER_COEF_READ_DATA_2 + offs, 0); - } - - ad9361_spi_write(spi, REG_TX_FILTER_CONF + offs, fir_conf); - fir_conf &= ~FIR_START_CLK; - ad9361_spi_write(spi, REG_TX_FILTER_CONF + offs, fir_conf); - - ret = ad9361_verify_fir_filter_coef(phy, dest, ntaps, coef); - - if (dest & FIR_IS_RX) - ad9361_spi_writef(phy->spi, REG_RX_ENABLE_FILTER_CTRL, - RX_FIR_ENABLE_DECIMATION(~0), fir_enable); - else - ad9361_spi_writef(phy->spi, REG_TX_ENABLE_FILTER_CTRL, - TX_FIR_ENABLE_INTERPOLATION(~0), fir_enable); - - ad9361_ensm_restore_prev_state(phy); - - return ret; -} - -static int ad9361_parse_fir(struct ad9361_rf_phy *phy, - char *data, u32 size) -{ - struct ad9361_rf_phy_state *st = phy->state; - char *line; - int i = 0, ret, txc, rxc; - int tx = -1, tx_gain, tx_int; - int rx = -1, rx_gain, rx_dec; - int rtx = -1, rrx = -1; - short coef_tx[128]; - short coef_rx[128]; - char *ptr = data; - - st->filt_rx_bw_Hz = 0; - st->filt_tx_bw_Hz = 0; - st->filt_valid = false; - - while ((line = strsep(&ptr, "\n"))) { - if (line >= data + size) { - break; - } - - if (line[0] == '#') - continue; - - if (tx < 0) { - ret = sscanf(line, "TX %d GAIN %d INT %d", - &tx, &tx_gain, &tx_int); - if (ret == 3) - continue; - else - tx = -1; - } - if (rx < 0) { - ret = sscanf(line, "RX %d GAIN %d DEC %d", - &rx, &rx_gain, &rx_dec); - if (ret == 3) - continue; - else - rx = -1; - } - - if (rtx < 0) { - ret = sscanf(line, "RTX %lu %lu %lu %lu %lu %lu", - &st->filt_tx_path_clks[0], - &st->filt_tx_path_clks[1], - &st->filt_tx_path_clks[2], - &st->filt_tx_path_clks[3], - &st->filt_tx_path_clks[4], - &st->filt_tx_path_clks[5]); - if (ret == 6) { - rtx = 0; - continue; - } else { - rtx = -1; - } - } - - if (rrx < 0) { - ret = sscanf(line, "RRX %lu %lu %lu %lu %lu %lu", - &st->filt_rx_path_clks[0], - &st->filt_rx_path_clks[1], - &st->filt_rx_path_clks[2], - &st->filt_rx_path_clks[3], - &st->filt_rx_path_clks[4], - &st->filt_rx_path_clks[5]); - if (ret == 6) { - rrx = 0; - continue; - } else { - rrx = -1; - } - } - - if (!st->filt_rx_bw_Hz) { - ret = sscanf(line, "BWRX %d", &st->filt_rx_bw_Hz); - if (ret == 1) - continue; - else - st->filt_rx_bw_Hz = 0; - } - - if (!st->filt_tx_bw_Hz) { - ret = sscanf(line, "BWTX %d", &st->filt_tx_bw_Hz); - if (ret == 1) - continue; - else - st->filt_tx_bw_Hz = 0; - } - - ret = sscanf(line, "%d,%d", &txc, &rxc); - if (ret == 1) { - if (i >= ARRAY_SIZE(coef_tx)) - return -EINVAL; - - coef_tx[i] = coef_rx[i] = (short)txc; - i++; - continue; - } else if (ret == 2) { - if (i >= ARRAY_SIZE(coef_tx)) - return -EINVAL; - - coef_tx[i] = (short)txc; - coef_rx[i] = (short)rxc; - i++; - continue; - } - } - - if (tx != -1) { - switch (tx) { - case FIR_TX1: - case FIR_TX2: - case FIR_TX1_TX2: - st->tx_fir_int = tx_int; - ret = ad9361_load_fir_filter_coef(phy, tx, tx_gain, i, coef_tx); - - break; - default: - ret = -EINVAL; - } - } - - if (rx != -1) { - switch (rx | FIR_IS_RX) { - case FIR_RX1: - case FIR_RX2: - case FIR_RX1_RX2: - st->rx_fir_dec = rx_dec; - ret = ad9361_load_fir_filter_coef(phy, rx | FIR_IS_RX, - rx_gain, i, coef_rx); - break; - default: - ret = -EINVAL; - } - } - - if (tx == -1 && rx == -1) - ret = -EINVAL; - - if (ret < 0) - return ret; - - if (!(rrx | rtx)) - st->filt_valid = true; - - return size; -} - -static int ad9361_validate_enable_fir(struct ad9361_rf_phy *phy) -{ - struct ad9361_rf_phy_state *st = phy->state; - struct device *dev = &phy->spi->dev; - int ret; - unsigned long rx[6], tx[6]; - u32 max, valid; - - dev_dbg(dev, "%s: TX FIR EN=%d/TAPS%d/INT%d, RX FIR EN=%d/TAPS%d/DEC%d", - __func__, !st->bypass_tx_fir, st->tx_fir_ntaps, st->tx_fir_int, - !st->bypass_rx_fir, st->rx_fir_ntaps, st->rx_fir_dec); - - if (!st->bypass_tx_fir) { - if (!(st->tx_fir_int == 1 || st->tx_fir_int == 2 || - st->tx_fir_int == 4)) { - dev_err(dev, - "%s: Invalid: Interpolation %d in filter config", - __func__, st->tx_fir_int); - return -EINVAL; - } - - - if (st->tx_fir_int == 1 && st->tx_fir_ntaps > 64) { - dev_err(dev, - "%s: Invalid: TAPS > 64 and Interpolation = 1", - __func__); - return -EINVAL; - } - } - - if (!st->bypass_rx_fir) { - if (!(st->rx_fir_dec == 1 || st->rx_fir_dec == 2 || - st->rx_fir_dec == 4)) { - dev_err(dev, - "%s: Invalid: Decimation %d in filter config", - __func__, st->rx_fir_dec); - - return -EINVAL; - } - } - - if (!st->filt_valid || st->bypass_rx_fir || st->bypass_tx_fir) { - ret = ad9361_calculate_rf_clock_chain(phy, - clk_get_rate(phy->clks[TX_SAMPL_CLK]), - st->rate_governor, rx, tx); - if (ret < 0) { - u32 min = st->rate_governor ? 1500000U : 1000000U; - dev_err(dev, - "%s: Calculating filter rates failed %d " - "using min frequency",__func__, ret); - ret = ad9361_calculate_rf_clock_chain(phy, min, - st->rate_governor, rx, tx); - if (ret < 0) { - return ret; - } - - } - valid = false; - } else { - memcpy(rx, st->filt_rx_path_clks, sizeof(rx)); - memcpy(tx, st->filt_tx_path_clks, sizeof(tx)); - valid = true; - - } - -#ifdef _DEBUG - dev_dbg(&phy->spi->dev, "%s:RX %lu %lu %lu %lu %lu %lu", - __func__, rx[BBPLL_FREQ], rx[ADC_FREQ], - rx[R2_FREQ], rx[R1_FREQ], - rx[CLKRF_FREQ], rx[RX_SAMPL_FREQ]); - - dev_dbg(&phy->spi->dev, "%s:TX %lu %lu %lu %lu %lu %lu", - __func__, tx[BBPLL_FREQ], tx[ADC_FREQ], - tx[R2_FREQ], tx[R1_FREQ], - tx[CLKRF_FREQ], tx[RX_SAMPL_FREQ]); -#endif - - if (!st->bypass_tx_fir) { - max = (tx[DAC_FREQ] / tx[TX_SAMPL_FREQ]) * 16; - if (st->tx_fir_ntaps > max) { - dev_err(dev, - "%s: Invalid: ratio ADC/2 / TX_SAMPL * 16 > TAPS" - "(max %d, adc %lu, tx %lu)", - __func__, max, rx[ADC_FREQ], tx[TX_SAMPL_FREQ]); - return -EINVAL; - } - } - - if (!st->bypass_rx_fir) { - max = ((rx[ADC_FREQ] / ((rx[ADC_FREQ] == rx[R2_FREQ]) ? 1 : 2)) / - rx[RX_SAMPL_FREQ]) * 16; - if (st->rx_fir_ntaps > max) { - dev_err(dev, - "%s: Invalid: ratio ADC/2 / RX_SAMPL * 16 > TAPS (max %d)", - __func__, max); - return -EINVAL; - } - } - - ret = ad9361_set_trx_clock_chain(phy, rx, tx); - if (ret < 0) - return ret; - - /* See also: ad9361_set_trx_clock_chain() */ - if (!phy->pdata->dig_interface_tune_fir_disable && - st->bypass_tx_fir && st->bypass_rx_fir) - ad9361_dig_tune(phy, 0, RESTORE_DEFAULT); - - return ad9361_update_rf_bandwidth(phy, - (valid && st->filt_rx_bw_Hz) ? st->filt_rx_bw_Hz : st->current_rx_bw_Hz, - (valid && st->filt_tx_bw_Hz) ? st->filt_tx_bw_Hz : st->current_tx_bw_Hz); -} - -static void ad9361_work_func(struct work_struct *work) -{ - struct ad9361_rf_phy *phy = - container_of(work, struct ad9361_rf_phy, work); - struct ad9361_rf_phy_state *st = phy->state; - int ret; - - dev_dbg(&phy->spi->dev, "%s:", __func__); - - ret = ad9361_do_calib_run(phy, TX_QUAD_CAL, st->last_tx_quad_cal_phase); - if (ret < 0) - dev_err(&phy->spi->dev, - "%s: TX QUAD cal failed", __func__); - - complete_all(&phy->complete); - clear_bit(0, &st->flags); -} - -/* - * AD9361 Clocks - */ - -#define to_clk_priv(_hw) container_of(_hw, struct refclk_scale, hw) - -static inline int ad9361_set_muldiv(struct refclk_scale *priv, u32 mul, u32 div) -{ - priv->mult = mul; - priv->div = div; - return 0; -} - -static int ad9361_get_clk_scaler(struct clk_hw *hw) -{ - struct refclk_scale *clk_priv = to_clk_priv(hw); - struct spi_device *spi = clk_priv->spi; - u32 tmp, tmp1; - - switch (clk_priv->source) { - case BB_REFCLK: - tmp = ad9361_spi_read(spi, REG_CLOCK_CTRL); - tmp &= 0x3; - break; - case RX_REFCLK: - tmp = ad9361_spi_readf(spi, REG_REF_DIVIDE_CONFIG_1, - RX_REF_DIVIDER_MSB); - tmp1 = ad9361_spi_readf(spi, REG_REF_DIVIDE_CONFIG_2, - RX_REF_DIVIDER_LSB); - tmp = (tmp << 1) | tmp1; - break; - case TX_REFCLK: - tmp = ad9361_spi_readf(spi, REG_REF_DIVIDE_CONFIG_2, - TX_REF_DIVIDER(~0)); - break; - case ADC_CLK: - tmp = ad9361_spi_read(spi, REG_BBPLL); - return ad9361_set_muldiv(clk_priv, 1, 1 << (tmp & 0x7)); - case R2_CLK: - tmp = ad9361_spi_readf(spi, REG_RX_ENABLE_FILTER_CTRL, - DEC3_ENABLE_DECIMATION(~0)); - return ad9361_set_muldiv(clk_priv, 1, tmp + 1); - case R1_CLK: - tmp = ad9361_spi_readf(spi, REG_RX_ENABLE_FILTER_CTRL, RHB2_EN); - return ad9361_set_muldiv(clk_priv, 1, tmp + 1); - case CLKRF_CLK: - tmp = ad9361_spi_readf(spi, REG_RX_ENABLE_FILTER_CTRL, RHB1_EN); - return ad9361_set_muldiv(clk_priv, 1, tmp + 1); - case RX_SAMPL_CLK: - tmp = ad9361_spi_readf(spi, REG_RX_ENABLE_FILTER_CTRL, - RX_FIR_ENABLE_DECIMATION(~0)); - - if (!tmp) - tmp = 1; /* bypass filter */ - else - tmp = (1 << (tmp - 1)); - - return ad9361_set_muldiv(clk_priv, 1, tmp); - case DAC_CLK: - tmp = ad9361_spi_readf(spi, REG_BBPLL, BIT(3)); - return ad9361_set_muldiv(clk_priv, 1, tmp + 1); - case T2_CLK: - tmp = ad9361_spi_readf(spi, REG_TX_ENABLE_FILTER_CTRL, - THB3_ENABLE_INTERP(~0)); - return ad9361_set_muldiv(clk_priv, 1, tmp + 1); - case T1_CLK: - tmp = ad9361_spi_readf(spi, REG_TX_ENABLE_FILTER_CTRL, THB2_EN); - return ad9361_set_muldiv(clk_priv, 1, tmp + 1); - case CLKTF_CLK: - tmp = ad9361_spi_readf(spi, REG_TX_ENABLE_FILTER_CTRL, THB1_EN); - return ad9361_set_muldiv(clk_priv, 1, tmp + 1); - case TX_SAMPL_CLK: - tmp = ad9361_spi_readf(spi, REG_TX_ENABLE_FILTER_CTRL, - TX_FIR_ENABLE_INTERPOLATION(~0)); - - if (!tmp) - tmp = 1; /* bypass filter */ - else - tmp = (1 << (tmp - 1)); - - return ad9361_set_muldiv(clk_priv, 1, tmp); - default: - return -EINVAL; - } - - /* REFCLK Scaler */ - switch (tmp) { - case 0: - ad9361_set_muldiv(clk_priv, 1, 1); - break; - case 1: - ad9361_set_muldiv(clk_priv, 1, 2); - break; - case 2: - ad9361_set_muldiv(clk_priv, 1, 4); - break; - case 3: - ad9361_set_muldiv(clk_priv, 2, 1); - break; - default: - return -EINVAL; - - } - - return 0; -} - -static int ad9361_to_refclk_scaler(struct refclk_scale *clk_priv) -{ - /* REFCLK Scaler */ - switch (((clk_priv->mult & 0xF) << 4) | (clk_priv->div & 0xF)) { - case 0x11: - return 0; - case 0x12: - return 1; - case 0x14: - return 2; - case 0x21: - return 3; - default: - return -EINVAL; - } -}; - -static int ad9361_set_clk_scaler(struct clk_hw *hw, bool set) -{ - struct refclk_scale *clk_priv = to_clk_priv(hw); - struct spi_device *spi = clk_priv->spi; - u32 tmp; - int ret; - - switch (clk_priv->source) { - case BB_REFCLK: - ret = ad9361_to_refclk_scaler(clk_priv); - if (ret < 0) - return ret; - if (set) - return ad9361_spi_writef(spi, REG_CLOCK_CTRL, - REF_FREQ_SCALER(~0), ret); - break; - - case RX_REFCLK: - ret = ad9361_to_refclk_scaler(clk_priv); - if (ret < 0) - return ret; - if (set) { - tmp = ret; - ret = ad9361_spi_writef(spi, REG_REF_DIVIDE_CONFIG_1, - RX_REF_DIVIDER_MSB, tmp >> 1); - ret |= ad9361_spi_writef(spi, REG_REF_DIVIDE_CONFIG_2, - RX_REF_DIVIDER_LSB, tmp & 1); - return ret; - } - break; - case TX_REFCLK: - ret = ad9361_to_refclk_scaler(clk_priv); - if (ret < 0) - return ret; - if (set) - return ad9361_spi_writef(spi, REG_REF_DIVIDE_CONFIG_2, - TX_REF_DIVIDER(~0), ret); - break; - case ADC_CLK: - tmp = ilog2((u8)clk_priv->div); - if (clk_priv->mult != 1 || tmp > 6 || tmp < 1) - return -EINVAL; - - if (set) - return ad9361_spi_writef(spi, REG_BBPLL, 0x7, tmp); - break; - case R2_CLK: - if (clk_priv->mult != 1 || clk_priv->div > 3 || clk_priv->div < 1) - return -EINVAL; - if (set) - return ad9361_spi_writef(spi, REG_RX_ENABLE_FILTER_CTRL, - DEC3_ENABLE_DECIMATION(~0), - clk_priv->div - 1); - break; - case R1_CLK: - if (clk_priv->mult != 1 || clk_priv->div > 2 || clk_priv->div < 1) - return -EINVAL; - if (set) - return ad9361_spi_writef(spi, REG_RX_ENABLE_FILTER_CTRL, - RHB2_EN, clk_priv->div - 1); - break; - case CLKRF_CLK: - if (clk_priv->mult != 1 || clk_priv->div > 2 || clk_priv->div < 1) - return -EINVAL; - if (set) - return ad9361_spi_writef(spi, REG_RX_ENABLE_FILTER_CTRL, - RHB1_EN, clk_priv->div - 1); - break; - case RX_SAMPL_CLK: - if (clk_priv->mult != 1 || clk_priv->div > 4 || - clk_priv->div < 1 || clk_priv->div == 3) - return -EINVAL; - - if (clk_priv->phy->state->bypass_rx_fir) - tmp = 0; - else - tmp = ilog2(clk_priv->div) + 1; - - if (set) - return ad9361_spi_writef(spi, REG_RX_ENABLE_FILTER_CTRL, - RX_FIR_ENABLE_DECIMATION(~0), tmp); - break; - case DAC_CLK: - if (clk_priv->mult != 1 || clk_priv->div > 2 || clk_priv->div < 1) - return -EINVAL; - if (set) - return ad9361_spi_writef(spi, REG_BBPLL, - BIT(3), clk_priv->div - 1); - break; - case T2_CLK: - if (clk_priv->mult != 1 || clk_priv->div > 3 || clk_priv->div < 1) - return -EINVAL; - if (set) - return ad9361_spi_writef(spi, REG_TX_ENABLE_FILTER_CTRL, - THB3_ENABLE_INTERP(~0), - clk_priv->div - 1); - break; - case T1_CLK: - if (clk_priv->mult != 1 || clk_priv->div > 2 || clk_priv->div < 1) - return -EINVAL; - if (set) - return ad9361_spi_writef(spi, REG_TX_ENABLE_FILTER_CTRL, - THB2_EN, clk_priv->div - 1); - break; - case CLKTF_CLK: - if (clk_priv->mult != 1 || clk_priv->div > 2 || clk_priv->div < 1) - return -EINVAL; - if (set) - return ad9361_spi_writef(spi, REG_TX_ENABLE_FILTER_CTRL, - THB1_EN, clk_priv->div - 1); - break; - case TX_SAMPL_CLK: - if (clk_priv->mult != 1 || clk_priv->div > 4 || - clk_priv->div < 1 || clk_priv->div == 3) - return -EINVAL; - - if (clk_priv->phy->state->bypass_tx_fir) - tmp = 0; - else - tmp = ilog2(clk_priv->div) + 1; - - if (set) - return ad9361_spi_writef(spi, REG_TX_ENABLE_FILTER_CTRL, - TX_FIR_ENABLE_INTERPOLATION(~0), tmp); - break; - default: - return -EINVAL; - } - - return 0; -} - -static unsigned long ad9361_clk_factor_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct refclk_scale *clk_priv = to_clk_priv(hw); - u64 rate; - - ad9361_get_clk_scaler(hw); - rate = (parent_rate * clk_priv->mult) / clk_priv->div; - - return (unsigned long)rate; -} - -static long ad9361_clk_factor_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) -{ - struct refclk_scale *clk_priv = to_clk_priv(hw); - int ret; - - if (rate >= *prate) { - clk_priv->mult = DIV_ROUND_CLOSEST(rate, *prate); - clk_priv->div = 1; - - } else { - clk_priv->div = DIV_ROUND_CLOSEST(*prate, rate); - clk_priv->mult = 1; - if (!clk_priv->div) { - dev_err(&clk_priv->spi->dev, "%s: divide by zero", - __func__); - clk_priv->div = 1; - } - } - - ret = ad9361_set_clk_scaler(hw, false); - if (ret < 0) - return ret; - - return (*prate / clk_priv->div) * clk_priv->mult; -} - -static int ad9361_clk_factor_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - struct refclk_scale *clk_priv = to_clk_priv(hw); - - dev_dbg(&clk_priv->spi->dev, "%s: Rate %lu Hz Parent Rate %lu Hz", - __func__, rate, parent_rate); - - if (rate >= parent_rate) { - clk_priv->mult = DIV_ROUND_CLOSEST(rate, parent_rate); - clk_priv->div = 1; - } else { - clk_priv->div = DIV_ROUND_CLOSEST(parent_rate, rate); - clk_priv->mult = 1; - if (!clk_priv->div) { - dev_err(&clk_priv->spi->dev, "%s: divide by zero", - __func__); - clk_priv->div = 1; - } - } - - return ad9361_set_clk_scaler(hw, true); -} - -static const struct clk_ops refclk_scale_ops = { - .round_rate = ad9361_clk_factor_round_rate, - .set_rate = ad9361_clk_factor_set_rate, - .recalc_rate = ad9361_clk_factor_recalc_rate, -}; - -/* - * BBPLL - */ - -static unsigned long ad9361_bbpll_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct refclk_scale *clk_priv = to_clk_priv(hw); - u64 rate; - unsigned long fract, integer; - u8 buf[4]; - - ad9361_spi_readm(clk_priv->spi, REG_INTEGER_BB_FREQ_WORD, &buf[0], - REG_INTEGER_BB_FREQ_WORD - REG_FRACT_BB_FREQ_WORD_1 + 1); - - fract = (buf[3] << 16) | (buf[2] << 8) | buf[1]; - integer = buf[0]; - - rate = ((u64)parent_rate * fract); - do_div(rate, BBPLL_MODULUS); - rate += (u64)parent_rate * integer; - - return (unsigned long)rate; -} - -static long ad9361_bbpll_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) -{ - u64 tmp, rate64 = rate; - u32 fract, integer; - - if (rate > MAX_BBPLL_FREQ) - return MAX_BBPLL_FREQ; - - if (rate < MIN_BBPLL_FREQ) - return MIN_BBPLL_FREQ; - - tmp = do_div(rate64, *prate); - tmp = tmp * BBPLL_MODULUS + (*prate >> 1); - do_div(tmp, *prate); - - integer = rate64; - fract = tmp; - - tmp = *prate * (u64)fract; - do_div(tmp, BBPLL_MODULUS); - tmp += *prate * integer; - - return tmp; -} - -static int ad9361_bbpll_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - struct refclk_scale *clk_priv = to_clk_priv(hw); - struct spi_device *spi = clk_priv->spi; - u64 tmp, rate64 = rate; - u32 fract, integer; - int icp_val; - u8 lf_defaults[3] = {0x35, 0x5B, 0xE8}; - - dev_dbg(&spi->dev, "%s: Rate %lu Hz Parent Rate %lu Hz", - __func__, rate, parent_rate); - - /* - * Setup Loop Filter and CP Current - * Scale is 150uA @ (1280MHz BBPLL, 40MHz REFCLK) - */ - tmp = (rate64 >> 7) * 150ULL; - do_div(tmp, (parent_rate >> 7) * 32UL); - - /* 25uA/LSB, Offset 25uA */ - icp_val = DIV_ROUND_CLOSEST((u32)tmp, 25U) - 1; - - icp_val = clamp(icp_val, 1, 64); - - ad9361_spi_write(spi, REG_CP_CURRENT, icp_val); - ad9361_spi_writem(spi, REG_LOOP_FILTER_3, lf_defaults, - ARRAY_SIZE(lf_defaults)); - - /* Allow calibration to occur and set cal count to 1024 for max accuracy */ - ad9361_spi_write(spi, REG_VCO_CTRL, - FREQ_CAL_ENABLE | FREQ_CAL_COUNT_LENGTH(3)); - /* Set calibration clock to REFCLK/4 for more accuracy */ - ad9361_spi_write(spi, REG_SDM_CTRL, 0x10); - - /* Calculate and set BBPLL frequency word */ - tmp = do_div(rate64, parent_rate); - tmp = tmp *(u64) BBPLL_MODULUS + (parent_rate >> 1); - do_div(tmp, parent_rate); - - integer = rate64; - fract = tmp; - - ad9361_spi_write(spi, REG_INTEGER_BB_FREQ_WORD, integer); - ad9361_spi_write(spi, REG_FRACT_BB_FREQ_WORD_3, fract); - ad9361_spi_write(spi, REG_FRACT_BB_FREQ_WORD_2, fract >> 8); - ad9361_spi_write(spi, REG_FRACT_BB_FREQ_WORD_1, fract >> 16); - - ad9361_spi_write(spi, REG_SDM_CTRL_1, INIT_BB_FO_CAL | BBPLL_RESET_BAR); /* Start BBPLL Calibration */ - ad9361_spi_write(spi, REG_SDM_CTRL_1, BBPLL_RESET_BAR); /* Clear BBPLL start calibration bit */ - - ad9361_spi_write(spi, REG_VCO_PROGRAM_1, 0x86); /* Increase BBPLL KV and phase margin */ - ad9361_spi_write(spi, REG_VCO_PROGRAM_2, 0x01); /* Increase BBPLL KV and phase margin */ - ad9361_spi_write(spi, REG_VCO_PROGRAM_2, 0x05); /* Increase BBPLL KV and phase margin */ - - return ad9361_check_cal_done(clk_priv->phy, REG_CH_1_OVERFLOW, - BBPLL_LOCK, 1); -} - -static const struct clk_ops bbpll_clk_ops = { - .round_rate = ad9361_bbpll_round_rate, - .set_rate = ad9361_bbpll_set_rate, - .recalc_rate = ad9361_bbpll_recalc_rate, -}; - -/* - * RFPLL - */ - -static u64 ad9361_calc_rfpll_freq(u64 parent_rate, - u64 integer, - u64 fract, u32 vco_div) -{ - u64 rate; - - rate = parent_rate * fract; - do_div(rate, RFPLL_MODULUS); - rate += parent_rate * integer; - - return rate >> (vco_div + 1); -} - -static int ad9361_calc_rfpll_divder(struct ad9361_rf_phy *phy, - struct refclk_scale *clk_priv, u64 freq, - u64 parent_rate, u32 *integer, - u32 *fract, int *vco_div, u64 *vco_freq) -{ - u64 tmp; - int div, ret; - - ret = ad9361_validate_rfpll(phy, clk_priv->source == TX_RFPLL_INT, freq); - if (ret) - return ret; - - div = -1; - - while (freq <= MIN_VCO_FREQ_HZ) { - freq <<= 1; - div++; - } - - *vco_div = div; - *vco_freq = freq; - tmp = do_div(freq, parent_rate); - tmp = tmp * RFPLL_MODULUS + (parent_rate >> 1); - do_div(tmp, parent_rate); - *integer = freq; - *fract = tmp; - - return 0; -} - -static unsigned long ad9361_rfpll_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct refclk_scale *clk_priv = to_clk_priv(hw); - struct ad9361_rf_phy *phy = clk_priv->phy; - struct ad9361_rf_phy_state *st = phy->state; - unsigned long fract, integer; - u8 buf[5]; - u32 reg, div_mask, vco_div, profile; - - dev_dbg(&clk_priv->spi->dev, "%s: Parent Rate %lu Hz", - __func__, parent_rate); - - switch (clk_priv->source) { - case RX_RFPLL_INT: - reg = REG_RX_FRACT_BYTE_2; - div_mask = RX_VCO_DIVIDER(~0); - profile = st->fastlock.current_profile[0]; - break; - case TX_RFPLL_INT: - reg = REG_TX_FRACT_BYTE_2; - div_mask = TX_VCO_DIVIDER(~0); - profile = st->fastlock.current_profile[1]; - break; - default: - return -EINVAL; - } - - if (profile) { - bool tx = clk_priv->source == TX_RFPLL_INT; - profile = profile - 1; - - buf[0] = ad9361_fastlock_readval(phy->spi, tx, profile, 4); - buf[1] = ad9361_fastlock_readval(phy->spi, tx, profile, 3); - buf[2] = ad9361_fastlock_readval(phy->spi, tx, profile, 2); - buf[3] = ad9361_fastlock_readval(phy->spi, tx, profile, 1); - buf[4] = ad9361_fastlock_readval(phy->spi, tx, profile, 0); - vco_div = ad9361_fastlock_readval(phy->spi, tx, profile, 12) & 0xF; - - } else { - ad9361_spi_readm(clk_priv->spi, reg, &buf[0], ARRAY_SIZE(buf)); - vco_div = ad9361_spi_readf(clk_priv->spi, REG_RFPLL_DIVIDERS, div_mask); - } - - fract = (SYNTH_FRACT_WORD(buf[0]) << 16) | (buf[1] << 8) | buf[2]; - integer = (SYNTH_INTEGER_WORD(buf[3]) << 8) | buf[4]; - - return ad9361_to_clk(ad9361_calc_rfpll_freq(parent_rate, integer, - fract, vco_div)); -} - -static int ad9361_rfpll_determine_rate(struct clk_hw *hw, - struct clk_rate_request *req) -{ - struct refclk_scale *clk_priv = to_clk_priv(hw); - struct ad9361_rf_phy *phy = clk_priv->phy; - int ret; - dev_dbg(&clk_priv->spi->dev, "%s: Rate %lu Hz", __func__, req->rate); - - ret = ad9361_validate_rfpll(phy, clk_priv->source == TX_RFPLL_INT, - ad9361_from_clk(req->rate)); - if (ret) - return ret; - - return 0; -} - -static int ad9361_rfpll_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - struct refclk_scale *clk_priv = to_clk_priv(hw); - struct ad9361_rf_phy *phy = clk_priv->phy; - struct ad9361_rf_phy_state *st = phy->state; - u64 vco; - u8 buf[5]; - u32 reg, div_mask, lock_reg, fract, integer; - int vco_div, ret, fixup_other; - - dev_dbg(&clk_priv->spi->dev, "%s: %s Rate %lu Hz Parent Rate %lu Hz", - __func__, clk_priv->source == TX_RFPLL_INT ? "TX" : "RX", - rate, parent_rate); - - ad9361_fastlock_prepare(phy, clk_priv->source == TX_RFPLL_INT, 0, false); - - ret = ad9361_calc_rfpll_divder(phy, clk_priv, ad9361_from_clk(rate), parent_rate, - &integer, &fract, &vco_div, &vco); - if (ret) - return ret; - - switch (clk_priv->source) { - case RX_RFPLL_INT: - reg = REG_RX_FRACT_BYTE_2; - lock_reg = REG_RX_CP_OVERRANGE_VCO_LOCK; - div_mask = RX_VCO_DIVIDER(~0); - st->cached_rx_rfpll_div = vco_div; - st->current_rx_lo_freq = rate; - break; - case TX_RFPLL_INT: - reg = REG_TX_FRACT_BYTE_2; - lock_reg = REG_TX_CP_OVERRANGE_VCO_LOCK; - div_mask = TX_VCO_DIVIDER(~0); - st->cached_tx_rfpll_div = vco_div; - st->current_tx_lo_freq = rate; - break; - default: - return -EINVAL; - } - - /* Option to skip VCO cal in TDD mode when moving from TX/RX to Alert */ - if (phy->pdata->tdd_skip_vco_cal) - ad9361_trx_vco_cal_control(phy, clk_priv->source == TX_RFPLL_INT, - true); - do { - fixup_other = 0; - ad9361_rfpll_vco_init(phy, div_mask == TX_VCO_DIVIDER(~0), - vco, parent_rate); - - buf[0] = SYNTH_FRACT_WORD(fract >> 16); - buf[1] = fract >> 8; - buf[2] = fract & 0xFF; - buf[3] = SYNTH_INTEGER_WORD(integer >> 8) | - (~SYNTH_INTEGER_WORD(~0) & - ad9361_spi_read(clk_priv->spi, reg - 3)); - buf[4] = integer & 0xFF; - - ad9361_spi_writem(clk_priv->spi, reg, buf, 5); - ad9361_spi_writef(clk_priv->spi, REG_RFPLL_DIVIDERS, div_mask, vco_div); - - ret = ad9361_check_cal_done(phy, lock_reg, VCO_LOCK, 1); - - /* In FDD mode with RX LO == TX LO frequency we use TDD tables to - * reduce VCO pulling - */ - - if (((phy->pdata->fdd && !phy->pdata->fdd_independent_mode) && - (st->current_tx_lo_freq == st->current_rx_lo_freq) && - (st->current_tx_use_tdd_table != st->current_rx_use_tdd_table)) || - ((phy->pdata->fdd && !phy->pdata->fdd_independent_mode) && - (st->current_tx_lo_freq != st->current_rx_lo_freq) && - (st->current_tx_use_tdd_table || st->current_rx_use_tdd_table))) { - unsigned long _rate; - - switch (clk_priv->source) { - case RX_RFPLL_INT: - reg = REG_TX_FRACT_BYTE_2; - lock_reg = REG_TX_CP_OVERRANGE_VCO_LOCK; - div_mask = TX_VCO_DIVIDER(~0); - _rate = st->current_tx_lo_freq; - break; - case TX_RFPLL_INT: - reg = REG_RX_FRACT_BYTE_2; - lock_reg = REG_RX_CP_OVERRANGE_VCO_LOCK; - div_mask = RX_VCO_DIVIDER(~0); - _rate = st->current_rx_lo_freq; - break; - default: - return -EINVAL; - - } - - if (st->current_tx_lo_freq != st->current_rx_lo_freq) { - ad9361_calc_rfpll_divder(phy, clk_priv, ad9361_from_clk(_rate), - parent_rate, &integer, &fract, &vco_div, &vco); - - ad9361_fastlock_prepare(phy, clk_priv->source == RX_RFPLL_INT, 0, false); - } - - fixup_other = 1; - } - - } while (fixup_other); - - if (phy->pdata->tdd_skip_vco_cal) - ad9361_trx_vco_cal_control(phy, clk_priv->source == TX_RFPLL_INT, - false); - - return ret; -} - -static const struct clk_ops rfpll_clk_ops_int = { - .determine_rate = ad9361_rfpll_determine_rate, - .set_rate = ad9361_rfpll_set_rate, - .recalc_rate = ad9361_rfpll_recalc_rate, -}; - -static unsigned long ad9361_rfpll_dummy_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct refclk_scale *clk_priv = to_clk_priv(hw); - return clk_priv->rate; -} - -static int ad9361_rfpll_dummy_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - struct refclk_scale *clk_priv = to_clk_priv(hw); - clk_priv->rate = rate; - - return 0; -} - -static const struct clk_ops rfpll_dummy_clk_ops_int = { - .determine_rate = ad9361_rfpll_determine_rate, - .set_rate = ad9361_rfpll_dummy_set_rate, - .recalc_rate = ad9361_rfpll_dummy_recalc_rate, -}; - - -static u8 ad9361_clk_mux_get_parent(struct clk_hw *hw) -{ - struct refclk_scale *clk_priv = to_clk_priv(hw); - dev_dbg(&clk_priv->spi->dev, "%s: index %d", __func__, clk_priv->mult); - - return clk_priv->mult; -} - -static int ad9361_clk_mux_set_parent(struct clk_hw *hw, u8 index) -{ - struct refclk_scale *clk_priv = to_clk_priv(hw); - struct ad9361_rf_phy *phy = clk_priv->phy; - int ret; - - dev_dbg(&clk_priv->spi->dev, "%s: index %d", __func__, index); - - ad9361_ensm_force_state(phy, ENSM_STATE_ALERT); - - ret = ad9361_trx_ext_lo_control(phy, clk_priv->source == TX_RFPLL, index == 1); - if (ret >= 0) - clk_priv->mult = index; - - ad9361_ensm_restore_prev_state(phy); - - return ret; -} - -static const struct clk_ops rfpll_clk_ops = { - .get_parent = ad9361_clk_mux_get_parent, - .set_parent = ad9361_clk_mux_set_parent, - .determine_rate = __clk_mux_determine_rate, -}; - -static int ad9361_rx_rfpll_rate_change(struct notifier_block *nb, - unsigned long flags, void *data) -{ - struct clk_notifier_data *cnd = data; - struct ad9361_rf_phy *phy = - container_of(nb, struct ad9361_rf_phy, clk_nb_rx); - u64 new_rate; - - - if (flags == POST_RATE_CHANGE) { - new_rate = ad9361_from_clk(cnd->new_rate); - dev_dbg(&phy->spi->dev, "%s: rate %llu Hz", __func__, - new_rate); - if (cnd->new_rate) - ad9361_load_gt(phy, new_rate, GT_RX1 + GT_RX2); - ad9361_adjust_rx_ext_band_settings(phy, new_rate); - } - - return NOTIFY_OK; -} - -static int ad9361_tx_rfpll_rate_change(struct notifier_block *nb, - unsigned long flags, void *data) -{ - struct clk_notifier_data *cnd = data; - struct ad9361_rf_phy *phy = - container_of(nb, struct ad9361_rf_phy, clk_nb_tx); - struct ad9361_rf_phy_state *st = phy->state; - u64 new_rate; - - if (flags == POST_RATE_CHANGE) { - new_rate = ad9361_from_clk(cnd->new_rate); - dev_dbg(&phy->spi->dev, "%s: rate %llu Hz", __func__, - new_rate); - /* For RX LO we typically have the tracking option enabled - * so for now do nothing here. - */ - if (st->auto_cal_en) - if (abs(st->last_tx_quad_cal_freq - new_rate) > - st->cal_threshold_freq) { - - set_bit(0, &st->flags); - reinit_completion(&phy->complete); - schedule_work(&phy->work); - st->last_tx_quad_cal_freq = new_rate; - } - ad9361_adjust_tx_ext_band_settings(phy, new_rate); - } - - return NOTIFY_OK; -} - - -#define AD9361_MAX_CLK_NAME 79 - -static char *ad9361_clk_set_dev_name(struct ad9361_rf_phy *phy, - char *dest, const char *name) -{ - size_t len = 0; - - if (name == NULL) - return NULL; - - if (*name == '-') - len = strlcpy(dest, dev_name(&phy->spi->dev), - AD9361_MAX_CLK_NAME); - else - *dest = '\0'; - - return strncat(dest, name, AD9361_MAX_CLK_NAME - len); -} - -static int ad9361_clk_register(struct ad9361_rf_phy *phy, - const char *name, const char *parent_name, - const char *parent_name2, unsigned long flags, - u32 source) -{ - struct refclk_scale *clk_priv = &phy->clk_priv[source]; - struct clk_init_data init; - struct clk *clk; - char c_name[AD9361_MAX_CLK_NAME + 1], p_name[2][AD9361_MAX_CLK_NAME + 1]; - const char *_parent_name[2]; - - /* struct refclk_scale assignments */ - clk_priv->source = source; - clk_priv->hw.init = &init; - clk_priv->spi = phy->spi; - clk_priv->phy = phy; - - _parent_name[0] = ad9361_clk_set_dev_name(phy, p_name[0], parent_name); - _parent_name[1] = ad9361_clk_set_dev_name(phy, p_name[1], parent_name2); - - init.name = ad9361_clk_set_dev_name(phy, c_name, name);; - init.flags = flags; - init.parent_names = &_parent_name[0]; - init.num_parents = _parent_name[1] ? 2 : _parent_name[0] ? 1 : 0; - - switch (source) { - case BBPLL_CLK: - init.ops = &bbpll_clk_ops; - break; - case RX_RFPLL_INT: - case TX_RFPLL_INT: - init.ops = &rfpll_clk_ops_int; - break; - case RX_RFPLL_DUMMY: - init.ops = &rfpll_dummy_clk_ops_int; - clk_priv->rate = ad9361_to_clk(phy->pdata->rx_synth_freq); - break; - case TX_RFPLL_DUMMY: - init.ops = &rfpll_dummy_clk_ops_int; - clk_priv->rate = ad9361_to_clk(phy->pdata->tx_synth_freq); - break; - case RX_RFPLL: - case TX_RFPLL: - init.ops = &rfpll_clk_ops; - break; - default: - init.ops = &refclk_scale_ops; - } - - clk = devm_clk_register(&phy->spi->dev, &clk_priv->hw); - phy->clks[source] = clk; - - return 0; -} - -static int ad9361_clks_disable(struct ad9361_rf_phy *phy) -{ - clk_disable_unprepare(phy->clks[TX_RFPLL]); - clk_disable_unprepare(phy->clks[RX_RFPLL]); - - return 0; -} - -static int ad9361_clks_resync(struct ad9361_rf_phy *phy) -{ - int i; - - for (i = TX_RFPLL; i >= 0; i--) - clk_get_rate(phy->clks[i]); - - return 0; -} - -static int register_clocks(struct ad9361_rf_phy *phy) -{ - const char *parent_name; - const char *ext_tx_lo = NULL; - const char *ext_rx_lo = NULL; - u32 flags = CLK_GET_RATE_NOCACHE; - int ret; - - parent_name = __clk_get_name(phy->clk_refin); - - phy->clk_data.clks = phy->clks; - phy->clk_data.clk_num = NUM_AD9361_CLKS; - - /* Dummy Clock in case no external LO clock given */ - - phy->clk_ext_lo_rx = devm_clk_get(&phy->spi->dev, "ext_rx_lo"); - phy->clk_ext_lo_tx = devm_clk_get(&phy->spi->dev, "ext_tx_lo"); - - if (PTR_ERR(phy->clk_ext_lo_rx) == -EPROBE_DEFER) - return -EPROBE_DEFER; - - if (PTR_ERR(phy->clk_ext_lo_tx) == -EPROBE_DEFER) - return -EPROBE_DEFER; - - if (IS_ERR_OR_NULL(phy->clk_ext_lo_rx)) { - ad9361_clk_register(phy, "-rx_lo_dummy", NULL, NULL, - CLK_IGNORE_UNUSED, RX_RFPLL_DUMMY); - - phy->clk_ext_lo_rx = phy->clks[RX_RFPLL_DUMMY]; - ext_rx_lo = "-rx_lo_dummy"; - } else { - ext_rx_lo = __clk_get_name(phy->clk_ext_lo_rx); - } - - if (IS_ERR_OR_NULL(phy->clk_ext_lo_tx)) { - ad9361_clk_register(phy, "-tx_lo_dummy", NULL, NULL, - CLK_IGNORE_UNUSED, TX_RFPLL_DUMMY); - - phy->clk_ext_lo_tx = phy->clks[TX_RFPLL_DUMMY]; - ext_tx_lo = "-tx_lo_dummy"; - } else { - ext_tx_lo = __clk_get_name(phy->clk_ext_lo_tx); - } - - /* Scaled Reference Clocks */ - ad9361_clk_register(phy, "-tx_refclk", parent_name, NULL, - flags | CLK_IGNORE_UNUSED, TX_REFCLK); - - ad9361_clk_register(phy, "-rx_refclk", parent_name, NULL, - flags | CLK_IGNORE_UNUSED, RX_REFCLK); - - ad9361_clk_register(phy, "-bb_refclk", parent_name, NULL, - flags | CLK_IGNORE_UNUSED, BB_REFCLK); - - /* Base Band PLL Clock */ - ad9361_clk_register(phy, "-bbpll_clk", "-bb_refclk", NULL, - flags | CLK_IGNORE_UNUSED, BBPLL_CLK); - - ad9361_clk_register(phy, "-adc_clk", "-bbpll_clk", NULL, - flags | CLK_IGNORE_UNUSED, ADC_CLK); - - ad9361_clk_register(phy, "-r2_clk", "-adc_clk", NULL, - flags | CLK_IGNORE_UNUSED, R2_CLK); - - ad9361_clk_register(phy, "-r1_clk", "-r2_clk", NULL, - flags | CLK_IGNORE_UNUSED, R1_CLK); - - ad9361_clk_register(phy, "-clkrf_clk", "-r1_clk", NULL, - flags | CLK_IGNORE_UNUSED, CLKRF_CLK); - - ad9361_clk_register(phy, "-rx_sampl_clk", "-clkrf_clk", NULL, - flags | CLK_IGNORE_UNUSED, RX_SAMPL_CLK); - - ad9361_clk_register(phy, "-dac_clk", "-adc_clk", NULL, - flags | CLK_IGNORE_UNUSED, DAC_CLK); - - ad9361_clk_register(phy, "-t2_clk", "-dac_clk", NULL, - flags | CLK_IGNORE_UNUSED, T2_CLK); - - ad9361_clk_register(phy, "-t1_clk", "-t2_clk", NULL, - flags | CLK_IGNORE_UNUSED, T1_CLK); - - ad9361_clk_register(phy, "-clktf_clk", "-t1_clk", NULL, - flags | CLK_IGNORE_UNUSED, CLKTF_CLK); - - ad9361_clk_register(phy, "-tx_sampl_clk", "-clktf_clk", NULL, - flags | CLK_IGNORE_UNUSED, TX_SAMPL_CLK); - - ad9361_clk_register(phy, "-rx_rfpll_int", "-rx_refclk", NULL, - flags | CLK_IGNORE_UNUSED, RX_RFPLL_INT); - - ad9361_clk_register(phy, "-tx_rfpll_int", "-tx_refclk", NULL, - flags | CLK_IGNORE_UNUSED, TX_RFPLL_INT); - - ad9361_clk_register(phy, "-rx_rfpll", "-rx_rfpll_int", ext_rx_lo, - flags | CLK_IGNORE_UNUSED | CLK_SET_RATE_NO_REPARENT | - CLK_SET_RATE_PARENT, RX_RFPLL); - - ad9361_clk_register(phy, "-tx_rfpll", "-tx_rfpll_int", ext_tx_lo, - flags | CLK_IGNORE_UNUSED | CLK_SET_RATE_NO_REPARENT | - CLK_SET_RATE_PARENT, TX_RFPLL); - - phy->clk_nb_rx.notifier_call = ad9361_rx_rfpll_rate_change; - ret = clk_notifier_register(phy->clks[RX_RFPLL], &phy->clk_nb_rx); - if (ret < 0) - return ret; - - phy->clk_nb_tx.notifier_call = ad9361_tx_rfpll_rate_change; - ret = clk_notifier_register(phy->clks[TX_RFPLL], &phy->clk_nb_tx); - if (ret < 0) - return ret; - - return 0; -} - -enum ad9361_iio_dev_attr { - AD9361_RF_RX_BANDWIDTH, - AD9361_RF_TX_BANDWIDTH, - AD9361_ENSM_MODE, - AD9361_ENSM_MODE_AVAIL, - AD9361_CALIB_MODE, - AD9361_CALIB_MODE_AVAIL, - AD9361_RSSI_GAIN_STEP_ERROR, - AD9361_RX_PATH_FREQ, - AD9361_TX_PATH_FREQ, - AD9361_TRX_RATE_GOV, - AD9361_TRX_RATE_GOV_AVAIL, - AD9361_FIR_RX_ENABLE, - AD9361_FIR_TX_ENABLE, - AD9361_FIR_TRX_ENABLE, - AD9361_BBDC_OFFS_ENABLE, - AD9361_RFDC_OFFS_ENABLE, - AD9361_QUAD_ENABLE, - AD9361_DCXO_TUNE_COARSE, - AD9361_DCXO_TUNE_COARSE_AVAILABLE, - AD9361_DCXO_TUNE_FINE, - AD9361_DCXO_TUNE_FINE_AVAILABLE, - AD9361_XO_CORRECTION, - AD9361_XO_CORRECTION_AVAILABLE, - AD9361_MCS_SYNC, -}; - -static ssize_t ad9361_phy_store(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t len) -{ - struct iio_dev *indio_dev = dev_to_iio_dev(dev); - struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); - struct ad9361_rf_phy *phy = iio_priv(indio_dev); - struct ad9361_rf_phy_state *st = phy->state; - long readin; - int ret = 0, arg = -1; - u32 val; - bool res; - - if (st->curr_ensm_state == ENSM_STATE_SLEEP && - this_attr->address != AD9361_ENSM_MODE) - return -EINVAL; - - mutex_lock(&indio_dev->mlock); - - switch ((u32)this_attr->address) { - case AD9361_RF_RX_BANDWIDTH: - ret = kstrtol(buf, 10, &readin); - if (ret) - break; - - readin = ad9361_validate_rf_bw(phy, readin); - - if (st->current_rx_bw_Hz != readin) - ret = ad9361_update_rf_bandwidth(phy, readin, - st->current_tx_bw_Hz); - else - ret = 0; - break; - case AD9361_RF_TX_BANDWIDTH: - ret = kstrtol(buf, 10, &readin); - if (ret) - break; - - readin = ad9361_validate_rf_bw(phy, readin); - - if (st->current_tx_bw_Hz != readin) - ret = ad9361_update_rf_bandwidth(phy, - st->current_rx_bw_Hz, readin); - else - ret = 0; - break; - case AD9361_ENSM_MODE: - res = false; - phy->pdata->fdd_independent_mode = false; - - if (sysfs_streq(buf, "tx")) - val = ENSM_STATE_TX; - else if (sysfs_streq(buf, "rx")) - val = ENSM_STATE_RX; - else if (sysfs_streq(buf, "alert")) - val = ENSM_STATE_ALERT; - else if (sysfs_streq(buf, "fdd")) - val = ENSM_STATE_FDD; - else if (sysfs_streq(buf, "wait")) - val = ENSM_STATE_SLEEP_WAIT; - else if (sysfs_streq(buf, "sleep")) - val = ENSM_STATE_SLEEP; - else if (sysfs_streq(buf, "pinctrl")) { - res = true; - val = ENSM_STATE_SLEEP_WAIT; - } else if (sysfs_streq(buf, "pinctrl_fdd_indep")) { - val = ENSM_STATE_FDD; - phy->pdata->fdd_independent_mode = true; - } else - break; - - ad9361_set_ensm_mode(phy, phy->pdata->fdd, res); - ret = ad9361_ensm_set_state(phy, val, res); - break; - case AD9361_TRX_RATE_GOV: - if (sysfs_streq(buf, "highest_osr")) - st->rate_governor = 0; - else if (sysfs_streq(buf, "nominal")) - st->rate_governor = 1; - else - ret = -EINVAL; - break; - case AD9361_FIR_TRX_ENABLE: - ret = strtobool(buf, &res); - if (ret < 0) - break; - - if ((st->bypass_rx_fir == st->bypass_tx_fir) && - (st->bypass_rx_fir == !res)) - break; - - st->bypass_rx_fir = st->bypass_tx_fir = !res; - - ret = ad9361_validate_enable_fir(phy); - if (ret < 0) { - st->bypass_rx_fir = true; - st->bypass_tx_fir = true; - } - - break; - case AD9361_FIR_RX_ENABLE: - ret = strtobool(buf, &res); - if (ret < 0) - break; - - if (st->bypass_rx_fir == !res) - break; - - st->bypass_rx_fir = !res; - - ret = ad9361_validate_enable_fir(phy); - if (ret < 0) { - st->bypass_rx_fir = true; - } - - break; - case AD9361_FIR_TX_ENABLE: - ret = strtobool(buf, &res); - if (ret < 0) - break; - - if (st->bypass_tx_fir == !res) - break; - - st->bypass_tx_fir = !res; - - ret = ad9361_validate_enable_fir(phy); - if (ret < 0) { - st->bypass_tx_fir = true; - } - - - break; - case AD9361_CALIB_MODE: - val = 0; - if (sysfs_streq(buf, "auto")) { - st->auto_cal_en = true; - st->manual_tx_quad_cal_en = false; - } else if (sysfs_streq(buf, "manual")) { - st->auto_cal_en = false; - st->manual_tx_quad_cal_en = false; - } else if (sysfs_streq(buf, "manual_tx_quad")) { - st->auto_cal_en = false; - st->manual_tx_quad_cal_en = true; - } else if (!strncmp(buf, "tx_quad", 7)) { - ret = sscanf(buf, "tx_quad %d", &arg); - if (ret != 1) - arg = -1; - val = TX_QUAD_CAL; - } else if (sysfs_streq(buf, "rf_dc_offs")) - val = RFDC_CAL; - else if (sysfs_streq(buf, "rssi_gain_step")) - ret = ad9361_rssi_gain_step_calib(phy); - else - break; - - if (val) - ret = ad9361_do_calib_run(phy, val, arg); - - break; - case AD9361_RSSI_GAIN_STEP_ERROR: - ret = sscanf(buf, "lna_error: %d %d %d %d " - "mixer_error: %d %d %d %d %d %d %d %d " - "%d %d %d %d %d %d %d %d " - "gain_step_calib_reg_val: %d %d %d %d %d", - &phy->pdata->rssi_lna_err_tbl[0], - &phy->pdata->rssi_lna_err_tbl[1], - &phy->pdata->rssi_lna_err_tbl[2], - &phy->pdata->rssi_lna_err_tbl[3], - &phy->pdata->rssi_mixer_err_tbl[0], - &phy->pdata->rssi_mixer_err_tbl[1], - &phy->pdata->rssi_mixer_err_tbl[2], - &phy->pdata->rssi_mixer_err_tbl[3], - &phy->pdata->rssi_mixer_err_tbl[4], - &phy->pdata->rssi_mixer_err_tbl[5], - &phy->pdata->rssi_mixer_err_tbl[6], - &phy->pdata->rssi_mixer_err_tbl[7], - &phy->pdata->rssi_mixer_err_tbl[8], - &phy->pdata->rssi_mixer_err_tbl[9], - &phy->pdata->rssi_mixer_err_tbl[10], - &phy->pdata->rssi_mixer_err_tbl[11], - &phy->pdata->rssi_mixer_err_tbl[12], - &phy->pdata->rssi_mixer_err_tbl[13], - &phy->pdata->rssi_mixer_err_tbl[14], - &phy->pdata->rssi_mixer_err_tbl[15], - &phy->pdata->rssi_gain_step_calib_reg_val[0], - &phy->pdata->rssi_gain_step_calib_reg_val[1], - &phy->pdata->rssi_gain_step_calib_reg_val[2], - &phy->pdata->rssi_gain_step_calib_reg_val[3], - &phy->pdata->rssi_gain_step_calib_reg_val[4]); - if (ret == 25) { - ad9361_ensm_force_state(phy, ENSM_STATE_ALERT); - ad9361_rssi_program_lna_gain(phy); - ad9361_rssi_write_err_tbl(phy); - ad9361_spi_write(phy->spi, REG_SETTLE_TIME, - ENABLE_DIG_GAIN_CORR | SETTLE_TIME(0x10)); - ad9361_ensm_restore_prev_state(phy); - ret = 0; - } else - ret = -EINVAL; - break; - case AD9361_BBDC_OFFS_ENABLE: - ret = strtobool(buf, &st->bbdc_track_en); - if (ret < 0) - break; - ret = ad9361_tracking_control(phy, st->bbdc_track_en, - st->rfdc_track_en, st->quad_track_en); - break; - case AD9361_RFDC_OFFS_ENABLE: - ret = strtobool(buf, &st->rfdc_track_en); - if (ret < 0) - break; - ret = ad9361_tracking_control(phy, st->bbdc_track_en, - st->rfdc_track_en, st->quad_track_en); - break; - case AD9361_QUAD_ENABLE: - ret = strtobool(buf, &st->quad_track_en); - if (ret < 0) - break; - ret = ad9361_tracking_control(phy, st->bbdc_track_en, - st->rfdc_track_en, st->quad_track_en); - break; - - case AD9361_DCXO_TUNE_COARSE: - ret = kstrtol(buf, 10, &readin); - if (ret) - break; - val = clamp_t(u32, (u32)readin, 0 , 63U); - if (val == phy->pdata->dcxo_coarse) - break; - - phy->pdata->dcxo_coarse = val; - ret = ad9361_set_dcxo_tune(phy, phy->pdata->dcxo_coarse, - phy->pdata->dcxo_fine); - break; - case AD9361_DCXO_TUNE_FINE: - ret = kstrtol(buf, 10, &readin); - if (ret) - break; - val = clamp_t(u32, (u32)readin, 0 , 8191U); - if (val == phy->pdata->dcxo_fine) - break; - - phy->pdata->dcxo_fine = val; - ret = ad9361_set_dcxo_tune(phy, phy->pdata->dcxo_coarse, - phy->pdata->dcxo_fine); - break; - case AD9361_XO_CORRECTION: - { - unsigned long rx, tx; - ret = kstrtol(buf, 10, &readin); - if (ret) - break; - if (readin == clk_get_rate(phy->clk_refin)) - break; - - rx = st->current_rx_lo_freq; - tx = st->current_tx_lo_freq; - - ret = clk_set_rate(phy->clk_refin, (unsigned long) readin); - if (ret < 0) - break; - - ad9361_set_trx_clock_chain(phy, st->current_rx_path_clks, st->current_tx_path_clks); - clk_set_rate(phy->clks[RX_RFPLL], rx); - clk_set_rate(phy->clks[TX_RFPLL], tx); - break; - } - case AD9361_MCS_SYNC: - ret = kstrtol(buf, 10, &readin); - if (ret) - break; - ret = ad9361_mcs(phy, readin); - break; - default: - ret = -EINVAL; - } - - mutex_unlock(&indio_dev->mlock); - - return ret ? ret : len; -} - -static ssize_t ad9361_phy_show(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - struct iio_dev *indio_dev = dev_to_iio_dev(dev); - struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); - struct ad9361_rf_phy *phy = iio_priv(indio_dev); - struct ad9361_rf_phy_state *st = phy->state; - int ret = 0; - unsigned long clk[6]; - u64 delta; - - mutex_lock(&indio_dev->mlock); - switch ((u32)this_attr->address) { - case AD9361_RF_RX_BANDWIDTH: - ret = sprintf(buf, "%u\n", st->current_rx_bw_Hz); - break; - case AD9361_RF_TX_BANDWIDTH: - ret = sprintf(buf, "%u\n", st->current_tx_bw_Hz); - break; - case AD9361_ENSM_MODE: - ret = ad9361_spi_readf(phy->spi, REG_STATE, ENSM_STATE(~0)); - if (ret < 0) - break; - if (ret >= ARRAY_SIZE(ad9361_ensm_states) || - ad9361_ensm_states[ret] == NULL) { - ret = -EIO; - break; - } - ret = sprintf(buf, "%s\n", ad9361_ensm_states[ret]); - break; - case AD9361_ENSM_MODE_AVAIL: - ret = sprintf(buf, "%s\n", phy->pdata->fdd ? - "sleep wait alert fdd pinctrl pinctrl_fdd_indep" : - "sleep wait alert rx tx pinctrl"); - break; - case AD9361_TX_PATH_FREQ: - ad9361_get_trx_clock_chain(phy, NULL, clk); - ret = sprintf(buf, "BBPLL:%lu DAC:%lu T2:%lu T1:%lu TF:%lu TXSAMP:%lu\n", - clk[0], clk[1], clk[2], clk[3], clk[4], clk[5]); - break; - case AD9361_RX_PATH_FREQ: - ad9361_get_trx_clock_chain(phy, clk, NULL); - ret = sprintf(buf, "BBPLL:%lu ADC:%lu R2:%lu R1:%lu RF:%lu RXSAMP:%lu\n", - clk[0], clk[1], clk[2], clk[3], clk[4], clk[5]); - break; - case AD9361_TRX_RATE_GOV: - ret = sprintf(buf, "%s\n", st->rate_governor ? - "nominal" : "highest_osr"); - break; - case AD9361_TRX_RATE_GOV_AVAIL: - ret = sprintf(buf, "%s\n", "nominal highest_osr"); - break; - case AD9361_FIR_RX_ENABLE: - ret = sprintf(buf, "%d\n", !st->bypass_rx_fir); - break; - case AD9361_FIR_TX_ENABLE: - ret = sprintf(buf, "%d\n", !st->bypass_tx_fir); - break; - case AD9361_FIR_TRX_ENABLE: - ret = sprintf(buf, "%d\n", !st->bypass_tx_fir && !st->bypass_rx_fir); - break; - case AD9361_CALIB_MODE_AVAIL: - ret = sprintf(buf, "auto manual manual_tx_quad tx_quad rf_dc_offs rssi_gain_step\n"); - break; - case AD9361_CALIB_MODE: - if (st->manual_tx_quad_cal_en) - ret = sprintf(buf, "manual_tx_quad %d\n", st->last_tx_quad_cal_phase); - else - ret = sprintf(buf, "%s\n", st->auto_cal_en ? "auto" : "manual"); - break; - case AD9361_RSSI_GAIN_STEP_ERROR: - ret = sprintf(buf, "lna_error: %d %d %d %d\n" - "mixer_error: %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d\n" - "gain_step_calib_reg_val: %d %d %d %d %d\n", - phy->pdata->rssi_lna_err_tbl[0], phy->pdata->rssi_lna_err_tbl[1], - phy->pdata->rssi_lna_err_tbl[2], phy->pdata->rssi_lna_err_tbl[3], - phy->pdata->rssi_mixer_err_tbl[0], phy->pdata->rssi_mixer_err_tbl[1], - phy->pdata->rssi_mixer_err_tbl[2], phy->pdata->rssi_mixer_err_tbl[3], - phy->pdata->rssi_mixer_err_tbl[4], phy->pdata->rssi_mixer_err_tbl[5], - phy->pdata->rssi_mixer_err_tbl[6], phy->pdata->rssi_mixer_err_tbl[7], - phy->pdata->rssi_mixer_err_tbl[8], phy->pdata->rssi_mixer_err_tbl[9], - phy->pdata->rssi_mixer_err_tbl[10], phy->pdata->rssi_mixer_err_tbl[11], - phy->pdata->rssi_mixer_err_tbl[12], phy->pdata->rssi_mixer_err_tbl[13], - phy->pdata->rssi_mixer_err_tbl[14], phy->pdata->rssi_mixer_err_tbl[15], - phy->pdata->rssi_gain_step_calib_reg_val[0], - phy->pdata->rssi_gain_step_calib_reg_val[1], - phy->pdata->rssi_gain_step_calib_reg_val[2], - phy->pdata->rssi_gain_step_calib_reg_val[3], - phy->pdata->rssi_gain_step_calib_reg_val[4]); - break; - case AD9361_BBDC_OFFS_ENABLE: - ret = sprintf(buf, "%d\n", st->bbdc_track_en); - break; - case AD9361_RFDC_OFFS_ENABLE: - ret = sprintf(buf, "%d\n", st->rfdc_track_en); - break; - case AD9361_QUAD_ENABLE: - ret = sprintf(buf, "%d\n", st->quad_track_en); - break; - case AD9361_DCXO_TUNE_COARSE: - if (phy->pdata->use_extclk) - ret = -ENODEV; - else - ret = sprintf(buf, "%d\n", phy->pdata->dcxo_coarse); - break; - case AD9361_DCXO_TUNE_FINE: - if (phy->pdata->use_extclk) - ret = -ENODEV; - else - ret = sprintf(buf, "%d\n", phy->pdata->dcxo_fine); - break; - case AD9361_DCXO_TUNE_COARSE_AVAILABLE: - ret = sprintf(buf, "%s\n", phy->pdata->use_extclk ? "[0 0 0]" : "[0 1 63]"); - break; - case AD9361_DCXO_TUNE_FINE_AVAILABLE: - ret = sprintf(buf, "%s\n", phy->pdata->use_extclk ? "[0 0 0]" : "[0 1 8191]"); - break; - case AD9361_XO_CORRECTION: - ret = sprintf(buf, "%lu\n", clk_get_rate(phy->clk_refin)); - break; - case AD9361_XO_CORRECTION_AVAILABLE: - clk[0] = clk_get_rate(phy->clk_refin); - delta = (u64) clk[0] * (u64) clk_get_accuracy(phy->clk_refin); - do_div(delta, 1000000000U); - ret = sprintf(buf, "[%llu 1 %llu]\n", clk[0] - delta, clk[0] + delta); - break; - default: - ret = -EINVAL; - } - mutex_unlock(&indio_dev->mlock); - - return ret; -} - -static IIO_DEVICE_ATTR(in_voltage_rf_bandwidth, S_IRUGO | S_IWUSR, - ad9361_phy_show, - ad9361_phy_store, - AD9361_RF_RX_BANDWIDTH); - -static IIO_CONST_ATTR(in_voltage_rf_bandwidth_available, "[200000 1 56000000]"); - -static IIO_DEVICE_ATTR(out_voltage_rf_bandwidth, S_IRUGO | S_IWUSR, - ad9361_phy_show, - ad9361_phy_store, - AD9361_RF_TX_BANDWIDTH); - -static IIO_CONST_ATTR(out_voltage_rf_bandwidth_available, "[200000 1 40000000]"); - -static IIO_DEVICE_ATTR(ensm_mode, S_IRUGO | S_IWUSR, - ad9361_phy_show, - ad9361_phy_store, - AD9361_ENSM_MODE); - -static IIO_DEVICE_ATTR(ensm_mode_available, S_IRUGO, - ad9361_phy_show, - NULL, - AD9361_ENSM_MODE_AVAIL); - -static IIO_DEVICE_ATTR(calib_mode, S_IRUGO | S_IWUSR, - ad9361_phy_show, - ad9361_phy_store, - AD9361_CALIB_MODE); - -static IIO_DEVICE_ATTR(calib_mode_available, S_IRUGO, - ad9361_phy_show, - NULL, - AD9361_CALIB_MODE_AVAIL); - -static IIO_DEVICE_ATTR(rssi_gain_step_error, S_IRUGO, - ad9361_phy_show, - ad9361_phy_store, - AD9361_RSSI_GAIN_STEP_ERROR); - -static IIO_DEVICE_ATTR(rx_path_rates, S_IRUGO, - ad9361_phy_show, - NULL, - AD9361_RX_PATH_FREQ); - -static IIO_DEVICE_ATTR(tx_path_rates, S_IRUGO, - ad9361_phy_show, - NULL, - AD9361_TX_PATH_FREQ); - -static IIO_DEVICE_ATTR(trx_rate_governor, S_IRUGO | S_IWUSR, - ad9361_phy_show, - ad9361_phy_store, - AD9361_TRX_RATE_GOV); - -static IIO_DEVICE_ATTR(trx_rate_governor_available, S_IRUGO, - ad9361_phy_show, - NULL, - AD9361_TRX_RATE_GOV_AVAIL); - -static IIO_DEVICE_ATTR(in_voltage_filter_fir_en, S_IRUGO | S_IWUSR, - ad9361_phy_show, - ad9361_phy_store, - AD9361_FIR_RX_ENABLE); - -static IIO_DEVICE_ATTR(out_voltage_filter_fir_en, S_IRUGO | S_IWUSR, - ad9361_phy_show, - ad9361_phy_store, - AD9361_FIR_TX_ENABLE); - -static IIO_DEVICE_ATTR(in_out_voltage_filter_fir_en, S_IRUGO | S_IWUSR, - ad9361_phy_show, - ad9361_phy_store, - AD9361_FIR_TRX_ENABLE); - -static IIO_DEVICE_ATTR(in_voltage_bb_dc_offset_tracking_en, S_IRUGO | S_IWUSR, - ad9361_phy_show, - ad9361_phy_store, - AD9361_BBDC_OFFS_ENABLE); - -static IIO_DEVICE_ATTR(in_voltage_rf_dc_offset_tracking_en, S_IRUGO | S_IWUSR, - ad9361_phy_show, - ad9361_phy_store, - AD9361_RFDC_OFFS_ENABLE); - -static IIO_DEVICE_ATTR(in_voltage_quadrature_tracking_en, S_IRUGO | S_IWUSR, - ad9361_phy_show, - ad9361_phy_store, - AD9361_QUAD_ENABLE); - -static IIO_DEVICE_ATTR(dcxo_tune_coarse, S_IRUGO | S_IWUSR, - ad9361_phy_show, - ad9361_phy_store, - AD9361_DCXO_TUNE_COARSE); - -static IIO_DEVICE_ATTR(dcxo_tune_coarse_available, S_IRUGO, - ad9361_phy_show, - NULL, - AD9361_DCXO_TUNE_COARSE_AVAILABLE); - -static IIO_DEVICE_ATTR(dcxo_tune_fine, S_IRUGO | S_IWUSR, - ad9361_phy_show, - ad9361_phy_store, - AD9361_DCXO_TUNE_FINE); - -static IIO_DEVICE_ATTR(dcxo_tune_fine_available, S_IRUGO, - ad9361_phy_show, - NULL, - AD9361_DCXO_TUNE_FINE_AVAILABLE); - -static IIO_DEVICE_ATTR(xo_correction, S_IRUGO | S_IWUSR, - ad9361_phy_show, - ad9361_phy_store, - AD9361_XO_CORRECTION); - -static IIO_DEVICE_ATTR(xo_correction_available, S_IRUGO, - ad9361_phy_show, - NULL, - AD9361_XO_CORRECTION_AVAILABLE); - -static IIO_DEVICE_ATTR(multichip_sync, S_IWUSR, - NULL, - ad9361_phy_store, - AD9361_MCS_SYNC); - -static struct attribute *ad9361_phy_attributes[] = { - &iio_dev_attr_in_voltage_filter_fir_en.dev_attr.attr, - &iio_dev_attr_out_voltage_filter_fir_en.dev_attr.attr, - &iio_dev_attr_in_out_voltage_filter_fir_en.dev_attr.attr, - &iio_dev_attr_in_voltage_rf_bandwidth.dev_attr.attr, - &iio_dev_attr_out_voltage_rf_bandwidth.dev_attr.attr, - &iio_dev_attr_ensm_mode.dev_attr.attr, - &iio_dev_attr_ensm_mode_available.dev_attr.attr, - &iio_dev_attr_calib_mode.dev_attr.attr, - &iio_dev_attr_calib_mode_available.dev_attr.attr, - &iio_dev_attr_rssi_gain_step_error.dev_attr.attr, - &iio_dev_attr_tx_path_rates.dev_attr.attr, - &iio_dev_attr_rx_path_rates.dev_attr.attr, - &iio_dev_attr_trx_rate_governor.dev_attr.attr, - &iio_dev_attr_trx_rate_governor_available.dev_attr.attr, - &iio_dev_attr_in_voltage_bb_dc_offset_tracking_en.dev_attr.attr, - &iio_dev_attr_in_voltage_rf_dc_offset_tracking_en.dev_attr.attr, - &iio_dev_attr_in_voltage_quadrature_tracking_en.dev_attr.attr, - &iio_dev_attr_dcxo_tune_coarse.dev_attr.attr, - &iio_dev_attr_dcxo_tune_fine.dev_attr.attr, - &iio_dev_attr_xo_correction.dev_attr.attr, - &iio_dev_attr_multichip_sync.dev_attr.attr, - &iio_const_attr_in_voltage_rf_bandwidth_available.dev_attr.attr, - &iio_const_attr_out_voltage_rf_bandwidth_available.dev_attr.attr, - &iio_dev_attr_dcxo_tune_coarse_available.dev_attr.attr, - &iio_dev_attr_dcxo_tune_fine_available.dev_attr.attr, - &iio_dev_attr_xo_correction_available.dev_attr.attr, - NULL, -}; - -static const struct attribute_group ad9361_phy_attribute_group = { - .attrs = ad9361_phy_attributes, -}; - - -static int ad9361_phy_reg_access(struct iio_dev *indio_dev, - u32 reg, u32 writeval, - u32 *readval) -{ - struct ad9361_rf_phy *phy = iio_priv(indio_dev); - int ret; - - mutex_lock(&indio_dev->mlock); - if (readval == NULL) { - ret = ad9361_spi_write(phy->spi, reg, writeval); - } else { - *readval = ad9361_spi_read(phy->spi, reg); - ret = 0; - } - mutex_unlock(&indio_dev->mlock); - - return ret; -} - -enum lo_ext_info { - LOEXT_FREQ, - LOEXT_FREQ_AVAILABLE, - LOEXT_STORE, - LOEXT_RECALL, - LOEXT_LOAD, - LOEXT_SAVE, - LOEXT_EXTERNAL, - LOEXT_PD, -}; - -static ssize_t ad9361_phy_lo_write(struct iio_dev *indio_dev, - uintptr_t private, - const struct iio_chan_spec *chan, - const char *buf, size_t len) -{ - struct ad9361_rf_phy *phy = iio_priv(indio_dev); - struct ad9361_rf_phy_state *st = phy->state; - u64 readin; - bool res; - int ret = 0; - - if (st->curr_ensm_state == ENSM_STATE_SLEEP) - return -EINVAL; - - if (private != LOEXT_LOAD) { - - } - - switch (private) { - case LOEXT_FREQ: - case LOEXT_STORE: - case LOEXT_RECALL: - case LOEXT_SAVE: - ret = kstrtoull(buf, 10, &readin); - if (ret) - return ret; - break; - case LOEXT_EXTERNAL: - case LOEXT_PD: - ret = strtobool(buf, &res); - if (ret < 0) - return ret; - break; - case LOEXT_LOAD: - break; - } - - mutex_lock(&indio_dev->mlock); - switch (private) { - case LOEXT_FREQ: - switch (chan->channel) { - case 0: - ret = clk_set_rate(phy->clks[RX_RFPLL], - ad9361_to_clk(readin)); - break; - case 1: - ret = clk_set_rate(phy->clks[TX_RFPLL], - ad9361_to_clk(readin)); - if (test_bit(0, &st->flags)) - wait_for_completion(&phy->complete); - - break; - default: - ret = -EINVAL; - } - break; - case LOEXT_STORE: - ret = ad9361_fastlock_store(phy, chan->channel == 1, readin); - break; - case LOEXT_RECALL: - ret = ad9361_fastlock_recall(phy, chan->channel == 1, readin); - break; - case LOEXT_LOAD: { - char *line, *ptr = (char*) buf; - u8 faslock_vals[16]; - u32 profile = 0, val, val2, i = 0; - - while ((line = strsep(&ptr, ","))) { - if (line >= buf + len) - break; - - ret = sscanf(line, "%u %u", &val, &val2); - if (ret == 1) { - faslock_vals[i++] = val; - continue; - } else if (ret == 2) { - profile = val; - faslock_vals[i++] = val2; - continue; - } - } - if (i == 16) - ret = ad9361_fastlock_load(phy, chan->channel == 1, - profile, faslock_vals); - else - ret = -EINVAL; - break; - } - case LOEXT_SAVE: - st->fastlock.save_profile = readin; - break; - case LOEXT_EXTERNAL: - switch(spi_get_device_id(phy->spi)->driver_data) { - case ID_AD9363A: - ret = -ENODEV; - break; - default: - switch (chan->channel) { - case 0: - if (phy->clk_ext_lo_rx) - ret = clk_set_parent(phy->clks[RX_RFPLL], - res ? phy->clk_ext_lo_rx : - phy->clks[RX_RFPLL_INT]); - else - ret = -ENODEV; - break; - - case 1: - if (phy->clk_ext_lo_tx) - ret = clk_set_parent(phy->clks[TX_RFPLL], - res ? phy->clk_ext_lo_tx : - phy->clks[TX_RFPLL_INT]); - else - ret = -ENODEV; - break; - - default: - ret = -EINVAL; - } - } - break; - case LOEXT_PD: - switch (chan->channel) { - case 0: - ret = ad9361_synth_lo_powerdown(phy, res ? LO_OFF : LO_ON, LO_DONTCARE); - break; - case 1: - ret = ad9361_synth_lo_powerdown(phy, LO_DONTCARE, res ? LO_OFF : LO_ON); - break; - } - - break; - } - mutex_unlock(&indio_dev->mlock); - - return ret ? ret : len; -} - -static ssize_t ad9361_phy_lo_read(struct iio_dev *indio_dev, - uintptr_t private, - const struct iio_chan_spec *chan, - char *buf) -{ - struct ad9361_rf_phy *phy = iio_priv(indio_dev); - struct ad9361_rf_phy_state *st = phy->state; - u64 val = 0; - size_t len; - int ret = 0; - - mutex_lock(&indio_dev->mlock); - switch (private) { - case LOEXT_FREQ: - val = ad9361_from_clk(clk_get_rate(phy->clks[chan->channel ? - TX_RFPLL : RX_RFPLL])); - break; - case LOEXT_SAVE: { - u8 faslock_vals[16]; - int i; - ret = ad9361_fastlock_save(phy, chan->channel == 1, - st->fastlock.save_profile, faslock_vals); - len = sprintf(buf, "%u ", st->fastlock.save_profile); - - for (i = 0; i < RX_FAST_LOCK_CONFIG_WORD_NUM; i++) - len += sprintf(buf + len, "%u%c", faslock_vals[i], - i == 15 ? '\n' : ','); - - mutex_unlock(&indio_dev->mlock); - return len; - } - case LOEXT_RECALL: - ret = st->fastlock.current_profile[chan->channel == 1]; - if (ret == 0) - ret = -EINVAL; - else - val = ret - 1; - break; - case LOEXT_EXTERNAL: - switch (chan->channel) { - case 0: - val = clk_get_parent(phy->clks[RX_RFPLL]) != phy->clks[RX_RFPLL_INT]; - break; - case 1: - val = clk_get_parent(phy->clks[TX_RFPLL]) != phy->clks[TX_RFPLL_INT]; - break; - default: - ret = -EINVAL; - } - break; - case LOEXT_PD: - val = !!(st->cached_synth_pd[chan->channel ? 0 : 1] & RX_LO_POWER_DOWN); - break; - case LOEXT_FREQ_AVAILABLE: { - u64 min, max; - - switch(spi_get_device_id(phy->spi)->driver_data) { - case ID_AD9363A: - min = AD9363A_MIN_CARRIER_FREQ_HZ; - max = AD9363A_MAX_CARRIER_FREQ_HZ; - break; - default: - min = chan->channel ? MIN_TX_CARRIER_FREQ_HZ : MIN_RX_CARRIER_FREQ_HZ; - max = MAX_CARRIER_FREQ_HZ; - break; - } - - len = sprintf(buf, "[%llu 1 %llu]\n", min, max); - mutex_unlock(&indio_dev->mlock); - return len; - } - default: - ret = 0; - - } - mutex_unlock(&indio_dev->mlock); - - return ret < 0 ? ret : sprintf(buf, "%llu\n", val); -} - -#define _AD9361_EXT_LO_INFO(_name, _ident) { \ - .name = _name, \ - .read = ad9361_phy_lo_read, \ - .write = ad9361_phy_lo_write, \ - .private = _ident, \ -} - -#define _AD9361_EXT_LO_INFO_RO(_name, _ident) { \ - .name = _name, \ - .read = ad9361_phy_lo_read, \ - .private = _ident, \ -} - -static const struct iio_chan_spec_ext_info ad9361_phy_ext_info[] = { - /* Ideally we use IIO_CHAN_INFO_FREQUENCY, but there are - * values > 2^32 in order to support the entire frequency range - * in Hz. Using scale is a bit ugly. - */ - _AD9361_EXT_LO_INFO("frequency", LOEXT_FREQ), - _AD9361_EXT_LO_INFO_RO("frequency_available", LOEXT_FREQ_AVAILABLE), - _AD9361_EXT_LO_INFO("fastlock_store", LOEXT_STORE), - _AD9361_EXT_LO_INFO("fastlock_recall", LOEXT_RECALL), - _AD9361_EXT_LO_INFO("fastlock_load", LOEXT_LOAD), - _AD9361_EXT_LO_INFO("fastlock_save", LOEXT_SAVE), - _AD9361_EXT_LO_INFO("external", LOEXT_EXTERNAL), - _AD9361_EXT_LO_INFO("powerdown", LOEXT_PD), - { }, -}; - -static int ad9361_set_agc_mode(struct iio_dev *indio_dev, - const struct iio_chan_spec *chan, u32 mode) -{ - struct ad9361_rf_phy *phy = iio_priv(indio_dev); - struct ad9361_rf_phy_state *st = phy->state; - struct rf_gain_ctrl gc = {0}; - - if (st->agc_mode[chan->channel] == mode) - return 0; - - gc.ant = ad9361_1rx1tx_channel_map(phy, false, chan->channel + 1); - gc.mode = st->agc_mode[chan->channel] = mode; - - return ad9361_set_gain_ctrl_mode(phy, &gc); -} - -static int ad9361_get_agc_mode(struct iio_dev *indio_dev, - const struct iio_chan_spec *chan) -{ - struct ad9361_rf_phy *phy = iio_priv(indio_dev); - struct ad9361_rf_phy_state *st = phy->state; - - return st->agc_mode[chan->channel]; -} - -static const char * const ad9361_agc_modes[] = - {"manual", "fast_attack", "slow_attack", "hybrid"}; - -static const struct iio_enum ad9361_agc_modes_available = { - .items = ad9361_agc_modes, - .num_items = ARRAY_SIZE(ad9361_agc_modes), - .get = ad9361_get_agc_mode, - .set = ad9361_set_agc_mode, - -}; - -static int ad9361_set_rf_port(struct iio_dev *indio_dev, - const struct iio_chan_spec *chan, u32 mode) -{ - struct ad9361_rf_phy *phy = iio_priv(indio_dev); - struct ad9361_rf_phy_state *st = phy->state; - - if (chan->output) { - if (phy->pdata->rf_tx_output_sel_lock && - mode != st->rf_tx_output_sel) - return -EINVAL; - return ad9361_set_tx_port(phy, mode); - } else { - if (phy->pdata->rf_rx_input_sel_lock && - mode != st->rf_rx_input_sel) - return -EINVAL; - return ad9361_set_rx_port(phy, mode); - } -} - -static int ad9361_get_rf_port(struct iio_dev *indio_dev, - const struct iio_chan_spec *chan) -{ - struct ad9361_rf_phy *phy = iio_priv(indio_dev); - struct ad9361_rf_phy_state *st = phy->state; - - if (chan->output) - return st->rf_tx_output_sel; - else - return st->rf_rx_input_sel; -} - -static const char * const ad9361_rf_rx_port[] = - {"A_BALANCED", "B_BALANCED", "C_BALANCED", - "A_N", "A_P", "B_N", "B_P", "C_N", "C_P", "TX_MONITOR1", - "TX_MONITOR2", "TX_MONITOR1_2"}; - -static const struct iio_enum ad9361_rf_rx_port_available = { - .items = ad9361_rf_rx_port, - .num_items = ARRAY_SIZE(ad9361_rf_rx_port), - .get = ad9361_get_rf_port, - .set = ad9361_set_rf_port, - -}; - -static const char * const ad9361_rf_tx_port[] = - {"A", "B"}; - -static const struct iio_enum ad9361_rf_tx_port_available = { - .items = ad9361_rf_tx_port, - .num_items = ARRAY_SIZE(ad9361_rf_tx_port), - .get = ad9361_get_rf_port, - .set = ad9361_set_rf_port, - -}; - -static ssize_t ad9361_phy_rx_write(struct iio_dev *indio_dev, - uintptr_t private, - const struct iio_chan_spec *chan, - const char *buf, size_t len) -{ -// struct ad9361_rf_phy *phy = iio_priv(indio_dev); - u64 readin; - int ret = 0; - - ret = kstrtoull(buf, 10, &readin); - if (ret) - return ret; - - mutex_lock(&indio_dev->mlock); - switch (chan->channel) { - case 0: - - break; - - case 1: - - break; - - default: - ret = -EINVAL; - ret = 0; - } - mutex_unlock(&indio_dev->mlock); - - return ret ? ret : len; -} - -static ssize_t ad9361_phy_rx_read(struct iio_dev *indio_dev, - uintptr_t private, - const struct iio_chan_spec *chan, - char *buf) -{ - struct ad9361_rf_phy *phy = iio_priv(indio_dev); - struct rf_rssi rssi = {0}; - int val; - int ret = 0; - - mutex_lock(&indio_dev->mlock); - - rssi.ant = ad9361_1rx1tx_channel_map(phy, false, chan->channel + 1); - rssi.duration = 1; - ret = ad9361_read_rssi(phy, &rssi); - val = rssi.symbol; - - mutex_unlock(&indio_dev->mlock); - - return ret < 0 ? ret : sprintf(buf, "%u.%02u dB\n", - val / rssi.multiplier, val % rssi.multiplier); -} - -#define _AD9361_EXT_RX_INFO(_name, _ident) { \ - .name = _name, \ - .read = ad9361_phy_rx_read, \ - .write = ad9361_phy_rx_write, \ - .private = _ident, \ -} - -static ssize_t ad9361_phy_tx_read(struct iio_dev *indio_dev, - uintptr_t private, - const struct iio_chan_spec *chan, - char *buf) -{ - struct ad9361_rf_phy *phy = iio_priv(indio_dev); - u8 reg_val_buf[3]; - u32 val; - int ret; - - mutex_lock(&indio_dev->mlock); - ret = ad9361_spi_readm(phy->spi, REG_TX_RSSI_LSB, - reg_val_buf, ARRAY_SIZE(reg_val_buf)); - - switch (chan->channel) { - case 0: - val = (reg_val_buf[2] << 1) | (reg_val_buf[0] & TX_RSSI_1); - break; - case 1: - val = (reg_val_buf[1] << 1) | ((reg_val_buf[0] & TX_RSSI_2) >> 1); - break; - default: - ret = -EINVAL; - } - mutex_unlock(&indio_dev->mlock); - - val *= RSSI_RESOLUTION; - - return ret < 0 ? ret : sprintf(buf, "%u.%02u dB\n", - val / RSSI_MULTIPLIER, val % RSSI_MULTIPLIER); -} - -#define _AD9361_EXT_TX_INFO(_name, _ident) { \ - .name = _name, \ - .read = ad9361_phy_tx_read, \ - .private = _ident, \ -} - -static const struct iio_chan_spec_ext_info ad9361_phy_rx_ext_info[] = { - /* Ideally we use IIO_CHAN_INFO_FREQUENCY, but there are - * values > 2^32 in order to support the entire frequency range - * in Hz. Using scale is a bit ugly. - */ - IIO_ENUM_AVAILABLE("gain_control_mode", &ad9361_agc_modes_available), - IIO_ENUM("gain_control_mode", false, &ad9361_agc_modes_available), - _AD9361_EXT_RX_INFO("rssi", 1), - IIO_ENUM_AVAILABLE("rf_port_select", &ad9361_rf_rx_port_available), - IIO_ENUM("rf_port_select", false, &ad9361_rf_rx_port_available), - { }, -}; - -static const struct iio_chan_spec_ext_info ad9361_phy_tx_ext_info[] = { - IIO_ENUM_AVAILABLE("rf_port_select", &ad9361_rf_tx_port_available), - IIO_ENUM("rf_port_select", false, &ad9361_rf_tx_port_available), - _AD9361_EXT_TX_INFO("rssi", 0), - { }, -}; - -static int ad9361_phy_read_raw(struct iio_dev *indio_dev, - struct iio_chan_spec const *chan, - int *val, - int *val2, - long m) -{ - struct ad9361_rf_phy *phy = iio_priv(indio_dev); - int ret; - - mutex_lock(&indio_dev->mlock); - switch (m) { - case IIO_CHAN_INFO_HARDWAREGAIN: - if (chan->output) { - ret = ad9361_get_tx_atten(phy, - ad9361_1rx1tx_channel_map(phy, true, - chan->channel + 1)); - if (ret < 0) { - ret = -EINVAL; - goto out_unlock; - } - - *val = -1 * (ret / 1000); - *val2 = (ret % 1000) * 1000; - if (!*val) - *val2 *= -1; - - } else { - struct rf_rx_gain rx_gain = {0}; - ret = ad9361_get_rx_gain(phy, ad9361_1rx1tx_channel_map(phy, - false, chan->channel + 1), &rx_gain); - *val = rx_gain.gain_db; - *val2 = 0; - } - ret = IIO_VAL_INT_PLUS_MICRO_DB; - break; - case IIO_CHAN_INFO_SAMP_FREQ: - if (chan->output) - *val = (int)clk_get_rate(phy->clks[TX_SAMPL_CLK]); - else - *val = (int)clk_get_rate(phy->clks[RX_SAMPL_CLK]); - ret = IIO_VAL_INT; - break; - case IIO_CHAN_INFO_PROCESSED: - *val = ad9361_get_temp(phy); - ret = IIO_VAL_INT; - break; - case IIO_CHAN_INFO_RAW: - if (chan->output) { - if (chan->channel == 2) - ret = ad9361_auxdac_get(phy, 1); - else if (chan->channel == 3) - ret = ad9361_auxdac_get(phy, 2); - else - ret = -EINVAL; - - if (ret >= 0) { - *val = ret; - ret = IIO_VAL_INT; - } - } else { - ret = ad9361_get_auxadc(phy); - if (ret >= 0) { - *val = ret; - ret = IIO_VAL_INT; - } - } - break; - case IIO_CHAN_INFO_OFFSET: - *val = 57; /* AuxADC */ - ret = IIO_VAL_INT; - break; - case IIO_CHAN_INFO_SCALE: - if (chan->output) { - *val = 1; /* AuxDAC */ - *val2 = 0; - } else { - *val = 0; /* AuxADC */ - *val2 = 305250; - } - - ret = IIO_VAL_INT_PLUS_MICRO; - break; - default: - ret = -EINVAL; - } - -out_unlock: - mutex_unlock(&indio_dev->mlock); - - return ret; -}; - -static int ad9361_phy_write_raw(struct iio_dev *indio_dev, - struct iio_chan_spec const *chan, - int val, - int val2, - long mask) -{ - struct ad9361_rf_phy *phy = iio_priv(indio_dev); - struct ad9361_rf_phy_state *st = phy->state; - u32 code; - int ret; - - if (st->curr_ensm_state == ENSM_STATE_SLEEP) - return -EINVAL; - - mutex_lock(&indio_dev->mlock); - switch (mask) { - case IIO_CHAN_INFO_HARDWAREGAIN: - if (chan->output) { - int ch; - if (val > 0 || (val == 0 && val2 > 0)) { - ret = -EINVAL; - goto out; - } - - code = ((abs(val) * 1000) + (abs(val2) / 1000)); - - - ch = ad9361_1rx1tx_channel_map(phy, true, chan->channel); - ret = ad9361_set_tx_atten(phy, code, ch == 0, ch == 1, - !phy->pdata->update_tx_gain_via_alert); - } else { - struct rf_rx_gain rx_gain = {0}; - rx_gain.gain_db = val; - ret = ad9361_set_rx_gain(phy, - ad9361_1rx1tx_channel_map(phy, false, - chan->channel + 1), &rx_gain); - } - break; - - case IIO_CHAN_INFO_SAMP_FREQ: - if (st->rx_eq_2tx && (chan->output == 0)) { - ret = 0; - break; - } - - ret = ad9361_set_trx_clock_chain_freq(phy, val); - if (ret < 0) - goto out; - ret = ad9361_update_rf_bandwidth(phy, st->current_rx_bw_Hz, - st->current_tx_bw_Hz); - break; - - case IIO_CHAN_INFO_RAW: - if (chan->output) { - if (chan->channel == 2) - ret = ad9361_auxdac_set(phy, 1, val); - else if (chan->channel == 3) - ret = ad9361_auxdac_set(phy, 2, val); - else - ret = -EINVAL; - - } else { - ret = -EINVAL; - } - break; - default: - ret = -EINVAL; - } -out: - mutex_unlock(&indio_dev->mlock); - - return ret; -} - -static int ad9361_phy_read_avail(struct iio_dev *indio_dev, - struct iio_chan_spec const *chan, - const int **vals, int *type, int *length, - long mask) -{ - struct ad9361_rf_phy *phy = iio_priv(indio_dev); - struct ad9361_rf_phy_state *st = phy->state; - - switch (mask) { - case IIO_CHAN_INFO_HARDWAREGAIN: - if (chan->output) { - static const int tx_hw_gain[] = { - 89, -750000, 0, 250000, 0, 0 - }; - *vals = tx_hw_gain; - *type = IIO_VAL_INT_PLUS_MICRO; - return IIO_AVAIL_RANGE; - } else { - st->rx_gain_avail[0] = phy->gt_info[ad9361_gt(phy)].abs_gain_tbl[0]; - st->rx_gain_avail[1] = 1; - st->rx_gain_avail[2] = phy->gt_info[ad9361_gt(phy)].abs_gain_tbl[phy->gt_info[ad9361_gt(phy)].max_index - 1]; - *vals = st->rx_gain_avail; - *type = IIO_VAL_INT; - return IIO_AVAIL_RANGE; - } - break; - case IIO_CHAN_INFO_SAMP_FREQ: { - int int_dec, max; - - if (phy->pdata->port_ctrl.pp_conf[2] & LVDS_MODE) - max = 61440000U; - else - max = 61440000U / (phy->pdata->rx2tx2 ? 2 : 1); - - if (chan->output) { - if (st->bypass_tx_fir) - int_dec = 1; - else - int_dec = st->tx_fir_int; - - if (int_dec == 4) - max = MAX_TX_HB1 / 4; - - st->tx_sampl_freq_avail[0] = MIN_ADC_CLK / (12 * int_dec); - st->tx_sampl_freq_avail[1] = 1; - st->tx_sampl_freq_avail[2] = max; - - *vals = st->tx_sampl_freq_avail; - *type = IIO_VAL_INT; - return IIO_AVAIL_RANGE; - } else { - if (st->bypass_rx_fir) - int_dec = 1; - else - int_dec = st->rx_fir_dec; - - if (int_dec == 4) - max = MAX_RX_HB1 / 4; - - st->rx_sampl_freq_avail[0] = MIN_ADC_CLK / (12 * int_dec); - st->rx_sampl_freq_avail[1] = 1; - st->rx_sampl_freq_avail[2] = max; - - *vals = st->rx_sampl_freq_avail; - *type = IIO_VAL_INT; - return IIO_AVAIL_RANGE; - } - break; - } - } - - return -EINVAL; -} - -static const struct iio_chan_spec ad9361_phy_chan[] = { -{ - .type = IIO_TEMP, - .indexed = 1, - .channel = 0, - .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), -}, { /* RX LO */ - .type = IIO_ALTVOLTAGE, - .indexed = 1, - .output = 1, - .channel = 0, - .extend_name = "RX_LO", - .ext_info = ad9361_phy_ext_info, -}, { /* TX LO */ - .type = IIO_ALTVOLTAGE, - .indexed = 1, - .output = 1, - .channel = 1, - .extend_name = "TX_LO", - .ext_info = ad9361_phy_ext_info, -}, { /* TX1 */ - .type = IIO_VOLTAGE, - .indexed = 1, - .output = 1, - .channel = 0, - .info_mask_separate = BIT(IIO_CHAN_INFO_HARDWAREGAIN), - .info_mask_separate_available = BIT(IIO_CHAN_INFO_HARDWAREGAIN), - .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ), - .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SAMP_FREQ), - .ext_info = ad9361_phy_tx_ext_info, -}, { /* RX1 */ - .type = IIO_VOLTAGE, - .indexed = 1, - .channel = 0, - .info_mask_separate = BIT(IIO_CHAN_INFO_HARDWAREGAIN), - .info_mask_separate_available = BIT(IIO_CHAN_INFO_HARDWAREGAIN), - .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ), - .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SAMP_FREQ), - .ext_info = ad9361_phy_rx_ext_info, -}, { /* AUXDAC1 */ - .type = IIO_VOLTAGE, - .indexed = 1, - .output = 1, - .channel = 2, - .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), -}, { /* AUXDAC2 */ - .type = IIO_VOLTAGE, - .indexed = 1, - .output = 1, - .channel = 3, - .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), -}, { /* AUXADC1 */ - .type = IIO_VOLTAGE, - .indexed = 1, - .channel = 2, - .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | - BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_OFFSET), -}, { /* TX2 */ - .type = IIO_VOLTAGE, - .indexed = 1, - .output = 1, - .channel = 1, - .info_mask_separate = BIT(IIO_CHAN_INFO_HARDWAREGAIN), - .info_mask_separate_available = BIT(IIO_CHAN_INFO_HARDWAREGAIN), - .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ), - .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SAMP_FREQ), - .ext_info = ad9361_phy_tx_ext_info, -}, { /* RX2 */ - .type = IIO_VOLTAGE, - .indexed = 1, - .channel = 1, - .info_mask_separate = BIT(IIO_CHAN_INFO_HARDWAREGAIN), - .info_mask_separate_available = BIT(IIO_CHAN_INFO_HARDWAREGAIN), - .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ), - .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SAMP_FREQ), - .ext_info = ad9361_phy_rx_ext_info, -}}; - -static const struct iio_info ad9361_phy_info = { - .read_raw = &ad9361_phy_read_raw, - .write_raw = &ad9361_phy_write_raw, - .read_avail = ad9361_phy_read_avail, - .debugfs_reg_access = &ad9361_phy_reg_access, - .attrs = &ad9361_phy_attribute_group, - .driver_module = THIS_MODULE, -}; - -#ifdef CONFIG_OF -static ssize_t ad9361_debugfs_read(struct file *file, char __user *userbuf, - size_t count, loff_t *ppos) -{ - struct ad9361_debugfs_entry *entry = file->private_data; - struct ad9361_rf_phy *phy = entry->phy; - char buf[700]; - u32 val = 0; - ssize_t len = 0; - int ret; - - if (entry->out_value) { - switch (entry->size){ - case 1: - val = *(u8*)entry->out_value; - break; - case 2: - val = *(u16*)entry->out_value; - break; - case 4: - val = *(u32*)entry->out_value; - break; - case 5: - val = *(bool*)entry->out_value; - break; - default: - ret = -EINVAL; - } - - } else if (entry->cmd == DBGFS_RXGAIN_1 || entry->cmd == DBGFS_RXGAIN_2) { - struct rf_rx_gain rx_gain = {0}; - mutex_lock(&phy->indio_dev->mlock); - ret = ad9361_get_rx_gain(phy, (entry->cmd == DBGFS_RXGAIN_1) ? - 1 : 2, &rx_gain); - mutex_unlock(&phy->indio_dev->mlock); - if (ret < 0) - return ret; - - len = snprintf(buf, sizeof(buf), "%d %u %u %u %u %u %u %u\n", - rx_gain.gain_db, - rx_gain.fgt_lmt_index, - rx_gain.digital_gain, - rx_gain.lmt_gain, - rx_gain.lpf_gain, - rx_gain.lna_index, - rx_gain.tia_index, - rx_gain.mixer_index); - - } else if (entry->cmd == DBGFS_BIST_DT_ANALYSIS) { - if (entry->val) - len = ad9361_dig_interface_timing_analysis(phy, - buf, sizeof(buf)); - - entry->val = 0; - } else if (entry->cmd) { - val = entry->val; - } else - return -EFAULT; - - if (!len) - len = snprintf(buf, sizeof(buf), "%u\n", val); - - return simple_read_from_buffer(userbuf, count, ppos, buf, len); -} - -static ssize_t ad9361_debugfs_write(struct file *file, - const char __user *userbuf, size_t count, loff_t *ppos) -{ - struct ad9361_debugfs_entry *entry = file->private_data; - struct ad9361_rf_phy *phy = entry->phy; - struct gpo_control *ctrl = &phy->pdata->gpo_ctrl; - u32 val, val2, val3, val4, mask; - char buf[80]; - int ret; - - count = min_t(size_t, count, (sizeof(buf)-1)); - if (copy_from_user(buf, userbuf, count)) - return -EFAULT; - - buf[count] = 0; - - ret = sscanf(buf, "%i %i %i %i", &val, &val2, &val3, &val4); - if (ret < 1) - return -EINVAL; - - - switch (entry->cmd) { - case DBGFS_INIT: - if (!(ret == 1 && val == 1)) - return -EINVAL; - mutex_lock(&phy->indio_dev->mlock); - clk_set_rate(phy->clks[TX_SAMPL_CLK], 1); - clk_set_parent(phy->clks[RX_RFPLL], phy->clk_ext_lo_rx); - clk_set_parent(phy->clks[TX_RFPLL], phy->clk_ext_lo_tx); - ad9361_reset(phy); - ad9361_clks_resync(phy); - ad9361_clks_disable(phy); - ad9361_clear_state(phy); - ret = ad9361_setup(phy); - mutex_unlock(&phy->indio_dev->mlock); - if (ret < 0) - return ret; - - return count; - case DBGFS_LOOPBACK: - if (ret != 1) - return -EINVAL; - mutex_lock(&phy->indio_dev->mlock); - ret = ad9361_bist_loopback(phy, val); - mutex_unlock(&phy->indio_dev->mlock); - if (ret < 0) - return ret; - - entry->val = val; - return count; - case DBGFS_BIST_PRBS: - if (ret != 1) - return -EINVAL; - mutex_lock(&phy->indio_dev->mlock); - ret = ad9361_bist_prbs(phy, val); - mutex_unlock(&phy->indio_dev->mlock); - if (ret < 0) - return ret; - - entry->val = val; - return count; - case DBGFS_BIST_TONE: - if (ret != 4) - return -EINVAL; - mutex_lock(&phy->indio_dev->mlock); - ret = ad9361_bist_tone(phy, val, val2, val3, val4); - mutex_unlock(&phy->indio_dev->mlock); - if (ret < 0) - return ret; - - entry->val = val; - return count; - case DBGFS_MCS: - if (ret != 1) - return -EINVAL; - mutex_lock(&phy->indio_dev->mlock); - ret = ad9361_mcs(phy, val); - mutex_unlock(&phy->indio_dev->mlock); - if (ret < 0) - return ret; - - entry->val = val; - return count; - case DBGFS_CAL_SW_CTRL: - if (ret != 1) - return -EINVAL; - - if (phy->pdata->cal_sw1_gpio && - phy->pdata->cal_sw2_gpio) { - mutex_lock(&phy->indio_dev->mlock); - gpiod_set_value(phy->pdata->cal_sw1_gpio, !!(val & BIT(0))); - gpiod_set_value(phy->pdata->cal_sw2_gpio, !!(val & BIT(1))); - mutex_unlock(&phy->indio_dev->mlock); - } else { - return -ENODEV; - } - - entry->val = val; - return count; - case DBGFS_DIGITAL_TUNE: - if (ret != 2) - return -EINVAL; - mutex_lock(&phy->indio_dev->mlock); - ret = ad9361_dig_tune(phy, val, val2); - mutex_unlock(&phy->indio_dev->mlock); - if (ret < 0) - return ret; - - entry->val = val; - return count; - case DBGFS_BIST_DT_ANALYSIS: - entry->val = val; - return count; - case DBGFS_GPO_SET: - if (ret != 2) - return -EINVAL; - - if (!ctrl->gpo_manual_mode_en) { - dev_warn(&phy->spi->dev, "GPO manual mode not enabled!"); - return -EINVAL; - } - - switch (val) { - case 0: - case 1: - case 2: - case 3: - mask = BIT(val); - if (val2) - val3 = mask; - else - val3 = 0; - break; - case 0xF: - mask = 0xF; - val3 = val2 & 0xF; - break; - default: - return -EINVAL; - } - - mutex_lock(&phy->indio_dev->mlock); - ctrl->gpo_manual_mode_enable_mask &= ~mask; - ctrl->gpo_manual_mode_enable_mask |= val3; - - ret = ad9361_spi_write(phy->spi, REG_GPO_FORCE_AND_INIT, - GPO_MANUAL_CTRL(ctrl->gpo_manual_mode_enable_mask) | - GPO_INIT_STATE(ctrl->gpo0_inactive_state_high_en | - (ctrl->gpo1_inactive_state_high_en << 1) | - (ctrl->gpo2_inactive_state_high_en << 2) | - (ctrl->gpo3_inactive_state_high_en << 3))); - - /* - * GPO manual mode conflicts with automatic ENSM slave - * and eLNA mode - */ - - val3 = ad9361_spi_read(phy->spi, REG_EXTERNAL_LNA_CTRL); - if (!(val3 & GPO_MANUAL_SELECT)) - ad9361_spi_write(phy->spi, REG_EXTERNAL_LNA_CTRL, - val3 | GPO_MANUAL_SELECT); - mutex_unlock(&phy->indio_dev->mlock); - if (ret < 0) - return ret; - - entry->val = val; - return count; - default: - break; - } - - - if (entry->out_value) { - switch (entry->size){ - case 1: - *(u8*)entry->out_value = val; - break; - case 2: - *(u16*)entry->out_value = val; - break; - case 4: - *(u32*)entry->out_value = val; - break; - case 5: - *(bool*)entry->out_value = val; - break; - default: - ret = -EINVAL; - } - } - - return count; -} - -static const struct file_operations ad9361_debugfs_reg_fops = { - .open = simple_open, - .read = ad9361_debugfs_read, - .write = ad9361_debugfs_write, -}; - -static void ad9361_add_debugfs_entry(struct ad9361_rf_phy *phy, - const char *propname, unsigned int cmd) -{ - unsigned int i = phy->ad9361_debugfs_entry_index; - - if (WARN_ON(i >= ARRAY_SIZE(phy->debugfs_entry))) - return; - - phy->debugfs_entry[i].phy = phy; - phy->debugfs_entry[i].propname = propname; - phy->debugfs_entry[i].cmd = cmd; - - phy->ad9361_debugfs_entry_index++; -} - -static int ad9361_register_debugfs(struct iio_dev *indio_dev) -{ - struct ad9361_rf_phy *phy = iio_priv(indio_dev); - struct dentry *d; - int i; - - if (!iio_get_debugfs_dentry(indio_dev)) - return -ENODEV; - - ad9361_add_debugfs_entry(phy, "initialize", DBGFS_INIT); - ad9361_add_debugfs_entry(phy, "loopback", DBGFS_LOOPBACK); - ad9361_add_debugfs_entry(phy, "bist_prbs", DBGFS_BIST_PRBS); - ad9361_add_debugfs_entry(phy, "bist_tone", DBGFS_BIST_TONE); - ad9361_add_debugfs_entry(phy, "gpo_set", DBGFS_GPO_SET); - ad9361_add_debugfs_entry(phy, "bist_timing_analysis", - DBGFS_BIST_DT_ANALYSIS); - ad9361_add_debugfs_entry(phy, "gaininfo_rx1", DBGFS_RXGAIN_1); - ad9361_add_debugfs_entry(phy, "gaininfo_rx2", DBGFS_RXGAIN_2); - ad9361_add_debugfs_entry(phy, "multichip_sync", DBGFS_MCS); - ad9361_add_debugfs_entry(phy, "calibration_switch_control", - DBGFS_CAL_SW_CTRL); - ad9361_add_debugfs_entry(phy, "digital_tune", DBGFS_DIGITAL_TUNE); - - for (i = 0; i < phy->ad9361_debugfs_entry_index; i++) - d = debugfs_create_file( - phy->debugfs_entry[i].propname, 0644, - iio_get_debugfs_dentry(indio_dev), - &phy->debugfs_entry[i], - &ad9361_debugfs_reg_fops); - return 0; -} - -struct ad9361_dport_config { - u8 reg; - u8 offset; - char name[40]; -}; - -static const struct ad9361_dport_config ad9361_dport_config[] = { - {1, 7, "adi,pp-tx-swap-enable"}, - {1, 6, "adi,pp-rx-swap-enable"}, - {1, 5, "adi,tx-channel-swap-enable"}, - {1, 4, "adi,rx-channel-swap-enable"}, - {1, 3, "adi,rx-frame-pulse-mode-enable"}, - {1, 2, "adi,2t2r-timing-enable"}, - {1, 1, "adi,invert-data-bus-enable"}, - {1, 0, "adi,invert-data-clk-enable"}, - {2, 7, "adi,fdd-alt-word-order-enable"}, - {2, 2, "adi,invert-rx-frame-enable"}, - {3, 7, "adi,fdd-rx-rate-2tx-enable"}, - {3, 6, "adi,swap-ports-enable"}, - {3, 5, "adi,single-data-rate-enable"}, - {3, 4, "adi,lvds-mode-enable"}, - {3, 3, "adi,half-duplex-mode-enable"}, - {3, 2, "adi,single-port-mode-enable"}, - {3, 1, "adi,full-port-enable"}, - {3, 0, "adi,full-duplex-swap-bits-enable"}, -}; - - - -static int __ad9361_of_get_u32(struct iio_dev *indio_dev, - struct device_node *np, const char *propname, - u32 defval, void *out_value, u32 size) -{ - struct ad9361_rf_phy *phy = iio_priv(indio_dev); - u32 tmp = defval; - int ret; - - ret = of_property_read_u32(np, propname, &tmp); - - if (out_value) { - switch (size){ - case 1: - *(u8*)out_value = tmp; - break; - case 2: - *(u16*)out_value = tmp; - break; - case 4: - *(u32*)out_value = tmp; - break; - default: - ret = -EINVAL; - } - } - - if (WARN_ON(phy->ad9361_debugfs_entry_index >= - ARRAY_SIZE(phy->debugfs_entry))) - return ret; - - phy->debugfs_entry[phy->ad9361_debugfs_entry_index++] = - (struct ad9361_debugfs_entry) { - .out_value = out_value, - .propname = propname, - .size = size, - .phy = phy, - }; - - return ret; -} -#define ad9361_of_get_u32(iodev, dnp, name, def, outp) \ - __ad9361_of_get_u32(iodev, dnp, name, def, outp, sizeof(*outp)) - -static void ad9361_of_get_bool(struct iio_dev *indio_dev, struct device_node *np, - const char *propname, bool *out_value) -{ - struct ad9361_rf_phy *phy = iio_priv(indio_dev); - *out_value = of_property_read_bool(np, propname); - - if (WARN_ON(phy->ad9361_debugfs_entry_index >= - ARRAY_SIZE(phy->debugfs_entry))) - return; - - phy->debugfs_entry[phy->ad9361_debugfs_entry_index++] = - (struct ad9361_debugfs_entry) { - .out_value = out_value, - .propname = propname, - .phy = phy, - .size = 5, - }; - -} - -static struct ad9361_phy_platform_data - *ad9361_phy_parse_dt(struct iio_dev *iodev, struct device *dev) -{ - struct device_node *np = dev->of_node; - struct ad9361_rf_phy *phy = iio_priv(iodev); - struct ad9361_rf_phy_state *st = phy->state; - struct ad9361_phy_platform_data *pdata; - u32 tx_path_clks[NUM_TX_CLOCKS]; - u32 rx_path_clks[NUM_RX_CLOCKS]; - u32 tmp; - u64 tmpl; - u32 array[6] = {0}; - int ret, i; - - pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); - if (!pdata) { - dev_err(dev, "could not allocate memory for platform data\n"); - return NULL; - } - - ad9361_of_get_bool(iodev, np, "adi,frequency-division-duplex-mode-enable", - &pdata->fdd); - - ad9361_of_get_bool(iodev, np, "adi,frequency-division-duplex-independent-mode-enable", - &pdata->fdd_independent_mode); - - ad9361_of_get_bool(iodev, np, "adi,ensm-enable-pin-pulse-mode-enable", - &pdata->ensm_pin_pulse_mode); - - ad9361_of_get_bool(iodev, np, "adi,ensm-enable-txnrx-control-enable", - &pdata->ensm_pin_ctrl); - - ad9361_of_get_bool(iodev, np, "adi,debug-mode-enable", - &pdata->debug_mode); - - ad9361_of_get_bool(iodev, np, "adi,tdd-use-dual-synth-mode-enable", - &pdata->tdd_use_dual_synth); - - ad9361_of_get_bool(iodev, np, "adi,tdd-skip-vco-cal-enable", - &pdata->tdd_skip_vco_cal); - - ad9361_of_get_u32(iodev, np, "adi,tx-fastlock-delay-ns", 0, - &pdata->rx_fastlock_delay_ns); - - ad9361_of_get_u32(iodev, np, "adi,rx-fastlock-delay-ns", 0, - &pdata->tx_fastlock_delay_ns); - - ad9361_of_get_bool(iodev, np, "adi,rx-fastlock-pincontrol-enable", - &pdata->trx_fastlock_pinctrl_en[0]); - - ad9361_of_get_bool(iodev, np, "adi,tx-fastlock-pincontrol-enable", - &pdata->trx_fastlock_pinctrl_en[1]); - - for (i = 0; i < ARRAY_SIZE(ad9361_dport_config); i++) - pdata->port_ctrl.pp_conf[ad9361_dport_config[i].reg - 1] |= - (of_property_read_bool(np, ad9361_dport_config[i].name) - << ad9361_dport_config[i].offset); - - tmp = 0; - of_property_read_u32(np, "adi,delay-rx-data", &tmp); - pdata->port_ctrl.pp_conf[1] |= (tmp & 0x3); - - tmp = 0; - of_property_read_u32(np, "adi,rx-data-clock-delay", &tmp); - pdata->port_ctrl.rx_clk_data_delay = DATA_CLK_DELAY(tmp); - tmp = 0; - of_property_read_u32(np, "adi,rx-data-delay", &tmp); - pdata->port_ctrl.rx_clk_data_delay |= RX_DATA_DELAY(tmp); - - tmp = 0; - of_property_read_u32(np, "adi,tx-fb-clock-delay", &tmp); - pdata->port_ctrl.tx_clk_data_delay = FB_CLK_DELAY(tmp); - tmp = 0; - of_property_read_u32(np, "adi,tx-data-delay", &tmp); - pdata->port_ctrl.tx_clk_data_delay |= TX_DATA_DELAY(tmp); - - tmp = 75; - of_property_read_u32(np, "adi,lvds-bias-mV", &tmp); - pdata->port_ctrl.lvds_bias_ctrl = ((tmp - 75) / 75) & 0x7; - pdata->port_ctrl.lvds_bias_ctrl |= (of_property_read_bool(np, - "adi,lvds-rx-onchip-termination-enable") << 5); - - tmp = 0xFF; - of_property_read_u32(np, "adi,lvds-invert1-control", &tmp); - pdata->port_ctrl.lvds_invert[0] = tmp; - - tmp = 0x0F; - of_property_read_u32(np, "adi,lvds-invert2-control", &tmp); - pdata->port_ctrl.lvds_invert[1] = tmp; - - ad9361_of_get_u32(iodev, np, "adi,digital-interface-tune-skip-mode", 0, - &pdata->dig_interface_tune_skipmode); - - ad9361_of_get_bool(iodev, np, "adi,digital-interface-tune-fir-disable", - &pdata->dig_interface_tune_fir_disable); - - ad9361_of_get_bool(iodev, np, "adi,2rx-2tx-mode-enable", &pdata->rx2tx2); - - ad9361_of_get_u32(iodev, np, "adi,1rx-1tx-mode-use-rx-num", 1, - &pdata->rx1tx1_mode_use_rx_num); - - ad9361_of_get_u32(iodev, np, "adi,1rx-1tx-mode-use-tx-num", 1, - &pdata->rx1tx1_mode_use_tx_num); - - ad9361_of_get_bool(iodev, np, "adi,split-gain-table-mode-enable", - &pdata->split_gt); - - ad9361_of_get_u32(iodev, np, "adi,rx-rf-port-input-select", 0, - &st->rf_rx_input_sel); - ad9361_of_get_u32(iodev, np, "adi,tx-rf-port-input-select", 0, - &st->rf_tx_output_sel); - - ad9361_of_get_bool(iodev, np, "adi,rx-rf-port-input-select-lock-enable", - &pdata->rf_rx_input_sel_lock); - - ad9361_of_get_bool(iodev, np, "adi,tx-rf-port-input-select-lock-enable", - &pdata->rf_tx_output_sel_lock); - - ad9361_of_get_bool(iodev, np, "adi,rx1-rx2-phase-inversion-enable", - &pdata->rx1rx2_phase_inversion_en); - - ad9361_of_get_u32(iodev, np, "adi,trx-synthesizer-target-fref-overwrite-hz", - MAX_SYNTH_FREF, &pdata->trx_synth_max_fref); - - ad9361_of_get_bool(iodev, np, "adi,tx-lo-powerdown-managed-enable", - &pdata->lo_powerdown_managed_en); - - tmpl = 2400000000ULL; - of_property_read_u64(np, "adi,rx-synthesizer-frequency-hz", &tmpl); - pdata->rx_synth_freq = tmpl; - - tmpl = 2440000000ULL; - of_property_read_u64(np, "adi,tx-synthesizer-frequency-hz", &tmpl); - pdata->tx_synth_freq = tmpl; - - ret = of_property_read_u32_array(np, "adi,dcxo-coarse-and-fine-tune", - array, 2); - - pdata->dcxo_coarse = (ret < 0) ? 8 : array[0]; - pdata->dcxo_fine = (ret < 0) ? 5920 : array[1]; - - - switch(spi_get_device_id(phy->spi)->driver_data) { - case ID_AD9363A: - pdata->use_extclk = true; - pdata->use_ext_tx_lo = false; - pdata->use_ext_rx_lo = false; - break; - default: - ad9361_of_get_bool(iodev, np, "adi,xo-disable-use-ext-refclk-enable", - &pdata->use_extclk); - ad9361_of_get_bool(iodev, np, "adi,external-tx-lo-enable", - &pdata->use_ext_tx_lo); - ad9361_of_get_bool(iodev, np, "adi,external-rx-lo-enable", - &pdata->use_ext_rx_lo); - } - - ad9361_of_get_u32(iodev, np, "adi,clk-output-mode-select", CLKOUT_DISABLE, - &pdata->ad9361_clkout_mode); - - /* - * adi,dc-offset-tracking-update-event-mask: - * BIT(0) Apply a new tracking word when a gain change occurs. - * BIT(1) Apply a new tracking word when the received signal is - * less than the SOI Threshold. - * BIT(2) Apply a new tracking word after the device exits the - * receive state. - */ - - ad9361_of_get_u32(iodev, np, "adi,dc-offset-tracking-update-event-mask", 5, - &pdata->dc_offset_update_events); - - ad9361_of_get_u32(iodev, np, "adi,dc-offset-attenuation-high-range", 6, - &pdata->dc_offset_attenuation_high); - - ad9361_of_get_u32(iodev, np, "adi,dc-offset-attenuation-low-range", 5, - &pdata->dc_offset_attenuation_low); - - ad9361_of_get_u32(iodev, np, "adi,dc-offset-count-high-range", 0x28, - &pdata->rf_dc_offset_count_high); - - ad9361_of_get_u32(iodev, np, "adi,dc-offset-count-low-range", 0x32, - &pdata->rf_dc_offset_count_low); - - ad9361_of_get_bool(iodev, np, "adi,qec-tracking-slow-mode-enable", - &pdata->qec_tracking_slow_mode_en); - - ret = of_property_read_u32_array(np, "adi,rx-path-clock-frequencies", - rx_path_clks, ARRAY_SIZE(rx_path_clks)); - if (ret < 0) - return NULL; - - for (i = 0; i < ARRAY_SIZE(rx_path_clks); i++) - pdata->rx_path_clks[i] = rx_path_clks[i]; - - ret = of_property_read_u32_array(np, "adi,tx-path-clock-frequencies", - tx_path_clks, ARRAY_SIZE(tx_path_clks)); - if (ret < 0) - return NULL; - - for (i = 0; i < ARRAY_SIZE(tx_path_clks); i++) - pdata->tx_path_clks[i] = tx_path_clks[i]; - - ad9361_of_get_u32(iodev, np, "adi,rf-rx-bandwidth-hz", 18000000UL, - &pdata->rf_rx_bandwidth_Hz); - ad9361_of_get_u32(iodev, np, "adi,rf-tx-bandwidth-hz", 18000000UL, - &pdata->rf_tx_bandwidth_Hz); - ad9361_of_get_u32(iodev, np, "adi,tx-attenuation-mdB", 10000, &pdata->tx_atten); - - ad9361_of_get_bool(iodev, np, "adi,update-tx-gain-in-alert-enable", - &pdata->update_tx_gain_via_alert); - - /* Gain Control */ - - ad9361_of_get_u32(iodev, np, "adi,gc-rx1-mode", 0, &pdata->gain_ctrl.rx1_mode); - ad9361_of_get_u32(iodev, np, "adi,gc-rx2-mode", 0, &pdata->gain_ctrl.rx2_mode); - ad9361_of_get_u32(iodev, np, "adi,gc-adc-ovr-sample-size", 4, - &pdata->gain_ctrl.adc_ovr_sample_size); - ad9361_of_get_u32(iodev, np, "adi,gc-adc-small-overload-thresh", 47, - &pdata->gain_ctrl.adc_small_overload_thresh); - ad9361_of_get_u32(iodev, np, "adi,gc-adc-large-overload-thresh", 58, - &pdata->gain_ctrl.adc_large_overload_thresh); - ad9361_of_get_u32(iodev, np, "adi,gc-lmt-overload-high-thresh", 800, - &pdata->gain_ctrl.lmt_overload_high_thresh); - ad9361_of_get_u32(iodev, np, "adi,gc-lmt-overload-low-thresh", 704, - &pdata->gain_ctrl.lmt_overload_low_thresh); - ad9361_of_get_u32(iodev, np, "adi,gc-dec-pow-measurement-duration", 8192, - &pdata->gain_ctrl.dec_pow_measuremnt_duration); - ad9361_of_get_u32(iodev, np, "adi,gc-low-power-thresh", 24, - &pdata->gain_ctrl.low_power_thresh); - ad9361_of_get_bool(iodev, np, "adi,gc-dig-gain-enable", - &pdata->gain_ctrl.dig_gain_en); - ad9361_of_get_u32(iodev, np, "adi,gc-max-dig-gain", 15, - &pdata->gain_ctrl.max_dig_gain); - ad9361_of_get_bool(iodev, np, "adi,gc-use-rx-fir-out-for-dec-pwr-meas-enable", - &pdata->gain_ctrl.use_rx_fir_out_for_dec_pwr_meas); - - ad9361_of_get_bool(iodev, np, "adi,mgc-rx1-ctrl-inp-enable", - &pdata->gain_ctrl.mgc_rx1_ctrl_inp_en); - ad9361_of_get_bool(iodev, np, "adi,mgc-rx2-ctrl-inp-enable", - &pdata->gain_ctrl.mgc_rx2_ctrl_inp_en); - ad9361_of_get_u32(iodev, np, "adi,mgc-inc-gain-step", 2, - &pdata->gain_ctrl.mgc_inc_gain_step); - ad9361_of_get_u32(iodev, np, "adi,mgc-dec-gain-step", 2, - &pdata->gain_ctrl.mgc_dec_gain_step); - ad9361_of_get_u32(iodev, np, "adi,mgc-split-table-ctrl-inp-gain-mode", 0, - &pdata->gain_ctrl.mgc_split_table_ctrl_inp_gain_mode); - ad9361_of_get_u32(iodev, np, "adi,agc-attack-delay-extra-margin-us", 1, - &pdata->gain_ctrl.agc_attack_delay_extra_margin_us); - ad9361_of_get_u32(iodev, np, "adi,agc-outer-thresh-high", 5, - &pdata->gain_ctrl.agc_outer_thresh_high); - ad9361_of_get_u32(iodev, np, "adi,agc-outer-thresh-high-dec-steps", 2, - &pdata->gain_ctrl.agc_outer_thresh_high_dec_steps); - ad9361_of_get_u32(iodev, np, "adi,agc-inner-thresh-high", 10, - &pdata->gain_ctrl.agc_inner_thresh_high); - ad9361_of_get_u32(iodev, np, "adi,agc-inner-thresh-high-dec-steps", 1, - &pdata->gain_ctrl.agc_inner_thresh_high_dec_steps); - ad9361_of_get_u32(iodev, np, "adi,agc-inner-thresh-low", 12, - &pdata->gain_ctrl.agc_inner_thresh_low); - ad9361_of_get_u32(iodev, np, "adi,agc-inner-thresh-low-inc-steps", 1, - &pdata->gain_ctrl.agc_inner_thresh_low_inc_steps); - ad9361_of_get_u32(iodev, np, "adi,agc-outer-thresh-low", 18, - &pdata->gain_ctrl.agc_outer_thresh_low); - ad9361_of_get_u32(iodev, np, "adi,agc-outer-thresh-low-inc-steps", 2, - &pdata->gain_ctrl.agc_outer_thresh_low_inc_steps); - ad9361_of_get_u32(iodev, np, "adi,agc-adc-small-overload-exceed-counter", 10, - &pdata->gain_ctrl.adc_small_overload_exceed_counter); - ad9361_of_get_u32(iodev, np, "adi,agc-adc-large-overload-exceed-counter", 10, - &pdata->gain_ctrl.adc_large_overload_exceed_counter); - ad9361_of_get_u32(iodev, np, "adi,agc-adc-large-overload-inc-steps", 2, - &pdata->gain_ctrl.adc_large_overload_inc_steps); /* Name is misleading should be dec-steps */ - ad9361_of_get_bool(iodev, np, "adi,agc-adc-lmt-small-overload-prevent-gain-inc-enable", - &pdata->gain_ctrl.adc_lmt_small_overload_prevent_gain_inc); - ad9361_of_get_u32(iodev, np, "adi,agc-lmt-overload-large-exceed-counter", 10, - &pdata->gain_ctrl.lmt_overload_large_exceed_counter); - ad9361_of_get_u32(iodev, np, "adi,agc-lmt-overload-small-exceed-counter", 10, - &pdata->gain_ctrl.lmt_overload_small_exceed_counter); - ad9361_of_get_u32(iodev, np, "adi,agc-lmt-overload-large-inc-steps", 2, - &pdata->gain_ctrl.lmt_overload_large_inc_steps); - ad9361_of_get_u32(iodev, np, "adi,agc-dig-saturation-exceed-counter", 3, - &pdata->gain_ctrl.dig_saturation_exceed_counter); - ad9361_of_get_u32(iodev, np, "adi,agc-dig-gain-step-size", 4, - &pdata->gain_ctrl.dig_gain_step_size); - ad9361_of_get_bool(iodev, np, "adi,agc-sync-for-gain-counter-enable", - &pdata->gain_ctrl.sync_for_gain_counter_en); - ad9361_of_get_u32(iodev, np, "adi,agc-gain-update-interval-us", 1000, - &pdata->gain_ctrl.gain_update_interval_us); - ad9361_of_get_bool(iodev, np, "adi,agc-immed-gain-change-if-large-adc-overload-enable", - &pdata->gain_ctrl.immed_gain_change_if_large_adc_overload); - ad9361_of_get_bool(iodev, np, "adi,agc-immed-gain-change-if-large-lmt-overload-enable", - &pdata->gain_ctrl.immed_gain_change_if_large_lmt_overload); - - /* - * Fast AGC - */ - - ad9361_of_get_u32(iodev, np, "adi,fagc-dec-pow-measurement-duration", 64, - &pdata->gain_ctrl.f_agc_dec_pow_measuremnt_duration); - - ad9361_of_get_u32(iodev, np, "adi,fagc-state-wait-time-ns", 260, - &pdata->gain_ctrl.f_agc_state_wait_time_ns); /* 0x117 0..31 RX samples -> time-ns */ - /* Fast AGC - Low Power */ - ad9361_of_get_bool(iodev, np, "adi,fagc-allow-agc-gain-increase-enable", - &pdata->gain_ctrl.f_agc_allow_agc_gain_increase); /* 0x110:1 */ - ad9361_of_get_u32(iodev, np, "adi,fagc-lp-thresh-increment-time", 5, - &pdata->gain_ctrl.f_agc_lp_thresh_increment_time); /* 0x11B RX samples */ - ad9361_of_get_u32(iodev, np, "adi,fagc-lp-thresh-increment-steps", 1, - &pdata->gain_ctrl.f_agc_lp_thresh_increment_steps); /* 0x117 1..8 */ - - ad9361_of_get_bool(iodev, np, "adi,fagc-lock-level-lmt-gain-increase-enable", - &pdata->gain_ctrl.f_agc_lock_level_lmt_gain_increase_en); /* 0x111:6 (split table)*/ - ad9361_of_get_u32(iodev, np, "adi,fagc-lock-level-gain-increase-upper-limit", 5, - &pdata->gain_ctrl.f_agc_lock_level_gain_increase_upper_limit); /* 0x118 0..63 */ - /* Fast AGC - Peak Detectors and Final Settling */ - ad9361_of_get_u32(iodev, np, "adi,fagc-lpf-final-settling-steps", 1, - &pdata->gain_ctrl.f_agc_lpf_final_settling_steps); /* 0x112:6 0..3 (Post Lock Level Step)*/ - ad9361_of_get_u32(iodev, np, "adi,fagc-lmt-final-settling-steps", 1, - &pdata->gain_ctrl.f_agc_lmt_final_settling_steps); /* 0x113:6 0..3 (Post Lock Level Step)*/ - ad9361_of_get_u32(iodev, np, "adi,fagc-final-overrange-count", 3, - &pdata->gain_ctrl.f_agc_final_overrange_count); /* 0x116:5 0..7 */ - /* Fast AGC - Final Power Test */ - ad9361_of_get_bool(iodev, np, "adi,fagc-gain-increase-after-gain-lock-enable", - &pdata->gain_ctrl.f_agc_gain_increase_after_gain_lock_en); /* 0x110:7 */ - /* Fast AGC - Unlocking the Gain */ - /* 0 = MAX Gain, 1 = Optimized Gain, 2 = Set Gain */ - ad9361_of_get_u32(iodev, np, "adi,fagc-gain-index-type-after-exit-rx-mode", 0, - &pdata->gain_ctrl.f_agc_gain_index_type_after_exit_rx_mode); /* 0x110:[4,2] */ - - ad9361_of_get_bool(iodev, np, "adi,fagc-use-last-lock-level-for-set-gain-enable", - &pdata->gain_ctrl.f_agc_use_last_lock_level_for_set_gain_en); /* 0x111:7 */ - ad9361_of_get_bool(iodev, np, "adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable", - &pdata->gain_ctrl.f_agc_rst_gla_stronger_sig_thresh_exceeded_en); /* 0x111:7 */ - ad9361_of_get_u32(iodev, np, "adi,fagc-optimized-gain-offset", 5, - &pdata->gain_ctrl.f_agc_optimized_gain_offset); /*0x116 0..15 steps */ - - ad9361_of_get_u32(iodev, np, "adi,fagc-rst-gla-stronger-sig-thresh-above-ll", 10, - &pdata->gain_ctrl.f_agc_rst_gla_stronger_sig_thresh_above_ll); /*0x113 0..63 dbFS */ - ad9361_of_get_bool(iodev, np, "adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable", - &pdata->gain_ctrl.f_agc_rst_gla_engergy_lost_sig_thresh_exceeded_en); /* 0x110:6 */ - ad9361_of_get_bool(iodev, np, "adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable", - &pdata->gain_ctrl.f_agc_rst_gla_engergy_lost_goto_optim_gain_en); /* 0x110:6 */ - ad9361_of_get_u32(iodev, np, "adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll", 10, - &pdata->gain_ctrl.f_agc_rst_gla_engergy_lost_sig_thresh_below_ll); /* 0x112 */ - ad9361_of_get_u32(iodev, np, "adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt", 8, - &pdata->gain_ctrl.f_agc_energy_lost_stronger_sig_gain_lock_exit_cnt); /* 0x119 0..63 RX samples */ - ad9361_of_get_bool(iodev, np, "adi,fagc-rst-gla-large-adc-overload-enable", - &pdata->gain_ctrl.f_agc_rst_gla_large_adc_overload_en); /*0x110:~1 and 0x114:~7 */ - ad9361_of_get_bool(iodev, np, "adi,fagc-rst-gla-large-lmt-overload-enable", - &pdata->gain_ctrl.f_agc_rst_gla_large_lmt_overload_en); /*0x110:~1 */ - - ad9361_of_get_bool(iodev, np, "adi,fagc-rst-gla-en-agc-pulled-high-enable", - &pdata->gain_ctrl.f_agc_rst_gla_en_agc_pulled_high_en); - - ad9361_of_get_u32(iodev, np, "adi,fagc-rst-gla-if-en-agc-pulled-high-mode", 0, - &pdata->gain_ctrl.f_agc_rst_gla_if_en_agc_pulled_high_mode); /* 0x0FB, 0x111 */ - ad9361_of_get_u32(iodev, np, "adi,fagc-power-measurement-duration-in-state5", 64, - &pdata->gain_ctrl.f_agc_power_measurement_duration_in_state5); /* 0x109, 0x10a RX samples 0..524288 */ - - ad9361_of_get_u32(iodev, np, "adi,fagc-adc-large-overload-inc-steps", 2, /* 0x106 [D6:D4] 0..7 */ - &pdata->gain_ctrl.f_agc_large_overload_inc_steps); /* Name is misleading should be dec-steps */ - - /* RSSI Control */ - - ad9361_of_get_u32(iodev, np, "adi,rssi-restart-mode", 3, - &pdata->rssi_ctrl.restart_mode); - ad9361_of_get_bool(iodev, np, "adi,rssi-unit-is-rx-samples-enable", - &pdata->rssi_ctrl.rssi_unit_is_rx_samples); - ad9361_of_get_u32(iodev, np, "adi,rssi-delay", 1, - &pdata->rssi_ctrl.rssi_delay); - ad9361_of_get_u32(iodev, np, "adi,rssi-wait", 1, - &pdata->rssi_ctrl.rssi_wait); - ad9361_of_get_u32(iodev, np, "adi,rssi-duration", 1000, - &pdata->rssi_ctrl.rssi_duration); - - /* RSSI Gain Step Error Tables */ - - ret = of_property_read_u32_array(np, - "adi,rssi-gain-step-lna-error-table", - pdata->rssi_lna_err_tbl, 4); - ret |= of_property_read_u32_array(np, - "adi,rssi-gain-step-mixer-error-table", - pdata->rssi_mixer_err_tbl, 16); - ret |= of_property_read_u32_array(np, - "adi,rssi-gain-step-calibration-register-values", - pdata->rssi_gain_step_calib_reg_val, 5); - if (ret) - pdata->rssi_skip_calib = true; - else - pdata->rssi_skip_calib = false; - - /* Control Outs Control */ - - ad9361_of_get_u32(iodev, np, "adi,ctrl-outs-index", 0, - &pdata->ctrl_outs_ctrl.index); - ad9361_of_get_u32(iodev, np, "adi,ctrl-outs-enable-mask", 0xFF, - &pdata->ctrl_outs_ctrl.en_mask); - - /* eLNA Control */ - - ad9361_of_get_u32(iodev, np, "adi,elna-settling-delay-ns", 0, - &pdata->elna_ctrl.settling_delay_ns); - ad9361_of_get_u32(iodev, np, "adi,elna-gain-mdB", 0, - &pdata->elna_ctrl.gain_mdB); - ad9361_of_get_u32(iodev, np, "adi,elna-bypass-loss-mdB", 0, - &pdata->elna_ctrl.bypass_loss_mdB); - ad9361_of_get_bool(iodev, np, "adi,elna-rx1-gpo0-control-enable", - &pdata->elna_ctrl.elna_1_control_en); - ad9361_of_get_bool(iodev, np, "adi,elna-rx2-gpo1-control-enable", - &pdata->elna_ctrl.elna_2_control_en); - ad9361_of_get_bool(iodev, np, "adi,elna-gaintable-all-index-enable", - &pdata->elna_ctrl.elna_in_gaintable_all_index_en); - - /* AuxADC Temp Sense Control */ - - ad9361_of_get_u32(iodev, np, "adi,temp-sense-measurement-interval-ms", 1000, - &pdata->auxadc_ctrl.temp_time_inteval_ms); - ad9361_of_get_u32(iodev, np, "adi,temp-sense-offset-signed", 0xBD, - &pdata->auxadc_ctrl.offset); /* signed */ - ad9361_of_get_bool(iodev, np, "adi,temp-sense-periodic-measurement-enable", - &pdata->auxadc_ctrl.periodic_temp_measuremnt); - ad9361_of_get_u32(iodev, np, "adi,temp-sense-decimation", 256, - &pdata->auxadc_ctrl.temp_sensor_decimation); - ad9361_of_get_u32(iodev, np, "adi,aux-adc-rate", 40000000UL, - &pdata->auxadc_ctrl.auxadc_clock_rate); - ad9361_of_get_u32(iodev, np, "adi,aux-adc-decimation", 256, - &pdata->auxadc_ctrl.auxadc_decimation); - - /* AuxDAC Control */ - - ad9361_of_get_bool(iodev, np, "adi,aux-dac-manual-mode-enable", - &pdata->auxdac_ctrl.auxdac_manual_mode_en); - - ad9361_of_get_u32(iodev, np, "adi,aux-dac1-default-value-mV", 0, - &pdata->auxdac_ctrl.dac1_default_value); - ad9361_of_get_bool(iodev, np, "adi,aux-dac1-active-in-rx-enable", - &pdata->auxdac_ctrl.dac1_in_rx_en); - ad9361_of_get_bool(iodev, np, "adi,aux-dac1-active-in-tx-enable", - &pdata->auxdac_ctrl.dac1_in_tx_en); - ad9361_of_get_bool(iodev, np, "adi,aux-dac1-active-in-alert-enable", - &pdata->auxdac_ctrl.dac1_in_alert_en); - ad9361_of_get_u32(iodev, np, "adi,aux-dac1-rx-delay-us", 0, - &pdata->auxdac_ctrl.dac1_rx_delay_us); - ad9361_of_get_u32(iodev, np, "adi,aux-dac1-tx-delay-us", 0, - &pdata->auxdac_ctrl.dac1_tx_delay_us); - - ad9361_of_get_u32(iodev, np, "adi,aux-dac2-default-value-mV", 0, - &pdata->auxdac_ctrl.dac2_default_value); - ad9361_of_get_bool(iodev, np, "adi,aux-dac2-active-in-rx-enable", - &pdata->auxdac_ctrl.dac2_in_rx_en); - ad9361_of_get_bool(iodev, np, "adi,aux-dac2-active-in-tx-enable", - &pdata->auxdac_ctrl.dac2_in_tx_en); - ad9361_of_get_bool(iodev, np, "adi,aux-dac2-active-in-alert-enable", - &pdata->auxdac_ctrl.dac2_in_alert_en); - ad9361_of_get_u32(iodev, np, "adi,aux-dac2-rx-delay-us", 0, - &pdata->auxdac_ctrl.dac2_rx_delay_us); - ad9361_of_get_u32(iodev, np, "adi,aux-dac2-tx-delay-us", 0, - &pdata->auxdac_ctrl.dac2_tx_delay_us); - - /* GPO Control */ - - ad9361_of_get_bool(iodev, np, "adi,gpo-manual-mode-enable", - &pdata->gpo_ctrl.gpo_manual_mode_en); - - ad9361_of_get_u32(iodev, np, "adi,gpo-manual-mode-enable-mask", 0, - &pdata->gpo_ctrl.gpo_manual_mode_enable_mask); - - ad9361_of_get_bool(iodev, np, "adi,gpo0-inactive-state-high-enable", - &pdata->gpo_ctrl.gpo0_inactive_state_high_en); - ad9361_of_get_bool(iodev, np, "adi,gpo1-inactive-state-high-enable", - &pdata->gpo_ctrl.gpo1_inactive_state_high_en); - ad9361_of_get_bool(iodev, np, "adi,gpo2-inactive-state-high-enable", - &pdata->gpo_ctrl.gpo2_inactive_state_high_en); - ad9361_of_get_bool(iodev, np, "adi,gpo3-inactive-state-high-enable", - &pdata->gpo_ctrl.gpo3_inactive_state_high_en); - - ad9361_of_get_bool(iodev, np, "adi,gpo0-slave-rx-enable", - &pdata->gpo_ctrl.gpo0_slave_rx_en); - ad9361_of_get_bool(iodev, np, "adi,gpo0-slave-tx-enable", - &pdata->gpo_ctrl.gpo0_slave_tx_en); - ad9361_of_get_bool(iodev, np, "adi,gpo1-slave-rx-enable", - &pdata->gpo_ctrl.gpo1_slave_rx_en); - ad9361_of_get_bool(iodev, np, "adi,gpo1-slave-tx-enable", - &pdata->gpo_ctrl.gpo1_slave_tx_en); - ad9361_of_get_bool(iodev, np, "adi,gpo2-slave-rx-enable", - &pdata->gpo_ctrl.gpo2_slave_rx_en); - ad9361_of_get_bool(iodev, np, "adi,gpo2-slave-tx-enable", - &pdata->gpo_ctrl.gpo2_slave_tx_en); - ad9361_of_get_bool(iodev, np, "adi,gpo3-slave-rx-enable", - &pdata->gpo_ctrl.gpo3_slave_rx_en); - ad9361_of_get_bool(iodev, np, "adi,gpo3-slave-tx-enable", - &pdata->gpo_ctrl.gpo3_slave_tx_en); - - ad9361_of_get_u32(iodev, np, "adi,gpo0-rx-delay-us", 0, - &pdata->gpo_ctrl.gpo0_rx_delay_us); - ad9361_of_get_u32(iodev, np, "adi,gpo0-tx-delay-us", 0, - &pdata->gpo_ctrl.gpo0_tx_delay_us); - ad9361_of_get_u32(iodev, np, "adi,gpo1-rx-delay-us", 0, - &pdata->gpo_ctrl.gpo1_rx_delay_us); - ad9361_of_get_u32(iodev, np, "adi,gpo1-tx-delay-us", 0, - &pdata->gpo_ctrl.gpo1_tx_delay_us); - ad9361_of_get_u32(iodev, np, "adi,gpo2-rx-delay-us", 0, - &pdata->gpo_ctrl.gpo2_rx_delay_us); - ad9361_of_get_u32(iodev, np, "adi,gpo2-tx-delay-us", 0, - &pdata->gpo_ctrl.gpo2_tx_delay_us); - ad9361_of_get_u32(iodev, np, "adi,gpo3-rx-delay-us", 0, - &pdata->gpo_ctrl.gpo3_rx_delay_us); - ad9361_of_get_u32(iodev, np, "adi,gpo3-tx-delay-us", 0, - &pdata->gpo_ctrl.gpo3_tx_delay_us); - - /* Tx Monitor Control */ - - ad9361_of_get_u32(iodev, np, "adi,txmon-low-high-thresh", 37000, - &pdata->txmon_ctrl.low_high_gain_threshold_mdB); - ad9361_of_get_u32(iodev, np, "adi,txmon-low-gain", 0, - &pdata->txmon_ctrl.low_gain_dB); - ad9361_of_get_u32(iodev, np, "adi,txmon-high-gain", 24, - &pdata->txmon_ctrl.high_gain_dB); - ad9361_of_get_bool(iodev, np, "adi,txmon-dc-tracking-enable", - &pdata->txmon_ctrl.tx_mon_track_en); - ad9361_of_get_bool(iodev, np, "adi,txmon-one-shot-mode-enable", - &pdata->txmon_ctrl.one_shot_mode_en); - ad9361_of_get_u32(iodev, np, "adi,txmon-delay", 511, - &pdata->txmon_ctrl.tx_mon_delay); - ad9361_of_get_u32(iodev, np, "adi,txmon-duration", 8192, - &pdata->txmon_ctrl.tx_mon_duration); - ad9361_of_get_u32(iodev, np, "adi,txmon-1-front-end-gain", 2, - &pdata->txmon_ctrl.tx1_mon_front_end_gain); - ad9361_of_get_u32(iodev, np, "adi,txmon-2-front-end-gain", 2, - &pdata->txmon_ctrl.tx2_mon_front_end_gain); - ad9361_of_get_u32(iodev, np, "adi,txmon-1-lo-cm", 48, - &pdata->txmon_ctrl.tx1_mon_lo_cm); - ad9361_of_get_u32(iodev, np, "adi,txmon-2-lo-cm", 48, - &pdata->txmon_ctrl.tx2_mon_lo_cm); - - - return pdata; -} -#else -static inline struct ad9361_phy_platform_data - *ad9361_phy_parse_dt(struct iio_dev *iodev, struct device *dev) -{ - return NULL; -} -#endif - -static ssize_t -ad9361_fir_bin_write(struct file *filp, struct kobject *kobj, - struct bin_attribute *bin_attr, - char *buf, loff_t off, size_t count) -{ - - struct iio_dev *indio_dev = dev_to_iio_dev(kobj_to_dev(kobj)); - struct ad9361_rf_phy *phy = iio_priv(indio_dev); - - return ad9361_parse_fir(phy, buf, count); -} - -static ssize_t -ad9361_fir_bin_read(struct file *filp, struct kobject *kobj, - struct bin_attribute *bin_attr, - char *buf, loff_t off, size_t count) -{ - - struct iio_dev *indio_dev = dev_to_iio_dev(kobj_to_dev(kobj)); - struct ad9361_rf_phy *phy = iio_priv(indio_dev); - struct ad9361_rf_phy_state *st = phy->state; - - if (off) - return 0; - - return sprintf(buf, "FIR Rx: %d,%d Tx: %d,%d\n", - st->rx_fir_ntaps, st->rx_fir_dec, - st->tx_fir_ntaps, st->tx_fir_int); -} - -static void ad9361_free_gt(struct ad9361_rf_phy *phy, struct gain_table_info *table) -{ - int i; - - if (!table || table == ad9361_adi_gt_info) - return; - - for (i = 0; i < MAX_NUM_GAIN_TABLES; i++) - if (table[i].abs_gain_tbl) { - devm_kfree(&phy->spi->dev, table[i].abs_gain_tbl); - } - - devm_kfree(&phy->spi->dev, table); -} - -static struct gain_table_info * ad9361_parse_gt(struct ad9361_rf_phy *phy, - char *data, u32 size) -{ - struct gain_table_info *table; - bool header_found; - int i = 0, ret, table_num = 0; - char *line, *ptr = data; - u8 *p; - - header_found = false; - - table = devm_kzalloc(&phy->spi->dev, - sizeof(struct gain_table_info) * - MAX_NUM_GAIN_TABLES, GFP_KERNEL); - if (!table) { - ret = -ENOMEM; - goto out; - } - - while ((line = strsep(&ptr, "\n"))) { - if (line >= data + size) { - break; - } - - if (line[0] == '#') /* skip comment lines */ - continue; - - if (strstr(line, "list>")) /* skip <[/]list> */ - continue; - - if (!header_found) { - char type[40]; - unsigned model, dest; - u64 start; - u64 end; - - ret = sscanf(line, " ", - &model , type, &dest, &start, &end); - - if (ret == 5) { - if (!(model == 9361 || model == 9364)) { - ret = -EINVAL; - goto out; - } - if (start >= end) { - ret = -EINVAL; - goto out; - } - - p = devm_kzalloc(&phy->spi->dev, - sizeof(u8[MAX_GAIN_TABLE_SIZE]) + - sizeof(u8[3][MAX_GAIN_TABLE_SIZE]), - GFP_KERNEL); - if (!p) { - ret = -ENOMEM; - goto out; - } - - table[table_num].abs_gain_tbl = (s8 *) p; - table[table_num].tab = (u8 (*) [3]) (p + - sizeof(u8[MAX_GAIN_TABLE_SIZE])); - - table[table_num].split_table = sysfs_streq(type, "SPLIT"); - table[table_num].start = start; - table[table_num].end = end; - - header_found = true; - i = 0; - - continue; - } else { - header_found = false; - } - } - - if (header_found) { - int a,b,c,d; - ret = sscanf(line, " %i,%i,%i,%i", &a, &b, &c, &d); - if (ret == 4) { - if (i >= MAX_GAIN_TABLE_SIZE) - goto out; - - if ((i > 0) && (a < table[table_num].abs_gain_tbl[i - 1])) - dev_warn(&phy->spi->dev, - "Gain table must be monotonic"); - - table[table_num].abs_gain_tbl[i] = a; - table[table_num].tab[i][0] = b; - table[table_num].tab[i][1] = c; - table[table_num].tab[i][2] = d; - i++; - continue; - } else if (strstr(line, "")) { - table[table_num].max_index = i; - header_found = false; - table_num++; - - if (table_num >= (MAX_NUM_GAIN_TABLES - 2)) { - dev_warn(&phy->spi->dev, - "Skipping tables"); - goto done; - } - - continue; - } else { - dev_err(&phy->spi->dev, - "ERROR: Malformed gain table"); - goto out_free_tables; - } - } - } - -done: - dev_dbg(&phy->spi->dev, "%s: table_num %d header_found %d", - __func__, table_num, header_found); - - if (table_num > 0 && !header_found) - return table; - else - return ERR_PTR(-EFAULT); - -out_free_tables: - ad9361_free_gt(phy, table); - -out: - return ERR_PTR(ret); -} - -static int ad9361_request_gt(struct ad9361_rf_phy *phy, char *filename) -{ - struct ad9361_rf_phy_state *st = phy->state; - const struct firmware *fw; - struct gain_table_info *table; - const char *name; - char *cpy; - int ret; - - if (filename == NULL) { - if (phy->spi->dev.of_node) { - if (of_property_read_string(phy->spi->dev.of_node, - "adi,gaintable-name", &name)) - return -ENOENT; - } else { - return -ENOENT; - } - } else { - name = filename; - } - - dev_dbg(&phy->spi->dev, "request gaintable: %s\n", name); - - ret = request_firmware(&fw, name, &phy->spi->dev); - if (ret) { - dev_err(&phy->spi->dev, - "request_firmware(%s) failed with %i\n", name, ret); - return ret; - } - - cpy = kzalloc(fw->size, GFP_KERNEL); - if (!cpy) - goto out; - - memcpy(cpy, fw->data, fw->size); - - table = ad9361_parse_gt(phy, cpy, fw->size); - if (IS_ERR_OR_NULL(table)) { - ret = PTR_ERR(table); - goto out_free; - } - - ad9361_free_gt(phy, phy->gt_info); - - st->current_table = -1; - phy->gt_info = table; - -out_free: - kfree(cpy); -out: - release_firmware(fw); - - return ret; -} - -static ssize_t -ad9361_gt_bin_write(struct file *filp, struct kobject *kobj, - struct bin_attribute *bin_attr, - char *buf, loff_t off, size_t count) -{ - - struct iio_dev *indio_dev = dev_to_iio_dev(kobj_to_dev(kobj)); - struct ad9361_rf_phy *phy = iio_priv(indio_dev); - struct ad9361_rf_phy_state *st = phy->state; - struct gain_table_info *table; - - if (off == 0) { - if (phy->bin_attr_buf == NULL) { - phy->bin_attr_buf = devm_kzalloc(&phy->spi->dev, - bin_attr->size, GFP_KERNEL); - if (!phy->bin_attr_buf) - return -ENOMEM; - } else { - memset(phy->bin_attr_buf, 0, bin_attr->size); - } - } - - memcpy(phy->bin_attr_buf + off, buf, count); - - if (strnstr(phy->bin_attr_buf, "", off + count) == NULL) - return count; - - table = ad9361_parse_gt(phy, phy->bin_attr_buf, off + count); - if (IS_ERR_OR_NULL(table)) - return PTR_ERR(table); - - mutex_lock(&phy->indio_dev->mlock); - ad9361_free_gt(phy, phy->gt_info); - - st->current_table = -1; - phy->gt_info = table; - - ad9361_load_gt(phy, ad9361_from_clk( - clk_get_rate(phy->clks[RX_RFPLL])), - GT_RX1 + GT_RX2); - - mutex_unlock(&phy->indio_dev->mlock); - - return count; -} - -static ssize_t -ad9361_gt_bin_read(struct file *filp, struct kobject *kobj, - struct bin_attribute *bin_attr, - char *buf, loff_t off, size_t count) -{ - - struct iio_dev *indio_dev = dev_to_iio_dev(kobj_to_dev(kobj)); - struct ad9361_rf_phy *phy = iio_priv(indio_dev); - int ret, j, len = 0; - char *tab; - - tab = kzalloc(bin_attr->size, GFP_KERNEL); - if (tab == NULL) - return -ENOMEM; - - len += snprintf(tab + len, bin_attr->size - len, - "\n", 9361, - phy->gt_info[ad9361_gt(phy)].split_table ? "SPLIT" : "FULL", 3, - phy->gt_info[ad9361_gt(phy)].start, - phy->gt_info[ad9361_gt(phy)].end); - - for (j = 0; j < phy->gt_info[ad9361_gt(phy)].max_index; j++) - len += snprintf(tab + len, bin_attr->size - len, - "%d, 0x%.2X, 0x%.2X, 0x%.2X\n", - phy->gt_info[ad9361_gt(phy)].abs_gain_tbl[j], - phy->gt_info[ad9361_gt(phy)].tab[j][0], - phy->gt_info[ad9361_gt(phy)].tab[j][1], - phy->gt_info[ad9361_gt(phy)].tab[j][2]); - - len += snprintf(tab + len, bin_attr->size - len, "\n"); - - ret = memory_read_from_buffer(buf, count, &off, tab, bin_attr->size); - - kfree(tab); - - return ret; -} - -static int ad9361_probe(struct spi_device *spi) -{ - struct iio_dev *indio_dev; - struct ad9361_rf_phy_state *st; - struct ad9361_rf_phy *phy; - struct clk *clk = NULL; - int ret, rev; - - dev_info(&spi->dev, "%s : enter (%s)", __func__, - spi_get_device_id(spi)->name); - - clk = devm_clk_get(&spi->dev, NULL); - if (IS_ERR(clk)) { - return -EPROBE_DEFER; - } - - indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*phy)); - if (indio_dev == NULL) - return -ENOMEM; - - st = devm_kzalloc(&spi->dev, sizeof(*st), GFP_KERNEL); - if (st == NULL) - return -ENOMEM; - - phy = iio_priv(indio_dev); - phy->state = st; - phy->indio_dev = indio_dev; - phy->spi = spi; - phy->clk_refin = clk; - - ad9361_init_state(phy); - - phy->pdata = ad9361_phy_parse_dt(indio_dev, &spi->dev); - if (phy->pdata == NULL) - return -EINVAL; - - phy->pdata->reset_gpio = devm_gpiod_get_optional(&spi->dev, "reset", - GPIOD_OUT_HIGH); - if (IS_ERR(phy->pdata->reset_gpio)) - return PTR_ERR(phy->pdata->reset_gpio); - - /* Optional: next three used for MCS synchronization */ - phy->pdata->sync_gpio = devm_gpiod_get_optional(&spi->dev, "sync", - GPIOD_OUT_LOW); - if (IS_ERR(phy->pdata->sync_gpio)) - return PTR_ERR(phy->pdata->sync_gpio); - - phy->pdata->cal_sw1_gpio = devm_gpiod_get_optional(&spi->dev, "cal-sw1", - GPIOD_OUT_LOW); - if (IS_ERR(phy->pdata->cal_sw1_gpio)) - return PTR_ERR(phy->pdata->cal_sw1_gpio); - - phy->pdata->cal_sw2_gpio = devm_gpiod_get_optional(&spi->dev, "cal-sw2", - GPIOD_OUT_LOW); - if (IS_ERR(phy->pdata->cal_sw2_gpio)) - return PTR_ERR(phy->pdata->cal_sw2_gpio); - - ret = ad9361_register_ext_band_control(phy); - if (ret < 0) - dev_warn(&spi->dev, - "%s: failed to initialize ext band control\n", - __func__); - - phy->gt_info = ad9361_adi_gt_info; - - ad9361_request_gt(phy, NULL); - - ad9361_reset(phy); - - ret = ad9361_spi_read(spi, REG_PRODUCT_ID); - if ((ret & PRODUCT_ID_MASK) != PRODUCT_ID_9361) { - dev_err(&spi->dev, "%s : Unsupported PRODUCT_ID 0x%X", - __func__, ret); - return -ENODEV; - } - - rev = ret & REV_MASK; - - if (spi_get_device_id(spi)->driver_data == ID_AD9364) { - phy->pdata->rx2tx2 = false; - phy->pdata->rx1tx1_mode_use_rx_num = 1; - phy->pdata->rx1tx1_mode_use_tx_num = 1; - } - - INIT_WORK(&phy->work, ad9361_work_func); - init_completion(&phy->complete); - - ret = register_clocks(phy); - if (ret < 0) - return ret; - - ret = ad9361_setup(phy); - if (ret < 0) - goto out_unregister_notifier; - - ret = of_clk_add_provider(spi->dev.of_node, - of_clk_src_onecell_get, &phy->clk_data); - if (ret) - goto out_disable_clocks; - - sysfs_bin_attr_init(&phy->bin); - phy->bin.attr.name = "filter_fir_config"; - phy->bin.attr.mode = S_IWUSR | S_IRUGO; - phy->bin.write = ad9361_fir_bin_write; - phy->bin.read = ad9361_fir_bin_read; - phy->bin.size = 4096; - - sysfs_bin_attr_init(&phy->bin_gt); - phy->bin_gt.attr.name = "gain_table_config"; - phy->bin_gt.attr.mode = S_IWUSR | S_IRUGO; - phy->bin_gt.write = ad9361_gt_bin_write; - phy->bin_gt.read = ad9361_gt_bin_read; - phy->bin_gt.size = 4096; - - indio_dev->dev.parent = &spi->dev; - - if (spi->dev.of_node) - indio_dev->name = spi->dev.of_node->name; - else - indio_dev->name = "ad9361-phy"; - - indio_dev->info = &ad9361_phy_info; - indio_dev->modes = INDIO_DIRECT_MODE; - indio_dev->channels = ad9361_phy_chan; - indio_dev->num_channels = ARRAY_SIZE(ad9361_phy_chan) - - (phy->pdata->rx2tx2 ? 0 : 2); - - ret = iio_device_register(indio_dev); - if (ret < 0) - goto out_clk_del_provider; - ret = ad9361_register_axi_converter(phy); - if (ret < 0) - goto out_iio_device_unregister; - ret = sysfs_create_bin_file(&indio_dev->dev.kobj, &phy->bin); - if (ret < 0) - goto out_iio_device_unregister; - ret = sysfs_create_bin_file(&indio_dev->dev.kobj, &phy->bin_gt); - if (ret < 0) - goto out_iio_device_unregister; - - - ret = ad9361_register_debugfs(indio_dev); - if (ret < 0) - dev_warn(&spi->dev, "%s: failed to register debugfs", __func__); - - dev_info(&spi->dev, "%s : AD936x Rev %d successfully initialized", - __func__, rev); - - return 0; - -out_iio_device_unregister: - iio_device_unregister(indio_dev); -out_clk_del_provider: - of_clk_del_provider(spi->dev.of_node); -out_disable_clocks: - ad9361_clks_disable(phy); -out_unregister_notifier: - clk_notifier_unregister(phy->clks[RX_RFPLL], &phy->clk_nb_rx); - clk_notifier_unregister(phy->clks[TX_RFPLL], &phy->clk_nb_tx); - - return ret; -} - -static int ad9361_remove(struct spi_device *spi) -{ - struct ad9361_rf_phy *phy = ad9361_spi_to_phy(spi); - - ad9361_unregister_ext_band_control(phy); - sysfs_remove_bin_file(&phy->indio_dev->dev.kobj, &phy->bin_gt); - sysfs_remove_bin_file(&phy->indio_dev->dev.kobj, &phy->bin); - iio_device_unregister(phy->indio_dev); - of_clk_del_provider(spi->dev.of_node); - clk_notifier_unregister(phy->clks[RX_RFPLL], &phy->clk_nb_rx); - clk_notifier_unregister(phy->clks[TX_RFPLL], &phy->clk_nb_tx); - ad9361_clks_disable(phy); - - return 0; -} - -static const struct spi_device_id ad9361_id[] = { - {"ad9361", ID_AD9361}, /* 2RX2TX */ - {"ad9364", ID_AD9364}, /* 1RX1TX */ - {"ad9361-2x", ID_AD9361_2}, /* 2 x 2RX2TX */ - {"ad9363a", ID_AD9363A}, /* 2RX2TX */ - {} -}; -MODULE_DEVICE_TABLE(spi, ad9361_id); - -static struct spi_driver ad9361_driver = { - .driver = { - .name = "ad9361", - .owner = THIS_MODULE, - }, - .probe = ad9361_probe, - .remove = ad9361_remove, - .id_table = ad9361_id, -}; -module_spi_driver(ad9361_driver); - -MODULE_AUTHOR("Michael Hennerich "); -MODULE_DESCRIPTION("Analog Devices AD9361 ADC"); -MODULE_LICENSE("GPL v2"); diff --git a/driver/ad9361/ad9361_conv.c b/driver/ad9361/ad9361_conv.c deleted file mode 100644 index 280b86f..0000000 --- a/driver/ad9361/ad9361_conv.c +++ /dev/null @@ -1,821 +0,0 @@ -/* - * AD9361 Agile RF Transceiver - * - * Copyright 2013-2017 Analog Devices Inc. - * - * Licensed under the GPL-2. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include -#include - -#include "ad9361.h" - -#if IS_ENABLED(CONFIG_CF_AXI_ADC) -#include "cf_axi_adc.h" - -static void ad9361_set_intf_delay(struct ad9361_rf_phy *phy, bool tx, - unsigned int clock_delay, - unsigned int data_delay, bool clock_changed) -{ - if (clock_changed) - ad9361_ensm_force_state(phy, ENSM_STATE_ALERT); - ad9361_spi_write(phy->spi, - REG_RX_CLOCK_DATA_DELAY + (tx ? 1 : 0), - RX_DATA_DELAY(data_delay) | - DATA_CLK_DELAY(clock_delay)); - if (clock_changed) - ad9361_ensm_force_state(phy, ENSM_STATE_FDD); -} - -static unsigned int ad9361_num_phy_chan(struct axiadc_converter *conv) -{ - if (conv->chip_info->num_channels > 4) - return 4; - return conv->chip_info->num_channels; -} - -static int ad9361_check_pn(struct axiadc_converter *conv, bool tx, - unsigned int delay) -{ - struct axiadc_state *st = iio_priv(conv->indio_dev); - unsigned int num_chan = ad9361_num_phy_chan(conv); - unsigned int chan; - - for (chan = 0; chan < num_chan; chan++) - axiadc_write(st, ADI_REG_CHAN_STATUS(chan), - ADI_PN_ERR | ADI_PN_OOS); - mdelay(delay); - - if (!tx && !(axiadc_read(st, ADI_REG_STATUS) & ADI_STATUS)) - return 1; - - for (chan = 0; chan < num_chan; chan++) { - if (axiadc_read(st, ADI_REG_CHAN_STATUS(chan))) - return 1; - } - - return 0; -} - -ssize_t ad9361_dig_interface_timing_analysis(struct ad9361_rf_phy *phy, - char *buf, unsigned buflen) -{ - struct axiadc_converter *conv = spi_get_drvdata(phy->spi); - struct ad9361_dig_tune_data data; - int i, j, len = 0; - int ret; - u8 field[16][16]; - u8 rx; - - if (!conv) - return -ENODEV; - - ret = ad9361_get_dig_tune_data(phy, &data); - if (ret < 0) - return ret; - - dev_dbg(&phy->spi->dev, "%s:\n", __func__); - - rx = ad9361_spi_read(phy->spi, REG_RX_CLOCK_DATA_DELAY); - - /* Mute TX, we don't want to transmit the PRBS */ - ad9361_tx_mute(phy, 1); - - ad9361_ensm_mode_disable_pinctrl(phy); - - ad9361_bist_loopback(phy, 0); - ad9361_bist_prbs(phy, BIST_INJ_RX); - - for (i = 0; i < 16; i++) { - for (j = 0; j < 16; j++) { - ad9361_set_intf_delay(phy, false, i, j, j == 0); - field[j][i] = ad9361_check_pn(conv, false, 1); - } - } - - ad9361_ensm_force_state(phy, ENSM_STATE_ALERT); - ad9361_spi_write(phy->spi, REG_RX_CLOCK_DATA_DELAY, rx); - ad9361_bist_loopback(phy, data.bist_loopback_mode); - ad9361_write_bist_reg(phy, data.bist_config); - - ad9361_ensm_mode_restore_pinctrl(phy); - ad9361_ensm_restore_state(phy, data.ensm_state); - - ad9361_tx_mute(phy, 0); - - len += snprintf(buf + len, buflen, "CLK: %lu Hz 'o' = PASS\n", - clk_get_rate(phy->clks[RX_SAMPL_CLK])); - len += snprintf(buf + len, buflen, "DC"); - for (i = 0; i < 16; i++) - len += snprintf(buf + len, buflen, "%x:", i); - len += snprintf(buf + len, buflen, "\n"); - - for (i = 0; i < 16; i++) { - len += snprintf(buf + len, buflen, "%x:", i); - for (j = 0; j < 16; j++) { - len += snprintf(buf + len, buflen, "%c ", - (field[i][j] ? '.' : 'o')); - } - len += snprintf(buf + len, buflen, "\n"); - } - len += snprintf(buf + len, buflen, "\n"); - - return len; -} -EXPORT_SYMBOL(ad9361_dig_interface_timing_analysis); - -static ssize_t samples_pps_read(struct iio_dev *indio_dev, - uintptr_t private, - const struct iio_chan_spec *chan, char *buf) -{ - struct axiadc_converter *conv = iio_device_get_drvdata(indio_dev); - struct axiadc_state *st = iio_priv(conv->indio_dev); - u32 config, val, mode; - - config = axiadc_read(st, ADI_REG_CONFIG); - - if (!(config & ADI_PPS_RECEIVER_ENABLE)) - return -ENODEV; - - val = axiadc_read(st, ADI_REG_CLOCKS_PER_PPS_STATUS); - if (val & ADI_CLOCKS_PER_PPS_STAT_INVAL) - return -ETIMEDOUT; - - mode = axiadc_read(st, ADI_REG_CNTRL); - - /* - * Counts DATA_CLK cycles therefore needs to be corrected - * for 2rx2tx mode or for LVDS vs. CMOS mode. - */ - - val = axiadc_read(st, ADI_REG_CLOCKS_PER_PPS); - - if (!(mode & ADI_R1_MODE)) - val /= 2; - - if (!(config & ADI_CMOS_OR_LVDS_N)) - val /= 2; - - return sprintf(buf, "%u\n", val); -} - -/* - * Returns the number of samples during a 1PPS (Pulse Per Second) interval. - */ - -static struct iio_chan_spec_ext_info axiadc_ext_info[] = { - { - .name = "samples_pps", - .read = samples_pps_read, - .shared = IIO_SHARED_BY_TYPE, - }, - {}, -}; - -#define AIM_CHAN(_chan, _si, _bits, _sign) \ - { .type = IIO_VOLTAGE, \ - .indexed = 1, \ - .channel = _chan, \ - .info_mask_separate = BIT(IIO_CHAN_INFO_CALIBSCALE) | \ - BIT(IIO_CHAN_INFO_CALIBBIAS) | \ - BIT(IIO_CHAN_INFO_CALIBPHASE), \ - .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ - .ext_info = axiadc_ext_info, \ - .scan_index = _si, \ - .scan_type = { \ - .sign = _sign, \ - .realbits = _bits, \ - .storagebits = 16, \ - .shift = 0, \ - }, \ - } - -#define AIM_MC_CHAN(_chan, _si, _bits, _sign) \ - { .type = IIO_VOLTAGE, \ - .indexed = 1, \ - .channel = _chan, \ - .scan_index = _si, \ - .scan_type = { \ - .sign = _sign, \ - .realbits = _bits, \ - .storagebits = 16, \ - .shift = 0, \ - }, \ - } - - -static const unsigned long ad9361_2x2_available_scan_masks[] = { - 0x01, 0x02, 0x04, 0x08, 0x03, 0x0C, /* 1 & 2 chan */ - 0x10, 0x20, 0x40, 0x80, 0x30, 0xC0, /* 1 & 2 chan */ - 0x33, 0xCC, 0xC3, 0x3C, 0x0F, 0xF0, /* 4 chan */ - 0xFF, /* 8 chan */ - 0x00, -}; - -static const unsigned long ad9361_available_scan_masks[] = { - 0x01, 0x02, 0x04, 0x08, 0x03, 0x0C, 0x0F, - 0x00, -}; - -static const struct axiadc_chip_info axiadc_chip_info_tbl[] = { - [ID_AD9361] = { - .name = "AD9361", - .max_rate = 61440000UL, - .max_testmode = 0, - .num_channels = 4, - .scan_masks = ad9361_available_scan_masks, - .channel[0] = AIM_CHAN(0, 0, 12, 'S'), - .channel[1] = AIM_CHAN(1, 1, 12, 'S'), - .channel[2] = AIM_CHAN(2, 2, 12, 'S'), - .channel[3] = AIM_CHAN(3, 3, 12, 'S'), - }, - [ID_AD9361_2] = { /* MCS/MIMO 2x AD9361 */ - .name = "AD9361-2", - .max_rate = 61440000UL, - .max_testmode = 0, - .num_channels = 8, - .num_shadow_slave_channels = 4, - .scan_masks = ad9361_2x2_available_scan_masks, - .channel[0] = AIM_CHAN(0, 0, 12, 'S'), - .channel[1] = AIM_CHAN(1, 1, 12, 'S'), - .channel[2] = AIM_CHAN(2, 2, 12, 'S'), - .channel[3] = AIM_CHAN(3, 3, 12, 'S'), - .channel[4] = AIM_MC_CHAN(4, 4, 12, 'S'), - .channel[5] = AIM_MC_CHAN(5, 5, 12, 'S'), - .channel[6] = AIM_MC_CHAN(6, 6, 12, 'S'), - .channel[7] = AIM_MC_CHAN(7, 7, 12, 'S'), - }, - [ID_AD9364] = { - .name = "AD9364", - .max_rate = 61440000UL, - .max_testmode = 0, - .num_channels = 2, - .channel[0] = AIM_CHAN(0, 0, 12, 'S'), - .channel[1] = AIM_CHAN(1, 1, 12, 'S'), - }, - -}; - -static int ad9361_read_raw(struct iio_dev *indio_dev, - struct iio_chan_spec const *chan, - int *val, - int *val2, - long m) -{ - struct axiadc_converter *conv = iio_device_get_drvdata(indio_dev); - - switch (m) { - case IIO_CHAN_INFO_SAMP_FREQ: - if (!conv->clk) - return -ENODEV; - - *val = conv->adc_clk = clk_get_rate(conv->clk); - - return IIO_VAL_INT; - - } - return -EINVAL; -} - -static int ad9361_write_raw(struct iio_dev *indio_dev, - struct iio_chan_spec const *chan, - int val, - int val2, - long mask) -{ - struct axiadc_converter *conv = iio_device_get_drvdata(indio_dev); - unsigned long r_clk; - int ret; - - switch (mask) { - case IIO_CHAN_INFO_SAMP_FREQ: - if (!conv->clk) - return -ENODEV; - - if (chan->extend_name) - return -ENODEV; - - r_clk = clk_round_rate(conv->clk, val); - if (r_clk < 0 || r_clk > conv->chip_info->max_rate) { - dev_warn(&conv->spi->dev, - "Error setting ADC sample rate %ld", r_clk); - return -EINVAL; - } - - ret = clk_set_rate(conv->clk, r_clk); - if (ret < 0) - return ret; - - return 0; - break; - default: - return -EINVAL; - } - - return 0; -} - -int ad9361_hdl_loopback(struct ad9361_rf_phy *phy, bool enable) -{ - struct axiadc_converter *conv = spi_get_drvdata(phy->spi); - struct axiadc_state *st; - unsigned reg, addr, chan, version; - - if (!conv) - return -ENODEV; - - st = iio_priv(conv->indio_dev); - version = axiadc_read(st, 0x4000); - - /* Still there but implemented a bit different */ - if (ADI_AXI_PCORE_VER_MAJOR(version) > 7) - addr = 0x4418; - else - addr = 0x4414; - - for (chan = 0; chan < conv->chip_info->num_channels; chan++) { - reg = axiadc_read(st, addr + (chan) * 0x40); - - if (ADI_AXI_PCORE_VER_MAJOR(version) > 7) { - if (enable) { - if (reg != 0x8) { - conv->scratch_reg[chan] = reg; - reg = 0x8; - } - } else if (reg == 0x8) { - reg = conv->scratch_reg[chan]; - } - } else { - /* DAC_LB_ENB If set enables loopback of receive data */ - if (enable) - reg |= BIT(1); - else - reg &= ~BIT(1); - } - axiadc_write(st, addr + (chan) * 0x40, reg); - } - - return 0; -} -EXPORT_SYMBOL(ad9361_hdl_loopback); - -static int ad9361_iodelay_set(struct axiadc_state *st, unsigned lane, - unsigned val, bool tx) -{ - if (tx) { - if (ADI_AXI_PCORE_VER_MAJOR(st->pcore_version) > 8) - axiadc_write(st, 0x4000 + ADI_REG_DELAY(lane), val); - else - return -ENODEV; - } else { - axiadc_idelay_set(st, lane, val); - } - - return 0; -} - -static int ad9361_midscale_iodelay(struct ad9361_rf_phy *phy, bool tx) -{ - struct axiadc_converter *conv = spi_get_drvdata(phy->spi); - struct axiadc_state *st = iio_priv(conv->indio_dev); - int ret = 0, i; - - for (i = 0; i < 7; i++) - ret |= ad9361_iodelay_set(st, i, 15, tx); - - return 0; -} - -static int ad9361_dig_tune_iodelay(struct ad9361_rf_phy *phy, bool tx) -{ - struct axiadc_converter *conv = spi_get_drvdata(phy->spi); - struct axiadc_state *st = iio_priv(conv->indio_dev); - int i, j; - u32 s0, c0; - u8 field[32]; - - for (i = 0; i < 7; i++) { - for (j = 0; j < 32; j++) { - ad9361_iodelay_set(st, i, j, tx); - mdelay(1); - field[j] = ad9361_check_pn(conv, tx, 10); - } - - c0 = ad9361_find_opt(&field[0], 32, &s0); - ad9361_iodelay_set(st, i, s0 + c0 / 2, tx); - - dev_info(&phy->spi->dev, - "%s Lane %d, window cnt %d , start %d, IODELAY set to %d\n", - tx ? "TX" :"RX", i , c0, s0, s0 + c0 / 2); - - } - - return 0; -} - -static void ad9361_dig_tune_verbose_print(struct ad9361_rf_phy *phy, - u8 field[][16], bool tx, - int sel_clk, int sel_data) -{ - int i, j; - char c; - - pr_info("SAMPL CLK: %lu tuning: %s\n", - clk_get_rate(phy->clks[RX_SAMPL_CLK]), tx ? "TX" : "RX"); - pr_info(" "); - for (i = 0; i < 16; i++) - pr_cont("%x:", i); - pr_cont("\n"); - - for (i = 0; i < 2; i++) { - pr_info("%x:", i); - for (j = 0; j < 16; j++) { - if (field[i][j]) - c = '#'; - else if ((i == 0 && j == sel_data) || - (i == 1 && j == sel_clk)) - c = 'O'; - else - c = 'o'; - pr_cont("%c ", c); - } - pr_cont("\n"); - } -} - -static int ad9361_dig_tune_delay(struct ad9361_rf_phy *phy, - unsigned long max_freq, - enum dig_tune_flags flags, bool tx) -{ - // static const unsigned int rates[3] = {25000000U, 40000000U, 61440000U}; - static const unsigned int rates[3] = {25000000U, 40000000U, 40000000U}; - struct axiadc_converter *conv = spi_get_drvdata(phy->spi); - unsigned int s0, s1, c0, c1; - unsigned int i, j, r; - bool half_data_rate; - u8 field[2][16]; - - if (ad9361_uses_lvds_mode(phy) || !ad9361_uses_rx2tx2(phy)) - half_data_rate = false; - else - half_data_rate = true; - - memset(field, 0, 32); - for (r = 0; r < (max_freq ? ARRAY_SIZE(rates) : 1); r++) { - if (max_freq) - ad9361_set_trx_clock_chain_freq(phy, - half_data_rate ? rates[r] / 2 : rates[r]); - - for (i = 0; i < 2; i++) { - for (j = 0; j < 16; j++) { - /* - * i == 0: clock delay = 0, data delay from 0 to 15 - * i == 1: clock delay = 15, data delay from 15 to 0 - */ - ad9361_set_intf_delay(phy, tx, i ? 15 : 0, - i ? 15 - j : j, j == 0); - field[i][j] |= ad9361_check_pn(conv, tx, 4); - } - } - - if ((flags & BE_MOREVERBOSE) && max_freq) { - ad9361_dig_tune_verbose_print(phy, field, tx, -1, -1); - } - } - - c0 = ad9361_find_opt(&field[0][0], 16, &s0); - c1 = ad9361_find_opt(&field[1][0], 16, &s1); - - if (!c0 && !c1) { - ad9361_dig_tune_verbose_print(phy, field, tx, -1, -1); - dev_err(&phy->spi->dev, "%s: Tuning %s FAILED!", __func__, - tx ? "TX" : "RX"); - return -EIO; - } else if (flags & BE_VERBOSE) { - ad9361_dig_tune_verbose_print(phy, field, tx, - c1 > c0 ? (s1 + c1 / 2) : -1, - c1 > c0 ? -1 : (s0 + c0 / 2)); - } - - if (c1 > c0) - ad9361_set_intf_delay(phy, tx, s1 + c1 / 2, 0, true); - else - ad9361_set_intf_delay(phy, tx, 0, s0 + c0 / 2, true); - - return 0; -} - -static int ad9361_dig_tune_rx(struct ad9361_rf_phy *phy, unsigned long max_freq, - enum dig_tune_flags flags) -{ - struct axiadc_converter *conv = spi_get_drvdata(phy->spi); - struct axiadc_state *st = iio_priv(conv->indio_dev); - int ret; - - ad9361_bist_loopback(phy, 0); - ad9361_bist_prbs(phy, BIST_INJ_RX); - - ret = ad9361_dig_tune_delay(phy, max_freq, flags, false); - if (flags & DO_IDELAY) - ad9361_dig_tune_iodelay(phy, false); - - axiadc_write(st, ADI_REG_RSTN, ADI_MMCM_RSTN); - axiadc_write(st, ADI_REG_RSTN, ADI_RSTN | ADI_MMCM_RSTN); - - return ret; -} - -static int ad9361_dig_tune_tx(struct ad9361_rf_phy *phy, unsigned long max_freq, - enum dig_tune_flags flags) -{ - struct axiadc_converter *conv = spi_get_drvdata(phy->spi); - struct axiadc_state *st = iio_priv(conv->indio_dev); - u32 saved_dsel[4], saved_chan_ctrl6[4], saved_chan_ctrl0[4]; - unsigned int chan, num_chan; - unsigned int hdl_dac_version; - u32 tmp, saved = 0; - int ret; - - num_chan = ad9361_num_phy_chan(conv); - hdl_dac_version = axiadc_read(st, 0x4000); - - ad9361_bist_prbs(phy, BIST_DISABLE); - ad9361_bist_loopback(phy, 1); - axiadc_write(st, 0x4000 + ADI_REG_RSTN, ADI_RSTN | ADI_MMCM_RSTN); - - for (chan = 0; chan < num_chan; chan++) { - saved_chan_ctrl0[chan] = axiadc_read(st, ADI_REG_CHAN_CNTRL(chan)); - axiadc_write(st, ADI_REG_CHAN_CNTRL(chan), - ADI_FORMAT_SIGNEXT | ADI_FORMAT_ENABLE | - ADI_ENABLE | ADI_IQCOR_ENB); - axiadc_set_pnsel(st, chan, ADC_PN_CUSTOM); - saved_chan_ctrl6[chan] = axiadc_read(st, 0x4414 + (chan) * 0x40); - if (ADI_AXI_PCORE_VER_MAJOR(hdl_dac_version) > 7) { - saved_dsel[chan] = axiadc_read(st, 0x4418 + (chan) * 0x40); - axiadc_write(st, 0x4418 + (chan) * 0x40, 9); - axiadc_write(st, 0x4414 + (chan) * 0x40, 0); /* !IQCOR_ENB */ - axiadc_write(st, 0x4044, 1); - } else { - axiadc_write(st, 0x4414 + (chan) * 0x40, 1); /* DAC_PN_ENB */ - } - } - if (ADI_AXI_PCORE_VER_MAJOR(hdl_dac_version) < 8) { - saved = tmp = axiadc_read(st, 0x4048); - tmp &= ~0xF; - tmp |= 1; - axiadc_write(st, 0x4048, tmp); - } - - ret = ad9361_dig_tune_delay(phy, max_freq, flags, true); - if (flags & DO_ODELAY) - ad9361_dig_tune_iodelay(phy, true); - - if (ADI_AXI_PCORE_VER_MAJOR(hdl_dac_version) < 8) - axiadc_write(st, 0x4048, saved); - - for (chan = 0; chan < num_chan; chan++) { - axiadc_write(st, ADI_REG_CHAN_CNTRL(chan), - saved_chan_ctrl0[chan]); - axiadc_set_pnsel(st, chan, ADC_PN9); - if (ADI_AXI_PCORE_VER_MAJOR(hdl_dac_version) > 7) { - axiadc_write(st, 0x4418 + chan * 0x40, - saved_dsel[chan]); - axiadc_write(st, 0x4044, 1); - } - - axiadc_write(st, 0x4414 + chan * 0x40, saved_chan_ctrl6[chan]); - } - - return ret; -} - -int ad9361_dig_tune(struct ad9361_rf_phy *phy, unsigned long max_freq, - enum dig_tune_flags flags) -{ - struct axiadc_converter *conv = spi_get_drvdata(phy->spi); - struct ad9361_dig_tune_data data; - struct axiadc_state *st; - bool restore = false; - int ret = 0; - - if (!conv) - return -ENODEV; - - ret = ad9361_get_dig_tune_data(phy, &data); - if (ret < 0) - return ret; - - dev_dbg(&phy->spi->dev, "%s: freq %lu flags 0x%X\n", __func__, - max_freq, flags); - - st = iio_priv(conv->indio_dev); - - if ((data.skip_mode == SKIP_ALL) || - (flags & RESTORE_DEFAULT)) { - /* skip completely and use defaults */ - restore = true; - } else { - /* Mute TX, we don't want to transmit the PRBS */ - ad9361_tx_mute(phy, 1); - - ad9361_ensm_mode_disable_pinctrl(phy); - - if (flags & DO_IDELAY) - ad9361_midscale_iodelay(phy, false); - - if (flags & DO_ODELAY) - ad9361_midscale_iodelay(phy, true); - - ret = ad9361_dig_tune_rx(phy, max_freq, flags); - if (ret == 0 && (data.skip_mode == TUNE_RX_TX)) - ret = ad9361_dig_tune_tx(phy, max_freq, flags); - - ad9361_bist_loopback(phy, data.bist_loopback_mode); - ad9361_write_bist_reg(phy, data.bist_config); - - if (ret == -EIO) - restore = true; - if (!max_freq) - ret = 0; - } - - if (restore) { - ad9361_ensm_force_state(phy, ENSM_STATE_ALERT); - ad9361_write_clock_data_delays(phy); - } else if (!(flags & SKIP_STORE_RESULT)) { - ad9361_read_clock_data_delays(phy); - } - - ad9361_ensm_mode_restore_pinctrl(phy); - ad9361_ensm_restore_state(phy, data.ensm_state); - - axiadc_write(st, ADI_REG_RSTN, ADI_MMCM_RSTN); - axiadc_write(st, ADI_REG_RSTN, ADI_RSTN | ADI_MMCM_RSTN); - - ad9361_tx_mute(phy, 0); - - return ret; -} -EXPORT_SYMBOL(ad9361_dig_tune); - -static int ad9361_post_setup(struct iio_dev *indio_dev) -{ - struct axiadc_state *st = iio_priv(indio_dev); - struct axiadc_converter *conv = iio_device_get_drvdata(indio_dev); - struct ad9361_rf_phy *phy = conv->phy; - bool rx2tx2 = ad9361_uses_rx2tx2(phy); - unsigned tmp, num_chan, flags; - int i, ret; - - num_chan = ad9361_num_phy_chan(conv); - - conv->indio_dev = indio_dev; - axiadc_write(st, ADI_REG_CNTRL, rx2tx2 ? 0 : ADI_R1_MODE); - tmp = axiadc_read(st, 0x4048); - - if (!rx2tx2) { - axiadc_write(st, 0x4048, tmp | BIT(5)); /* R1_MODE */ - axiadc_write(st, 0x404c, - ad9361_uses_lvds_mode(phy) ? 1 : 0); /* RATE */ - } else { - tmp &= ~BIT(5); - axiadc_write(st, 0x4048, tmp); - axiadc_write(st, 0x404c, - ad9361_uses_lvds_mode(phy) ? 3 : 1); /* RATE */ - } - - for (i = 0; i < num_chan; i++) { - axiadc_write(st, ADI_REG_CHAN_CNTRL_1(i), - ADI_DCFILT_OFFSET(0)); - axiadc_write(st, ADI_REG_CHAN_CNTRL_2(i), - (i & 1) ? 0x00004000 : 0x40000000); - axiadc_write(st, ADI_REG_CHAN_CNTRL(i), - ADI_FORMAT_SIGNEXT | ADI_FORMAT_ENABLE | - ADI_ENABLE | ADI_IQCOR_ENB); - } - - flags = 0; - - ret = ad9361_dig_tune(phy, (axiadc_read(st, ADI_AXI_REG_ID)) ? - 0 : 61440000, flags); - if (ret < 0) - goto error; - - if (flags & (DO_IDELAY | DO_ODELAY)) { - ret = ad9361_dig_tune(phy, (axiadc_read(st, ADI_AXI_REG_ID)) ? - 0 : 61440000, flags & BE_VERBOSE); - if (ret < 0) - goto error; - } - - ret = ad9361_set_trx_clock_chain_default(phy); - - ad9361_ensm_force_state(phy, ENSM_STATE_ALERT); - ad9361_ensm_restore_prev_state(phy); - - return 0; - -error: - spi_set_drvdata(phy->spi, NULL); - return ret; -} - -int ad9361_register_axi_converter(struct ad9361_rf_phy *phy) -{ - struct axiadc_converter *conv; - struct spi_device *spi = phy->spi; - int ret; - - conv = devm_kzalloc(&spi->dev, sizeof(*conv), GFP_KERNEL); - if (conv == NULL) - return -ENOMEM; - - conv->id = ad9361_spi_read(spi, REG_PRODUCT_ID) & PRODUCT_ID_MASK; - if (conv->id != PRODUCT_ID_9361) { - dev_err(&spi->dev, "Unrecognized CHIP_ID 0x%X\n", conv->id); - ret = -ENODEV; - goto out; - } - - conv->chip_info = &axiadc_chip_info_tbl[ - (spi_get_device_id(spi)->driver_data == ID_AD9361_2) ? - ID_AD9361_2 : ad9361_uses_rx2tx2(phy) ? ID_AD9361 : ID_AD9364]; - conv->write_raw = ad9361_write_raw; - conv->read_raw = ad9361_read_raw; - conv->post_setup = ad9361_post_setup; - conv->spi = spi; - conv->phy = phy; - - conv->clk = phy->clks[RX_SAMPL_CLK]; - conv->adc_clk = clk_get_rate(conv->clk); - - spi_set_drvdata(spi, conv); /* Take care here */ - - return 0; -out: - spi_set_drvdata(spi, NULL); - return ret; -} -EXPORT_SYMBOL(ad9361_register_axi_converter); - -struct ad9361_rf_phy* ad9361_spi_to_phy(struct spi_device *spi) -{ - struct axiadc_converter *conv = spi_get_drvdata(spi); - return conv->phy; -} -EXPORT_SYMBOL(ad9361_spi_to_phy); - -#else /* CONFIG_CF_AXI_ADC */ - -int ad9361_dig_tune(struct ad9361_rf_phy *phy, unsigned long max_freq, - enum dig_tune_flags flags) -{ - return -ENODEV; -} -EXPORT_SYMBOL(ad9361_dig_tune); - -ssize_t ad9361_dig_interface_timing_analysis(struct ad9361_rf_phy *phy, - char *buf, unsigned buflen) -{ - return 0; -} -EXPORT_SYMBOL(ad9361_dig_interface_timing_analysis); - -int ad9361_hdl_loopback(struct ad9361_rf_phy *phy, bool enable) -{ - return -ENODEV; -} -EXPORT_SYMBOL(ad9361_hdl_loopback); - -int ad9361_register_axi_converter(struct ad9361_rf_phy *phy) -{ - struct spi_device *spi = phy->spi; - spi_set_drvdata(spi, phy); /* Take care here */ - - return 0; -} -EXPORT_SYMBOL(ad9361_register_axi_converter); - -struct ad9361_rf_phy* ad9361_spi_to_phy(struct spi_device *spi) -{ - return spi_get_drvdata(spi); -} -EXPORT_SYMBOL(ad9361_spi_to_phy); - -#endif /* CONFIG_CF_AXI_ADC */ diff --git a/driver/hw_def.h b/driver/hw_def.h index 9c9b324..d77d6a4 100644 --- a/driver/hw_def.h +++ b/driver/hw_def.h @@ -205,6 +205,7 @@ const char *openofdm_rx_compatible_str = "sdr,openofdm_rx"; #define OPENOFDM_RX_REG_POWER_THRES_ADDR (2*4) #define OPENOFDM_RX_REG_MIN_PLATEAU_ADDR (3*4) #define OPENOFDM_RX_REG_SOFT_DECODING_ADDR (4*4) +#define OPENOFDM_RX_REG_FFT_WIN_SHIFT_ADDR (5*4) #define OPENOFDM_RX_REG_STATE_HISTORY_ADDR (20*4) enum openofdm_rx_mode { @@ -236,11 +237,16 @@ enum openofdm_rx_mode { // 11a/g BPSK 6m, Rx sensitivity level dmesg report -86dBm // priv->rssi_correction = 148; rssi_half_db/2 = 148-86=62; rssi_half_db = 124 -#define OPENOFDM_RX_RSSI_DBM_TH_DEFAULT (-84) +#define OPENOFDM_RX_RSSI_DBM_TH_DEFAULT (-85) //-85 will remove lots of false alarm. the best openwifi reported sensitivity is like -90/-92 (set it manually if conductive test with wifi tester) #define OPENOFDM_RX_DC_RUNNING_SUM_TH_INIT 64 #define OPENOFDM_RX_MIN_PLATEAU_INIT 100 +#define OPENOFDM_RX_FFT_WIN_SHIFT_INIT 1 +#define OPENOFDM_RX_SMALL_EQ_OUT_COUNTER_TH 48 -#define OPENWIFI_MAX_SIGNAL_LEN_TH 1700 //Packet longer than this threshold will result in receiver early termination. It goes to openofdm_rx/xpu/rx_intf +#define OPENWIFI_MAX_SIGNAL_LEN_TH 1700 //Packet longer than this threshold will result in receiver early termination. It goes to openofdm_rx/xpu/rx_intf + +#define OPENWIFI_MIN_SIGNAL_LEN_TH 14 //Packet shorter than this threshold will result in receiver early termination. It goes to openofdm_rx/xpu/rx_intf + //due to CRC32, at least 4 bytes needed to push out expected CRC result struct openofdm_rx_driver_api { u32 (*hw_init)(enum openofdm_rx_mode mode); @@ -255,6 +261,7 @@ struct openofdm_rx_driver_api { void (*OPENOFDM_RX_REG_POWER_THRES_write)(u32 value); void (*OPENOFDM_RX_REG_MIN_PLATEAU_write)(u32 value); void (*OPENOFDM_RX_REG_SOFT_DECODING_write)(u32 value); + void (*OPENOFDM_RX_REG_FFT_WIN_SHIFT_write)(u32 value); }; // ---------------------------------------openofdm tx------------------------------- @@ -310,9 +317,9 @@ const char *xpu_compatible_str = "sdr,xpu"; #define XPU_REG_SEND_ACK_WAIT_TOP_ADDR (18*4) #define XPU_REG_CSMA_CFG_ADDR (19*4) -#define XPU_REG_SLICE_COUNT_TOTAL_ADDR (20*4) -#define XPU_REG_SLICE_COUNT_START_ADDR (21*4) -#define XPU_REG_SLICE_COUNT_END_ADDR (22*4) +#define XPU_REG_SLICE_COUNT_TOTAL_ADDR (20*4) +#define XPU_REG_SLICE_COUNT_START_ADDR (21*4) +#define XPU_REG_SLICE_COUNT_END_ADDR (22*4) #define XPU_REG_CTS_TO_RTS_CONFIG_ADDR (26*4) #define XPU_REG_FILTER_FLAG_ADDR (27*4) @@ -321,26 +328,11 @@ const char *xpu_compatible_str = "sdr,xpu"; #define XPU_REG_MAC_ADDR_LOW_ADDR (30*4) #define XPU_REG_MAC_ADDR_HIGH_ADDR (31*4) -#define XPU_REG_FC_DI_ADDR (34*4) -#define XPU_REG_ADDR1_LOW_ADDR (35*4) -#define XPU_REG_ADDR1_HIGH_ADDR (36*4) -#define XPU_REG_ADDR2_LOW_ADDR (37*4) -#define XPU_REG_ADDR2_HIGH_ADDR (38*4) -#define XPU_REG_ADDR3_LOW_ADDR (39*4) -#define XPU_REG_ADDR3_HIGH_ADDR (40*4) - -#define XPU_REG_SC_LOW_ADDR (41*4) -#define XPU_REG_ADDR4_HIGH_ADDR (42*4) -#define XPU_REG_ADDR4_LOW_ADDR (43*4) - -#define XPU_REG_TRX_STATUS_ADDR (50*4) -#define XPU_REG_TX_RESULT_ADDR (51*4) - #define XPU_REG_TSF_RUNTIME_VAL_LOW_ADDR (58*4) #define XPU_REG_TSF_RUNTIME_VAL_HIGH_ADDR (59*4) -#define XPU_REG_RSSI_HALF_DB_ADDR (60*4) -#define XPU_REG_IQ_RSSI_HALF_DB_ADDR (61*4) +#define XPU_REG_MAC_ADDR_READ_BACK_ADDR (62*4) +#define XPU_REG_FPGA_GIT_REV_ADDR (63*4) enum xpu_mode { XPU_TEST = 0, diff --git a/driver/make_all.sh b/driver/make_all.sh index 33d9d38..7ba0fcc 100755 --- a/driver/make_all.sh +++ b/driver/make_all.sh @@ -31,7 +31,7 @@ else exit 1 fi -if [ -d "$XILINX_DIR/SDK" ]; then +if [ -d "$XILINX_DIR/Vitis" ]; then echo "\$XILINX_DIR is found!" else echo "\$XILINX_DIR is not correct. Please check!" @@ -72,7 +72,7 @@ if [[ -n $7 ]]; then echo "#define $DEFINE5" >> pre_def.h fi -source $XILINX_DIR/SDK/2018.3/settings64.sh +source $XILINX_DIR/Vitis/2021.1/settings64.sh if [ "$ARCH_OPTION" == "64" ]; then LINUX_KERNEL_SRC_DIR=$OPENWIFI_DIR/adi-linux-64/ ARCH="arm64" @@ -85,7 +85,7 @@ fi # check if user entered the right path to analog device linux if [ -d "$LINUX_KERNEL_SRC_DIR" ]; then - echo " setup linux kernel path ${LINUX_KERNEL_SRC_DIR}" + echo "setup linux kernel path ${LINUX_KERNEL_SRC_DIR}" else echo "Error: path to adi linux: ${LINUX_KERNEL_SRC_DIR} not found. Can not continue." exit 1 @@ -101,7 +101,6 @@ if git log -1; then else echo "#define GIT_REV 0xFFFFFFFF" > git_rev.h fi -make KDIR=$LINUX_KERNEL_SRC_DIR ARCH=$ARCH CROSS_COMPILE=$CROSS_COMPILE cd $OPENWIFI_DIR/driver/openofdm_tx make KDIR=$LINUX_KERNEL_SRC_DIR ARCH=$ARCH CROSS_COMPILE=$CROSS_COMPILE cd $OPENWIFI_DIR/driver/openofdm_rx @@ -115,4 +114,10 @@ make KDIR=$LINUX_KERNEL_SRC_DIR ARCH=$ARCH CROSS_COMPILE=$CROSS_COMPILE # cd $OPENWIFI_DIR/driver/ad9361 # make KDIR=$LINUX_KERNEL_SRC_DIR ARCH=$ARCH CROSS_COMPILE=$CROSS_COMPILE +cd $OPENWIFI_DIR/driver/side_ch +./make_driver.sh $XILINX_DIR $ARCH_OPTION + +cd $OPENWIFI_DIR/driver/ +make KDIR=$LINUX_KERNEL_SRC_DIR ARCH=$ARCH CROSS_COMPILE=$CROSS_COMPILE + cd $home_dir diff --git a/driver/openofdm_rx/openofdm_rx.c b/driver/openofdm_rx/openofdm_rx.c index cb93a5e..0a14f92 100644 --- a/driver/openofdm_rx/openofdm_rx.c +++ b/driver/openofdm_rx/openofdm_rx.c @@ -55,6 +55,9 @@ static inline void OPENOFDM_RX_REG_MIN_PLATEAU_write(u32 Data) { static inline void OPENOFDM_RX_REG_SOFT_DECODING_write(u32 Data) { reg_write(OPENOFDM_RX_REG_SOFT_DECODING_ADDR, Data); } +static inline void OPENOFDM_RX_REG_FFT_WIN_SHIFT_write(u32 Data) { + reg_write(OPENOFDM_RX_REG_FFT_WIN_SHIFT_ADDR, Data); +} static const struct of_device_id dev_of_ids[] = { { .compatible = "sdr,openofdm_rx", }, {} @@ -93,7 +96,8 @@ static inline u32 hw_init(enum openofdm_rx_mode mode){ // 1) power threshold configuration and reset openofdm_rx_api->OPENOFDM_RX_REG_POWER_THRES_write((OPENOFDM_RX_DC_RUNNING_SUM_TH_INIT<<16)|OPENOFDM_RX_POWER_THRES_INIT); // turn on signal watchdog by default openofdm_rx_api->OPENOFDM_RX_REG_MIN_PLATEAU_write(OPENOFDM_RX_MIN_PLATEAU_INIT); - openofdm_rx_api->OPENOFDM_RX_REG_SOFT_DECODING_write((OPENWIFI_MAX_SIGNAL_LEN_TH<<16)|1); //bit1 enable soft decoding; bit31~16 max pkt length threshold + openofdm_rx_api->OPENOFDM_RX_REG_SOFT_DECODING_write((OPENWIFI_MAX_SIGNAL_LEN_TH<<16)|(OPENWIFI_MIN_SIGNAL_LEN_TH<<12)|1); //bit1 enable soft decoding; bit15~12 min pkt length threshold; bit31~16 max pkt length threshold + openofdm_rx_api->OPENOFDM_RX_REG_FFT_WIN_SHIFT_write((OPENOFDM_RX_SMALL_EQ_OUT_COUNTER_TH<<4)|OPENOFDM_RX_FFT_WIN_SHIFT_INIT); //rst for (i=0;i<8;i++) @@ -139,6 +143,7 @@ static int dev_probe(struct platform_device *pdev) openofdm_rx_api->OPENOFDM_RX_REG_POWER_THRES_write=OPENOFDM_RX_REG_POWER_THRES_write; openofdm_rx_api->OPENOFDM_RX_REG_MIN_PLATEAU_write=OPENOFDM_RX_REG_MIN_PLATEAU_write; openofdm_rx_api->OPENOFDM_RX_REG_SOFT_DECODING_write=OPENOFDM_RX_REG_SOFT_DECODING_write; + openofdm_rx_api->OPENOFDM_RX_REG_FFT_WIN_SHIFT_write=OPENOFDM_RX_REG_FFT_WIN_SHIFT_write; /* Request and map I/O memory */ io = platform_get_resource(pdev, IORESOURCE_MEM, 0); diff --git a/driver/sdr.c b/driver/sdr.c index e1a6854..8c93f7b 100644 --- a/driver/sdr.c +++ b/driver/sdr.c @@ -44,6 +44,8 @@ #include #include +// #include + #define IIO_AD9361_USE_PRIVATE_H_ #include <../../drivers/iio/adc/ad9361_regs.h> #include <../../drivers/iio/adc/ad9361.h> @@ -174,22 +176,23 @@ inline int rssi_correction_lookup_table(u32 freq_MHz) inline void ad9361_tx_calibration(struct openwifi_priv *priv, u32 actual_tx_lo) { - struct timeval tv; - unsigned long time_before = 0; - unsigned long time_after = 0; + // struct timespec64 tv; + // unsigned long time_before = 0; + // unsigned long time_after = 0; u32 spi_disable; priv->last_tx_quad_cal_lo = actual_tx_lo; - do_gettimeofday(&tv); - time_before = tv.tv_usec + ((u64)1000000ull)*((u64)tv.tv_sec ); + // do_gettimeofday(&tv); + // time_before = tv.tv_usec + ((u64)1000000ull)*((u64)tv.tv_sec ); spi_disable = xpu_api->XPU_REG_SPI_DISABLE_read(); // backup current fpga spi disable state xpu_api->XPU_REG_SPI_DISABLE_write(1); // disable FPGA SPI module ad9361_do_calib_run(priv->ad9361_phy, TX_QUAD_CAL, (int)priv->ad9361_phy->state->last_tx_quad_cal_phase); xpu_api->XPU_REG_SPI_DISABLE_write(spi_disable); // restore original SPI disable state - do_gettimeofday(&tv); - time_after = tv.tv_usec + ((u64)1000000ull)*((u64)tv.tv_sec ); + // do_gettimeofday(&tv); + // time_after = tv.tv_usec + ((u64)1000000ull)*((u64)tv.tv_sec ); - printk("%s ad9361_tx_calibration %dMHz tx_quad_cal duration %lu us\n", sdr_compatible_str, actual_tx_lo, time_after-time_before); + // printk("%s ad9361_tx_calibration %dMHz tx_quad_cal duration %lu us\n", sdr_compatible_str, actual_tx_lo, time_after-time_before); + printk("%s ad9361_tx_calibration %dMHz tx_quad_cal duration unknown us\n", sdr_compatible_str, actual_tx_lo); } inline void openwifi_rf_rx_update_after_tuning(struct openwifi_priv *priv, u32 actual_rx_lo) @@ -200,10 +203,7 @@ inline void openwifi_rf_rx_update_after_tuning(struct openwifi_priv *priv, u32 a priv->rssi_correction = rssi_correction_lookup_table(actual_rx_lo); // set appropriate lbt threshold - // xpu_api->XPU_REG_LBT_TH_write((priv->rssi_correction-62)<<1); // -62dBm - // xpu_api->XPU_REG_LBT_TH_write((priv->rssi_correction-62-16)<<1); // wei's magic value is 135, here is 134 @ ch 44 - // auto_lbt_th = ((priv->rssi_correction-62-16)<<1); - auto_lbt_th = rssi_dbm_to_rssi_half_db(-78, priv->rssi_correction); // -78dBm, the same as above ((priv->rssi_correction-62-16)<<1) + auto_lbt_th = rssi_dbm_to_rssi_half_db(-62, priv->rssi_correction); // -62dBm static_lbt_th = rssi_dbm_to_rssi_half_db(-(priv->drv_xpu_reg_val[DRV_XPU_REG_IDX_LBT_TH]), priv->rssi_correction); fpga_lbt_th = (priv->drv_xpu_reg_val[DRV_XPU_REG_IDX_LBT_TH]==0?auto_lbt_th:static_lbt_th); xpu_api->XPU_REG_LBT_TH_write(fpga_lbt_th); @@ -1097,7 +1097,8 @@ static void openwifi_tx(struct ieee80211_hw *dev, if (use_ht_aggr && rate_hw_value==0) rate_hw_value = 1; - sifs = (priv->actual_rx_lo<2500?10:16); + // sifs = (priv->actual_rx_lo<2500?10:16); + sifs = 16; // for ofdm, sifs is always 16 if (use_ht_rate) { // printk("%s openwifi_tx: rate_hw_value %d aggr %d sifs %d\n", sdr_compatible_str, rate_hw_value, use_ht_aggr, sifs); @@ -1569,18 +1570,24 @@ static int openwifi_start(struct ieee80211_hw *dev) rx_intf_api->RX_INTF_REG_INTERRUPT_TEST_write(0x100); // disable rx interrupt by interrupt test mode rx_intf_api->RX_INTF_REG_M_AXIS_RST_write(1); // hold M AXIS in reset status - priv->rx_chan = dma_request_slave_channel(&(priv->pdev->dev), "rx_dma_s2mm"); + // priv->rx_chan = dma_request_slave_channel(&(priv->pdev->dev), "rx_dma_s2mm"); + priv->rx_chan = dma_request_chan(&(priv->pdev->dev), "rx_dma_s2mm"); if (IS_ERR(priv->rx_chan) || priv->rx_chan==NULL) { ret = PTR_ERR(priv->rx_chan); - pr_err("%s openwifi_start: No Rx channel ret %d priv->rx_chan 0x%p\n",sdr_compatible_str, ret, priv->rx_chan); - goto err_dma; + if (ret != -EPROBE_DEFER) { + pr_err("%s openwifi_start: No Rx channel ret %d priv->rx_chan 0x%p\n",sdr_compatible_str, ret, priv->rx_chan); + goto err_dma; + } } - priv->tx_chan = dma_request_slave_channel(&(priv->pdev->dev), "tx_dma_mm2s"); + // priv->tx_chan = dma_request_slave_channel(&(priv->pdev->dev), "tx_dma_mm2s"); + priv->tx_chan = dma_request_chan(&(priv->pdev->dev), "tx_dma_mm2s"); if (IS_ERR(priv->tx_chan) || priv->tx_chan==NULL) { ret = PTR_ERR(priv->tx_chan); - pr_err("%s openwifi_start: No Tx channel ret %d priv->tx_chan 0x%p\n",sdr_compatible_str, ret, priv->tx_chan); - goto err_dma; + if (ret != -EPROBE_DEFER) { + pr_err("%s openwifi_start: No Tx channel ret %d priv->tx_chan 0x%p\n",sdr_compatible_str, ret, priv->tx_chan); + goto err_dma; + } } printk("%s openwifi_start: DMA channel setup successfully. priv->rx_chan 0x%p priv->tx_chan 0x%p\n",sdr_compatible_str, priv->rx_chan, priv->tx_chan); @@ -2085,16 +2092,16 @@ static const struct of_device_id openwifi_dev_of_ids[] = { }; MODULE_DEVICE_TABLE(of, openwifi_dev_of_ids); -static int custom_match_spi_dev(struct device *dev, void *data) +static int custom_match_spi_dev(struct device *dev, const void *data) { - const char *name = data; + const char *name = data; bool ret = sysfs_streq(name, dev->of_node->name); printk("%s custom_match_spi_dev %s %s %d\n", sdr_compatible_str,name, dev->of_node->name, ret); return ret; } -static int custom_match_platform_dev(struct device *dev, void *data) +static int custom_match_platform_dev(struct device *dev, const void *data) { struct platform_device *plat_dev = to_platform_device(dev); const char *name = data; @@ -2440,7 +2447,6 @@ static int openwifi_dev_probe(struct platform_device *pdev) * is mapped on the highst tx ring IDX. */ dev->queues = MAX_NUM_HW_QUEUE; - //dev->queues = 1; ieee80211_hw_set(dev, SIGNAL_DBM); diff --git a/driver/sdr.h b/driver/sdr.h index 3923ebd..858007b 100644 --- a/driver/sdr.h +++ b/driver/sdr.h @@ -129,7 +129,10 @@ enum sdrctl_reg_cat { #define LEN_PHY_CRC 4 #define LEN_MPDU_DELIM 4 -#define RING_ROOM_THRESHOLD 2 +#define MAX_NUM_HW_QUEUE 4 // number of queue in FPGA +#define MAX_NUM_SW_QUEUE 4 // number of queue in Linux, depends on the number we report by dev->queues in openwifi_dev_probe + +#define RING_ROOM_THRESHOLD (2+MAX_NUM_SW_QUEUE) // MAX_NUM_SW_QUEUE is for the room of MAX_NUM_SW_QUEUE last packets from MAX_NUM_SW_QUEUE queue before stop #define NUM_BIT_NUM_TX_BD 6 #define NUM_TX_BD (1<queues in openwifi_dev_probe #define NUM_BIT_MAX_PHY_TX_SN 10 // decrease 12 to 10 to reserve 2 bits storing related linux prio idx #define MAX_PHY_TX_SN ((1<rssi_correction); xpu_api->XPU_REG_LBT_TH_write( tmp ); - printk("%s override FPGA LBT threshold to %d(%ddBm). The last_auto_fpga_lbt_th %d(%ddBm)\n", sdr_compatible_str, tmp, tmp_int, priv->last_auto_fpga_lbt_th, rssi_half_db_to_rssi_dbm(priv->last_auto_fpga_lbt_th, priv->rssi_correction)); + printk("%s override FPGA LBT threshold to %d(%ddBm). The last_auto_fpga_lbt_th %d(%ddBm). rssi corr %d (%d/%dMHz)\n", sdr_compatible_str, tmp, tmp_int, priv->last_auto_fpga_lbt_th, rssi_half_db_to_rssi_dbm(priv->last_auto_fpga_lbt_th, priv->rssi_correction), priv->rssi_correction, priv->actual_tx_lo, priv->actual_rx_lo); } else { xpu_api->XPU_REG_LBT_TH_write(priv->last_auto_fpga_lbt_th); - printk("%s Restore last_auto_fpga_lbt_th %d(%ddBm) to FPGA. ad9361_rf_set_channel will take control\n", sdr_compatible_str, priv->last_auto_fpga_lbt_th, rssi_half_db_to_rssi_dbm(priv->last_auto_fpga_lbt_th, priv->rssi_correction)); + printk("%s Restore last_auto_fpga_lbt_th %d(%ddBm) to FPGA. ad9361_rf_set_channel will take control. rssi corr %d (%d/%dMHz)\n", sdr_compatible_str, priv->last_auto_fpga_lbt_th, rssi_half_db_to_rssi_dbm(priv->last_auto_fpga_lbt_th, priv->rssi_correction), priv->rssi_correction, priv->actual_tx_lo, priv->actual_rx_lo); } } } else { @@ -412,7 +412,7 @@ static int openwifi_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif * if (reg_addr_idx==DRV_XPU_REG_IDX_LBT_TH) { tmp = xpu_api->XPU_REG_LBT_TH_read();//rssi_half_db tmp_int = rssi_half_db_to_rssi_dbm(tmp, priv->rssi_correction); //rssi_dbm - printk("%s FPGA LBT threshold %d(%ddBm). The last_auto_fpga_lbt_th %d(%ddBm)\n", sdr_compatible_str, tmp, tmp_int, priv->last_auto_fpga_lbt_th, rssi_half_db_to_rssi_dbm(priv->last_auto_fpga_lbt_th, priv->rssi_correction)); + printk("%s FPGA LBT threshold %d(%ddBm). The last_auto_fpga_lbt_th %d(%ddBm). rssi corr %d (%d/%dMHz)\n", sdr_compatible_str, tmp, tmp_int, priv->last_auto_fpga_lbt_th, rssi_half_db_to_rssi_dbm(priv->last_auto_fpga_lbt_th, priv->rssi_correction), priv->rssi_correction, priv->actual_tx_lo, priv->actual_rx_lo); } tmp = priv->drv_xpu_reg_val[reg_addr_idx]; } else { diff --git a/driver/side_ch/make_driver.sh b/driver/side_ch/make_driver.sh index 77a1d7a..4e5f092 100755 --- a/driver/side_ch/make_driver.sh +++ b/driver/side_ch/make_driver.sh @@ -20,7 +20,7 @@ else exit 1 fi -if [ -d "$XILINX_DIR/SDK" ]; then +if [ -d "$XILINX_DIR/Vitis" ]; then echo "\$XILINX_DIR is found!" else echo "\$XILINX_DIR is not correct. Please check!" @@ -34,7 +34,7 @@ else echo "\$ARCH_OPTION is valid!" fi -source $XILINX_DIR/SDK/2018.3/settings64.sh +source $XILINX_DIR/Vitis/2021.1/settings64.sh if [ "$ARCH_OPTION" == "64" ]; then LINUX_KERNEL_SRC_DIR=$OPENWIFI_DIR/adi-linux-64/ ARCH="arm64" diff --git a/driver/side_ch/side_ch.c b/driver/side_ch/side_ch.c index 98d6160..7892f09 100644 --- a/driver/side_ch/side_ch.c +++ b/driver/side_ch/side_ch.c @@ -599,11 +599,13 @@ static int dev_probe(struct platform_device *pdev) { // goto free_chan_to_pl; // } - chan_to_ps = dma_request_slave_channel(&(pdev->dev), "tx_dma_s2mm"); - if (IS_ERR(chan_to_ps)) { + chan_to_ps = dma_request_chan(&(pdev->dev), "tx_dma_s2mm"); + if (IS_ERR(chan_to_ps) || chan_to_ps==NULL) { err = PTR_ERR(chan_to_ps); - pr_err("%s dev_probe: No channel to PS. %d\n",side_ch_compatible_str,err); - goto free_chan_to_ps; + if (err != -EPROBE_DEFER) { + pr_err("%s dev_probe: No chan_to_ps ret %d chan_to_ps 0x%p\n",side_ch_compatible_str, err, chan_to_ps); + goto free_chan_to_ps; + } } printk("%s dev_probe: DMA channel setup successfully. chan_to_pl 0x%p chan_to_ps 0x%p\n",side_ch_compatible_str, chan_to_pl, chan_to_ps); diff --git a/driver/sysfs_intf.c b/driver/sysfs_intf.c index fe4dab0..1434f4c 100644 --- a/driver/sysfs_intf.c +++ b/driver/sysfs_intf.c @@ -990,10 +990,12 @@ static ssize_t csma_cfg0_show(struct device *input_dev, struct device_attribute reg_val = xpu_api->XPU_REG_FORCE_IDLE_MISC_read(); priv->stat.csma_cfg0 = reg_val; - return sprintf(buf, "nav_disable %d difs_disable %d eifs_disable %d cw_override %d cw override val %d wait_after_decode_top %d\n", + return sprintf(buf, "nav_disable %d difs_disable %d eifs_disable %d eifs_by_rx_fail_disable %d eifs_by_tx_fail_disable %d cw_override %d cw override val %d wait_after_decode_top %d\n", (reg_val>>31)&1, (reg_val>>30)&1, (reg_val>>29)&1, + (reg_val>>27)&1, + (reg_val>>26)&1, (reg_val>>28)&1, (reg_val>>16)&0xf, (reg_val>>0)&0xff); diff --git a/driver/tx_intf/tx_intf.c b/driver/tx_intf/tx_intf.c index ad60732..3e7c459 100644 --- a/driver/tx_intf/tx_intf.c +++ b/driver/tx_intf/tx_intf.c @@ -311,7 +311,7 @@ static inline u32 hw_init(enum tx_intf_mode mode, u32 tx_config, u32 num_dma_sym if (mode!=TX_INTF_AXIS_LOOP_BACK) { tx_intf_api->TX_INTF_REG_MULTI_RST_write(0); tx_intf_api->TX_INTF_REG_CSI_FUZZER_write(0); - tx_intf_api->TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write( ((16*10)<<16)|(10*10) );//high 16bit 5GHz; low 16 bit 2.4GHz. counter speed 10MHz is assumed + tx_intf_api->TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write( ((16*10)<<16)|(16*10) );//high 16bit 5GHz; low 16 bit 2.4GHz. counter speed 10MHz is assumed tx_intf_api->TX_INTF_REG_TX_CONFIG_write(tx_config); tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write(num_dma_symbol_to_ps); @@ -350,9 +350,9 @@ static inline u32 hw_init(enum tx_intf_mode mode, u32 tx_config, u32 num_dma_sym tx_intf_api->TX_INTF_REG_MULTI_RST_write(0); } - if (mode == TX_INTF_BYPASS) { - tx_intf_api->TX_INTF_REG_CFG_DATA_TO_ANT_write(0x100); //slv_reg10[8] - } + // if (mode == TX_INTF_BYPASS) { + // tx_intf_api->TX_INTF_REG_CFG_DATA_TO_ANT_write(0x100); //slv_reg10[8] -- bit 8 not used anymore. only bit0/1 are still reserved. + // } printk("%s hw_init err %d\n", tx_intf_compatible_str, err); return(err); diff --git a/driver/xpu/xpu.c b/driver/xpu/xpu.c index 00636b7..ef66055 100644 --- a/driver/xpu/xpu.c +++ b/driver/xpu/xpu.c @@ -150,14 +150,6 @@ static inline u32 XPU_REG_FORCE_IDLE_MISC_read(void){ return reg_read(XPU_REG_FORCE_IDLE_MISC_ADDR); } -static inline u32 XPU_REG_TRX_STATUS_read(void){ - return reg_read(XPU_REG_TRX_STATUS_ADDR); -} - -static inline u32 XPU_REG_TX_RESULT_read(void){ - return reg_read(XPU_REG_TX_RESULT_ADDR); -} - static inline u32 XPU_REG_TSF_RUNTIME_VAL_LOW_read(void){ return reg_read(XPU_REG_TSF_RUNTIME_VAL_LOW_ADDR); } @@ -180,34 +172,6 @@ static inline void XPU_REG_TSF_LOAD_VAL_write(u32 high_value, u32 low_value){ XPU_REG_TSF_LOAD_VAL_HIGH_write(high_value&(~0x80000000)); // msb low } -static inline u32 XPU_REG_FC_DI_read(void){ - return reg_read(XPU_REG_FC_DI_ADDR); -} - -static inline u32 XPU_REG_ADDR1_LOW_read(void){ - return reg_read(XPU_REG_ADDR1_LOW_ADDR); -} - -static inline u32 XPU_REG_ADDR1_HIGH_read(void){ - return reg_read(XPU_REG_ADDR1_HIGH_ADDR); -} - -static inline u32 XPU_REG_ADDR2_LOW_read(void){ - return reg_read(XPU_REG_ADDR2_LOW_ADDR); -} - -static inline u32 XPU_REG_ADDR2_HIGH_read(void){ - return reg_read(XPU_REG_ADDR2_HIGH_ADDR); -} - -// static inline void XPU_REG_LBT_TH_write(u32 value, u32 en_flag) { -// if (en_flag) { -// reg_write(XPU_REG_LBT_TH_ADDR, value&0x7FFFFFFF); -// } else { -// reg_write(XPU_REG_LBT_TH_ADDR, value|0x80000000); -// } -// } - static inline void XPU_REG_LBT_TH_write(u32 value) { reg_write(XPU_REG_LBT_TH_ADDR, value); } @@ -370,31 +334,12 @@ static inline u32 hw_init(enum xpu_mode mode){ // From CMW measurement: lo up 1us before the packet; lo down 0.4us after the packet/RF port switches 1.2us before and 0.2us after xpu_api->XPU_REG_BB_RF_DELAY_write((16<<24)|(0<<16)|(26<<8)|9); // calibrated by ila and spectrum analyzer (trigger mode) - // setup time schedule of 4 slices - // slice 0 - xpu_api->XPU_REG_SLICE_COUNT_TOTAL_write(50000-1); // total 50ms - xpu_api->XPU_REG_SLICE_COUNT_START_write(0); //start 0ms - xpu_api->XPU_REG_SLICE_COUNT_END_write(50000-1); //end 50ms - - // slice 1 - xpu_api->XPU_REG_SLICE_COUNT_TOTAL_write((1<<20)|(50000-1)); // total 50ms - xpu_api->XPU_REG_SLICE_COUNT_START_write((1<<20)|(0)); //start 0ms - //xpu_api->XPU_REG_SLICE_COUNT_END_write((1<<20)|(20000-1)); //end 20ms - xpu_api->XPU_REG_SLICE_COUNT_END_write((1<<20)|(50000-1)); //end 20ms - - // slice 2 - xpu_api->XPU_REG_SLICE_COUNT_TOTAL_write((2<<20)|(50000-1)); // total 50ms - //xpu_api->XPU_REG_SLICE_COUNT_START_write((2<<20)|(20000)); //start 20ms - xpu_api->XPU_REG_SLICE_COUNT_START_write((2<<20)|(0)); //start 20ms - //xpu_api->XPU_REG_SLICE_COUNT_END_write((2<<20)|(40000-1)); //end 20ms - xpu_api->XPU_REG_SLICE_COUNT_END_write((2<<20)|(50000-1)); //end 20ms - - // slice 3 - xpu_api->XPU_REG_SLICE_COUNT_TOTAL_write((3<<20)|(50000-1)); // total 50ms - //xpu_api->XPU_REG_SLICE_COUNT_START_write((3<<20)|(40000)); //start 40ms - xpu_api->XPU_REG_SLICE_COUNT_START_write((3<<20)|(0)); //start 40ms - //xpu_api->XPU_REG_SLICE_COUNT_END_write((3<<20)|(50000-1)); //end 20ms - xpu_api->XPU_REG_SLICE_COUNT_END_write((3<<20)|(50000-1)); //end 20ms + // setup time schedule of all queues. all time open. + for (i=0; i<4; i++) { + xpu_api->XPU_REG_SLICE_COUNT_TOTAL_write((i<<20)|16);//total 16us + xpu_api->XPU_REG_SLICE_COUNT_START_write((i<<20)|0); //start 0us + xpu_api->XPU_REG_SLICE_COUNT_END_write((i<<20)|16); //end 16us + } // all slice sync rest xpu_api->XPU_REG_MULTI_RST_write(1<<7); //bit7 reset the counter for all queues at the same time @@ -425,7 +370,9 @@ static inline u32 hw_init(enum xpu_mode mode){ rssi_half_db_th = 87<<1; // -62dBm xpu_api->XPU_REG_LBT_TH_write(rssi_half_db_th); // set IQ rssi th step .5dB to xxx and enable it - xpu_api->XPU_REG_FORCE_IDLE_MISC_write(75); //control the duration to force ch_idle after decoding a packet due to imperfection of agc and signals + // control the duration to force ch_idle after decoding a packet due to imperfection of agc and signals + // (1<<26) to disable eifs_trigger_by_last_tx_fail by default (standard does not ask so) + xpu_api->XPU_REG_FORCE_IDLE_MISC_write((1<<26)|75); //xpu_api->XPU_REG_CSMA_DEBUG_write((1<<31)|(20<<24)|(4<<19)|(3<<14)|(10<<7)|(5)); xpu_api->XPU_REG_CSMA_DEBUG_write(0); @@ -433,43 +380,17 @@ static inline u32 hw_init(enum xpu_mode mode){ // xpu_api->XPU_REG_CSMA_CFG_write(268435459); // Linux will do config for each queue via openwifi_conf_tx // xpu_api->XPU_REG_CSMA_CFG_write(0xe0000000); // Linux will do config for each queue via openwifi_conf_tx - xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( ((16+23)<<16)|(0+23) ); - - xpu_api->XPU_REG_RECV_ACK_COUNT_TOP0_write( (1<<31) | (((45+2+2)*10 + 15)<<16) | 10 );//2.4GHz. extra 300 clocks are needed when rx core fall into fake ht detection phase (rx mcs 6M) +// // ------- assume 2.4 and 5GHz have the same SIFS (6us signal extension) -------- + xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( ((16+25)<<16)|((16+25)<<0) ); + xpu_api->XPU_REG_RECV_ACK_COUNT_TOP0_write( (1<<31) | (((51+2+2)*10 + 15)<<16) | 10 );//2.4GHz. extra 300 clocks are needed when rx core fall into fake ht detection phase (rx mcs 6M) xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_write( (1<<31) | (((51+2+2)*10 + 15)<<16) | 10 );//5GHz. extra 300 clocks are needed when rx core fall into fake ht detection phase (rx mcs 6M) +// // ------- assume 2.4 and 5GHz have different SIFS -------- + // xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( ((16+23)<<16)|(0+23) ); + // xpu_api->XPU_REG_RECV_ACK_COUNT_TOP0_write( (1<<31) | (((45+2+2)*10 + 15)<<16) | 10 );//2.4GHz. extra 300 clocks are needed when rx core fall into fake ht detection phase (rx mcs 6M) + // xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_write( (1<<31) | (((51+2+2)*10 + 15)<<16) | 10 );//5GHz. extra 300 clocks are needed when rx core fall into fake ht detection phase (rx mcs 6M) xpu_api->XPU_REG_DIFS_ADVANCE_write((OPENWIFI_MAX_SIGNAL_LEN_TH<<16)|2); //us. bit31~16 max pkt length threshold - // setup time schedule of 4 slices - // slice 0 - xpu_api->XPU_REG_SLICE_COUNT_TOTAL_write(50000-1); // total 50ms - xpu_api->XPU_REG_SLICE_COUNT_START_write(0); //start 0ms - xpu_api->XPU_REG_SLICE_COUNT_END_write(50000-1); //end 50ms - - // slice 1 - xpu_api->XPU_REG_SLICE_COUNT_TOTAL_write((1<<20)|(50000-1)); // total 50ms - xpu_api->XPU_REG_SLICE_COUNT_START_write((1<<20)|(0)); //start 0ms - //xpu_api->XPU_REG_SLICE_COUNT_END_write((1<<20)|(20000-1)); //end 20ms - xpu_api->XPU_REG_SLICE_COUNT_END_write((1<<20)|(50000-1)); //end 20ms - - // slice 2 - xpu_api->XPU_REG_SLICE_COUNT_TOTAL_write((2<<20)|(50000-1)); // total 50ms - //xpu_api->XPU_REG_SLICE_COUNT_START_write((2<<20)|(20000)); //start 20ms - xpu_api->XPU_REG_SLICE_COUNT_START_write((2<<20)|(0)); //start 20ms - //xpu_api->XPU_REG_SLICE_COUNT_END_write((2<<20)|(40000-1)); //end 20ms - xpu_api->XPU_REG_SLICE_COUNT_END_write((2<<20)|(50000-1)); //end 20ms - - // slice 3 - xpu_api->XPU_REG_SLICE_COUNT_TOTAL_write((3<<20)|(50000-1)); // total 50ms - //xpu_api->XPU_REG_SLICE_COUNT_START_write((3<<20)|(40000)); //start 40ms - xpu_api->XPU_REG_SLICE_COUNT_START_write((3<<20)|(0)); //start 40ms - //xpu_api->XPU_REG_SLICE_COUNT_END_write((3<<20)|(50000-1)); //end 20ms - xpu_api->XPU_REG_SLICE_COUNT_END_write((3<<20)|(50000-1)); //end 20ms - - // all slice sync rest - xpu_api->XPU_REG_MULTI_RST_write(1<<7); //bit7 reset the counter for all queues at the same time - xpu_api->XPU_REG_MULTI_RST_write(0<<7); - printk("%s hw_init err %d\n", xpu_compatible_str, err); return(err); } @@ -535,21 +456,12 @@ static int dev_probe(struct platform_device *pdev) xpu_api->XPU_REG_FORCE_IDLE_MISC_write=XPU_REG_FORCE_IDLE_MISC_write; xpu_api->XPU_REG_FORCE_IDLE_MISC_read=XPU_REG_FORCE_IDLE_MISC_read; - xpu_api->XPU_REG_TRX_STATUS_read=XPU_REG_TRX_STATUS_read; - xpu_api->XPU_REG_TX_RESULT_read=XPU_REG_TX_RESULT_read; - xpu_api->XPU_REG_TSF_RUNTIME_VAL_LOW_read=XPU_REG_TSF_RUNTIME_VAL_LOW_read; xpu_api->XPU_REG_TSF_RUNTIME_VAL_HIGH_read=XPU_REG_TSF_RUNTIME_VAL_HIGH_read; xpu_api->XPU_REG_TSF_LOAD_VAL_LOW_write=XPU_REG_TSF_LOAD_VAL_LOW_write; xpu_api->XPU_REG_TSF_LOAD_VAL_HIGH_write=XPU_REG_TSF_LOAD_VAL_HIGH_write; xpu_api->XPU_REG_TSF_LOAD_VAL_write=XPU_REG_TSF_LOAD_VAL_write; - xpu_api->XPU_REG_FC_DI_read=XPU_REG_FC_DI_read; - xpu_api->XPU_REG_ADDR1_LOW_read=XPU_REG_ADDR1_LOW_read; - xpu_api->XPU_REG_ADDR1_HIGH_read=XPU_REG_ADDR1_HIGH_read; - xpu_api->XPU_REG_ADDR2_LOW_read=XPU_REG_ADDR2_LOW_read; - xpu_api->XPU_REG_ADDR2_HIGH_read=XPU_REG_ADDR2_HIGH_read; - xpu_api->XPU_REG_LBT_TH_write=XPU_REG_LBT_TH_write; xpu_api->XPU_REG_LBT_TH_read=XPU_REG_LBT_TH_read; diff --git a/kernel_boot/10-network-device.rules b/kernel_boot/10-network-device.rules new file mode 100644 index 0000000..6e57983 --- /dev/null +++ b/kernel_boot/10-network-device.rules @@ -0,0 +1 @@ +SUBSYSTEM=="net", ACTION=="add", ATTR{address}=="66:55:44:33:22:*", NAME="sdr0" diff --git a/kernel_boot/ad9361.patch b/kernel_boot/ad9361.patch new file mode 100644 index 0000000..30e6cc8 --- /dev/null +++ b/kernel_boot/ad9361.patch @@ -0,0 +1,68 @@ +diff --git a/drivers/iio/adc/ad9361.c b/drivers/iio/adc/ad9361.c +index b21e2129e27c..b53d7b7ab20d 100644 +--- a/drivers/iio/adc/ad9361.c ++++ b/drivers/iio/adc/ad9361.c +@@ -1234,7 +1234,7 @@ static int ad9361_load_mixer_gm_subtable(struct ad9361_rf_phy *phy) + return 0; + } + +-static int ad9361_set_tx_atten(struct ad9361_rf_phy *phy, u32 atten_mdb, ++int ad9361_set_tx_atten(struct ad9361_rf_phy *phy, u32 atten_mdb, + bool tx1, bool tx2, bool immed) + { + u8 buf[2]; +@@ -1266,8 +1266,8 @@ static int ad9361_set_tx_atten(struct ad9361_rf_phy *phy, u32 atten_mdb, + + return ret; + } +- +-static int ad9361_get_tx_atten(struct ad9361_rf_phy *phy, u32 tx_num) ++EXPORT_SYMBOL(ad9361_set_tx_atten); ++int ad9361_get_tx_atten(struct ad9361_rf_phy *phy, u32 tx_num) + { + u8 buf[2]; + int ret = 0; +@@ -1285,7 +1285,7 @@ static int ad9361_get_tx_atten(struct ad9361_rf_phy *phy, u32 tx_num) + + return code; + } +- ++EXPORT_SYMBOL(ad9361_get_tx_atten); + int ad9361_tx_mute(struct ad9361_rf_phy *phy, u32 state) + { + struct ad9361_rf_phy_state *st = phy->state; +@@ -3744,7 +3744,7 @@ static int ad9361_get_auxadc(struct ad9361_rf_phy *phy) + // Setup Control Outs + //************************************************************ + +-static int ad9361_ctrl_outs_setup(struct ad9361_rf_phy *phy, ++int ad9361_ctrl_outs_setup(struct ad9361_rf_phy *phy, + struct ctrl_outs_control *ctrl) + { + struct spi_device *spi = phy->spi; +@@ -3754,6 +3754,7 @@ static int ad9361_ctrl_outs_setup(struct ad9361_rf_phy *phy, + ad9361_spi_write(spi, REG_CTRL_OUTPUT_POINTER, ctrl->index); // Ctrl Out index + return ad9361_spi_write(spi, REG_CTRL_OUTPUT_ENABLE, ctrl->en_mask); // Ctrl Out [7:0] output enable + } ++EXPORT_SYMBOL(ad9361_ctrl_outs_setup); + //************************************************************ + // Setup GPO + //************************************************************ +@@ -5235,7 +5236,7 @@ static int ad9361_setup(struct ad9361_rf_phy *phy) + + } + +-static int ad9361_do_calib_run(struct ad9361_rf_phy *phy, u32 cal, int arg) ++int ad9361_do_calib_run(struct ad9361_rf_phy *phy, u32 cal, int arg) + { + struct ad9361_rf_phy_state *st = phy->state; + int ret; +@@ -5268,7 +5269,7 @@ static int ad9361_do_calib_run(struct ad9361_rf_phy *phy, u32 cal, int arg) + + return ret; + } +- ++EXPORT_SYMBOL(ad9361_do_calib_run); + static int ad9361_update_rf_bandwidth(struct ad9361_rf_phy *phy, + u32 rf_rx_bw, u32 rf_tx_bw) + { diff --git a/kernel_boot/ad9361_conv.patch b/kernel_boot/ad9361_conv.patch new file mode 100644 index 0000000..bf16d15 --- /dev/null +++ b/kernel_boot/ad9361_conv.patch @@ -0,0 +1,14 @@ +diff --git a/drivers/iio/adc/ad9361_conv.c b/drivers/iio/adc/ad9361_conv.c +index 1902e7d07501..ef421dbd5e70 100644 +--- a/drivers/iio/adc/ad9361_conv.c ++++ b/drivers/iio/adc/ad9361_conv.c +@@ -449,7 +449,8 @@ static int ad9361_dig_tune_delay(struct ad9361_rf_phy *phy, + unsigned long max_freq, + enum dig_tune_flags flags, bool tx) + { +- static const unsigned int rates[3] = {25000000U, 40000000U, 61440000U}; ++ // static const unsigned int rates[3] = {25000000U, 40000000U, 61440000U}; ++ static const unsigned int rates[3] = {25000000U, 40000000U, 40000000U}; + struct axiadc_converter *conv = spi_get_drvdata(phy->spi); + unsigned int s0, s1, c0, c1; + unsigned int i, j, r; diff --git a/kernel_boot/axi_hdmi_crtc.patch b/kernel_boot/axi_hdmi_crtc.patch new file mode 100644 index 0000000..ab7df05 --- /dev/null +++ b/kernel_boot/axi_hdmi_crtc.patch @@ -0,0 +1,13 @@ +diff --git a/drivers/gpu/drm/adi_axi_hdmi/axi_hdmi_crtc.c b/drivers/gpu/drm/adi_axi_hdmi/axi_hdmi_crtc.c +index f24669f623d6..70c5769019fa 100644 +--- a/drivers/gpu/drm/adi_axi_hdmi/axi_hdmi_crtc.c ++++ b/drivers/gpu/drm/adi_axi_hdmi/axi_hdmi_crtc.c +@@ -54,7 +54,7 @@ static struct dma_async_tx_descriptor *axi_hdmi_vdma_prep_interleaved_desc( + memset(&vdma_config, 0, sizeof(vdma_config)); + vdma_config.park = 1; + vdma_config.coalesc = 0xff; +- xilinx_vdma_channel_set_config(axi_hdmi_crtc->dma, &vdma_config); ++ // xilinx_vdma_channel_set_config(axi_hdmi_crtc->dma, &vdma_config); + } + #endif + diff --git a/kernel_boot/boards/adrv9361z7035/u-boot.elf b/kernel_boot/boards/adrv9361z7035/u-boot.elf index d074293..e2822e9 100644 Binary files a/kernel_boot/boards/adrv9361z7035/u-boot.elf and b/kernel_boot/boards/adrv9361z7035/u-boot.elf differ diff --git a/kernel_boot/boards/adrv9361z7035_fmc/u-boot.elf b/kernel_boot/boards/adrv9361z7035_fmc/u-boot.elf index d074293..e2822e9 100644 Binary files a/kernel_boot/boards/adrv9361z7035_fmc/u-boot.elf and b/kernel_boot/boards/adrv9361z7035_fmc/u-boot.elf differ diff --git a/kernel_boot/boards/adrv9364z7020/devicetree.dtb b/kernel_boot/boards/adrv9364z7020/devicetree.dtb index ee77db3..ca88668 100644 Binary files a/kernel_boot/boards/adrv9364z7020/devicetree.dtb and b/kernel_boot/boards/adrv9364z7020/devicetree.dtb differ diff --git a/kernel_boot/boards/adrv9364z7020/devicetree.dts b/kernel_boot/boards/adrv9364z7020/devicetree.dts index aba3d6b..e06de8b 100644 --- a/kernel_boot/boards/adrv9364z7020/devicetree.dts +++ b/kernel_boot/boards/adrv9364z7020/devicetree.dts @@ -1,46 +1,49 @@ /dts-v1/; / { - #address-cells = <0x1>; - #size-cells = <0x1>; + #address-cells = <0x01>; + #size-cells = <0x01>; compatible = "xlnx,zynq-7000"; - interrupt-parent = <0x1>; + interrupt-parent = <0x01>; model = "Analog Devices ADRV9364-Z7020 (Z7020/AD9364)"; cpus { - #address-cells = <0x1>; - #size-cells = <0x0>; + #address-cells = <0x01>; + #size-cells = <0x00>; cpu@0 { compatible = "arm,cortex-a9"; device_type = "cpu"; - reg = <0x0>; - clocks = <0x2 0x3>; + reg = <0x00>; + clocks = <0x02 0x03>; clock-latency = <0x3e8>; - cpu0-supply = <0x3>; + cpu0-supply = <0x03>; operating-points = <0xa2c2b 0xf4240 0x51616 0xf4240>; + phandle = <0x11>; }; cpu@1 { compatible = "arm,cortex-a9"; device_type = "cpu"; - reg = <0x1>; - clocks = <0x2 0x3>; + reg = <0x01>; + clocks = <0x02 0x03>; + phandle = <0x13>; }; }; fpga-full { compatible = "fpga-region"; - fpga-mgr = <0x4>; - #address-cells = <0x1>; - #size-cells = <0x1>; + fpga-mgr = <0x04>; + #address-cells = <0x01>; + #size-cells = <0x01>; ranges; + phandle = <0x19>; }; pmu@f8891000 { compatible = "arm,cortex-a9-pmu"; - interrupts = <0x0 0x5 0x4 0x0 0x6 0x4>; - interrupt-parent = <0x1>; + interrupts = <0x00 0x05 0x04 0x00 0x06 0x04>; + interrupt-parent = <0x01>; reg = <0xf8891000 0x1000 0xf8893000 0x1000>; }; @@ -51,145 +54,194 @@ regulator-max-microvolt = <0xf4240>; regulator-boot-on; regulator-always-on; - linux,phandle = <0x3>; - phandle = <0x3>; + phandle = <0x03>; }; - amba { + replicator { + compatible = "arm,coresight-static-replicator"; + clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>; + clock-names = "apb_pclk\0dbg_trc\0dbg_apb"; + + out-ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x05>; + phandle = <0x0d>; + }; + }; + + port@1 { + reg = <0x01>; + + endpoint { + remote-endpoint = <0x06>; + phandle = <0x0c>; + }; + }; + }; + + in-ports { + + port { + + endpoint { + remote-endpoint = <0x07>; + phandle = <0x0e>; + }; + }; + }; + }; + + axi { u-boot,dm-pre-reloc; compatible = "simple-bus"; - #address-cells = <0x1>; - #size-cells = <0x1>; - interrupt-parent = <0x1>; + #address-cells = <0x01>; + #size-cells = <0x01>; + interrupt-parent = <0x01>; ranges; + phandle = <0x1a>; adc@f8007100 { compatible = "xlnx,zynq-xadc-1.00.a"; reg = <0xf8007100 0x20>; - interrupts = <0x0 0x7 0x4>; - interrupt-parent = <0x1>; - clocks = <0x2 0xc>; + interrupts = <0x00 0x07 0x04>; + interrupt-parent = <0x01>; + clocks = <0x02 0x0c>; + phandle = <0x1b>; }; can@e0008000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; - clocks = <0x2 0x13 0x2 0x24>; - clock-names = "can_clk", "pclk"; + clocks = <0x02 0x13 0x02 0x24>; + clock-names = "can_clk\0pclk"; reg = <0xe0008000 0x1000>; - interrupts = <0x0 0x1c 0x4>; - interrupt-parent = <0x1>; + interrupts = <0x00 0x1c 0x04>; + interrupt-parent = <0x01>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; + phandle = <0x1c>; }; can@e0009000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; - clocks = <0x2 0x14 0x2 0x25>; - clock-names = "can_clk", "pclk"; + clocks = <0x02 0x14 0x02 0x25>; + clock-names = "can_clk\0pclk"; reg = <0xe0009000 0x1000>; - interrupts = <0x0 0x33 0x4>; - interrupt-parent = <0x1>; + interrupts = <0x00 0x33 0x04>; + interrupt-parent = <0x01>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; + phandle = <0x1d>; }; gpio@e000a000 { compatible = "xlnx,zynq-gpio-1.0"; - #gpio-cells = <0x2>; - clocks = <0x2 0x2a>; + #gpio-cells = <0x02>; + clocks = <0x02 0x2a>; gpio-controller; interrupt-controller; - #interrupt-cells = <0x2>; - interrupt-parent = <0x1>; - interrupts = <0x0 0x14 0x4>; + #interrupt-cells = <0x02>; + interrupt-parent = <0x01>; + interrupts = <0x00 0x14 0x04>; reg = <0xe000a000 0x1000>; - linux,phandle = <0x6>; - phandle = <0x6>; + phandle = <0x09>; }; i2c@e0004000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; - clocks = <0x2 0x26>; - interrupt-parent = <0x1>; - interrupts = <0x0 0x19 0x4>; + clocks = <0x02 0x26>; + interrupt-parent = <0x01>; + interrupts = <0x00 0x19 0x04>; reg = <0xe0004000 0x1000>; - #address-cells = <0x1>; - #size-cells = <0x0>; + #address-cells = <0x01>; + #size-cells = <0x00>; + phandle = <0x1e>; }; i2c@e0005000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; - clocks = <0x2 0x27>; - interrupt-parent = <0x1>; - interrupts = <0x0 0x30 0x4>; + clocks = <0x02 0x27>; + interrupt-parent = <0x01>; + interrupts = <0x00 0x30 0x04>; reg = <0xe0005000 0x1000>; - #address-cells = <0x1>; - #size-cells = <0x0>; + #address-cells = <0x01>; + #size-cells = <0x00>; + phandle = <0x1f>; }; interrupt-controller@f8f01000 { compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <0x3>; + #interrupt-cells = <0x03>; interrupt-controller; reg = <0xf8f01000 0x1000 0xf8f00100 0x100>; - linux,phandle = <0x1>; - phandle = <0x1>; + phandle = <0x01>; }; cache-controller@f8f02000 { compatible = "arm,pl310-cache"; reg = <0xf8f02000 0x1000>; - interrupts = <0x0 0x2 0x4>; - arm,data-latency = <0x3 0x2 0x2>; - arm,tag-latency = <0x2 0x2 0x2>; + interrupts = <0x00 0x02 0x04>; + arm,data-latency = <0x03 0x02 0x02>; + arm,tag-latency = <0x02 0x02 0x02>; cache-unified; - cache-level = <0x2>; + cache-level = <0x02>; + phandle = <0x20>; }; memory-controller@f8006000 { compatible = "xlnx,zynq-ddrc-a05"; reg = <0xf8006000 0x1000>; + phandle = <0x21>; }; ocmc@f800c000 { compatible = "xlnx,zynq-ocmc-1.0"; - interrupt-parent = <0x1>; - interrupts = <0x0 0x3 0x4>; + interrupt-parent = <0x01>; + interrupts = <0x00 0x03 0x04>; reg = <0xf800c000 0x1000>; + phandle = <0x22>; }; serial@e0000000 { - compatible = "xlnx,xuartps", "cdns,uart-r1p8"; + compatible = "xlnx,xuartps\0cdns,uart-r1p8"; status = "disabled"; - clocks = <0x2 0x17 0x2 0x28>; - clock-names = "uart_clk", "pclk"; + clocks = <0x02 0x17 0x02 0x28>; + clock-names = "uart_clk\0pclk"; reg = <0xe0000000 0x1000>; - interrupts = <0x0 0x1b 0x4>; + interrupts = <0x00 0x1b 0x04>; + phandle = <0x23>; }; serial@e0001000 { - compatible = "xlnx,xuartps", "cdns,uart-r1p8"; + compatible = "xlnx,xuartps\0cdns,uart-r1p8"; status = "okay"; - clocks = <0x2 0x18 0x2 0x29>; - clock-names = "uart_clk", "pclk"; + clocks = <0x02 0x18 0x02 0x29>; + clock-names = "uart_clk\0pclk"; reg = <0xe0001000 0x1000>; - interrupts = <0x0 0x32 0x4>; + interrupts = <0x00 0x32 0x04>; + phandle = <0x24>; }; spi@e0006000 { compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0006000 0x1000>; status = "okay"; - interrupt-parent = <0x1>; - interrupts = <0x0 0x1a 0x4>; - clocks = <0x2 0x19 0x2 0x22>; - clock-names = "ref_clk", "pclk"; - #address-cells = <0x1>; - #size-cells = <0x0>; + interrupt-parent = <0x01>; + interrupts = <0x00 0x1a 0x04>; + clocks = <0x02 0x19 0x02 0x22>; + clock-names = "ref_clk\0pclk"; + #address-cells = <0x01>; + #size-cells = <0x00>; + phandle = <0x25>; ad9361-phy@0 { #address-cells = <0x1>; @@ -199,8 +251,8 @@ reg = <0x0>; spi-cpha; spi-max-frequency = <0x989680>; - clocks = <0x5 0x0>; - clock-names = "ad9364_ext_refclk"; + clocks = <0x08 0x00>; + clock-names = "ad9361_ext_refclk"; clock-output-names = "rx_sampl_clk", "tx_sampl_clk"; adi,digital-interface-tune-skip-mode = <0x0>; adi,pp-tx-swap-enable; @@ -291,13 +343,12 @@ adi,aux-dac2-default-value-mV = <0x0>; adi,aux-dac2-rx-delay-us = <0x0>; adi,aux-dac2-tx-delay-us = <0x0>; - en_agc-gpios = <0x6 0x62 0x0>; - sync-gpios = <0x6 0x63 0x0>; - reset-gpios = <0x6 0x64 0x0>; - enable-gpios = <0x6 0x65 0x0>; - txnrx-gpios = <0x6 0x66 0x0>; - linux,phandle = <0xb>; - phandle = <0xb>; + en_agc-gpios = <0x09 0x62 0x0>; + sync-gpios = <0x09 0x63 0x0>; + reset-gpios = <0x09 0x64 0x0>; + enable-gpios = <0x09 0x65 0x0>; + txnrx-gpios = <0x09 0x66 0x0>; + phandle = <0x17>; }; }; @@ -305,39 +356,42 @@ compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0007000 0x1000>; status = "disabled"; - interrupt-parent = <0x1>; - interrupts = <0x0 0x31 0x4>; - clocks = <0x2 0x1a 0x2 0x23>; - clock-names = "ref_clk", "pclk"; - #address-cells = <0x1>; - #size-cells = <0x0>; + interrupt-parent = <0x01>; + interrupts = <0x00 0x31 0x04>; + clocks = <0x02 0x1a 0x02 0x23>; + clock-names = "ref_clk\0pclk"; + #address-cells = <0x01>; + #size-cells = <0x00>; + phandle = <0x26>; }; spi@e000d000 { - clock-names = "ref_clk", "pclk"; - clocks = <0x2 0xa 0x2 0x2b>; + clock-names = "ref_clk\0pclk"; + clocks = <0x02 0x0a 0x02 0x2b>; compatible = "xlnx,zynq-qspi-1.0"; status = "okay"; - interrupt-parent = <0x1>; - interrupts = <0x0 0x13 0x4>; + interrupt-parent = <0x01>; + interrupts = <0x00 0x13 0x04>; reg = <0xe000d000 0x1000>; - #address-cells = <0x1>; - #size-cells = <0x0>; - is-dual = <0x0>; - num-cs = <0x1>; + #address-cells = <0x01>; + #size-cells = <0x00>; + is-dual = <0x00>; + num-cs = <0x01>; + phandle = <0x27>; ps7-qspi@0 { - #address-cells = <0x1>; - #size-cells = <0x1>; - spi-tx-bus-width = <0x1>; - spi-rx-bus-width = <0x4>; - compatible = "n25q256a", "jedec,spi-nor"; - reg = <0x0>; + #address-cells = <0x01>; + #size-cells = <0x01>; + spi-tx-bus-width = <0x01>; + spi-rx-bus-width = <0x04>; + compatible = "n25q256a\0jedec,spi-nor"; + reg = <0x00>; spi-max-frequency = <0x2faf080>; + phandle = <0x28>; partition@qspi-fsbl-uboot { label = "qspi-fsbl-uboot"; - reg = <0x0 0xe0000>; + reg = <0x00 0xe0000>; }; partition@qspi-uboot-env { @@ -368,275 +422,414 @@ }; memory-controller@e000e000 { - #address-cells = <0x1>; - #size-cells = <0x1>; + #address-cells = <0x01>; + #size-cells = <0x01>; status = "disabled"; - clock-names = "memclk", "aclk"; - clocks = <0x2 0xb 0x2 0x2c>; - compatible = "arm,pl353-smc-r2p1"; - interrupt-parent = <0x1>; - interrupts = <0x0 0x12 0x4>; + clock-names = "memclk\0apb_pclk"; + clocks = <0x02 0x0b 0x02 0x2c>; + compatible = "arm,pl353-smc-r2p1\0arm,primecell"; + interrupt-parent = <0x01>; + interrupts = <0x00 0x12 0x04>; ranges; reg = <0xe000e000 0x1000>; + phandle = <0x29>; flash@e1000000 { status = "disabled"; compatible = "arm,pl353-nand-r2p1"; reg = <0xe1000000 0x1000000>; - #address-cells = <0x1>; - #size-cells = <0x1>; + #address-cells = <0x01>; + #size-cells = <0x01>; + phandle = <0x2a>; }; flash@e2000000 { status = "disabled"; compatible = "cfi-flash"; reg = <0xe2000000 0x2000000>; - #address-cells = <0x1>; - #size-cells = <0x1>; + #address-cells = <0x01>; + #size-cells = <0x01>; + phandle = <0x2b>; }; }; ethernet@e000b000 { - compatible = "cdns,zynq-gem", "cdns,gem"; + compatible = "cdns,zynq-gem\0cdns,gem"; reg = <0xe000b000 0x1000>; status = "okay"; - interrupts = <0x0 0x16 0x4>; - clocks = <0x2 0x1e 0x2 0x1e 0x2 0xd>; - clock-names = "pclk", "hclk", "tx_clk"; - #address-cells = <0x1>; - #size-cells = <0x0>; - phy-handle = <0x7>; + interrupts = <0x00 0x16 0x04>; + clocks = <0x02 0x1e 0x02 0x1e 0x02 0x0d>; + clock-names = "pclk\0hclk\0tx_clk"; + #address-cells = <0x01>; + #size-cells = <0x00>; + phy-handle = <0x0a>; phy-mode = "rgmii-id"; + phandle = <0x2c>; phy@0 { device_type = "ethernet-phy"; - reg = <0x0>; - marvell,reg-init = <0x3 0x10 0xff00 0x1e 0x3 0x11 0xfff0 0x0>; - linux,phandle = <0x7>; - phandle = <0x7>; + reg = <0x00>; + marvell,reg-init = <0x03 0x10 0xff00 0x1e 0x03 0x11 0xfff0 0x00>; + phandle = <0x0a>; }; }; ethernet@e000c000 { - compatible = "cdns,zynq-gem", "cdns,gem"; + compatible = "cdns,zynq-gem\0cdns,gem"; reg = <0xe000c000 0x1000>; status = "disabled"; - interrupts = <0x0 0x2d 0x4>; - clocks = <0x2 0x1f 0x2 0x1f 0x2 0xe>; - clock-names = "pclk", "hclk", "tx_clk"; - #address-cells = <0x1>; - #size-cells = <0x0>; + interrupts = <0x00 0x2d 0x04>; + clocks = <0x02 0x1f 0x02 0x1f 0x02 0x0e>; + clock-names = "pclk\0hclk\0tx_clk"; + #address-cells = <0x01>; + #size-cells = <0x00>; + phandle = <0x2d>; }; mmc@e0100000 { compatible = "arasan,sdhci-8.9a"; status = "okay"; - clock-names = "clk_xin", "clk_ahb"; - clocks = <0x2 0x15 0x2 0x20>; - interrupt-parent = <0x1>; - interrupts = <0x0 0x18 0x4>; + clock-names = "clk_xin\0clk_ahb"; + clocks = <0x02 0x15 0x02 0x20>; + interrupt-parent = <0x01>; + interrupts = <0x00 0x18 0x04>; reg = <0xe0100000 0x1000>; disable-wp; + phandle = <0x2e>; }; mmc@e0101000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; - clock-names = "clk_xin", "clk_ahb"; - clocks = <0x2 0x16 0x2 0x21>; - interrupt-parent = <0x1>; - interrupts = <0x0 0x2f 0x4>; + clock-names = "clk_xin\0clk_ahb"; + clocks = <0x02 0x16 0x02 0x21>; + interrupt-parent = <0x01>; + interrupts = <0x00 0x2f 0x04>; reg = <0xe0101000 0x1000>; + phandle = <0x2f>; }; slcr@f8000000 { u-boot,dm-pre-reloc; - #address-cells = <0x1>; - #size-cells = <0x1>; - compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd"; + #address-cells = <0x01>; + #size-cells = <0x01>; + compatible = "xlnx,zynq-slcr\0syscon\0simple-mfd"; reg = <0xf8000000 0x1000>; ranges; - linux,phandle = <0x8>; - phandle = <0x8>; + phandle = <0x0b>; clkc@100 { u-boot,dm-pre-reloc; - #clock-cells = <0x1>; + #clock-cells = <0x01>; compatible = "xlnx,ps7-clkc"; - fclk-enable = <0xf>; - clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", "swdt", "dbg_trc", "dbg_apb"; + fclk-enable = <0x0f>; + clock-output-names = "armpll\0ddrpll\0iopll\0cpu_6or4x\0cpu_3or2x\0cpu_2x\0cpu_1x\0ddr2x\0ddr3x\0dci\0lqspi\0smc\0pcap\0gem0\0gem1\0fclk0\0fclk1\0fclk2\0fclk3\0can0\0can1\0sdio0\0sdio1\0uart0\0uart1\0spi0\0spi1\0dma\0usb0_aper\0usb1_aper\0gem0_aper\0gem1_aper\0sdio0_aper\0sdio1_aper\0spi0_aper\0spi1_aper\0can0_aper\0can1_aper\0i2c0_aper\0i2c1_aper\0uart0_aper\0uart1_aper\0gpio_aper\0lqspi_aper\0smc_aper\0swdt\0dbg_trc\0dbg_apb"; reg = <0x100 0x100>; ps-clk-frequency = <0x1fca055>; - linux,phandle = <0x2>; - phandle = <0x2>; + phandle = <0x02>; }; rstc@200 { compatible = "xlnx,zynq-reset"; reg = <0x200 0x48>; - #reset-cells = <0x1>; - syscon = <0x8>; + #reset-cells = <0x01>; + syscon = <0x0b>; + phandle = <0x30>; }; pinctrl@700 { compatible = "xlnx,pinctrl-zynq"; reg = <0x700 0x200>; - syscon = <0x8>; + syscon = <0x0b>; + phandle = <0x31>; }; }; dmac@f8003000 { - compatible = "arm,pl330", "arm,primecell"; + compatible = "arm,pl330\0arm,primecell"; reg = <0xf8003000 0x1000>; - interrupt-parent = <0x1>; - interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", "dma4", "dma5", "dma6", "dma7"; - interrupts = <0x0 0xd 0x4 0x0 0xe 0x4 0x0 0xf 0x4 0x0 0x10 0x4 0x0 0x11 0x4 0x0 0x28 0x4 0x0 0x29 0x4 0x0 0x2a 0x4 0x0 0x2b 0x4>; - #dma-cells = <0x1>; - #dma-channels = <0x8>; - #dma-requests = <0x4>; - clocks = <0x2 0x1b>; + interrupt-parent = <0x01>; + interrupt-names = "abort\0dma0\0dma1\0dma2\0dma3\0dma4\0dma5\0dma6\0dma7"; + interrupts = <0x00 0x0d 0x04 0x00 0x0e 0x04 0x00 0x0f 0x04 0x00 0x10 0x04 0x00 0x11 0x04 0x00 0x28 0x04 0x00 0x29 0x04 0x00 0x2a 0x04 0x00 0x2b 0x04>; + #dma-cells = <0x01>; + #dma-channels = <0x08>; + #dma-requests = <0x04>; + clocks = <0x02 0x1b>; clock-names = "apb_pclk"; + phandle = <0x32>; }; devcfg@f8007000 { compatible = "xlnx,zynq-devcfg-1.0"; - interrupt-parent = <0x1>; - interrupts = <0x0 0x8 0x4>; + interrupt-parent = <0x01>; + interrupts = <0x00 0x08 0x04>; reg = <0xf8007000 0x100>; - clocks = <0x2 0xc 0x2 0xf 0x2 0x10 0x2 0x11 0x2 0x12>; - clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; - syscon = <0x8>; - linux,phandle = <0x4>; - phandle = <0x4>; + clocks = <0x02 0x0c 0x02 0x0f 0x02 0x10 0x02 0x11 0x02 0x12>; + clock-names = "ref_clk\0fclk0\0fclk1\0fclk2\0fclk3"; + syscon = <0x0b>; + phandle = <0x04>; }; efuse@f800d000 { compatible = "xlnx,zynq-efuse"; reg = <0xf800d000 0x20>; + phandle = <0x33>; }; timer@f8f00200 { compatible = "arm,cortex-a9-global-timer"; reg = <0xf8f00200 0x20>; - interrupts = <0x1 0xb 0x301>; - interrupt-parent = <0x1>; - clocks = <0x2 0x4>; + interrupts = <0x01 0x0b 0x301>; + interrupt-parent = <0x01>; + clocks = <0x02 0x04>; + phandle = <0x34>; }; timer@f8001000 { - interrupt-parent = <0x1>; - interrupts = <0x0 0xa 0x4 0x0 0xb 0x4 0x0 0xc 0x4>; + interrupt-parent = <0x01>; + interrupts = <0x00 0x0a 0x04 0x00 0x0b 0x04 0x00 0x0c 0x04>; compatible = "cdns,ttc"; - clocks = <0x2 0x6>; + clocks = <0x02 0x06>; reg = <0xf8001000 0x1000>; + phandle = <0x35>; }; timer@f8002000 { - interrupt-parent = <0x1>; - interrupts = <0x0 0x25 0x4 0x0 0x26 0x4 0x0 0x27 0x4>; + interrupt-parent = <0x01>; + interrupts = <0x00 0x25 0x04 0x00 0x26 0x04 0x00 0x27 0x04>; compatible = "cdns,ttc"; - clocks = <0x2 0x6>; + clocks = <0x02 0x06>; reg = <0xf8002000 0x1000>; + phandle = <0x36>; }; timer@f8f00600 { - interrupt-parent = <0x1>; - interrupts = <0x1 0xd 0x301>; + interrupt-parent = <0x01>; + interrupts = <0x01 0x0d 0x301>; compatible = "arm,cortex-a9-twd-timer"; reg = <0xf8f00600 0x20>; - clocks = <0x2 0x4>; + clocks = <0x02 0x04>; + phandle = <0x37>; }; usb@e0002000 { - compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; + compatible = "xlnx,zynq-usb-2.20a\0chipidea,usb2"; status = "okay"; - clocks = <0x2 0x1c>; - interrupt-parent = <0x1>; - interrupts = <0x0 0x15 0x4>; + clocks = <0x02 0x1c>; + interrupt-parent = <0x01>; + interrupts = <0x00 0x15 0x04>; reg = <0xe0002000 0x1000>; phy_type = "ulpi"; dr_mode = "host"; - xlnx,phy-reset-gpio = <0x6 0x7 0x0>; + xlnx,phy-reset-gpio = <0x09 0x07 0x00>; + phandle = <0x38>; }; usb@e0003000 { - compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; + compatible = "xlnx,zynq-usb-2.20a\0chipidea,usb2"; status = "disabled"; - clocks = <0x2 0x1d>; - interrupt-parent = <0x1>; - interrupts = <0x0 0x2c 0x4>; + clocks = <0x02 0x1d>; + interrupt-parent = <0x01>; + interrupts = <0x00 0x2c 0x04>; reg = <0xe0003000 0x1000>; phy_type = "ulpi"; + phandle = <0x39>; }; watchdog@f8005000 { - clocks = <0x2 0x2d>; + clocks = <0x02 0x2d>; compatible = "cdns,wdt-r1p2"; - interrupt-parent = <0x1>; - interrupts = <0x0 0x9 0x1>; + interrupt-parent = <0x01>; + interrupts = <0x00 0x09 0x01>; reg = <0xf8005000 0x1000>; - timeout-sec = <0xa>; + timeout-sec = <0x0a>; + phandle = <0x3a>; + }; + + etb@f8801000 { + compatible = "arm,coresight-etb10\0arm,primecell"; + reg = <0xf8801000 0x1000>; + clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>; + clock-names = "apb_pclk\0dbg_trc\0dbg_apb"; + + in-ports { + + port { + + endpoint { + remote-endpoint = <0x0c>; + phandle = <0x06>; + }; + }; + }; + }; + + tpiu@f8803000 { + compatible = "arm,coresight-tpiu\0arm,primecell"; + reg = <0xf8803000 0x1000>; + clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>; + clock-names = "apb_pclk\0dbg_trc\0dbg_apb"; + + in-ports { + + port { + + endpoint { + remote-endpoint = <0x0d>; + phandle = <0x05>; + }; + }; + }; + }; + + funnel@f8804000 { + compatible = "arm,coresight-static-funnel\0arm,primecell"; + reg = <0xf8804000 0x1000>; + clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>; + clock-names = "apb_pclk\0dbg_trc\0dbg_apb"; + + out-ports { + + port { + + endpoint { + remote-endpoint = <0x0e>; + phandle = <0x07>; + }; + }; + }; + + in-ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x0f>; + phandle = <0x12>; + }; + }; + + port@1 { + reg = <0x01>; + + endpoint { + remote-endpoint = <0x10>; + phandle = <0x14>; + }; + }; + + port@2 { + reg = <0x02>; + + endpoint { + phandle = <0x3b>; + }; + }; + }; + }; + + ptm@f889c000 { + compatible = "arm,coresight-etm3x\0arm,primecell"; + reg = <0xf889c000 0x1000>; + clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>; + clock-names = "apb_pclk\0dbg_trc\0dbg_apb"; + cpu = <0x11>; + + out-ports { + + port { + + endpoint { + remote-endpoint = <0x12>; + phandle = <0x0f>; + }; + }; + }; + }; + + ptm@f889d000 { + compatible = "arm,coresight-etm3x\0arm,primecell"; + reg = <0xf889d000 0x1000>; + clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>; + clock-names = "apb_pclk\0dbg_trc\0dbg_apb"; + cpu = <0x13>; + + out-ports { + + port { + + endpoint { + remote-endpoint = <0x14>; + phandle = <0x10>; + }; + }; + }; }; }; aliases { - ethernet0 = "/amba/ethernet@e000b000"; - serial0 = "/amba/serial@e0001000"; + ethernet0 = "/axi/ethernet@e000b000"; + serial0 = "/axi/serial@e0001000"; + phandle = <0x3c>; }; memory { device_type = "memory"; - reg = <0x0 0x40000000>; + reg = <0x00 0x40000000>; }; chosen { - linux,stdout-path = "/amba@0/uart@E0001000"; + stdout-path = "/amba@0/uart@E0001000"; }; clocks { clock@0 { - #clock-cells = <0x0>; + #clock-cells = <0x00>; compatible = "adjustable-clock"; clock-frequency = <0x2625a00>; clock-accuracy = <0x30d40>; clock-output-names = "ad9364_ext_refclk"; - linux,phandle = <0x5>; - phandle = <0x5>; + phandle = <0x08>; }; clock@1 { - #clock-cells = <0x0>; + #clock-cells = <0x00>; compatible = "fixed-clock"; clock-frequency = <0x16e3600>; clock-output-names = "24MHz"; - linux,phandle = <0x9>; - phandle = <0x9>; + phandle = <0x15>; }; }; usb-ulpi-gpio-gate@0 { compatible = "gpio-gate-clock"; - clocks = <0x9>; - #clock-cells = <0x0>; - enable-gpios = <0x6 0x9 0x1>; + clocks = <0x15>; + #clock-cells = <0x00>; + enable-gpios = <0x09 0x09 0x01>; + phandle = <0x3d>; }; fpga-axi@0 { compatible = "simple-bus"; - #address-cells = <0x1>; - #size-cells = <0x1>; + #address-cells = <0x01>; + #size-cells = <0x01>; ranges; + phandle = <0x3e>; i2c@41600000 { - compatible = "xlnx,axi-iic-1.02.a", "xlnx,xps-iic-2.00.a"; + compatible = "xlnx,axi-iic-1.02.a\0xlnx,xps-iic-2.00.a"; reg = <0x41600000 0x10000>; - interrupt-parent = <0x1>; - interrupts = <0x0 0x3a 0x4>; - clocks = <0x2 0xf>; + interrupt-parent = <0x01>; + interrupts = <0x00 0x3a 0x04>; + clocks = <0x02 0x0f>; clock-names = "pclk"; - #address-cells = <0x1>; - #size-cells = <0x0>; + #address-cells = <0x01>; + #size-cells = <0x00>; + phandle = <0x3f>; ad7291@20 { compatible = "adi,ad7291"; @@ -657,22 +850,21 @@ // dma@7c400000 { // compatible = "adi,axi-dmac-1.00.a"; // reg = <0x7c400000 0x10000>; - // #dma-cells = <0x1>; - // interrupts = <0x0 0x39 0x0>; - // clocks = <0x2 0x10>; - // linux,phandle = <0xa>; - // phandle = <0xa>; + // #dma-cells = <0x01>; + // interrupts = <0x00 0x39 0x04>; + // clocks = <0x02 0x10>; + // phandle = <0x16>; // adi,channels { - // #size-cells = <0x0>; - // #address-cells = <0x1>; + // #size-cells = <0x00>; + // #address-cells = <0x01>; // dma-channel@0 { - // reg = <0x0>; + // reg = <0x00>; // adi,source-bus-width = <0x40>; - // adi,source-bus-type = <0x2>; + // adi,source-bus-type = <0x02>; // adi,destination-bus-width = <0x40>; - // adi,destination-bus-type = <0x0>; + // adi,destination-bus-type = <0x00>; // }; // }; // }; @@ -680,22 +872,21 @@ // dma@7c420000 { // compatible = "adi,axi-dmac-1.00.a"; // reg = <0x7c420000 0x10000>; - // #dma-cells = <0x1>; - // interrupts = <0x0 0x38 0x0>; - // clocks = <0x2 0x10>; - // linux,phandle = <0xc>; - // phandle = <0xc>; + // #dma-cells = <0x01>; + // interrupts = <0x00 0x38 0x04>; + // clocks = <0x02 0x10>; + // phandle = <0x18>; // adi,channels { - // #size-cells = <0x0>; - // #address-cells = <0x1>; + // #size-cells = <0x00>; + // #address-cells = <0x01>; // dma-channel@0 { - // reg = <0x0>; + // reg = <0x00>; // adi,source-bus-width = <0x40>; - // adi,source-bus-type = <0x0>; + // adi,source-bus-type = <0x00>; // adi,destination-bus-width = <0x40>; - // adi,destination-bus-type = <0x2>; + // adi,destination-bus-type = <0x02>; // }; // }; // }; @@ -710,12 +901,12 @@ interrupts = <0 29 1 0 30 1 0 33 1 0 34 1>; } ; - axidmatest_1: axidmatest@1 { - compatible ="xlnx,axi-dma-test-1.00.a"; - dmas = <&rx_dma 0 - &rx_dma 1>; - dma-names = "axidma0", "axidma1"; - } ; + // axidmatest_1: axidmatest@1 { + // compatible ="xlnx,axi-dma-test-1.00.a"; + // dmas = <&rx_dma 0 + // &rx_dma 1>; + // dma-names = "axidma0", "axidma1"; + // } ; tx_dma: dma@80400000 { #dma-cells = <1>; @@ -832,18 +1023,20 @@ cf-ad9361-lpc@79020000 { compatible = "adi,axi-ad9361-6.00.a"; reg = <0x79020000 0x6000>; - // dmas = <0xa 0x0>; + // dmas = <0x16 0x00>; // dma-names = "rx"; - spibus-connected = <0xb>; + spibus-connected = <0x17>; + phandle = <0x40>; }; cf-ad9361-dds-core-lpc@79024000 { compatible = "adi,axi-ad9361-dds-6.00.a"; reg = <0x79024000 0x1000>; - clocks = <0xb 0xd>; + clocks = <0x17 0x0d>; clock-names = "sampl_clk"; - // dmas = <0xc 0x0>; + // dmas = <0x18 0x00>; // dma-names = "tx"; + phandle = <0x41>; }; mwipcore@43c00000 { @@ -851,10 +1044,11 @@ reg = <0x43c00000 0xffff>; }; - /*axi-sysid-0@45000000 { - compatible = "adi,axi-sysid-1.00.a"; - reg = <0x45000000 0x10000>; - };*/ + // axi-sysid-0@45000000 { + // compatible = "adi,axi-sysid-1.00.a"; + // reg = <0x45000000 0x10000>; + // phandle = <0x42>; + // }; }; leds { @@ -862,81 +1056,81 @@ led0 { label = "led0:green"; - gpios = <0x6 0x3a 0x0>; + gpios = <0x09 0x3a 0x00>; }; led1 { label = "led1:green"; - gpios = <0x6 0x3b 0x0>; + gpios = <0x09 0x3b 0x00>; }; led2 { label = "led2:green"; - gpios = <0x6 0x3c 0x0>; + gpios = <0x09 0x3c 0x00>; }; led3 { label = "led3:green"; - gpios = <0x6 0x3d 0x0>; + gpios = <0x09 0x3d 0x00>; }; }; gpio_keys { compatible = "gpio-keys"; - #address-cells = <0x1>; - #size-cells = <0x0>; + #address-cells = <0x01>; + #size-cells = <0x00>; autorepeat; pb0 { label = "Left"; linux,code = <0x69>; - gpios = <0x6 0x36 0x0>; + gpios = <0x09 0x36 0x00>; }; pb1 { label = "Right"; linux,code = <0x6a>; - gpios = <0x6 0x37 0x0>; + gpios = <0x09 0x37 0x00>; }; pb2 { label = "Up"; linux,code = <0x67>; - gpios = <0x6 0x38 0x0>; + gpios = <0x09 0x38 0x00>; }; pb3 { label = "Down"; linux,code = <0x6c>; - gpios = <0x6 0x39 0x0>; + gpios = <0x09 0x39 0x00>; }; sw0 { label = "SW0"; - linux,input-type = <0x5>; - linux,code = <0x0>; - gpios = <0x6 0x3e 0x0>; + linux,input-type = <0x05>; + linux,code = <0x0d>; + gpios = <0x09 0x3e 0x00>; }; sw1 { label = "SW1"; - linux,input-type = <0x5>; - linux,code = <0x1>; - gpios = <0x6 0x3f 0x0>; + linux,input-type = <0x05>; + linux,code = <0x01>; + gpios = <0x09 0x3f 0x00>; }; sw2 { label = "SW2"; - linux,input-type = <0x5>; - linux,code = <0x2>; - gpios = <0x6 0x40 0x0>; + linux,input-type = <0x05>; + linux,code = <0x02>; + gpios = <0x09 0x40 0x00>; }; sw3 { label = "SW3"; - linux,input-type = <0x5>; - linux,code = <0x3>; - gpios = <0x6 0x41 0x0>; + linux,input-type = <0x05>; + linux,code = <0x03>; + gpios = <0x09 0x41 0x00>; }; }; }; diff --git a/kernel_boot/boards/adrv9364z7020/u-boot.elf b/kernel_boot/boards/adrv9364z7020/u-boot.elf index d074293..e2822e9 100644 Binary files a/kernel_boot/boards/adrv9364z7020/u-boot.elf and b/kernel_boot/boards/adrv9364z7020/u-boot.elf differ diff --git a/kernel_boot/boards/neptunesdr/devicetree.dtb b/kernel_boot/boards/neptunesdr/devicetree.dtb new file mode 100644 index 0000000..5c31a6f Binary files /dev/null and b/kernel_boot/boards/neptunesdr/devicetree.dtb differ diff --git a/kernel_boot/boards/neptunesdr/devicetree.dts b/kernel_boot/boards/neptunesdr/devicetree.dts new file mode 100644 index 0000000..d7c1c23 --- /dev/null +++ b/kernel_boot/boards/neptunesdr/devicetree.dts @@ -0,0 +1,1136 @@ +/dts-v1/; + +/ { + #address-cells = <0x01>; + #size-cells = <0x01>; + compatible = "xlnx,zynq-7000"; + interrupt-parent = <0x01>; + model = "neptunesdr"; + + cpus { + #address-cells = <0x01>; + #size-cells = <0x00>; + + cpu@0 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0x00>; + clocks = <0x02 0x03>; + clock-latency = <0x3e8>; + cpu0-supply = <0x03>; + operating-points = <0xa2c2b 0xf4240 0x51616 0xf4240>; + phandle = <0x11>; + }; + + cpu@1 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0x01>; + clocks = <0x02 0x03>; + phandle = <0x13>; + }; + }; + + fpga-full { + compatible = "fpga-region"; + fpga-mgr = <0x04>; + #address-cells = <0x01>; + #size-cells = <0x01>; + ranges; + phandle = <0x19>; + }; + + pmu@f8891000 { + compatible = "arm,cortex-a9-pmu"; + interrupts = <0x00 0x05 0x04 0x00 0x06 0x04>; + interrupt-parent = <0x01>; + reg = <0xf8891000 0x1000 0xf8893000 0x1000>; + }; + + fixedregulator { + compatible = "regulator-fixed"; + regulator-name = "VCCPINT"; + regulator-min-microvolt = <0xf4240>; + regulator-max-microvolt = <0xf4240>; + regulator-boot-on; + regulator-always-on; + phandle = <0x03>; + }; + + replicator { + compatible = "arm,coresight-static-replicator"; + clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>; + clock-names = "apb_pclk\0dbg_trc\0dbg_apb"; + + out-ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x05>; + phandle = <0x0d>; + }; + }; + + port@1 { + reg = <0x01>; + + endpoint { + remote-endpoint = <0x06>; + phandle = <0x0c>; + }; + }; + }; + + in-ports { + + port { + + endpoint { + remote-endpoint = <0x07>; + phandle = <0x0e>; + }; + }; + }; + }; + + axi { + u-boot,dm-pre-reloc; + compatible = "simple-bus"; + #address-cells = <0x01>; + #size-cells = <0x01>; + interrupt-parent = <0x01>; + ranges; + phandle = <0x1a>; + + adc@f8007100 { + compatible = "xlnx,zynq-xadc-1.00.a"; + reg = <0xf8007100 0x20>; + interrupts = <0x00 0x07 0x04>; + interrupt-parent = <0x01>; + clocks = <0x02 0x0c>; + phandle = <0x1b>; + }; + + can@e0008000 { + compatible = "xlnx,zynq-can-1.0"; + status = "disabled"; + clocks = <0x02 0x13 0x02 0x24>; + clock-names = "can_clk\0pclk"; + reg = <0xe0008000 0x1000>; + interrupts = <0x00 0x1c 0x04>; + interrupt-parent = <0x01>; + tx-fifo-depth = <0x40>; + rx-fifo-depth = <0x40>; + phandle = <0x1c>; + }; + + can@e0009000 { + compatible = "xlnx,zynq-can-1.0"; + status = "disabled"; + clocks = <0x02 0x14 0x02 0x25>; + clock-names = "can_clk\0pclk"; + reg = <0xe0009000 0x1000>; + interrupts = <0x00 0x33 0x04>; + interrupt-parent = <0x01>; + tx-fifo-depth = <0x40>; + rx-fifo-depth = <0x40>; + phandle = <0x1d>; + }; + + gpio@e000a000 { + compatible = "xlnx,zynq-gpio-1.0"; + #gpio-cells = <0x02>; + clocks = <0x02 0x2a>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <0x02>; + interrupt-parent = <0x01>; + interrupts = <0x00 0x14 0x04>; + reg = <0xe000a000 0x1000>; + phandle = <0x09>; + }; + + i2c@e0004000 { + compatible = "cdns,i2c-r1p10"; + status = "disabled"; + clocks = <0x02 0x26>; + interrupt-parent = <0x01>; + interrupts = <0x00 0x19 0x04>; + reg = <0xe0004000 0x1000>; + #address-cells = <0x01>; + #size-cells = <0x00>; + phandle = <0x1e>; + }; + + i2c@e0005000 { + compatible = "cdns,i2c-r1p10"; + status = "disabled"; + clocks = <0x02 0x27>; + interrupt-parent = <0x01>; + interrupts = <0x00 0x30 0x04>; + reg = <0xe0005000 0x1000>; + #address-cells = <0x01>; + #size-cells = <0x00>; + phandle = <0x1f>; + }; + + interrupt-controller@f8f01000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <0x03>; + interrupt-controller; + reg = <0xf8f01000 0x1000 0xf8f00100 0x100>; + phandle = <0x01>; + }; + + cache-controller@f8f02000 { + compatible = "arm,pl310-cache"; + reg = <0xf8f02000 0x1000>; + interrupts = <0x00 0x02 0x04>; + arm,data-latency = <0x03 0x02 0x02>; + arm,tag-latency = <0x02 0x02 0x02>; + cache-unified; + cache-level = <0x02>; + phandle = <0x20>; + }; + + memory-controller@f8006000 { + compatible = "xlnx,zynq-ddrc-a05"; + reg = <0xf8006000 0x1000>; + phandle = <0x21>; + }; + + ocmc@f800c000 { + compatible = "xlnx,zynq-ocmc-1.0"; + interrupt-parent = <0x01>; + interrupts = <0x00 0x03 0x04>; + reg = <0xf800c000 0x1000>; + phandle = <0x22>; + }; + + serial@e0000000 { + compatible = "xlnx,xuartps\0cdns,uart-r1p8"; + status = "disabled"; + clocks = <0x02 0x17 0x02 0x28>; + clock-names = "uart_clk\0pclk"; + reg = <0xe0000000 0x1000>; + interrupts = <0x00 0x1b 0x04>; + phandle = <0x23>; + }; + + serial@e0001000 { + compatible = "xlnx,xuartps\0cdns,uart-r1p8"; + status = "okay"; + clocks = <0x02 0x18 0x02 0x29>; + clock-names = "uart_clk\0pclk"; + reg = <0xe0001000 0x1000>; + interrupts = <0x00 0x32 0x04>; + phandle = <0x24>; + }; + + spi@e0006000 { + compatible = "xlnx,zynq-spi-r1p6"; + reg = <0xe0006000 0x1000>; + status = "okay"; + interrupt-parent = <0x01>; + interrupts = <0x00 0x1a 0x04>; + clocks = <0x02 0x19 0x02 0x22>; + clock-names = "ref_clk\0pclk"; + #address-cells = <0x01>; + #size-cells = <0x00>; + phandle = <0x25>; + + ad9361-phy@0 { + #address-cells = <0x1>; + #size-cells = <0x0>; + #clock-cells = <0x1>; + compatible = "adi,ad9361"; + reg = <0x0>; + spi-cpha; + spi-max-frequency = <0x989680>; + clocks = <0x08 0x00>; + clock-names = "ad9361_ext_refclk"; + clock-output-names = "rx_sampl_clk", "tx_sampl_clk"; + adi,digital-interface-tune-skip-mode = <0x0>; + adi,pp-tx-swap-enable; + adi,pp-rx-swap-enable; + adi,rx-frame-pulse-mode-enable; + adi,lvds-mode-enable; + adi,lvds-bias-mV = <0x96>; + adi,lvds-rx-onchip-termination-enable; + adi,rx-data-delay = <0x4>; + adi,tx-fb-clock-delay = <0x7>; + adi,xo-disable-use-ext-refclk-enable; + adi,2rx-2tx-mode-enable; + adi,frequency-division-duplex-mode-enable; + adi,rx-rf-port-input-select = <0x0>; + adi,tx-rf-port-input-select = <0x0>; + adi,tx-attenuation-mdB = <0x2710>; + adi,tx-lo-powerdown-managed-enable; + adi,rf-rx-bandwidth-hz = <0x112a880>; + adi,rf-tx-bandwidth-hz = <0x112a880>; + adi,rx-synthesizer-frequency-hz = <0x0 0x8f0d1800>; + adi,tx-synthesizer-frequency-hz = <0x0 0x92080880>; + adi,rx-path-clock-frequencies = <0x3a980000 0xea60000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>; + adi,tx-path-clock-frequencies = <0x3a980000 0x7530000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>; + adi,gc-rx1-mode = <0x2>; + adi,gc-rx2-mode = <0x2>; + adi,gc-adc-ovr-sample-size = <0x4>; + adi,gc-adc-small-overload-thresh = <0x2f>; + adi,gc-adc-large-overload-thresh = <0x3a>; + adi,gc-lmt-overload-high-thresh = <0x320>; + adi,gc-lmt-overload-low-thresh = <0x2c0>; + adi,gc-dec-pow-measurement-duration = <0x2000>; + adi,gc-low-power-thresh = <0x18>; + adi,mgc-inc-gain-step = <0x2>; + adi,mgc-dec-gain-step = <0x2>; + adi,mgc-split-table-ctrl-inp-gain-mode = <0x0>; + adi,agc-attack-delay-extra-margin-us = <0x1>; + adi,agc-outer-thresh-high = <0x5>; + adi,agc-outer-thresh-high-dec-steps = <0x2>; + adi,agc-inner-thresh-high = <0xa>; + adi,agc-inner-thresh-high-dec-steps = <0x1>; + adi,agc-inner-thresh-low = <0xc>; + adi,agc-inner-thresh-low-inc-steps = <0x1>; + adi,agc-outer-thresh-low = <0x12>; + adi,agc-outer-thresh-low-inc-steps = <0x2>; + adi,agc-adc-small-overload-exceed-counter = <0xa>; + adi,agc-adc-large-overload-exceed-counter = <0xa>; + adi,agc-adc-large-overload-inc-steps = <0x2>; + adi,agc-lmt-overload-large-exceed-counter = <0xa>; + adi,agc-lmt-overload-small-exceed-counter = <0xa>; + adi,agc-lmt-overload-large-inc-steps = <0x2>; + adi,agc-gain-update-interval-us = <0x3e8>; + adi,fagc-dec-pow-measurement-duration = <0x40>; + adi,fagc-lp-thresh-increment-steps = <0x1>; + adi,fagc-lp-thresh-increment-time = <0x5>; + adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <0x8>; + adi,fagc-final-overrange-count = <0x3>; + adi,fagc-gain-index-type-after-exit-rx-mode = <0x0>; + adi,fagc-lmt-final-settling-steps = <0x1>; + adi,fagc-lock-level = <0xa>; + adi,fagc-lock-level-gain-increase-upper-limit = <0x5>; + adi,fagc-lock-level-lmt-gain-increase-enable; + adi,fagc-lpf-final-settling-steps = <0x1>; + adi,fagc-optimized-gain-offset = <0x5>; + adi,fagc-power-measurement-duration-in-state5 = <0x40>; + adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable; + adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <0xa>; + adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable; + adi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0x0>; + adi,fagc-rst-gla-large-adc-overload-enable; + adi,fagc-rst-gla-large-lmt-overload-enable; + adi,fagc-rst-gla-stronger-sig-thresh-above-ll = <0xa>; + adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable; + adi,fagc-state-wait-time-ns = <0x104>; + adi,fagc-use-last-lock-level-for-set-gain-enable; + adi,rssi-restart-mode = <0x3>; + adi,rssi-delay = <0x1>; + adi,rssi-wait = <0x1>; + adi,rssi-duration = <0x3e8>; + adi,ctrl-outs-index = <0x0>; + adi,ctrl-outs-enable-mask = <0xff>; + adi,temp-sense-measurement-interval-ms = <0x3e8>; + adi,temp-sense-offset-signed = <0xce>; + adi,temp-sense-periodic-measurement-enable; + adi,aux-dac-manual-mode-enable; + adi,aux-dac1-default-value-mV = <0x0>; + adi,aux-dac1-rx-delay-us = <0x0>; + adi,aux-dac1-tx-delay-us = <0x0>; + adi,aux-dac2-default-value-mV = <0x0>; + adi,aux-dac2-rx-delay-us = <0x0>; + adi,aux-dac2-tx-delay-us = <0x0>; + en_agc-gpios = <0x09 0x62 0x0>; + sync-gpios = <0x09 0x63 0x0>; + reset-gpios = <0x09 0x64 0x0>; + enable-gpios = <0x09 0x65 0x0>; + txnrx-gpios = <0x09 0x66 0x0>; + phandle = <0x17>; + }; + }; + + spi@e0007000 { + compatible = "xlnx,zynq-spi-r1p6"; + reg = <0xe0007000 0x1000>; + status = "disabled"; + interrupt-parent = <0x01>; + interrupts = <0x00 0x31 0x04>; + clocks = <0x02 0x1a 0x02 0x23>; + clock-names = "ref_clk\0pclk"; + #address-cells = <0x01>; + #size-cells = <0x00>; + phandle = <0x26>; + }; + + spi@e000d000 { + clock-names = "ref_clk\0pclk"; + clocks = <0x02 0x0a 0x02 0x2b>; + compatible = "xlnx,zynq-qspi-1.0"; + status = "okay"; + interrupt-parent = <0x01>; + interrupts = <0x00 0x13 0x04>; + reg = <0xe000d000 0x1000>; + #address-cells = <0x01>; + #size-cells = <0x00>; + is-dual = <0x00>; + num-cs = <0x01>; + phandle = <0x27>; + + ps7-qspi@0 { + #address-cells = <0x01>; + #size-cells = <0x01>; + spi-tx-bus-width = <0x01>; + spi-rx-bus-width = <0x04>; + compatible = "n25q256a\0jedec,spi-nor"; + reg = <0x00>; + spi-max-frequency = <0x2faf080>; + phandle = <0x28>; + + partition@qspi-fsbl-uboot { + label = "qspi-fsbl-uboot"; + reg = <0x00 0xe0000>; + }; + + partition@qspi-uboot-env { + label = "qspi-uboot-env"; + reg = <0xe0000 0x20000>; + }; + + partition@qspi-linux { + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + + partition@qspi-device-tree { + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + + partition@qspi-rootfs { + label = "qspi-rootfs"; + reg = <0x620000 0xce0000>; + }; + + partition@qspi-bitstream { + label = "qspi-bitstream"; + reg = <0x1300000 0xd00000>; + }; + }; + }; + + memory-controller@e000e000 { + #address-cells = <0x01>; + #size-cells = <0x01>; + status = "disabled"; + clock-names = "memclk\0apb_pclk"; + clocks = <0x02 0x0b 0x02 0x2c>; + compatible = "arm,pl353-smc-r2p1\0arm,primecell"; + interrupt-parent = <0x01>; + interrupts = <0x00 0x12 0x04>; + ranges; + reg = <0xe000e000 0x1000>; + phandle = <0x29>; + + flash@e1000000 { + status = "disabled"; + compatible = "arm,pl353-nand-r2p1"; + reg = <0xe1000000 0x1000000>; + #address-cells = <0x01>; + #size-cells = <0x01>; + phandle = <0x2a>; + }; + + flash@e2000000 { + status = "disabled"; + compatible = "cfi-flash"; + reg = <0xe2000000 0x2000000>; + #address-cells = <0x01>; + #size-cells = <0x01>; + phandle = <0x2b>; + }; + }; + + ethernet@e000b000 { + compatible = "cdns,zynq-gem\0cdns,gem"; + reg = <0xe000b000 0x1000>; + status = "okay"; + interrupts = <0x00 0x16 0x04>; + clocks = <0x02 0x1e 0x02 0x1e 0x02 0x0d>; + clock-names = "pclk\0hclk\0tx_clk"; + #address-cells = <0x01>; + #size-cells = <0x00>; + phy-handle = <0x0a>; + phy-mode = "rgmii-id"; + phandle = <0x2c>; + + phy@0 { + device_type = "ethernet-phy"; + reg = <0x00>; + marvell,reg-init = <0x03 0x10 0xff00 0x1e 0x03 0x11 0xfff0 0x00>; + phandle = <0x0a>; + }; + }; + + ethernet@e000c000 { + compatible = "cdns,zynq-gem\0cdns,gem"; + reg = <0xe000c000 0x1000>; + status = "disabled"; + interrupts = <0x00 0x2d 0x04>; + clocks = <0x02 0x1f 0x02 0x1f 0x02 0x0e>; + clock-names = "pclk\0hclk\0tx_clk"; + #address-cells = <0x01>; + #size-cells = <0x00>; + phandle = <0x2d>; + }; + + mmc@e0100000 { + compatible = "arasan,sdhci-8.9a"; + status = "okay"; + clock-names = "clk_xin\0clk_ahb"; + clocks = <0x02 0x15 0x02 0x20>; + interrupt-parent = <0x01>; + interrupts = <0x00 0x18 0x04>; + reg = <0xe0100000 0x1000>; + disable-wp; + phandle = <0x2e>; + }; + + mmc@e0101000 { + compatible = "arasan,sdhci-8.9a"; + status = "disabled"; + clock-names = "clk_xin\0clk_ahb"; + clocks = <0x02 0x16 0x02 0x21>; + interrupt-parent = <0x01>; + interrupts = <0x00 0x2f 0x04>; + reg = <0xe0101000 0x1000>; + phandle = <0x2f>; + }; + + slcr@f8000000 { + u-boot,dm-pre-reloc; + #address-cells = <0x01>; + #size-cells = <0x01>; + compatible = "xlnx,zynq-slcr\0syscon\0simple-mfd"; + reg = <0xf8000000 0x1000>; + ranges; + phandle = <0x0b>; + + clkc@100 { + u-boot,dm-pre-reloc; + #clock-cells = <0x01>; + compatible = "xlnx,ps7-clkc"; + fclk-enable = <0x0f>; + clock-output-names = "armpll\0ddrpll\0iopll\0cpu_6or4x\0cpu_3or2x\0cpu_2x\0cpu_1x\0ddr2x\0ddr3x\0dci\0lqspi\0smc\0pcap\0gem0\0gem1\0fclk0\0fclk1\0fclk2\0fclk3\0can0\0can1\0sdio0\0sdio1\0uart0\0uart1\0spi0\0spi1\0dma\0usb0_aper\0usb1_aper\0gem0_aper\0gem1_aper\0sdio0_aper\0sdio1_aper\0spi0_aper\0spi1_aper\0can0_aper\0can1_aper\0i2c0_aper\0i2c1_aper\0uart0_aper\0uart1_aper\0gpio_aper\0lqspi_aper\0smc_aper\0swdt\0dbg_trc\0dbg_apb"; + reg = <0x100 0x100>; + ps-clk-frequency = <0x1fca055>; + phandle = <0x02>; + }; + + rstc@200 { + compatible = "xlnx,zynq-reset"; + reg = <0x200 0x48>; + #reset-cells = <0x01>; + syscon = <0x0b>; + phandle = <0x30>; + }; + + pinctrl@700 { + compatible = "xlnx,pinctrl-zynq"; + reg = <0x700 0x200>; + syscon = <0x0b>; + phandle = <0x31>; + }; + }; + + dmac@f8003000 { + compatible = "arm,pl330\0arm,primecell"; + reg = <0xf8003000 0x1000>; + interrupt-parent = <0x01>; + interrupt-names = "abort\0dma0\0dma1\0dma2\0dma3\0dma4\0dma5\0dma6\0dma7"; + interrupts = <0x00 0x0d 0x04 0x00 0x0e 0x04 0x00 0x0f 0x04 0x00 0x10 0x04 0x00 0x11 0x04 0x00 0x28 0x04 0x00 0x29 0x04 0x00 0x2a 0x04 0x00 0x2b 0x04>; + #dma-cells = <0x01>; + #dma-channels = <0x08>; + #dma-requests = <0x04>; + clocks = <0x02 0x1b>; + clock-names = "apb_pclk"; + phandle = <0x32>; + }; + + devcfg@f8007000 { + compatible = "xlnx,zynq-devcfg-1.0"; + interrupt-parent = <0x01>; + interrupts = <0x00 0x08 0x04>; + reg = <0xf8007000 0x100>; + clocks = <0x02 0x0c 0x02 0x0f 0x02 0x10 0x02 0x11 0x02 0x12>; + clock-names = "ref_clk\0fclk0\0fclk1\0fclk2\0fclk3"; + syscon = <0x0b>; + phandle = <0x04>; + }; + + efuse@f800d000 { + compatible = "xlnx,zynq-efuse"; + reg = <0xf800d000 0x20>; + phandle = <0x33>; + }; + + timer@f8f00200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0xf8f00200 0x20>; + interrupts = <0x01 0x0b 0x301>; + interrupt-parent = <0x01>; + clocks = <0x02 0x04>; + phandle = <0x34>; + }; + + timer@f8001000 { + interrupt-parent = <0x01>; + interrupts = <0x00 0x0a 0x04 0x00 0x0b 0x04 0x00 0x0c 0x04>; + compatible = "cdns,ttc"; + clocks = <0x02 0x06>; + reg = <0xf8001000 0x1000>; + phandle = <0x35>; + }; + + timer@f8002000 { + interrupt-parent = <0x01>; + interrupts = <0x00 0x25 0x04 0x00 0x26 0x04 0x00 0x27 0x04>; + compatible = "cdns,ttc"; + clocks = <0x02 0x06>; + reg = <0xf8002000 0x1000>; + phandle = <0x36>; + }; + + timer@f8f00600 { + interrupt-parent = <0x01>; + interrupts = <0x01 0x0d 0x301>; + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xf8f00600 0x20>; + clocks = <0x02 0x04>; + phandle = <0x37>; + }; + + usb@e0002000 { + compatible = "xlnx,zynq-usb-2.20a\0chipidea,usb2"; + status = "okay"; + clocks = <0x02 0x1c>; + interrupt-parent = <0x01>; + interrupts = <0x00 0x15 0x04>; + reg = <0xe0002000 0x1000>; + phy_type = "ulpi"; + dr_mode = "host"; + xlnx,phy-reset-gpio = <0x09 0x07 0x00>; + phandle = <0x38>; + }; + + usb@e0003000 { + compatible = "xlnx,zynq-usb-2.20a\0chipidea,usb2"; + status = "disabled"; + clocks = <0x02 0x1d>; + interrupt-parent = <0x01>; + interrupts = <0x00 0x2c 0x04>; + reg = <0xe0003000 0x1000>; + phy_type = "ulpi"; + phandle = <0x39>; + }; + + watchdog@f8005000 { + clocks = <0x02 0x2d>; + compatible = "cdns,wdt-r1p2"; + interrupt-parent = <0x01>; + interrupts = <0x00 0x09 0x01>; + reg = <0xf8005000 0x1000>; + timeout-sec = <0x0a>; + phandle = <0x3a>; + }; + + etb@f8801000 { + compatible = "arm,coresight-etb10\0arm,primecell"; + reg = <0xf8801000 0x1000>; + clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>; + clock-names = "apb_pclk\0dbg_trc\0dbg_apb"; + + in-ports { + + port { + + endpoint { + remote-endpoint = <0x0c>; + phandle = <0x06>; + }; + }; + }; + }; + + tpiu@f8803000 { + compatible = "arm,coresight-tpiu\0arm,primecell"; + reg = <0xf8803000 0x1000>; + clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>; + clock-names = "apb_pclk\0dbg_trc\0dbg_apb"; + + in-ports { + + port { + + endpoint { + remote-endpoint = <0x0d>; + phandle = <0x05>; + }; + }; + }; + }; + + funnel@f8804000 { + compatible = "arm,coresight-static-funnel\0arm,primecell"; + reg = <0xf8804000 0x1000>; + clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>; + clock-names = "apb_pclk\0dbg_trc\0dbg_apb"; + + out-ports { + + port { + + endpoint { + remote-endpoint = <0x0e>; + phandle = <0x07>; + }; + }; + }; + + in-ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x0f>; + phandle = <0x12>; + }; + }; + + port@1 { + reg = <0x01>; + + endpoint { + remote-endpoint = <0x10>; + phandle = <0x14>; + }; + }; + + port@2 { + reg = <0x02>; + + endpoint { + phandle = <0x3b>; + }; + }; + }; + }; + + ptm@f889c000 { + compatible = "arm,coresight-etm3x\0arm,primecell"; + reg = <0xf889c000 0x1000>; + clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>; + clock-names = "apb_pclk\0dbg_trc\0dbg_apb"; + cpu = <0x11>; + + out-ports { + + port { + + endpoint { + remote-endpoint = <0x12>; + phandle = <0x0f>; + }; + }; + }; + }; + + ptm@f889d000 { + compatible = "arm,coresight-etm3x\0arm,primecell"; + reg = <0xf889d000 0x1000>; + clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>; + clock-names = "apb_pclk\0dbg_trc\0dbg_apb"; + cpu = <0x13>; + + out-ports { + + port { + + endpoint { + remote-endpoint = <0x14>; + phandle = <0x10>; + }; + }; + }; + }; + }; + + aliases { + ethernet0 = "/axi/ethernet@e000b000"; + serial0 = "/axi/serial@e0001000"; + phandle = <0x3c>; + }; + + memory { + device_type = "memory"; + reg = <0x00 0x20000000>; + }; + + chosen { + stdout-path = "/amba@0/uart@E0001000"; + }; + + clocks { + + clock@0 { + #clock-cells = <0x00>; + compatible = "adjustable-clock"; + clock-frequency = <0x2625a00>; + clock-accuracy = <0x30d40>; + clock-output-names = "ad9364_ext_refclk"; + phandle = <0x08>; + }; + + clock@1 { + #clock-cells = <0x00>; + compatible = "fixed-clock"; + clock-frequency = <0x16e3600>; + clock-output-names = "24MHz"; + phandle = <0x15>; + }; + }; + + usb-ulpi-gpio-gate@0 { + compatible = "gpio-gate-clock"; + clocks = <0x15>; + #clock-cells = <0x00>; + enable-gpios = <0x09 0x09 0x01>; + phandle = <0x3d>; + }; + + fpga-axi@0 { + compatible = "simple-bus"; + #address-cells = <0x01>; + #size-cells = <0x01>; + ranges; + phandle = <0x3e>; + + i2c@41600000 { + compatible = "xlnx,axi-iic-1.02.a\0xlnx,xps-iic-2.00.a"; + reg = <0x41600000 0x10000>; + interrupt-parent = <0x01>; + interrupts = <0x00 0x3a 0x04>; + clocks = <0x02 0x0f>; + clock-names = "pclk"; + #address-cells = <0x01>; + #size-cells = <0x00>; + phandle = <0x3f>; + + ad7291@20 { + compatible = "adi,ad7291"; + reg = <0x20>; + }; + + ad7291-bob@2C { + compatible = "adi,ad7291"; + reg = <0x2c>; + }; + + eeprom@50 { + compatible = "at24,24c32"; + reg = <0x50>; + }; + }; + + // dma@7c400000 { + // compatible = "adi,axi-dmac-1.00.a"; + // reg = <0x7c400000 0x10000>; + // #dma-cells = <0x01>; + // interrupts = <0x00 0x39 0x04>; + // clocks = <0x02 0x10>; + // phandle = <0x16>; + + // adi,channels { + // #size-cells = <0x00>; + // #address-cells = <0x01>; + + // dma-channel@0 { + // reg = <0x00>; + // adi,source-bus-width = <0x40>; + // adi,source-bus-type = <0x02>; + // adi,destination-bus-width = <0x40>; + // adi,destination-bus-type = <0x00>; + // }; + // }; + // }; + + // dma@7c420000 { + // compatible = "adi,axi-dmac-1.00.a"; + // reg = <0x7c420000 0x10000>; + // #dma-cells = <0x01>; + // interrupts = <0x00 0x38 0x04>; + // clocks = <0x02 0x10>; + // phandle = <0x18>; + + // adi,channels { + // #size-cells = <0x00>; + // #address-cells = <0x01>; + + // dma-channel@0 { + // reg = <0x00>; + // adi,source-bus-width = <0x40>; + // adi,source-bus-type = <0x00>; + // adi,destination-bus-width = <0x40>; + // adi,destination-bus-type = <0x02>; + // }; + // }; + // }; + + sdr: sdr { + compatible ="sdr,sdr"; + dmas = <&rx_dma 1 + &tx_dma 0>; + dma-names = "rx_dma_s2mm", "tx_dma_mm2s"; + interrupt-names = "not_valid_anymore", "rx_pkt_intr", "tx_itrpt"; + interrupt-parent = <1>; + interrupts = <0 29 1 0 30 1 0 33 1 0 34 1>; + } ; + + // axidmatest_1: axidmatest@1 { + // compatible ="xlnx,axi-dma-test-1.00.a"; + // dmas = <&rx_dma 0 + // &rx_dma 1>; + // dma-names = "axidma0", "axidma1"; + // } ; + + tx_dma: dma@80400000 { + #dma-cells = <1>; + clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk"; + clocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>; + compatible = "xlnx,axi-dma-1.00.a"; + interrupt-names = "mm2s_introut", "s2mm_introut"; + interrupt-parent = <1>; + interrupts = <0 35 4 0 36 4>; + reg = <0x80400000 0x10000>; + xlnx,addrwidth = <0x20>; + xlnx,include-sg ; + xlnx,sg-length-width = <0xe>; + dma-channel@80400000 { + compatible = "xlnx,axi-dma-mm2s-channel"; + dma-channels = <0x1>; + interrupts = <0 35 4>; + xlnx,datawidth = <0x40>; + xlnx,device-id = <0x0>; + }; + dma-channel@80400030 { + compatible = "xlnx,axi-dma-s2mm-channel"; + dma-channels = <0x1>; + interrupts = <0 36 4>; + xlnx,datawidth = <0x40>; + xlnx,device-id = <0x0>; + }; + }; + + rx_dma: dma@80410000 { + #dma-cells = <1>; + clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk"; + clocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>; + compatible = "xlnx,axi-dma-1.00.a"; + //dma-coherent ; + interrupt-names = "mm2s_introut", "s2mm_introut"; + interrupt-parent = <1>; + interrupts = <0 31 4 0 32 4>; + reg = <0x80410000 0x10000>; + xlnx,addrwidth = <0x20>; + xlnx,include-sg ; + xlnx,sg-length-width = <0xe>; + dma-channel@80410000 { + compatible = "xlnx,axi-dma-mm2s-channel"; + dma-channels = <0x1>; + interrupts = <0 31 4>; + xlnx,datawidth = <0x40>; + xlnx,device-id = <0x1>; + }; + dma-channel@80410030 { + compatible = "xlnx,axi-dma-s2mm-channel"; + dma-channels = <0x1>; + interrupts = <0 32 4>; + xlnx,datawidth = <0x40>; + xlnx,device-id = <0x1>; + }; + }; + + tx_intf_0: tx_intf@83c00000 { + clock-names = "s00_axi_aclk", "s00_axis_aclk";//, "s01_axis_aclk", "m00_axis_aclk"; + clocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>, <0x2 0x11>; + compatible = "sdr,tx_intf"; + interrupt-names = "tx_itrpt"; + interrupt-parent = <1>; + interrupts = <0 34 1>; + reg = <0x83c00000 0x10000>; + xlnx,s00-axi-addr-width = <0x7>; + xlnx,s00-axi-data-width = <0x20>; + }; + + rx_intf_0: rx_intf@83c20000 { + clock-names = "s00_axi_aclk", "m00_axis_aclk";//, "s00_axis_aclk"; + clocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>; + compatible = "sdr,rx_intf"; + interrupt-names = "not_valid_anymore", "rx_pkt_intr"; + interrupt-parent = <1>; + interrupts = <0 29 1 0 30 1>; + reg = <0x83c20000 0x10000>; + xlnx,s00-axi-addr-width = <0x7>; + xlnx,s00-axi-data-width = <0x20>; + }; + + openofdm_tx_0: openofdm_tx@83c10000 { + clock-names = "clk"; + clocks = <0x2 0x11>; + compatible = "sdr,openofdm_tx"; + reg = <0x83c10000 0x10000>; + }; + + openofdm_rx_0: openofdm_rx@83c30000 { + clock-names = "clk"; + clocks = <0x2 0x11>; + compatible = "sdr,openofdm_rx"; + reg = <0x83c30000 0x10000>; + }; + + xpu_0: xpu@83c40000 { + clock-names = "s00_axi_aclk"; + clocks = <0x2 0x11>; + compatible = "sdr,xpu"; + reg = <0x83c40000 0x10000>; + }; + + side_ch_0: side_ch@83c50000 { + clock-names = "s00_axi_aclk"; + clocks = <0x2 0x11>; + compatible = "sdr,side_ch"; + reg = <0x83c50000 0x10000>; + dmas = <&rx_dma 0 + &tx_dma 1>; + dma-names = "rx_dma_mm2s", "tx_dma_s2mm"; + }; + + cf-ad9361-lpc@79020000 { + compatible = "adi,axi-ad9361-6.00.a"; + reg = <0x79020000 0x6000>; + // dmas = <0x16 0x00>; + // dma-names = "rx"; + spibus-connected = <0x17>; + phandle = <0x40>; + }; + + cf-ad9361-dds-core-lpc@79024000 { + compatible = "adi,axi-ad9361-dds-6.00.a"; + reg = <0x79024000 0x1000>; + clocks = <0x17 0x0d>; + clock-names = "sampl_clk"; + // dmas = <0x18 0x00>; + // dma-names = "tx"; + phandle = <0x41>; + }; + + mwipcore@43c00000 { + compatible = "mathworks,mwipcore-axi4lite-v1.00"; + reg = <0x43c00000 0xffff>; + }; + + // axi-sysid-0@45000000 { + // compatible = "adi,axi-sysid-1.00.a"; + // reg = <0x45000000 0x10000>; + // phandle = <0x42>; + // }; + }; + + leds { + compatible = "gpio-leds"; + + led0 { + label = "led0:green"; + gpios = <0x09 0x3a 0x00>; + }; + + led1 { + label = "led1:green"; + gpios = <0x09 0x3b 0x00>; + }; + + led2 { + label = "led2:green"; + gpios = <0x09 0x3c 0x00>; + }; + + led3 { + label = "led3:green"; + gpios = <0x09 0x3d 0x00>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <0x01>; + #size-cells = <0x00>; + autorepeat; + + pb0 { + label = "Left"; + linux,code = <0x69>; + gpios = <0x09 0x36 0x00>; + }; + + pb1 { + label = "Right"; + linux,code = <0x6a>; + gpios = <0x09 0x37 0x00>; + }; + + pb2 { + label = "Up"; + linux,code = <0x67>; + gpios = <0x09 0x38 0x00>; + }; + + pb3 { + label = "Down"; + linux,code = <0x6c>; + gpios = <0x09 0x39 0x00>; + }; + + sw0 { + label = "SW0"; + linux,input-type = <0x05>; + linux,code = <0x0d>; + gpios = <0x09 0x3e 0x00>; + }; + + sw1 { + label = "SW1"; + linux,input-type = <0x05>; + linux,code = <0x01>; + gpios = <0x09 0x3f 0x00>; + }; + + sw2 { + label = "SW2"; + linux,input-type = <0x05>; + linux,code = <0x02>; + gpios = <0x09 0x40 0x00>; + }; + + sw3 { + label = "SW3"; + linux,input-type = <0x05>; + linux,code = <0x03>; + gpios = <0x09 0x41 0x00>; + }; + }; +}; diff --git a/kernel_boot/boards/neptunesdr/u-boot.elf b/kernel_boot/boards/neptunesdr/u-boot.elf new file mode 100644 index 0000000..d074293 Binary files /dev/null and b/kernel_boot/boards/neptunesdr/u-boot.elf differ diff --git a/kernel_boot/boards/sdrpi/devicetree.dtb b/kernel_boot/boards/sdrpi/devicetree.dtb index 57af366..7bcc608 100644 Binary files a/kernel_boot/boards/sdrpi/devicetree.dtb and b/kernel_boot/boards/sdrpi/devicetree.dtb differ diff --git a/kernel_boot/boards/zc702_fmcs2/devicetree.dtb b/kernel_boot/boards/zc702_fmcs2/devicetree.dtb index 4cd81a1..a9dfab3 100644 Binary files a/kernel_boot/boards/zc702_fmcs2/devicetree.dtb and b/kernel_boot/boards/zc702_fmcs2/devicetree.dtb differ diff --git a/kernel_boot/boards/zc702_fmcs2/devicetree.dts b/kernel_boot/boards/zc702_fmcs2/devicetree.dts index ee59b40..e993da4 100644 --- a/kernel_boot/boards/zc702_fmcs2/devicetree.dts +++ b/kernel_boot/boards/zc702_fmcs2/devicetree.dts @@ -1,46 +1,49 @@ /dts-v1/; / { - #address-cells = <0x1>; - #size-cells = <0x1>; + #address-cells = <0x01>; + #size-cells = <0x01>; compatible = "xlnx,zynq-7000"; - interrupt-parent = <0x1>; + interrupt-parent = <0x01>; model = "Xilinx Zynq ZC702"; cpus { - #address-cells = <0x1>; - #size-cells = <0x0>; + #address-cells = <0x01>; + #size-cells = <0x00>; cpu@0 { compatible = "arm,cortex-a9"; device_type = "cpu"; - reg = <0x0>; - clocks = <0x2 0x3>; + reg = <0x00>; + clocks = <0x02 0x03>; clock-latency = <0x3e8>; - cpu0-supply = <0x3>; + cpu0-supply = <0x03>; operating-points = <0xa2c2b 0xf4240 0x51616 0xf4240>; + phandle = <0x12>; }; cpu@1 { compatible = "arm,cortex-a9"; device_type = "cpu"; - reg = <0x1>; - clocks = <0x2 0x3>; + reg = <0x01>; + clocks = <0x02 0x03>; + phandle = <0x14>; }; }; fpga-full { compatible = "fpga-region"; - fpga-mgr = <0x4>; - #address-cells = <0x1>; - #size-cells = <0x1>; + fpga-mgr = <0x04>; + #address-cells = <0x01>; + #size-cells = <0x01>; ranges; + phandle = <0x21>; }; pmu@f8891000 { compatible = "arm,cortex-a9-pmu"; - interrupts = <0x0 0x5 0x4 0x0 0x6 0x4>; - interrupt-parent = <0x1>; + interrupts = <0x00 0x05 0x04 0x00 0x06 0x04>; + interrupt-parent = <0x01>; reg = <0xf8891000 0x1000 0xf8893000 0x1000>; }; @@ -51,251 +54,299 @@ regulator-max-microvolt = <0xf4240>; regulator-boot-on; regulator-always-on; - linux,phandle = <0x3>; - phandle = <0x3>; + phandle = <0x03>; }; - amba { + replicator { + compatible = "arm,coresight-static-replicator"; + clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>; + clock-names = "apb_pclk\0dbg_trc\0dbg_apb"; + + out-ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x05>; + phandle = <0x0e>; + }; + }; + + port@1 { + reg = <0x01>; + + endpoint { + remote-endpoint = <0x06>; + phandle = <0x0d>; + }; + }; + }; + + in-ports { + + port { + + endpoint { + remote-endpoint = <0x07>; + phandle = <0x0f>; + }; + }; + }; + }; + + axi { u-boot,dm-pre-reloc; compatible = "simple-bus"; - #address-cells = <0x1>; - #size-cells = <0x1>; - interrupt-parent = <0x1>; + #address-cells = <0x01>; + #size-cells = <0x01>; + interrupt-parent = <0x01>; ranges; + phandle = <0x22>; adc@f8007100 { compatible = "xlnx,zynq-xadc-1.00.a"; reg = <0xf8007100 0x20>; - interrupts = <0x0 0x7 0x4>; - interrupt-parent = <0x1>; - clocks = <0x2 0xc>; + interrupts = <0x00 0x07 0x04>; + interrupt-parent = <0x01>; + clocks = <0x02 0x0c>; + phandle = <0x23>; }; can@e0008000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; - clocks = <0x2 0x13 0x2 0x24>; - clock-names = "can_clk", "pclk"; + clocks = <0x02 0x13 0x02 0x24>; + clock-names = "can_clk\0pclk"; reg = <0xe0008000 0x1000>; - interrupts = <0x0 0x1c 0x4>; - interrupt-parent = <0x1>; + interrupts = <0x00 0x1c 0x04>; + interrupt-parent = <0x01>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; + phandle = <0x24>; }; can@e0009000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; - clocks = <0x2 0x14 0x2 0x25>; - clock-names = "can_clk", "pclk"; + clocks = <0x02 0x14 0x02 0x25>; + clock-names = "can_clk\0pclk"; reg = <0xe0009000 0x1000>; - interrupts = <0x0 0x33 0x4>; - interrupt-parent = <0x1>; + interrupts = <0x00 0x33 0x04>; + interrupt-parent = <0x01>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; + phandle = <0x25>; }; gpio@e000a000 { compatible = "xlnx,zynq-gpio-1.0"; - #gpio-cells = <0x2>; - clocks = <0x2 0x2a>; + #gpio-cells = <0x02>; + clocks = <0x02 0x2a>; gpio-controller; interrupt-controller; - #interrupt-cells = <0x2>; - interrupt-parent = <0x1>; - interrupts = <0x0 0x14 0x4>; + #interrupt-cells = <0x02>; + interrupt-parent = <0x01>; + interrupts = <0x00 0x14 0x04>; reg = <0xe000a000 0x1000>; - linux,phandle = <0x6>; - phandle = <0x6>; + phandle = <0x09>; }; i2c@e0004000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; - clocks = <0x2 0x26>; - interrupt-parent = <0x1>; - interrupts = <0x0 0x19 0x4>; + clocks = <0x02 0x26>; + interrupt-parent = <0x01>; + interrupts = <0x00 0x19 0x04>; reg = <0xe0004000 0x1000>; - #address-cells = <0x1>; - #size-cells = <0x0>; + #address-cells = <0x01>; + #size-cells = <0x00>; + phandle = <0x26>; }; i2c@e0005000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; - clocks = <0x2 0x27>; - interrupt-parent = <0x1>; - interrupts = <0x0 0x30 0x4>; + clocks = <0x02 0x27>; + interrupt-parent = <0x01>; + interrupts = <0x00 0x30 0x04>; reg = <0xe0005000 0x1000>; - #address-cells = <0x1>; - #size-cells = <0x0>; + #address-cells = <0x01>; + #size-cells = <0x00>; + phandle = <0x27>; }; interrupt-controller@f8f01000 { compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <0x3>; + #interrupt-cells = <0x03>; interrupt-controller; reg = <0xf8f01000 0x1000 0xf8f00100 0x100>; - linux,phandle = <0x1>; - phandle = <0x1>; + phandle = <0x01>; }; cache-controller@f8f02000 { compatible = "arm,pl310-cache"; reg = <0xf8f02000 0x1000>; - interrupts = <0x0 0x2 0x4>; - arm,data-latency = <0x3 0x2 0x2>; - arm,tag-latency = <0x2 0x2 0x2>; + interrupts = <0x00 0x02 0x04>; + arm,data-latency = <0x03 0x02 0x02>; + arm,tag-latency = <0x02 0x02 0x02>; cache-unified; - cache-level = <0x2>; + cache-level = <0x02>; + phandle = <0x28>; }; memory-controller@f8006000 { compatible = "xlnx,zynq-ddrc-a05"; reg = <0xf8006000 0x1000>; + phandle = <0x29>; }; ocmc@f800c000 { compatible = "xlnx,zynq-ocmc-1.0"; - interrupt-parent = <0x1>; - interrupts = <0x0 0x3 0x4>; + interrupt-parent = <0x01>; + interrupts = <0x00 0x03 0x04>; reg = <0xf800c000 0x1000>; + phandle = <0x2a>; }; serial@e0000000 { - compatible = "xlnx,xuartps", "cdns,uart-r1p8"; + compatible = "xlnx,xuartps\0cdns,uart-r1p8"; status = "disabled"; - clocks = <0x2 0x17 0x2 0x28>; - clock-names = "uart_clk", "pclk"; + clocks = <0x02 0x17 0x02 0x28>; + clock-names = "uart_clk\0pclk"; reg = <0xe0000000 0x1000>; - interrupts = <0x0 0x1b 0x4>; + interrupts = <0x00 0x1b 0x04>; + phandle = <0x2b>; }; serial@e0001000 { - compatible = "xlnx,xuartps", "cdns,uart-r1p8"; + compatible = "xlnx,xuartps\0cdns,uart-r1p8"; status = "okay"; - clocks = <0x2 0x18 0x2 0x29>; - clock-names = "uart_clk", "pclk"; + clocks = <0x02 0x18 0x02 0x29>; + clock-names = "uart_clk\0pclk"; reg = <0xe0001000 0x1000>; - interrupts = <0x0 0x32 0x4>; + interrupts = <0x00 0x32 0x04>; + phandle = <0x2c>; }; spi@e0006000 { compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0006000 0x1000>; status = "okay"; - interrupt-parent = <0x1>; - interrupts = <0x0 0x1a 0x4>; - clocks = <0x2 0x19 0x2 0x22>; - clock-names = "ref_clk", "pclk"; - #address-cells = <0x1>; - #size-cells = <0x0>; + interrupt-parent = <0x01>; + interrupts = <0x00 0x1a 0x04>; + clocks = <0x02 0x19 0x02 0x22>; + clock-names = "ref_clk\0pclk"; + #address-cells = <0x01>; + #size-cells = <0x00>; + phandle = <0x2d>; ad9361-phy@0 { compatible = "adi,ad9361"; - reg = <0x0>; + reg = <0x00>; spi-cpha; spi-max-frequency = <0x989680>; - clocks = <0x5 0x0>; + clocks = <0x08 0x00>; clock-names = "ad9361_ext_refclk"; - clock-output-names = "rx_sampl_clk", "tx_sampl_clk"; - #clock-cells = <0x1>; - adi,digital-interface-tune-skip-mode = <0x0>; + clock-output-names = "rx_sampl_clk\0tx_sampl_clk"; + #clock-cells = <0x01>; + adi,digital-interface-tune-skip-mode = <0x00>; adi,pp-tx-swap-enable; adi,pp-rx-swap-enable; adi,rx-frame-pulse-mode-enable; adi,lvds-mode-enable; adi,lvds-bias-mV = <0x96>; adi,lvds-rx-onchip-termination-enable; - adi,rx-data-delay = <0x4>; - adi,tx-fb-clock-delay = <0x7>; - adi,dcxo-coarse-and-fine-tune = <0x8 0x1720>; + adi,rx-data-delay = <0x04>; + adi,tx-fb-clock-delay = <0x07>; + adi,dcxo-coarse-and-fine-tune = <0x08 0x1720>; adi,2rx-2tx-mode-enable; adi,frequency-division-duplex-mode-enable; - adi,rx-rf-port-input-select = <0x0>; - adi,tx-rf-port-input-select = <0x0>; + adi,rx-rf-port-input-select = <0x00>; + adi,tx-rf-port-input-select = <0x00>; adi,tx-attenuation-mdB = <0x2710>; adi,tx-lo-powerdown-managed-enable; adi,rf-rx-bandwidth-hz = <0x112a880>; adi,rf-tx-bandwidth-hz = <0x112a880>; - adi,rx-synthesizer-frequency-hz = <0x0 0x8f0d1800>; - adi,tx-synthesizer-frequency-hz = <0x0 0x92080880>; + adi,rx-synthesizer-frequency-hz = <0x00 0x8f0d1800>; + adi,tx-synthesizer-frequency-hz = <0x00 0x92080880>; adi,rx-path-clock-frequencies = <0x3a980000 0xea60000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>; adi,tx-path-clock-frequencies = <0x3a980000 0x7530000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>; - adi,gc-rx1-mode = <0x2>; - adi,gc-rx2-mode = <0x2>; - adi,gc-adc-ovr-sample-size = <0x4>; + adi,gc-rx1-mode = <0x02>; + adi,gc-rx2-mode = <0x02>; + adi,gc-adc-ovr-sample-size = <0x04>; adi,gc-adc-small-overload-thresh = <0x2f>; adi,gc-adc-large-overload-thresh = <0x3a>; adi,gc-lmt-overload-high-thresh = <0x320>; adi,gc-lmt-overload-low-thresh = <0x2c0>; adi,gc-dec-pow-measurement-duration = <0x2000>; adi,gc-low-power-thresh = <0x18>; - adi,mgc-inc-gain-step = <0x2>; - adi,mgc-dec-gain-step = <0x2>; - adi,mgc-split-table-ctrl-inp-gain-mode = <0x0>; - adi,agc-attack-delay-extra-margin-us = <0x1>; - adi,agc-outer-thresh-high = <0x5>; - adi,agc-outer-thresh-high-dec-steps = <0x2>; - adi,agc-inner-thresh-high = <0xa>; - adi,agc-inner-thresh-high-dec-steps = <0x1>; - adi,agc-inner-thresh-low = <0xc>; - adi,agc-inner-thresh-low-inc-steps = <0x1>; + adi,mgc-inc-gain-step = <0x02>; + adi,mgc-dec-gain-step = <0x02>; + adi,mgc-split-table-ctrl-inp-gain-mode = <0x00>; + adi,agc-attack-delay-extra-margin-us = <0x01>; + adi,agc-outer-thresh-high = <0x05>; + adi,agc-outer-thresh-high-dec-steps = <0x02>; + adi,agc-inner-thresh-high = <0x0a>; + adi,agc-inner-thresh-high-dec-steps = <0x01>; + adi,agc-inner-thresh-low = <0x0c>; + adi,agc-inner-thresh-low-inc-steps = <0x01>; adi,agc-outer-thresh-low = <0x12>; - adi,agc-outer-thresh-low-inc-steps = <0x2>; - adi,agc-adc-small-overload-exceed-counter = <0xa>; - adi,agc-adc-large-overload-exceed-counter = <0xa>; - adi,agc-adc-large-overload-inc-steps = <0x2>; - adi,agc-lmt-overload-large-exceed-counter = <0xa>; - adi,agc-lmt-overload-small-exceed-counter = <0xa>; - adi,agc-lmt-overload-large-inc-steps = <0x2>; + adi,agc-outer-thresh-low-inc-steps = <0x02>; + adi,agc-adc-small-overload-exceed-counter = <0x0a>; + adi,agc-adc-large-overload-exceed-counter = <0x0a>; + adi,agc-adc-large-overload-inc-steps = <0x02>; + adi,agc-lmt-overload-large-exceed-counter = <0x0a>; + adi,agc-lmt-overload-small-exceed-counter = <0x0a>; + adi,agc-lmt-overload-large-inc-steps = <0x02>; adi,agc-gain-update-interval-us = <0x3e8>; adi,fagc-dec-pow-measurement-duration = <0x40>; - adi,fagc-lp-thresh-increment-steps = <0x1>; - adi,fagc-lp-thresh-increment-time = <0x5>; - adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <0x8>; - adi,fagc-final-overrange-count = <0x3>; - adi,fagc-gain-index-type-after-exit-rx-mode = <0x0>; - adi,fagc-lmt-final-settling-steps = <0x1>; - adi,fagc-lock-level = <0xa>; - adi,fagc-lock-level-gain-increase-upper-limit = <0x5>; + adi,fagc-lp-thresh-increment-steps = <0x01>; + adi,fagc-lp-thresh-increment-time = <0x05>; + adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <0x08>; + adi,fagc-final-overrange-count = <0x03>; + adi,fagc-gain-index-type-after-exit-rx-mode = <0x00>; + adi,fagc-lmt-final-settling-steps = <0x01>; + adi,fagc-lock-level = <0x0a>; + adi,fagc-lock-level-gain-increase-upper-limit = <0x05>; adi,fagc-lock-level-lmt-gain-increase-enable; - adi,fagc-lpf-final-settling-steps = <0x1>; - adi,fagc-optimized-gain-offset = <0x5>; + adi,fagc-lpf-final-settling-steps = <0x01>; + adi,fagc-optimized-gain-offset = <0x05>; adi,fagc-power-measurement-duration-in-state5 = <0x40>; adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable; - adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <0xa>; + adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <0x0a>; adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable; - adi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0x0>; + adi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0x00>; adi,fagc-rst-gla-large-adc-overload-enable; adi,fagc-rst-gla-large-lmt-overload-enable; - adi,fagc-rst-gla-stronger-sig-thresh-above-ll = <0xa>; + adi,fagc-rst-gla-stronger-sig-thresh-above-ll = <0x0a>; adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable; adi,fagc-state-wait-time-ns = <0x104>; adi,fagc-use-last-lock-level-for-set-gain-enable; - adi,rssi-restart-mode = <0x3>; - adi,rssi-delay = <0x1>; - adi,rssi-wait = <0x1>; + adi,rssi-restart-mode = <0x03>; + adi,rssi-delay = <0x01>; + adi,rssi-wait = <0x01>; adi,rssi-duration = <0x3e8>; - adi,ctrl-outs-index = <0x0>; + adi,ctrl-outs-index = <0x00>; adi,ctrl-outs-enable-mask = <0xff>; adi,temp-sense-measurement-interval-ms = <0x3e8>; adi,temp-sense-offset-signed = <0xce>; adi,temp-sense-periodic-measurement-enable; adi,aux-dac-manual-mode-enable; - adi,aux-dac1-default-value-mV = <0x0>; - adi,aux-dac1-rx-delay-us = <0x0>; - adi,aux-dac1-tx-delay-us = <0x0>; - adi,aux-dac2-default-value-mV = <0x0>; - adi,aux-dac2-rx-delay-us = <0x0>; - adi,aux-dac2-tx-delay-us = <0x0>; - en_agc-gpios = <0x6 0x62 0x0>; - sync-gpios = <0x6 0x63 0x0>; - reset-gpios = <0x6 0x64 0x0>; - enable-gpios = <0x6 0x65 0x0>; - txnrx-gpios = <0x6 0x66 0x0>; - linux,phandle = <0x11>; - phandle = <0x11>; + adi,aux-dac1-default-value-mV = <0x00>; + adi,aux-dac1-rx-delay-us = <0x00>; + adi,aux-dac1-tx-delay-us = <0x00>; + adi,aux-dac2-default-value-mV = <0x00>; + adi,aux-dac2-rx-delay-us = <0x00>; + adi,aux-dac2-tx-delay-us = <0x00>; + en_agc-gpios = <0x09 0x62 0x00>; + sync-gpios = <0x09 0x63 0x00>; + reset-gpios = <0x09 0x64 0x00>; + enable-gpios = <0x09 0x65 0x00>; + txnrx-gpios = <0x09 0x66 0x00>; + phandle = <0x1d>; }; }; @@ -303,70 +354,76 @@ compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0007000 0x1000>; status = "okay"; - interrupt-parent = <0x1>; - interrupts = <0x0 0x31 0x4>; - clocks = <0x2 0x1a 0x2 0x23>; - clock-names = "ref_clk", "pclk"; - #address-cells = <0x1>; - #size-cells = <0x0>; + interrupt-parent = <0x01>; + interrupts = <0x00 0x31 0x04>; + clocks = <0x02 0x1a 0x02 0x23>; + clock-names = "ref_clk\0pclk"; + #address-cells = <0x01>; + #size-cells = <0x00>; + phandle = <0x2e>; adf4351-udc-tx-pmod@0 { compatible = "adi,adf4351"; - reg = <0x0>; + reg = <0x00>; spi-max-frequency = <0x989680>; - clocks = <0x7>; + clocks = <0x0a>; clock-names = "clkin"; adi,channel-spacing = <0xf4240>; adi,power-up-frequency = <0x160dc080>; adi,phase-detector-polarity-positive-enable; adi,charge-pump-current = <0x9c4>; - adi,output-power = <0x3>; + adi,output-power = <0x03>; adi,mute-till-lock-enable; - adi,muxout-select = <0x6>; - gpios = <0x6 0x68 0x0>; + adi,muxout-select = <0x06>; + gpios = <0x09 0x68 0x00>; + phandle = <0x2f>; }; adf4351-udc-rx-pmod@1 { compatible = "adi,adf4351"; - reg = <0x1>; + reg = <0x01>; spi-max-frequency = <0x989680>; - clocks = <0x7>; + clocks = <0x0a>; clock-names = "clkin"; adi,channel-spacing = <0xf4240>; adi,power-up-frequency = <0x1443fd00>; adi,phase-detector-polarity-positive-enable; adi,charge-pump-current = <0x9c4>; - adi,output-power = <0x3>; + adi,output-power = <0x03>; adi,mute-till-lock-enable; - adi,muxout-select = <0x6>; - gpios = <0x6 0x67 0x0>; + adi,muxout-select = <0x06>; + gpios = <0x09 0x67 0x00>; + phandle = <0x30>; }; }; spi@e000d000 { - clock-names = "ref_clk", "pclk"; - clocks = <0x2 0xa 0x2 0x2b>; + clock-names = "ref_clk\0pclk"; + clocks = <0x02 0x0a 0x02 0x2b>; compatible = "xlnx,zynq-qspi-1.0"; status = "okay"; - interrupt-parent = <0x1>; - interrupts = <0x0 0x13 0x4>; + interrupt-parent = <0x01>; + interrupts = <0x00 0x13 0x04>; reg = <0xe000d000 0x1000>; - #address-cells = <0x1>; - #size-cells = <0x0>; - is-dual = <0x0>; - num-cs = <0x1>; + #address-cells = <0x01>; + #size-cells = <0x00>; + is-dual = <0x00>; + num-cs = <0x01>; + phandle = <0x31>; ps7-qspi@0 { - #address-cells = <0x1>; - #size-cells = <0x1>; + #address-cells = <0x01>; + #size-cells = <0x01>; compatible = "n25q128a11"; - reg = <0x0>; - spi-tx-bus-width = <0x1>; - spi-rx-bus-width = <0x4>; + reg = <0x00>; + spi-tx-bus-width = <0x01>; + spi-rx-bus-width = <0x04>; + spi-max-frequency = <0x2faf080>; + phandle = <0x32>; partition@0 { label = "boot"; - reg = <0x0 0x500000>; + reg = <0x00 0x500000>; }; partition@500000 { @@ -386,236 +443,372 @@ partition@fc0000 { label = "spare"; - reg = <0xfc0000 0x0>; + reg = <0xfc0000 0x00>; }; }; }; memory-controller@e000e000 { - #address-cells = <0x1>; - #size-cells = <0x1>; + #address-cells = <0x01>; + #size-cells = <0x01>; status = "disabled"; - clock-names = "memclk", "aclk"; - clocks = <0x2 0xb 0x2 0x2c>; - compatible = "arm,pl353-smc-r2p1"; - interrupt-parent = <0x1>; - interrupts = <0x0 0x12 0x4>; + clock-names = "memclk\0apb_pclk"; + clocks = <0x02 0x0b 0x02 0x2c>; + compatible = "arm,pl353-smc-r2p1\0arm,primecell"; + interrupt-parent = <0x01>; + interrupts = <0x00 0x12 0x04>; ranges; reg = <0xe000e000 0x1000>; + phandle = <0x33>; flash@e1000000 { status = "disabled"; compatible = "arm,pl353-nand-r2p1"; reg = <0xe1000000 0x1000000>; - #address-cells = <0x1>; - #size-cells = <0x1>; + #address-cells = <0x01>; + #size-cells = <0x01>; + phandle = <0x34>; }; flash@e2000000 { status = "disabled"; compatible = "cfi-flash"; reg = <0xe2000000 0x2000000>; - #address-cells = <0x1>; - #size-cells = <0x1>; + #address-cells = <0x01>; + #size-cells = <0x01>; + phandle = <0x35>; }; }; ethernet@e000b000 { - compatible = "cdns,zynq-gem", "cdns,gem"; + compatible = "cdns,zynq-gem\0cdns,gem"; reg = <0xe000b000 0x1000>; status = "okay"; - interrupts = <0x0 0x16 0x4>; - clocks = <0x2 0x1e 0x2 0x1e 0x2 0xd>; - clock-names = "pclk", "hclk", "tx_clk"; - #address-cells = <0x1>; - #size-cells = <0x0>; - phy-handle = <0x8>; + interrupts = <0x00 0x16 0x04>; + clocks = <0x02 0x1e 0x02 0x1e 0x02 0x0d>; + clock-names = "pclk\0hclk\0tx_clk"; + #address-cells = <0x01>; + #size-cells = <0x00>; + phy-handle = <0x0b>; phy-mode = "rgmii-id"; + phandle = <0x36>; phy@7 { device_type = "ethernet-phy"; - reg = <0x7>; - linux,phandle = <0x8>; - phandle = <0x8>; + reg = <0x07>; + phandle = <0x0b>; }; }; ethernet@e000c000 { - compatible = "cdns,zynq-gem", "cdns,gem"; + compatible = "cdns,zynq-gem\0cdns,gem"; reg = <0xe000c000 0x1000>; status = "disabled"; - interrupts = <0x0 0x2d 0x4>; - clocks = <0x2 0x1f 0x2 0x1f 0x2 0xe>; - clock-names = "pclk", "hclk", "tx_clk"; - #address-cells = <0x1>; - #size-cells = <0x0>; + interrupts = <0x00 0x2d 0x04>; + clocks = <0x02 0x1f 0x02 0x1f 0x02 0x0e>; + clock-names = "pclk\0hclk\0tx_clk"; + #address-cells = <0x01>; + #size-cells = <0x00>; + phandle = <0x37>; }; mmc@e0100000 { compatible = "arasan,sdhci-8.9a"; status = "okay"; - clock-names = "clk_xin", "clk_ahb"; - clocks = <0x2 0x15 0x2 0x20>; - interrupt-parent = <0x1>; - interrupts = <0x0 0x18 0x4>; + clock-names = "clk_xin\0clk_ahb"; + clocks = <0x02 0x15 0x02 0x20>; + interrupt-parent = <0x01>; + interrupts = <0x00 0x18 0x04>; reg = <0xe0100000 0x1000>; + phandle = <0x38>; }; mmc@e0101000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; - clock-names = "clk_xin", "clk_ahb"; - clocks = <0x2 0x16 0x2 0x21>; - interrupt-parent = <0x1>; - interrupts = <0x0 0x2f 0x4>; + clock-names = "clk_xin\0clk_ahb"; + clocks = <0x02 0x16 0x02 0x21>; + interrupt-parent = <0x01>; + interrupts = <0x00 0x2f 0x04>; reg = <0xe0101000 0x1000>; + phandle = <0x39>; }; slcr@f8000000 { u-boot,dm-pre-reloc; - #address-cells = <0x1>; - #size-cells = <0x1>; - compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd"; + #address-cells = <0x01>; + #size-cells = <0x01>; + compatible = "xlnx,zynq-slcr\0syscon\0simple-mfd"; reg = <0xf8000000 0x1000>; ranges; - linux,phandle = <0x9>; - phandle = <0x9>; + phandle = <0x0c>; clkc@100 { u-boot,dm-pre-reloc; - #clock-cells = <0x1>; + #clock-cells = <0x01>; compatible = "xlnx,ps7-clkc"; - fclk-enable = <0xf>; - clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", "swdt", "dbg_trc", "dbg_apb"; + fclk-enable = <0x0f>; + clock-output-names = "armpll\0ddrpll\0iopll\0cpu_6or4x\0cpu_3or2x\0cpu_2x\0cpu_1x\0ddr2x\0ddr3x\0dci\0lqspi\0smc\0pcap\0gem0\0gem1\0fclk0\0fclk1\0fclk2\0fclk3\0can0\0can1\0sdio0\0sdio1\0uart0\0uart1\0spi0\0spi1\0dma\0usb0_aper\0usb1_aper\0gem0_aper\0gem1_aper\0sdio0_aper\0sdio1_aper\0spi0_aper\0spi1_aper\0can0_aper\0can1_aper\0i2c0_aper\0i2c1_aper\0uart0_aper\0uart1_aper\0gpio_aper\0lqspi_aper\0smc_aper\0swdt\0dbg_trc\0dbg_apb"; reg = <0x100 0x100>; ps-clk-frequency = <0x1fca055>; - linux,phandle = <0x2>; - phandle = <0x2>; + phandle = <0x02>; }; rstc@200 { compatible = "xlnx,zynq-reset"; reg = <0x200 0x48>; - #reset-cells = <0x1>; - syscon = <0x9>; + #reset-cells = <0x01>; + syscon = <0x0c>; + phandle = <0x3a>; }; pinctrl@700 { compatible = "xlnx,pinctrl-zynq"; reg = <0x700 0x200>; - syscon = <0x9>; + syscon = <0x0c>; + phandle = <0x3b>; }; }; dmac@f8003000 { - compatible = "arm,pl330", "arm,primecell"; + compatible = "arm,pl330\0arm,primecell"; reg = <0xf8003000 0x1000>; - interrupt-parent = <0x1>; - interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", "dma4", "dma5", "dma6", "dma7"; - interrupts = <0x0 0xd 0x4 0x0 0xe 0x4 0x0 0xf 0x4 0x0 0x10 0x4 0x0 0x11 0x4 0x0 0x28 0x4 0x0 0x29 0x4 0x0 0x2a 0x4 0x0 0x2b 0x4>; - #dma-cells = <0x1>; - #dma-channels = <0x8>; - #dma-requests = <0x4>; - clocks = <0x2 0x1b>; + interrupt-parent = <0x01>; + interrupt-names = "abort\0dma0\0dma1\0dma2\0dma3\0dma4\0dma5\0dma6\0dma7"; + interrupts = <0x00 0x0d 0x04 0x00 0x0e 0x04 0x00 0x0f 0x04 0x00 0x10 0x04 0x00 0x11 0x04 0x00 0x28 0x04 0x00 0x29 0x04 0x00 0x2a 0x04 0x00 0x2b 0x04>; + #dma-cells = <0x01>; + #dma-channels = <0x08>; + #dma-requests = <0x04>; + clocks = <0x02 0x1b>; clock-names = "apb_pclk"; - linux,phandle = <0xe>; - phandle = <0xe>; + phandle = <0x1a>; }; devcfg@f8007000 { compatible = "xlnx,zynq-devcfg-1.0"; - interrupt-parent = <0x1>; - interrupts = <0x0 0x8 0x4>; + interrupt-parent = <0x01>; + interrupts = <0x00 0x08 0x04>; reg = <0xf8007000 0x100>; - clocks = <0x2 0xc 0x2 0xf 0x2 0x10 0x2 0x11 0x2 0x12>; - clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; - syscon = <0x9>; - linux,phandle = <0x4>; - phandle = <0x4>; + clocks = <0x02 0x0c 0x02 0x0f 0x02 0x10 0x02 0x11 0x02 0x12>; + clock-names = "ref_clk\0fclk0\0fclk1\0fclk2\0fclk3"; + syscon = <0x0c>; + phandle = <0x04>; }; efuse@f800d000 { compatible = "xlnx,zynq-efuse"; reg = <0xf800d000 0x20>; + phandle = <0x3c>; }; timer@f8f00200 { compatible = "arm,cortex-a9-global-timer"; reg = <0xf8f00200 0x20>; - interrupts = <0x1 0xb 0x301>; - interrupt-parent = <0x1>; - clocks = <0x2 0x4>; + interrupts = <0x01 0x0b 0x301>; + interrupt-parent = <0x01>; + clocks = <0x02 0x04>; + phandle = <0x3d>; }; timer@f8001000 { - interrupt-parent = <0x1>; - interrupts = <0x0 0xa 0x4 0x0 0xb 0x4 0x0 0xc 0x4>; + interrupt-parent = <0x01>; + interrupts = <0x00 0x0a 0x04 0x00 0x0b 0x04 0x00 0x0c 0x04>; compatible = "cdns,ttc"; - clocks = <0x2 0x6>; + clocks = <0x02 0x06>; reg = <0xf8001000 0x1000>; + phandle = <0x3e>; }; timer@f8002000 { - interrupt-parent = <0x1>; - interrupts = <0x0 0x25 0x4 0x0 0x26 0x4 0x0 0x27 0x4>; + interrupt-parent = <0x01>; + interrupts = <0x00 0x25 0x04 0x00 0x26 0x04 0x00 0x27 0x04>; compatible = "cdns,ttc"; - clocks = <0x2 0x6>; + clocks = <0x02 0x06>; reg = <0xf8002000 0x1000>; + phandle = <0x3f>; }; timer@f8f00600 { - interrupt-parent = <0x1>; - interrupts = <0x1 0xd 0x301>; + interrupt-parent = <0x01>; + interrupts = <0x01 0x0d 0x301>; compatible = "arm,cortex-a9-twd-timer"; reg = <0xf8f00600 0x20>; - clocks = <0x2 0x4>; + clocks = <0x02 0x04>; + phandle = <0x40>; }; usb@e0002000 { - compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; + compatible = "xlnx,zynq-usb-2.20a\0chipidea,usb2"; status = "okay"; - clocks = <0x2 0x1c>; - interrupt-parent = <0x1>; - interrupts = <0x0 0x15 0x4>; + clocks = <0x02 0x1c>; + interrupt-parent = <0x01>; + interrupts = <0x00 0x15 0x04>; reg = <0xe0002000 0x1000>; phy_type = "ulpi"; dr_mode = "host"; - xlnx,phy-reset-gpio = <0x6 0x7 0x0>; + xlnx,phy-reset-gpio = <0x09 0x07 0x00>; + phandle = <0x41>; }; usb@e0003000 { - compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; + compatible = "xlnx,zynq-usb-2.20a\0chipidea,usb2"; status = "disabled"; - clocks = <0x2 0x1d>; - interrupt-parent = <0x1>; - interrupts = <0x0 0x2c 0x4>; + clocks = <0x02 0x1d>; + interrupt-parent = <0x01>; + interrupts = <0x00 0x2c 0x04>; reg = <0xe0003000 0x1000>; phy_type = "ulpi"; + phandle = <0x42>; }; watchdog@f8005000 { - clocks = <0x2 0x2d>; + clocks = <0x02 0x2d>; compatible = "cdns,wdt-r1p2"; - interrupt-parent = <0x1>; - interrupts = <0x0 0x9 0x1>; + interrupt-parent = <0x01>; + interrupts = <0x00 0x09 0x01>; reg = <0xf8005000 0x1000>; - timeout-sec = <0xa>; + timeout-sec = <0x0a>; + phandle = <0x43>; + }; + + etb@f8801000 { + compatible = "arm,coresight-etb10\0arm,primecell"; + reg = <0xf8801000 0x1000>; + clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>; + clock-names = "apb_pclk\0dbg_trc\0dbg_apb"; + + in-ports { + + port { + + endpoint { + remote-endpoint = <0x0d>; + phandle = <0x06>; + }; + }; + }; + }; + + tpiu@f8803000 { + compatible = "arm,coresight-tpiu\0arm,primecell"; + reg = <0xf8803000 0x1000>; + clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>; + clock-names = "apb_pclk\0dbg_trc\0dbg_apb"; + + in-ports { + + port { + + endpoint { + remote-endpoint = <0x0e>; + phandle = <0x05>; + }; + }; + }; + }; + + funnel@f8804000 { + compatible = "arm,coresight-static-funnel\0arm,primecell"; + reg = <0xf8804000 0x1000>; + clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>; + clock-names = "apb_pclk\0dbg_trc\0dbg_apb"; + + out-ports { + + port { + + endpoint { + remote-endpoint = <0x0f>; + phandle = <0x07>; + }; + }; + }; + + in-ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x10>; + phandle = <0x13>; + }; + }; + + port@1 { + reg = <0x01>; + + endpoint { + remote-endpoint = <0x11>; + phandle = <0x15>; + }; + }; + + port@2 { + reg = <0x02>; + + endpoint { + phandle = <0x44>; + }; + }; + }; + }; + + ptm@f889c000 { + compatible = "arm,coresight-etm3x\0arm,primecell"; + reg = <0xf889c000 0x1000>; + clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>; + clock-names = "apb_pclk\0dbg_trc\0dbg_apb"; + cpu = <0x12>; + + out-ports { + + port { + + endpoint { + remote-endpoint = <0x13>; + phandle = <0x10>; + }; + }; + }; + }; + + ptm@f889d000 { + compatible = "arm,coresight-etm3x\0arm,primecell"; + reg = <0xf889d000 0x1000>; + clocks = <0x02 0x1b 0x02 0x2e 0x02 0x2f>; + clock-names = "apb_pclk\0dbg_trc\0dbg_apb"; + cpu = <0x14>; + + out-ports { + + port { + + endpoint { + remote-endpoint = <0x15>; + phandle = <0x11>; + }; + }; + }; }; }; aliases { - ethernet0 = "/amba/ethernet@e000b000"; - serial0 = "/amba/serial@e0001000"; + ethernet0 = "/axi/ethernet@e000b000"; + serial0 = "/axi/serial@e0001000"; + phandle = <0x45>; }; memory { device_type = "memory"; - reg = <0x0 0x40000000>; + reg = <0x00 0x40000000>; }; chosen { bootargs = "console=ttyPS0,115200 root=/dev/mmcblk0p2 rw earlyprintk rootfstype=ext4 rootwait"; - linux,stdout-path = "/amba@0/uart@E0001000"; + stdout-path = "/amba@0/uart@E0001000"; }; leds { @@ -623,166 +816,165 @@ ds12 { label = "ds12:green"; - gpios = <0x6 0x8 0x0>; + gpios = <0x09 0x08 0x00>; }; ds15 { label = "ds15:green"; - gpios = <0x6 0x3a 0x0>; + gpios = <0x09 0x3a 0x00>; }; ds16 { label = "ds16:green"; - gpios = <0x6 0x3b 0x0>; + gpios = <0x09 0x3b 0x00>; }; ds17 { label = "ds17:green"; - gpios = <0x6 0x3c 0x0>; + gpios = <0x09 0x3c 0x00>; }; ds18 { label = "ds18:green"; - gpios = <0x6 0x3d 0x0>; + gpios = <0x09 0x3d 0x00>; }; ds19 { label = "ds19:green"; - gpios = <0x6 0x3e 0x0>; + gpios = <0x09 0x3e 0x00>; }; ds20 { label = "ds20:green"; - gpios = <0x6 0x3f 0x0>; + gpios = <0x09 0x3f 0x00>; }; ds21 { label = "ds21:green"; - gpios = <0x6 0x40 0x0>; + gpios = <0x09 0x40 0x00>; }; ds22 { label = "ds22:green"; - gpios = <0x6 0x41 0x0>; + gpios = <0x09 0x41 0x00>; }; ds23 { label = "ds23:green"; - gpios = <0x6 0xa 0x0>; + gpios = <0x09 0x0a 0x00>; }; }; gpio_keys { compatible = "gpio-keys"; - #address-cells = <0x1>; - #size-cells = <0x0>; + #address-cells = <0x01>; + #size-cells = <0x00>; autorepeat; sw5 { label = "Left"; linux,code = <0x69>; - gpios = <0x6 0x36 0x0>; + gpios = <0x09 0x36 0x00>; }; sw7 { label = "Right"; linux,code = <0x6a>; - gpios = <0x6 0x37 0x0>; + gpios = <0x09 0x37 0x00>; }; sw15_0 { label = "SW15_0"; - linux,code = <0x0>; - linux,input-type = <0x5>; - gpios = <0x6 0x38 0x0>; + linux,code = <0x0d>; + linux,input-type = <0x05>; + gpios = <0x09 0x38 0x00>; }; sw15_1 { label = "SW15_1"; - linux,code = <0x1>; - linux,input-type = <0x5>; - gpios = <0x6 0x39 0x0>; + linux,code = <0x01>; + linux,input-type = <0x05>; + gpios = <0x09 0x39 0x00>; }; sw13 { label = "Select"; linux,code = <0x1c>; - gpios = <0x6 0xe 0x0>; + gpios = <0x09 0x0e 0x00>; }; sw14 { label = "SW14"; - linux,code = <0x1>; - gpios = <0x6 0xc 0x0>; + linux,code = <0x01>; + gpios = <0x09 0x0c 0x00>; }; }; fpga-axi@0 { compatible = "simple-bus"; - #address-cells = <0x1>; - #size-cells = <0x1>; + #address-cells = <0x01>; + #size-cells = <0x01>; ranges; + phandle = <0x46>; i2c@41600000 { - compatible = "xlnx,axi-iic-1.02.a", "xlnx,xps-iic-2.00.a"; + compatible = "xlnx,axi-iic-1.02.a\0xlnx,xps-iic-2.00.a"; reg = <0x41600000 0x10000>; - interrupt-parent = <0x1>; - interrupts = <0x0 0x3a 0x4>; - clocks = <0x2 0xf>; + interrupt-parent = <0x01>; + interrupts = <0x00 0x3a 0x04>; + clocks = <0x02 0x0f>; clock-names = "pclk"; - #address-cells = <0x1>; - #size-cells = <0x0>; + #address-cells = <0x01>; + #size-cells = <0x00>; mux@74 { compatible = "pca9548"; reg = <0x74>; - #address-cells = <0x1>; - #size-cells = <0x0>; + #address-cells = <0x01>; + #size-cells = <0x00>; i2c@1 { - #size-cells = <0x0>; - #address-cells = <0x1>; - reg = <0x1>; + #size-cells = <0x00>; + #address-cells = <0x01>; + reg = <0x01>; adv7511@39 { compatible = "adi,adv7511"; reg = <0x39 0x3f>; - reg-names = "primary", "edid"; - adi,input-depth = <0x8>; + reg-names = "primary\0edid"; + adi,input-depth = <0x08>; adi,input-colorspace = "yuv422"; adi,input-clock = "1x"; - adi,input-style = <0x1>; + adi,input-style = <0x01>; adi,input-justification = "right"; - adi,clock-delay = <0x0>; - #sound-dai-cells = <0x0>; - linux,phandle = <0x14>; - phandle = <0x14>; + adi,clock-delay = <0x00>; + #sound-dai-cells = <0x01>; + phandle = <0x20>; ports { - #address-cells = <0x1>; - #size-cells = <0x0>; + #address-cells = <0x01>; + #size-cells = <0x00>; port@0 { - reg = <0x0>; + reg = <0x00>; endpoint { - remote-endpoint = <0xa>; - linux,phandle = <0xd>; - phandle = <0xd>; + remote-endpoint = <0x16>; + phandle = <0x19>; }; }; port@1 { - reg = <0x1>; + reg = <0x01>; }; }; }; }; i2c@4 { - #size-cells = <0x0>; - #address-cells = <0x1>; - reg = <0x4>; + #size-cells = <0x00>; + #address-cells = <0x01>; + reg = <0x04>; rtc@51 { compatible = "rtc8564"; @@ -791,9 +983,10 @@ }; i2c@5 { - #size-cells = <0x0>; - #address-cells = <0x1>; - reg = <0x5>; + #size-cells = <0x00>; + #address-cells = <0x01>; + reg = <0x05>; + phandle = <0x47>; ad7291@2f { compatible = "adi,ad7291"; @@ -811,22 +1004,21 @@ dma@43000000 { compatible = "adi,axi-dmac-1.00.a"; reg = <0x43000000 0x10000>; - #dma-cells = <0x1>; - interrupts = <0x0 0x3b 0x0>; - clocks = <0x2 0x10>; - linux,phandle = <0xb>; - phandle = <0xb>; + #dma-cells = <0x01>; + interrupts = <0x00 0x3b 0x04>; + clocks = <0x02 0x10>; + phandle = <0x17>; adi,channels { - #size-cells = <0x0>; - #address-cells = <0x1>; + #size-cells = <0x00>; + #address-cells = <0x01>; dma-channel@0 { - reg = <0x0>; + reg = <0x00>; adi,source-bus-width = <0x40>; - adi,source-bus-type = <0x0>; + adi,source-bus-type = <0x00>; adi,destination-bus-width = <0x40>; - adi,destination-bus-type = <0x1>; + adi,destination-bus-type = <0x01>; }; }; }; @@ -834,25 +1026,24 @@ axi-clkgen@79000000 { compatible = "adi,axi-clkgen-2.00.a"; reg = <0x79000000 0x10000>; - #clock-cells = <0x0>; - clocks = <0x2 0x10>; - linux,phandle = <0xc>; - phandle = <0xc>; + #clock-cells = <0x00>; + clocks = <0x02 0x0f 0x02 0x10>; + clock-names = "s_axi_aclk\0clkin1"; + phandle = <0x18>; }; axi_hdmi@70e00000 { compatible = "adi,axi-hdmi-tx-1.00.a"; reg = <0x70e00000 0x10000>; - dmas = <0xb 0x0>; + dmas = <0x17 0x00>; dma-names = "video"; - clocks = <0xc>; + clocks = <0x18>; port { endpoint { - remote-endpoint = <0xd>; - linux,phandle = <0xa>; - phandle = <0xa>; + remote-endpoint = <0x19>; + phandle = <0x16>; }; }; }; @@ -860,66 +1051,64 @@ axi-spdif-tx@75c00000 { compatible = "adi,axi-spdif-tx-1.00.a"; reg = <0x75c00000 0x1000>; - dmas = <0xe 0x0>; + dmas = <0x1a 0x00>; dma-names = "tx"; - clocks = <0x2 0xf 0xf>; - clock-names = "axi", "ref"; - #sound-dai-cells = <0x0>; - linux,phandle = <0x13>; - phandle = <0x13>; + clocks = <0x02 0x0f 0x1b>; + clock-names = "axi\0ref"; + #sound-dai-cells = <0x00>; + phandle = <0x1f>; }; -*/ - /*axi-sysid-0@45000000 { + + axi-sysid-0@45000000 { compatible = "adi,axi-sysid-1.00.a"; reg = <0x45000000 0x10000>; - };*/ + phandle = <0x48>; + }; - // dma@7c400000 { - // compatible = "adi,axi-dmac-1.00.a"; - // reg = <0x7c400000 0x10000>; - // #dma-cells = <0x1>; - // interrupts = <0x0 0x39 0x0>; - // clocks = <0x2 0x10>; - // linux,phandle = <0x10>; - // phandle = <0x10>; + dma@7c400000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x7c400000 0x10000>; + #dma-cells = <0x01>; + interrupts = <0x00 0x39 0x04>; + clocks = <0x02 0x10>; + phandle = <0x1c>; - // adi,channels { - // #size-cells = <0x0>; - // #address-cells = <0x1>; + adi,channels { + #size-cells = <0x00>; + #address-cells = <0x01>; - // dma-channel@0 { - // reg = <0x0>; - // adi,source-bus-width = <0x40>; - // adi,source-bus-type = <0x2>; - // adi,destination-bus-width = <0x40>; - // adi,destination-bus-type = <0x0>; - // }; - // }; - // }; + dma-channel@0 { + reg = <0x00>; + adi,source-bus-width = <0x40>; + adi,source-bus-type = <0x02>; + adi,destination-bus-width = <0x40>; + adi,destination-bus-type = <0x00>; + }; + }; + }; - // dma@7c420000 { - // compatible = "adi,axi-dmac-1.00.a"; - // reg = <0x7c420000 0x10000>; - // #dma-cells = <0x1>; - // interrupts = <0x0 0x38 0x0>; - // clocks = <0x2 0x10>; - // linux,phandle = <0x12>; - // phandle = <0x12>; + dma@7c420000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x7c420000 0x10000>; + #dma-cells = <0x01>; + interrupts = <0x00 0x38 0x04>; + clocks = <0x02 0x10>; + phandle = <0x1e>; - // adi,channels { - // #size-cells = <0x0>; - // #address-cells = <0x1>; - - // dma-channel@0 { - // reg = <0x0>; - // adi,source-bus-width = <0x40>; - // adi,source-bus-type = <0x0>; - // adi,destination-bus-width = <0x40>; - // adi,destination-bus-type = <0x2>; - // }; - // }; - // }; + adi,channels { + #size-cells = <0x00>; + #address-cells = <0x01>; + dma-channel@0 { + reg = <0x00>; + adi,source-bus-width = <0x40>; + adi,source-bus-type = <0x00>; + adi,destination-bus-width = <0x40>; + adi,destination-bus-type = <0x02>; + }; + }; + }; +*/ sdr: sdr { compatible ="sdr,sdr"; dmas = <&rx_dma 1 @@ -1052,46 +1241,47 @@ cf-ad9361-lpc@79020000 { compatible = "adi,axi-ad9361-6.00.a"; reg = <0x79020000 0x6000>; - // dmas = <0x10 0x0>; + // dmas = <0x1c 0x00>; // dma-names = "rx"; - spibus-connected = <0x11>; + spibus-connected = <0x1d>; + phandle = <0x49>; }; cf-ad9361-dds-core-lpc@79024000 { compatible = "adi,axi-ad9361-dds-6.00.a"; reg = <0x79024000 0x1000>; - clocks = <0x11 0xd>; + clocks = <0x1d 0x0d>; clock-names = "sampl_clk"; - // dmas = <0x12 0x0>; + // dmas = <0x1e 0x00>; // dma-names = "tx"; + phandle = <0x4a>; }; }; /* audio_clock { compatible = "fixed-clock"; - #clock-cells = <0x0>; + #clock-cells = <0x00>; clock-frequency = <0xbb8000>; - linux,phandle = <0xf>; - phandle = <0xf>; + phandle = <0x1b>; }; adv7511_hdmi_snd { compatible = "simple-audio-card"; simple-audio-card,name = "HDMI monitor"; - simple-audio-card,widgets = "Speaker", "Speaker"; - simple-audio-card,routing = "Speaker", "TX"; + simple-audio-card,widgets = "Speaker\0Speaker"; + simple-audio-card,routing = "Speaker\0TX"; simple-audio-card,dai-link@0 { format = "spdif"; cpu { - sound-dai = <0x13>; + sound-dai = <0x1f>; frame-master; bitclock-master; }; codec { - sound-dai = <0x14>; + sound-dai = <0x20 0x01>; }; }; }; @@ -1102,18 +1292,16 @@ compatible = "fixed-clock"; clock-frequency = <0x2625a00>; clock-output-names = "ad9361_ext_refclk"; - #clock-cells = <0x0>; - linux,phandle = <0x5>; - phandle = <0x5>; + #clock-cells = <0x00>; + phandle = <0x08>; }; clock@1 { compatible = "fixed-clock"; clock-frequency = <0x17d7840>; clock-output-names = "refclk"; - #clock-cells = <0x0>; - linux,phandle = <0x7>; - phandle = <0x7>; + #clock-cells = <0x00>; + phandle = <0x0a>; }; }; }; diff --git a/kernel_boot/boards/zc706_fmcs2/u-boot.elf b/kernel_boot/boards/zc706_fmcs2/u-boot.elf index 3d04955..87ce579 100644 Binary files a/kernel_boot/boards/zc706_fmcs2/u-boot.elf and b/kernel_boot/boards/zc706_fmcs2/u-boot.elf differ diff --git a/kernel_boot/boards/zcu102_fmcs2/bl31.elf b/kernel_boot/boards/zcu102_fmcs2/bl31.elf index 7e8295a..7461992 100644 Binary files a/kernel_boot/boards/zcu102_fmcs2/bl31.elf and b/kernel_boot/boards/zcu102_fmcs2/bl31.elf differ diff --git a/kernel_boot/boards/zcu102_fmcs2/system.dtb b/kernel_boot/boards/zcu102_fmcs2/system.dtb index 1311c75..fbfcee6 100644 Binary files a/kernel_boot/boards/zcu102_fmcs2/system.dtb and b/kernel_boot/boards/zcu102_fmcs2/system.dtb differ diff --git a/kernel_boot/boards/zcu102_fmcs2/system.dts b/kernel_boot/boards/zcu102_fmcs2/system.dts index 4939e63..8f7afd0 100644 --- a/kernel_boot/boards/zcu102_fmcs2/system.dts +++ b/kernel_boot/boards/zcu102_fmcs2/system.dts @@ -1,54 +1,58 @@ /dts-v1/; / { - compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; - #address-cells = <0x2>; - #size-cells = <0x2>; + compatible = "xlnx,zynqmp-zcu102-rev1.0\0xlnx,zynqmp-zcu102\0xlnx,zynqmp"; + #address-cells = <0x02>; + #size-cells = <0x02>; model = "ZynqMP ZCU102 Rev1.0"; cpus { - #address-cells = <0x1>; - #size-cells = <0x0>; + #address-cells = <0x01>; + #size-cells = <0x00>; cpu@0 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; - operating-points-v2 = <0x1>; - reg = <0x0>; - cpu-idle-states = <0x2>; - clocks = <0x3 0xa>; + operating-points-v2 = <0x01>; + reg = <0x00>; + cpu-idle-states = <0x02>; + clocks = <0x03 0x0a>; + phandle = <0x3f>; }; cpu@1 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; - reg = <0x1>; - operating-points-v2 = <0x1>; - cpu-idle-states = <0x2>; + reg = <0x01>; + operating-points-v2 = <0x01>; + cpu-idle-states = <0x02>; + phandle = <0x40>; }; cpu@2 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; - reg = <0x2>; - operating-points-v2 = <0x1>; - cpu-idle-states = <0x2>; + reg = <0x02>; + operating-points-v2 = <0x01>; + cpu-idle-states = <0x02>; + phandle = <0x41>; }; cpu@3 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; - reg = <0x3>; - operating-points-v2 = <0x1>; - cpu-idle-states = <0x2>; + reg = <0x03>; + operating-points-v2 = <0x01>; + cpu-idle-states = <0x02>; + phandle = <0x42>; }; idle-states { - entry-method = "arm,psci"; + entry-method = "psci"; cpu-sleep-0 { compatible = "arm,idle-state"; @@ -57,567 +61,73 @@ entry-latency-us = <0x12c>; exit-latency-us = <0x258>; min-residency-us = <0x2710>; - linux,phandle = <0x2>; - phandle = <0x2>; + phandle = <0x02>; }; }; }; - cpu_opp_table { + cpu-opp-table { compatible = "operating-points-v2"; opp-shared; - linux,phandle = <0x1>; - phandle = <0x1>; + phandle = <0x01>; opp00 { - opp-hz = <0x0 0x47868bf4>; + opp-hz = <0x00 0x47868bf4>; opp-microvolt = <0xf4240>; clock-latency-ns = <0x7a120>; }; opp01 { - opp-hz = <0x0 0x23c345fa>; + opp-hz = <0x00 0x23c345fa>; opp-microvolt = <0xf4240>; clock-latency-ns = <0x7a120>; }; opp02 { - opp-hz = <0x0 0x17d783fc>; + opp-hz = <0x00 0x17d783fc>; opp-microvolt = <0xf4240>; clock-latency-ns = <0x7a120>; }; opp03 { - opp-hz = <0x0 0x11e1a2fd>; + opp-hz = <0x00 0x11e1a2fd>; opp-microvolt = <0xf4240>; clock-latency-ns = <0x7a120>; }; }; + zynqmp_ipi { + u-boot,dm-pre-reloc; + compatible = "xlnx,zynqmp-ipi-mailbox"; + interrupt-parent = <0x04>; + interrupts = <0x00 0x23 0x04>; + xlnx,ipi-id = <0x00>; + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + phandle = <0x43>; + + mailbox@ff990400 { + u-boot,dm-pre-reloc; + reg = <0x00 0xff9905c0 0x00 0x20 0x00 0xff9905e0 0x00 0x20 0x00 0xff990e80 0x00 0x20 0x00 0xff990ea0 0x00 0x20>; + reg-names = "local_request_region\0local_response_region\0remote_request_region\0remote_response_region"; + #mbox-cells = <0x01>; + xlnx,ipi-id = <0x04>; + phandle = <0x05>; + }; + }; + dcc { compatible = "arm,dcc"; status = "okay"; u-boot,dm-pre-reloc; - }; - - pinctrl { - compatible = "xlnx,zynqmp-pinctrl"; - status = "okay"; - - i2c0-default { - linux,phandle = <0x18>; - phandle = <0x18>; - - mux { - groups = "i2c0_3_grp"; - function = "i2c0"; - }; - - conf { - groups = "i2c0_3_grp"; - bias-pull-up; - slew-rate = <0x1>; - io-standard = <0x1>; - }; - }; - - i2c0-gpio { - linux,phandle = <0x19>; - phandle = <0x19>; - - mux { - groups = "gpio0_14_grp", "gpio0_15_grp"; - function = "gpio0"; - }; - - conf { - groups = "gpio0_14_grp", "gpio0_15_grp"; - slew-rate = <0x1>; - io-standard = <0x1>; - }; - }; - - i2c1-default { - linux,phandle = <0x1c>; - phandle = <0x1c>; - - mux { - groups = "i2c1_4_grp"; - function = "i2c1"; - }; - - conf { - groups = "i2c1_4_grp"; - bias-pull-up; - slew-rate = <0x1>; - io-standard = <0x1>; - }; - }; - - i2c1-gpio { - linux,phandle = <0x1d>; - phandle = <0x1d>; - - mux { - groups = "gpio0_16_grp", "gpio0_17_grp"; - function = "gpio0"; - }; - - conf { - groups = "gpio0_16_grp", "gpio0_17_grp"; - slew-rate = <0x1>; - io-standard = <0x1>; - }; - }; - - uart0-default { - linux,phandle = <0x31>; - phandle = <0x31>; - - mux { - groups = "uart0_4_grp"; - function = "uart0"; - }; - - conf { - groups = "uart0_4_grp"; - slew-rate = <0x1>; - io-standard = <0x1>; - }; - - conf-rx { - pins = "MIO18"; - bias-high-impedance; - }; - - conf-tx { - pins = "MIO19"; - bias-disable; - }; - }; - - uart1-default { - linux,phandle = <0x33>; - phandle = <0x33>; - - mux { - groups = "uart1_5_grp"; - function = "uart1"; - }; - - conf { - groups = "uart1_5_grp"; - slew-rate = <0x1>; - io-standard = <0x1>; - }; - - conf-rx { - pins = "MIO21"; - bias-high-impedance; - }; - - conf-tx { - pins = "MIO20"; - bias-disable; - }; - }; - - usb0-default { - linux,phandle = <0x35>; - phandle = <0x35>; - - mux { - groups = "usb0_0_grp"; - function = "usb0"; - }; - - conf { - groups = "usb0_0_grp"; - slew-rate = <0x1>; - io-standard = <0x1>; - }; - - conf-rx { - pins = "MIO52", "MIO53", "MIO55"; - bias-high-impedance; - }; - - conf-tx { - pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; - bias-disable; - }; - }; - - gem3-default { - linux,phandle = <0x14>; - phandle = <0x14>; - - mux { - function = "ethernet3"; - groups = "ethernet3_0_grp"; - }; - - conf { - groups = "ethernet3_0_grp"; - slew-rate = <0x1>; - io-standard = <0x1>; - }; - - conf-rx { - pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; - bias-high-impedance; - low-power-disable; - }; - - conf-tx { - pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; - bias-disable; - low-power-enable; - }; - - mux-mdio { - function = "mdio3"; - groups = "mdio3_0_grp"; - }; - - conf-mdio { - groups = "mdio3_0_grp"; - slew-rate = <0x1>; - io-standard = <0x1>; - bias-disable; - }; - }; - - can1-default { - linux,phandle = <0x9>; - phandle = <0x9>; - - mux { - function = "can1"; - groups = "can1_6_grp"; - }; - - conf { - groups = "can1_6_grp"; - slew-rate = <0x1>; - io-standard = <0x1>; - }; - - conf-rx { - pins = "MIO25"; - bias-high-impedance; - }; - - conf-tx { - pins = "MIO24"; - bias-disable; - }; - }; - - sdhci1-default { - linux,phandle = <0x28>; - phandle = <0x28>; - - mux { - groups = "sdio1_0_grp"; - function = "sdio1"; - }; - - conf { - groups = "sdio1_0_grp"; - slew-rate = <0x1>; - io-standard = <0x1>; - bias-disable; - }; - - mux-cd { - groups = "sdio1_cd_0_grp"; - function = "sdio1_cd"; - }; - - conf-cd { - groups = "sdio1_cd_0_grp"; - bias-high-impedance; - bias-pull-up; - slew-rate = <0x1>; - io-standard = <0x1>; - }; - - mux-wp { - groups = "sdio1_wp_0_grp"; - function = "sdio1_wp"; - }; - - conf-wp { - groups = "sdio1_wp_0_grp"; - bias-high-impedance; - bias-pull-up; - slew-rate = <0x1>; - io-standard = <0x1>; - }; - }; - - gpio-default { - linux,phandle = <0x16>; - phandle = <0x16>; - - mux-sw { - function = "gpio0"; - groups = "gpio0_22_grp", "gpio0_23_grp"; - }; - - conf-sw { - groups = "gpio0_22_grp", "gpio0_23_grp"; - slew-rate = <0x1>; - io-standard = <0x1>; - }; - - mux-msp { - function = "gpio0"; - groups = "gpio0_13_grp", "gpio0_38_grp"; - }; - - conf-msp { - groups = "gpio0_13_grp", "gpio0_38_grp"; - slew-rate = <0x1>; - io-standard = <0x1>; - }; - - conf-pull-up { - pins = "MIO22", "MIO23"; - bias-pull-up; - }; - - conf-pull-none { - pins = "MIO13", "MIO38"; - bias-disable; - }; - }; - }; - - power-domains { - compatible = "xlnx,zynqmp-genpd"; - - pd-usb0 { - #power-domain-cells = <0x0>; - pd-id = <0x16>; - linux,phandle = <0x34>; - phandle = <0x34>; - }; - - pd-usb1 { - #power-domain-cells = <0x0>; - pd-id = <0x17>; - linux,phandle = <0x37>; - phandle = <0x37>; - }; - - pd-sata { - #power-domain-cells = <0x0>; - pd-id = <0x1c>; - linux,phandle = <0x24>; - phandle = <0x24>; - }; - - pd-spi0 { - #power-domain-cells = <0x0>; - pd-id = <0x23>; - linux,phandle = <0x29>; - phandle = <0x29>; - }; - - pd-spi1 { - #power-domain-cells = <0x0>; - pd-id = <0x24>; - linux,phandle = <0x2b>; - phandle = <0x2b>; - }; - - pd-uart0 { - #power-domain-cells = <0x0>; - pd-id = <0x21>; - linux,phandle = <0x30>; - phandle = <0x30>; - }; - - pd-uart1 { - #power-domain-cells = <0x0>; - pd-id = <0x22>; - linux,phandle = <0x32>; - phandle = <0x32>; - }; - - pd-eth0 { - #power-domain-cells = <0x0>; - pd-id = <0x1d>; - linux,phandle = <0xf>; - phandle = <0xf>; - }; - - pd-eth1 { - #power-domain-cells = <0x0>; - pd-id = <0x1e>; - linux,phandle = <0x10>; - phandle = <0x10>; - }; - - pd-eth2 { - #power-domain-cells = <0x0>; - pd-id = <0x1f>; - linux,phandle = <0x11>; - phandle = <0x11>; - }; - - pd-eth3 { - #power-domain-cells = <0x0>; - pd-id = <0x20>; - linux,phandle = <0x12>; - phandle = <0x12>; - }; - - pd-i2c0 { - #power-domain-cells = <0x0>; - pd-id = <0x25>; - linux,phandle = <0x17>; - phandle = <0x17>; - }; - - pd-i2c1 { - #power-domain-cells = <0x0>; - pd-id = <0x26>; - linux,phandle = <0x1b>; - phandle = <0x1b>; - }; - - pd-dp { - #power-domain-cells = <0x0>; - pd-id = <0x29>; - linux,phandle = <0x38>; - phandle = <0x38>; - }; - - pd-gdma { - #power-domain-cells = <0x0>; - pd-id = <0x2a>; - linux,phandle = <0xb>; - phandle = <0xb>; - }; - - pd-adma { - #power-domain-cells = <0x0>; - pd-id = <0x2b>; - linux,phandle = <0xd>; - phandle = <0xd>; - }; - - pd-ttc0 { - #power-domain-cells = <0x0>; - pd-id = <0x18>; - linux,phandle = <0x2c>; - phandle = <0x2c>; - }; - - pd-ttc1 { - #power-domain-cells = <0x0>; - pd-id = <0x19>; - linux,phandle = <0x2d>; - phandle = <0x2d>; - }; - - pd-ttc2 { - #power-domain-cells = <0x0>; - pd-id = <0x1a>; - linux,phandle = <0x2e>; - phandle = <0x2e>; - }; - - pd-ttc3 { - #power-domain-cells = <0x0>; - pd-id = <0x1b>; - linux,phandle = <0x2f>; - phandle = <0x2f>; - }; - - pd-sd0 { - #power-domain-cells = <0x0>; - pd-id = <0x27>; - linux,phandle = <0x26>; - phandle = <0x26>; - }; - - pd-sd1 { - #power-domain-cells = <0x0>; - pd-id = <0x28>; - linux,phandle = <0x27>; - phandle = <0x27>; - }; - - pd-nand { - #power-domain-cells = <0x0>; - pd-id = <0x2c>; - linux,phandle = <0xe>; - phandle = <0xe>; - }; - - pd-qspi { - #power-domain-cells = <0x0>; - pd-id = <0x2d>; - linux,phandle = <0x21>; - phandle = <0x21>; - }; - - pd-gpio { - #power-domain-cells = <0x0>; - pd-id = <0x2e>; - linux,phandle = <0x15>; - phandle = <0x15>; - }; - - pd-can0 { - #power-domain-cells = <0x0>; - pd-id = <0x2f>; - linux,phandle = <0x7>; - phandle = <0x7>; - }; - - pd-can1 { - #power-domain-cells = <0x0>; - pd-id = <0x30>; - linux,phandle = <0x8>; - phandle = <0x8>; - }; - - pd-pcie { - #power-domain-cells = <0x0>; - pd-id = <0x3b>; - linux,phandle = <0x20>; - phandle = <0x20>; - }; - - pd-gpu { - #power-domain-cells = <0x0>; - pd-id = <0x3a 0x14 0x15>; - linux,phandle = <0xc>; - phandle = <0xc>; - }; - }; - - mailbox@ff990400 { - compatible = "xlnx,zynqmp-ipi-mailbox"; - reg = <0x0 0xff9905c0 0x0 0x20 0x0 0xff9905e0 0x0 0x20 0x0 0xff990e80 0x0 0x20 0x0 0xff990ea0 0x0 0x20>; - reg-names = "local_request_region", "local_response_region", "remote_request_region", "remote_response_region"; - #mbox-cells = <0x1>; - xlnx,ipi-ids = <0x0 0x4>; - interrupt-parent = <0x4>; - interrupts = <0x0 0x23 0x4>; - linux,phandle = <0x5>; - phandle = <0x5>; + phandle = <0x44>; }; pmu { compatible = "arm,armv8-pmuv3"; - interrupt-parent = <0x4>; - interrupts = <0x0 0x8f 0x4 0x0 0x90 0x4 0x0 0x91 0x4 0x0 0x92 0x4>; + interrupt-parent = <0x04>; + interrupts = <0x00 0x8f 0x04 0x00 0x90 0x04 0x00 0x91 0x04 0x00 0x92 0x04>; }; psci { @@ -629,20 +139,447 @@ zynqmp-firmware { compatible = "xlnx,zynqmp-firmware"; + #power-domain-cells = <0x01>; method = "smc"; - }; - }; + u-boot,dm-pre-reloc; + phandle = <0x0c>; - zynqmp-power { - compatible = "xlnx,zynqmp-power"; - mboxes = <0x5 0x0 0x5 0x1>; - mbox-names = "tx", "rx"; + zynqmp-power { + u-boot,dm-pre-reloc; + compatible = "xlnx,zynqmp-power"; + interrupt-parent = <0x04>; + interrupts = <0x00 0x23 0x04>; + mboxes = <0x05 0x00 0x05 0x01>; + mbox-names = "tx\0rx"; + phandle = <0x45>; + }; + + nvmem_firmware { + compatible = "xlnx,zynqmp-nvmem-fw"; + #address-cells = <0x01>; + #size-cells = <0x01>; + + soc_revision@0 { + reg = <0x00 0x04>; + phandle = <0x1e>; + }; + + efuse_dna@c { + reg = <0x0c 0x0c>; + phandle = <0x46>; + }; + + efuse_usr0@20 { + reg = <0x20 0x04>; + phandle = <0x47>; + }; + + efuse_usr1@24 { + reg = <0x24 0x04>; + phandle = <0x48>; + }; + + efuse_usr2@28 { + reg = <0x28 0x04>; + phandle = <0x49>; + }; + + efuse_usr3@2c { + reg = <0x2c 0x04>; + phandle = <0x4a>; + }; + + efuse_usr4@30 { + reg = <0x30 0x04>; + phandle = <0x4b>; + }; + + efuse_usr5@34 { + reg = <0x34 0x04>; + phandle = <0x4c>; + }; + + efuse_usr6@38 { + reg = <0x38 0x04>; + phandle = <0x4d>; + }; + + efuse_usr7@3c { + reg = <0x3c 0x04>; + phandle = <0x4e>; + }; + + efuse_miscusr@40 { + reg = <0x40 0x04>; + phandle = <0x4f>; + }; + + efuse_chash@50 { + reg = <0x50 0x04>; + phandle = <0x50>; + }; + + efuse_pufmisc@54 { + reg = <0x54 0x04>; + phandle = <0x51>; + }; + + efuse_sec@58 { + reg = <0x58 0x04>; + phandle = <0x52>; + }; + + efuse_spkid@5c { + reg = <0x5c 0x04>; + phandle = <0x53>; + }; + + efuse_ppk0hash@a0 { + reg = <0xa0 0x30>; + phandle = <0x54>; + }; + + efuse_ppk1hash@d0 { + reg = <0xd0 0x30>; + phandle = <0x55>; + }; + }; + + pcap { + compatible = "xlnx,zynqmp-pcap-fpga"; + clock-names = "ref_clk"; + clocks = <0x03 0x29>; + phandle = <0x0b>; + }; + + zynqmp-aes { + compatible = "xlnx,zynqmp-aes"; + phandle = <0x56>; + }; + + reset-controller { + compatible = "xlnx,zynqmp-reset"; + #reset-cells = <0x01>; + phandle = <0x1c>; + }; + + pinctrl { + compatible = "xlnx,zynqmp-pinctrl"; + status = "okay"; + phandle = <0x57>; + + i2c0-default { + phandle = <0x12>; + + mux { + groups = "i2c0_3_grp"; + function = "i2c0"; + }; + + conf { + groups = "i2c0_3_grp"; + bias-pull-up; + slew-rate = <0x01>; + power-source = <0x01>; + }; + }; + + i2c0-gpio { + phandle = <0x13>; + + mux { + groups = "gpio0_14_grp\0gpio0_15_grp"; + function = "gpio0"; + }; + + conf { + groups = "gpio0_14_grp\0gpio0_15_grp"; + slew-rate = <0x01>; + power-source = <0x01>; + }; + }; + + i2c1-default { + phandle = <0x15>; + + mux { + groups = "i2c1_4_grp"; + function = "i2c1"; + }; + + conf { + groups = "i2c1_4_grp"; + bias-pull-up; + slew-rate = <0x01>; + power-source = <0x01>; + }; + }; + + i2c1-gpio { + phandle = <0x16>; + + mux { + groups = "gpio0_16_grp\0gpio0_17_grp"; + function = "gpio0"; + }; + + conf { + groups = "gpio0_16_grp\0gpio0_17_grp"; + slew-rate = <0x01>; + power-source = <0x01>; + }; + }; + + uart0-default { + phandle = <0x21>; + + mux { + groups = "uart0_4_grp"; + function = "uart0"; + }; + + conf { + groups = "uart0_4_grp"; + slew-rate = <0x01>; + power-source = <0x01>; + }; + + conf-rx { + pins = "MIO18"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO19"; + bias-disable; + }; + }; + + uart1-default { + phandle = <0x22>; + + mux { + groups = "uart1_5_grp"; + function = "uart1"; + }; + + conf { + groups = "uart1_5_grp"; + slew-rate = <0x01>; + power-source = <0x01>; + }; + + conf-rx { + pins = "MIO21"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO20"; + bias-disable; + }; + }; + + usb0-default { + phandle = <0x24>; + + mux { + groups = "usb0_0_grp"; + function = "usb0"; + }; + + conf { + groups = "usb0_0_grp"; + slew-rate = <0x01>; + power-source = <0x01>; + }; + + conf-rx { + pins = "MIO52\0MIO53\0MIO55"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO54\0MIO56\0MIO57\0MIO58\0MIO59\0MIO60\0MIO61\0MIO62\0MIO63"; + bias-disable; + }; + }; + + gem3-default { + phandle = <0x10>; + + mux { + function = "ethernet3"; + groups = "ethernet3_0_grp"; + }; + + conf { + groups = "ethernet3_0_grp"; + slew-rate = <0x01>; + power-source = <0x01>; + }; + + conf-rx { + pins = "MIO70\0MIO71\0MIO72\0MIO73\0MIO74\0MIO75"; + bias-high-impedance; + low-power-disable; + }; + + conf-tx { + pins = "MIO64\0MIO65\0MIO66\0MIO67\0MIO68\0MIO69"; + bias-disable; + low-power-enable; + }; + + mux-mdio { + function = "mdio3"; + groups = "mdio3_0_grp"; + }; + + conf-mdio { + groups = "mdio3_0_grp"; + slew-rate = <0x01>; + power-source = <0x01>; + bias-disable; + }; + }; + + can1-default { + phandle = <0x0d>; + + mux { + function = "can1"; + groups = "can1_6_grp"; + }; + + conf { + groups = "can1_6_grp"; + slew-rate = <0x01>; + power-source = <0x01>; + }; + + conf-rx { + pins = "MIO25"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO24"; + bias-disable; + }; + }; + + sdhci1-default { + phandle = <0x1f>; + + mux { + groups = "sdio1_0_grp"; + function = "sdio1"; + }; + + conf { + groups = "sdio1_0_grp"; + slew-rate = <0x01>; + power-source = <0x01>; + bias-disable; + }; + + mux-cd { + groups = "sdio1_cd_0_grp"; + function = "sdio1_cd"; + }; + + conf-cd { + groups = "sdio1_cd_0_grp"; + bias-high-impedance; + bias-pull-up; + slew-rate = <0x01>; + power-source = <0x01>; + }; + + mux-wp { + groups = "sdio1_wp_0_grp"; + function = "sdio1_wp"; + }; + + conf-wp { + groups = "sdio1_wp_0_grp"; + bias-high-impedance; + bias-pull-up; + slew-rate = <0x01>; + power-source = <0x01>; + }; + }; + + gpio-default { + phandle = <0x11>; + + mux-sw { + function = "gpio0"; + groups = "gpio0_22_grp\0gpio0_23_grp"; + }; + + conf-sw { + groups = "gpio0_22_grp\0gpio0_23_grp"; + slew-rate = <0x01>; + power-source = <0x01>; + }; + + mux-msp { + function = "gpio0"; + groups = "gpio0_13_grp\0gpio0_38_grp"; + }; + + conf-msp { + groups = "gpio0_13_grp\0gpio0_38_grp"; + slew-rate = <0x01>; + power-source = <0x01>; + }; + + conf-pull-up { + pins = "MIO22\0MIO23"; + bias-pull-up; + }; + + conf-pull-none { + pins = "MIO13\0MIO38"; + bias-disable; + }; + }; + }; + + sha384 { + compatible = "xlnx,zynqmp-keccak-384"; + phandle = <0x58>; + }; + + zynqmp-rsa { + compatible = "xlnx,zynqmp-rsa"; + phandle = <0x59>; + }; + + gpio { + compatible = "xlnx,zynqmp-gpio-modepin"; + gpio-controller; + #gpio-cells = <0x02>; + phandle = <0x23>; + }; + + clock-controller { + u-boot,dm-pre-reloc; + #clock-cells = <0x01>; + compatible = "xlnx,zynqmp-clk"; + clocks = <0x06 0x07 0x08 0x09 0x0a>; + clock-names = "pss_ref_clk\0video_clk\0pss_alt_ref_clk\0aux_ref_clk\0gt_crx_ref_clk"; + phandle = <0x03>; + }; + }; }; timer { compatible = "arm,armv8-timer"; - interrupt-parent = <0x4>; - interrupts = <0x1 0xd 0xf08 0x1 0xe 0xf08 0x1 0xb 0xf08 0x1 0xa 0xf08>; + interrupt-parent = <0x04>; + interrupts = <0x01 0x0d 0xf08 0x01 0x0e 0xf08 0x01 0x0b 0xf08 0x01 0x0a 0xf08>; }; edac { @@ -651,583 +588,502 @@ fpga-full { compatible = "fpga-region"; - fpga-mgr = <0x6>; - #address-cells = <0x2>; - #size-cells = <0x2>; - }; - - nvmem_firmware { - compatible = "xlnx,zynqmp-nvmem-fw"; - #address-cells = <0x1>; - #size-cells = <0x1>; - - soc_revision@0 { - reg = <0x0 0x4>; - linux,phandle = <0x22>; - phandle = <0x22>; - }; - - efuse_dna@c { - reg = <0xc 0xc>; - }; - - efuse_usr0@20 { - reg = <0x20 0x4>; - }; - - efuse_usr1@24 { - reg = <0x24 0x4>; - }; - - efuse_usr2@28 { - reg = <0x28 0x4>; - }; - - efuse_usr3@2c { - reg = <0x2c 0x4>; - }; - - efuse_usr4@30 { - reg = <0x30 0x4>; - }; - - efuse_usr5@34 { - reg = <0x34 0x4>; - }; - - efuse_usr6@38 { - reg = <0x38 0x4>; - }; - - efuse_usr7@3c { - reg = <0x3c 0x4>; - }; - - efuse_miscusr@40 { - reg = <0x40 0x4>; - }; - - efuse_chash@50 { - reg = <0x50 0x4>; - }; - - efuse_pufmisc@54 { - reg = <0x54 0x4>; - }; - - efuse_sec@58 { - reg = <0x58 0x4>; - }; - - efuse_spkid@5c { - reg = <0x5c 0x4>; - }; - - efuse_ppk0hash@a0 { - reg = <0xa0 0x30>; - }; - - efuse_ppk1hash@d0 { - reg = <0xd0 0x30>; - }; - }; - - pcap { - compatible = "xlnx,zynqmp-pcap-fpga"; - clock-names = "ref_clk"; - clocks = <0x3 0x29>; - linux,phandle = <0x6>; - phandle = <0x6>; - }; - - reset-controller { - compatible = "xlnx,zynqmp-reset"; - #reset-cells = <0x1>; - linux,phandle = <0x23>; - phandle = <0x23>; - }; - - zynqmp_rsa { - compatible = "xlnx,zynqmp-rsa"; - }; - - sha384 { - compatible = "xlnx,zynqmp-keccak-384"; - }; - - zynqmp_aes { - compatible = "xlnx,zynqmp-aes"; - }; - - amba_apu@0 { - compatible = "simple-bus"; - #address-cells = <0x2>; - #size-cells = <0x1>; - ranges = <0x0 0x0 0x0 0x0 0xffffffff>; - - interrupt-controller@f9010000 { - compatible = "arm,gic-400", "arm,cortex-a15-gic"; - #interrupt-cells = <0x3>; - reg = <0x0 0xf9010000 0x10000 0x0 0xf9020000 0x20000 0x0 0xf9040000 0x20000 0x0 0xf9060000 0x20000>; - interrupt-controller; - interrupt-parent = <0x4>; - interrupts = <0x1 0x9 0xf04>; - linux,phandle = <0x4>; - phandle = <0x4>; - }; + fpga-mgr = <0x0b>; + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + phandle = <0x5a>; }; smmu@fd800000 { compatible = "arm,mmu-500"; - reg = <0x0 0xfd800000 0x0 0x20000>; - #iommu-cells = <0x1>; + reg = <0x00 0xfd800000 0x00 0x20000>; + #iommu-cells = <0x01>; status = "disabled"; - #global-interrupts = <0x1>; - interrupt-parent = <0x4>; - interrupts = <0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4 0x0 0x9b 0x4>; - linux,phandle = <0xa>; - phandle = <0xa>; + #global-interrupts = <0x01>; + interrupt-parent = <0x04>; + interrupts = <0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04>; + phandle = <0x0e>; }; - amba { + axi { compatible = "simple-bus"; u-boot,dm-pre-reloc; - #address-cells = <0x2>; - #size-cells = <0x2>; + #address-cells = <0x02>; + #size-cells = <0x02>; ranges; + phandle = <0x5b>; can@ff060000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; - clock-names = "can_clk", "pclk"; - reg = <0x0 0xff060000 0x0 0x1000>; - interrupts = <0x0 0x17 0x4>; - interrupt-parent = <0x4>; + clock-names = "can_clk\0pclk"; + reg = <0x00 0xff060000 0x00 0x1000>; + interrupts = <0x00 0x17 0x04>; + interrupt-parent = <0x04>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; - power-domains = <0x7>; - clocks = <0x3 0x3f 0x3 0x1f>; + power-domains = <0x0c 0x2f>; + clocks = <0x03 0x3f 0x03 0x1f>; + phandle = <0x5c>; }; can@ff070000 { compatible = "xlnx,zynq-can-1.0"; status = "okay"; - clock-names = "can_clk", "pclk"; - reg = <0x0 0xff070000 0x0 0x1000>; - interrupts = <0x0 0x18 0x4>; - interrupt-parent = <0x4>; + clock-names = "can_clk\0pclk"; + reg = <0x00 0xff070000 0x00 0x1000>; + interrupts = <0x00 0x18 0x04>; + interrupt-parent = <0x04>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; - power-domains = <0x8>; - clocks = <0x3 0x40 0x3 0x1f>; + power-domains = <0x0c 0x30>; + clocks = <0x03 0x40 0x03 0x1f>; pinctrl-names = "default"; - pinctrl-0 = <0x9>; + pinctrl-0 = <0x0d>; + phandle = <0x5d>; }; cci@fd6e0000 { compatible = "arm,cci-400"; - reg = <0x0 0xfd6e0000 0x0 0x9000>; - ranges = <0x0 0x0 0xfd6e0000 0x10000>; - #address-cells = <0x1>; - #size-cells = <0x1>; + status = "disabled"; + reg = <0x00 0xfd6e0000 0x00 0x9000>; + ranges = <0x00 0x00 0xfd6e0000 0x10000>; + #address-cells = <0x01>; + #size-cells = <0x01>; + phandle = <0x5e>; pmu@9000 { compatible = "arm,cci-400-pmu,r1"; reg = <0x9000 0x5000>; - interrupt-parent = <0x4>; - interrupts = <0x0 0x7b 0x4 0x0 0x7b 0x4 0x0 0x7b 0x4 0x0 0x7b 0x4 0x0 0x7b 0x4>; + interrupt-parent = <0x04>; + interrupts = <0x00 0x7b 0x04 0x00 0x7b 0x04 0x00 0x7b 0x04 0x00 0x7b 0x04 0x00 0x7b 0x04>; }; }; dma@fd500000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xfd500000 0x0 0x1000>; - interrupt-parent = <0x4>; - interrupts = <0x0 0x7c 0x4>; - clock-names = "clk_main", "clk_apb"; + reg = <0x00 0xfd500000 0x00 0x1000>; + interrupt-parent = <0x04>; + interrupts = <0x00 0x7c 0x04>; + clock-names = "clk_main\0clk_apb"; xlnx,bus-width = <0x80>; - #stream-id-cells = <0x1>; - iommus = <0xa 0x14e8>; - power-domains = <0xb>; - clocks = <0x3 0x13 0x3 0x1f>; + #stream-id-cells = <0x01>; + iommus = <0x0e 0x14e8>; + power-domains = <0x0c 0x2a>; + clocks = <0x03 0x13 0x03 0x1f>; + phandle = <0x5f>; }; dma@fd510000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xfd510000 0x0 0x1000>; - interrupt-parent = <0x4>; - interrupts = <0x0 0x7d 0x4>; - clock-names = "clk_main", "clk_apb"; + reg = <0x00 0xfd510000 0x00 0x1000>; + interrupt-parent = <0x04>; + interrupts = <0x00 0x7d 0x04>; + clock-names = "clk_main\0clk_apb"; xlnx,bus-width = <0x80>; - #stream-id-cells = <0x1>; - iommus = <0xa 0x14e9>; - power-domains = <0xb>; - clocks = <0x3 0x13 0x3 0x1f>; + #stream-id-cells = <0x01>; + iommus = <0x0e 0x14e9>; + power-domains = <0x0c 0x2a>; + clocks = <0x03 0x13 0x03 0x1f>; + phandle = <0x60>; }; dma@fd520000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xfd520000 0x0 0x1000>; - interrupt-parent = <0x4>; - interrupts = <0x0 0x7e 0x4>; - clock-names = "clk_main", "clk_apb"; + reg = <0x00 0xfd520000 0x00 0x1000>; + interrupt-parent = <0x04>; + interrupts = <0x00 0x7e 0x04>; + clock-names = "clk_main\0clk_apb"; xlnx,bus-width = <0x80>; - #stream-id-cells = <0x1>; - iommus = <0xa 0x14ea>; - power-domains = <0xb>; - clocks = <0x3 0x13 0x3 0x1f>; + #stream-id-cells = <0x01>; + iommus = <0x0e 0x14ea>; + power-domains = <0x0c 0x2a>; + clocks = <0x03 0x13 0x03 0x1f>; + phandle = <0x61>; }; dma@fd530000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xfd530000 0x0 0x1000>; - interrupt-parent = <0x4>; - interrupts = <0x0 0x7f 0x4>; - clock-names = "clk_main", "clk_apb"; + reg = <0x00 0xfd530000 0x00 0x1000>; + interrupt-parent = <0x04>; + interrupts = <0x00 0x7f 0x04>; + clock-names = "clk_main\0clk_apb"; xlnx,bus-width = <0x80>; - #stream-id-cells = <0x1>; - iommus = <0xa 0x14eb>; - power-domains = <0xb>; - clocks = <0x3 0x13 0x3 0x1f>; + #stream-id-cells = <0x01>; + iommus = <0x0e 0x14eb>; + power-domains = <0x0c 0x2a>; + clocks = <0x03 0x13 0x03 0x1f>; + phandle = <0x62>; }; dma@fd540000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xfd540000 0x0 0x1000>; - interrupt-parent = <0x4>; - interrupts = <0x0 0x80 0x4>; - clock-names = "clk_main", "clk_apb"; + reg = <0x00 0xfd540000 0x00 0x1000>; + interrupt-parent = <0x04>; + interrupts = <0x00 0x80 0x04>; + clock-names = "clk_main\0clk_apb"; xlnx,bus-width = <0x80>; - #stream-id-cells = <0x1>; - iommus = <0xa 0x14ec>; - power-domains = <0xb>; - clocks = <0x3 0x13 0x3 0x1f>; + #stream-id-cells = <0x01>; + iommus = <0x0e 0x14ec>; + power-domains = <0x0c 0x2a>; + clocks = <0x03 0x13 0x03 0x1f>; + phandle = <0x63>; }; dma@fd550000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xfd550000 0x0 0x1000>; - interrupt-parent = <0x4>; - interrupts = <0x0 0x81 0x4>; - clock-names = "clk_main", "clk_apb"; + reg = <0x00 0xfd550000 0x00 0x1000>; + interrupt-parent = <0x04>; + interrupts = <0x00 0x81 0x04>; + clock-names = "clk_main\0clk_apb"; xlnx,bus-width = <0x80>; - #stream-id-cells = <0x1>; - iommus = <0xa 0x14ed>; - power-domains = <0xb>; - clocks = <0x3 0x13 0x3 0x1f>; + #stream-id-cells = <0x01>; + iommus = <0x0e 0x14ed>; + power-domains = <0x0c 0x2a>; + clocks = <0x03 0x13 0x03 0x1f>; + phandle = <0x64>; }; dma@fd560000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xfd560000 0x0 0x1000>; - interrupt-parent = <0x4>; - interrupts = <0x0 0x82 0x4>; - clock-names = "clk_main", "clk_apb"; + reg = <0x00 0xfd560000 0x00 0x1000>; + interrupt-parent = <0x04>; + interrupts = <0x00 0x82 0x04>; + clock-names = "clk_main\0clk_apb"; xlnx,bus-width = <0x80>; - #stream-id-cells = <0x1>; - iommus = <0xa 0x14ee>; - power-domains = <0xb>; - clocks = <0x3 0x13 0x3 0x1f>; + #stream-id-cells = <0x01>; + iommus = <0x0e 0x14ee>; + power-domains = <0x0c 0x2a>; + clocks = <0x03 0x13 0x03 0x1f>; + phandle = <0x65>; }; dma@fd570000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xfd570000 0x0 0x1000>; - interrupt-parent = <0x4>; - interrupts = <0x0 0x83 0x4>; - clock-names = "clk_main", "clk_apb"; + reg = <0x00 0xfd570000 0x00 0x1000>; + interrupt-parent = <0x04>; + interrupts = <0x00 0x83 0x04>; + clock-names = "clk_main\0clk_apb"; xlnx,bus-width = <0x80>; - #stream-id-cells = <0x1>; - iommus = <0xa 0x14ef>; - power-domains = <0xb>; - clocks = <0x3 0x13 0x3 0x1f>; + #stream-id-cells = <0x01>; + iommus = <0x0e 0x14ef>; + power-domains = <0x0c 0x2a>; + clocks = <0x03 0x13 0x03 0x1f>; + phandle = <0x66>; + }; + + interrupt-controller@f9010000 { + compatible = "arm,gic-400"; + #interrupt-cells = <0x03>; + reg = <0x00 0xf9010000 0x00 0x10000 0x00 0xf9020000 0x00 0x20000 0x00 0xf9040000 0x00 0x20000 0x00 0xf9060000 0x00 0x20000>; + interrupt-controller; + interrupt-parent = <0x04>; + interrupts = <0x01 0x09 0xf04>; + phandle = <0x04>; }; gpu@fd4b0000 { status = "okay"; - compatible = "arm,mali-400", "arm,mali-utgard"; - reg = <0x0 0xfd4b0000 0x0 0x10000>; - interrupt-parent = <0x4>; - interrupts = <0x0 0x84 0x4 0x0 0x84 0x4 0x0 0x84 0x4 0x0 0x84 0x4 0x0 0x84 0x4 0x0 0x84 0x4>; - interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1"; - clock-names = "gpu", "gpu_pp0", "gpu_pp1"; - power-domains = <0xc>; - clocks = <0x3 0x18 0x3 0x19 0x3 0x1a>; + compatible = "arm,mali-400\0arm,mali-utgard"; + reg = <0x00 0xfd4b0000 0x00 0x10000>; + interrupt-parent = <0x04>; + interrupts = <0x00 0x84 0x04 0x00 0x84 0x04 0x00 0x84 0x04 0x00 0x84 0x04 0x00 0x84 0x04 0x00 0x84 0x04>; + interrupt-names = "IRQGP\0IRQGPMMU\0IRQPP0\0IRQPPMMU0\0IRQPP1\0IRQPPMMU1"; + clock-names = "gpu\0gpu_pp0\0gpu_pp1"; + power-domains = <0x0c 0x3a>; + clocks = <0x03 0x18 0x03 0x19 0x03 0x1a>; + phandle = <0x67>; }; dma@ffa80000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xffa80000 0x0 0x1000>; - interrupt-parent = <0x4>; - interrupts = <0x0 0x4d 0x4>; - clock-names = "clk_main", "clk_apb"; + reg = <0x00 0xffa80000 0x00 0x1000>; + interrupt-parent = <0x04>; + interrupts = <0x00 0x4d 0x04>; + clock-names = "clk_main\0clk_apb"; xlnx,bus-width = <0x40>; - #stream-id-cells = <0x1>; - power-domains = <0xd>; - clocks = <0x3 0x44 0x3 0x1f>; + #stream-id-cells = <0x01>; + power-domains = <0x0c 0x2b>; + clocks = <0x03 0x44 0x03 0x1f>; + phandle = <0x68>; }; dma@ffa90000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xffa90000 0x0 0x1000>; - interrupt-parent = <0x4>; - interrupts = <0x0 0x4e 0x4>; - clock-names = "clk_main", "clk_apb"; + reg = <0x00 0xffa90000 0x00 0x1000>; + interrupt-parent = <0x04>; + interrupts = <0x00 0x4e 0x04>; + clock-names = "clk_main\0clk_apb"; xlnx,bus-width = <0x40>; - #stream-id-cells = <0x1>; - power-domains = <0xd>; - clocks = <0x3 0x44 0x3 0x1f>; + #stream-id-cells = <0x01>; + power-domains = <0x0c 0x2b>; + clocks = <0x03 0x44 0x03 0x1f>; + phandle = <0x69>; }; dma@ffaa0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xffaa0000 0x0 0x1000>; - interrupt-parent = <0x4>; - interrupts = <0x0 0x4f 0x4>; - clock-names = "clk_main", "clk_apb"; + reg = <0x00 0xffaa0000 0x00 0x1000>; + interrupt-parent = <0x04>; + interrupts = <0x00 0x4f 0x04>; + clock-names = "clk_main\0clk_apb"; xlnx,bus-width = <0x40>; - #stream-id-cells = <0x1>; - power-domains = <0xd>; - clocks = <0x3 0x44 0x3 0x1f>; + #stream-id-cells = <0x01>; + power-domains = <0x0c 0x2b>; + clocks = <0x03 0x44 0x03 0x1f>; + phandle = <0x6a>; }; dma@ffab0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xffab0000 0x0 0x1000>; - interrupt-parent = <0x4>; - interrupts = <0x0 0x50 0x4>; - clock-names = "clk_main", "clk_apb"; + reg = <0x00 0xffab0000 0x00 0x1000>; + interrupt-parent = <0x04>; + interrupts = <0x00 0x50 0x04>; + clock-names = "clk_main\0clk_apb"; xlnx,bus-width = <0x40>; - #stream-id-cells = <0x1>; - power-domains = <0xd>; - clocks = <0x3 0x44 0x3 0x1f>; + #stream-id-cells = <0x01>; + power-domains = <0x0c 0x2b>; + clocks = <0x03 0x44 0x03 0x1f>; + phandle = <0x6b>; }; dma@ffac0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xffac0000 0x0 0x1000>; - interrupt-parent = <0x4>; - interrupts = <0x0 0x51 0x4>; - clock-names = "clk_main", "clk_apb"; + reg = <0x00 0xffac0000 0x00 0x1000>; + interrupt-parent = <0x04>; + interrupts = <0x00 0x51 0x04>; + clock-names = "clk_main\0clk_apb"; xlnx,bus-width = <0x40>; - #stream-id-cells = <0x1>; - power-domains = <0xd>; - clocks = <0x3 0x44 0x3 0x1f>; + #stream-id-cells = <0x01>; + power-domains = <0x0c 0x2b>; + clocks = <0x03 0x44 0x03 0x1f>; + phandle = <0x6c>; }; dma@ffad0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xffad0000 0x0 0x1000>; - interrupt-parent = <0x4>; - interrupts = <0x0 0x52 0x4>; - clock-names = "clk_main", "clk_apb"; + reg = <0x00 0xffad0000 0x00 0x1000>; + interrupt-parent = <0x04>; + interrupts = <0x00 0x52 0x04>; + clock-names = "clk_main\0clk_apb"; xlnx,bus-width = <0x40>; - #stream-id-cells = <0x1>; - power-domains = <0xd>; - clocks = <0x3 0x44 0x3 0x1f>; + #stream-id-cells = <0x01>; + power-domains = <0x0c 0x2b>; + clocks = <0x03 0x44 0x03 0x1f>; + phandle = <0x6d>; }; dma@ffae0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xffae0000 0x0 0x1000>; - interrupt-parent = <0x4>; - interrupts = <0x0 0x53 0x4>; - clock-names = "clk_main", "clk_apb"; + reg = <0x00 0xffae0000 0x00 0x1000>; + interrupt-parent = <0x04>; + interrupts = <0x00 0x53 0x04>; + clock-names = "clk_main\0clk_apb"; xlnx,bus-width = <0x40>; - #stream-id-cells = <0x1>; - power-domains = <0xd>; - clocks = <0x3 0x44 0x3 0x1f>; + #stream-id-cells = <0x01>; + power-domains = <0x0c 0x2b>; + clocks = <0x03 0x44 0x03 0x1f>; + phandle = <0x6e>; }; dma@ffaf0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xffaf0000 0x0 0x1000>; - interrupt-parent = <0x4>; - interrupts = <0x0 0x54 0x4>; - clock-names = "clk_main", "clk_apb"; + reg = <0x00 0xffaf0000 0x00 0x1000>; + interrupt-parent = <0x04>; + interrupts = <0x00 0x54 0x04>; + clock-names = "clk_main\0clk_apb"; xlnx,bus-width = <0x40>; - #stream-id-cells = <0x1>; - power-domains = <0xd>; - clocks = <0x3 0x44 0x3 0x1f>; + #stream-id-cells = <0x01>; + power-domains = <0x0c 0x2b>; + clocks = <0x03 0x44 0x03 0x1f>; + phandle = <0x6f>; }; memory-controller@fd070000 { compatible = "xlnx,zynqmp-ddrc-2.40a"; - reg = <0x0 0xfd070000 0x0 0x30000>; - interrupt-parent = <0x4>; - interrupts = <0x0 0x70 0x4>; + reg = <0x00 0xfd070000 0x00 0x30000>; + interrupt-parent = <0x04>; + interrupts = <0x00 0x70 0x04>; + phandle = <0x70>; }; - nand@ff100000 { - compatible = "arasan,nfc-v3p10"; + nand-controller@ff100000 { + compatible = "xlnx,zynqmp-nand-controller\0arasan,nfc-v3p10"; status = "disabled"; - reg = <0x0 0xff100000 0x0 0x1000>; - clock-names = "clk_sys", "clk_flash"; - interrupt-parent = <0x4>; - interrupts = <0x0 0xe 0x4>; - #address-cells = <0x1>; - #size-cells = <0x0>; - #stream-id-cells = <0x1>; - iommus = <0xa 0x872>; - power-domains = <0xe>; - clocks = <0x3 0x3c 0x3 0x1f>; + reg = <0x00 0xff100000 0x00 0x1000>; + clock-names = "controller\0bus"; + interrupt-parent = <0x04>; + interrupts = <0x00 0x0e 0x04>; + #address-cells = <0x01>; + #size-cells = <0x00>; + #stream-id-cells = <0x01>; + iommus = <0x0e 0x872>; + power-domains = <0x0c 0x2c>; + clocks = <0x03 0x3c 0x03 0x1f>; + phandle = <0x71>; }; ethernet@ff0b0000 { - compatible = "cdns,zynqmp-gem", "cdns,gem"; + compatible = "cdns,zynqmp-gem\0cdns,gem"; status = "disabled"; - interrupt-parent = <0x4>; - interrupts = <0x0 0x39 0x4 0x0 0x39 0x4>; - reg = <0x0 0xff0b0000 0x0 0x1000>; - clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; - #address-cells = <0x1>; - #size-cells = <0x0>; - #stream-id-cells = <0x1>; - iommus = <0xa 0x874>; - power-domains = <0xf>; - clocks = <0x3 0x1f 0x3 0x68 0x3 0x2d 0x3 0x31 0x3 0x2c>; + interrupt-parent = <0x04>; + interrupts = <0x00 0x39 0x04 0x00 0x39 0x04>; + reg = <0x00 0xff0b0000 0x00 0x1000>; + clock-names = "pclk\0hclk\0tx_clk\0rx_clk\0tsu_clk"; + #address-cells = <0x01>; + #size-cells = <0x00>; + #stream-id-cells = <0x01>; + iommus = <0x0e 0x874>; + power-domains = <0x0c 0x1d>; + clocks = <0x03 0x1f 0x03 0x68 0x03 0x2d 0x03 0x31 0x03 0x2c>; + phandle = <0x72>; }; ethernet@ff0c0000 { - compatible = "cdns,zynqmp-gem", "cdns,gem"; + compatible = "cdns,zynqmp-gem\0cdns,gem"; status = "disabled"; - interrupt-parent = <0x4>; - interrupts = <0x0 0x3b 0x4 0x0 0x3b 0x4>; - reg = <0x0 0xff0c0000 0x0 0x1000>; - clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; - #address-cells = <0x1>; - #size-cells = <0x0>; - #stream-id-cells = <0x1>; - iommus = <0xa 0x875>; - power-domains = <0x10>; - clocks = <0x3 0x1f 0x3 0x69 0x3 0x2e 0x3 0x32 0x3 0x2c>; + interrupt-parent = <0x04>; + interrupts = <0x00 0x3b 0x04 0x00 0x3b 0x04>; + reg = <0x00 0xff0c0000 0x00 0x1000>; + clock-names = "pclk\0hclk\0tx_clk\0rx_clk\0tsu_clk"; + #address-cells = <0x01>; + #size-cells = <0x00>; + #stream-id-cells = <0x01>; + iommus = <0x0e 0x875>; + power-domains = <0x0c 0x1e>; + clocks = <0x03 0x1f 0x03 0x69 0x03 0x2e 0x03 0x32 0x03 0x2c>; + phandle = <0x73>; }; ethernet@ff0d0000 { - compatible = "cdns,zynqmp-gem", "cdns,gem"; + compatible = "cdns,zynqmp-gem\0cdns,gem"; status = "disabled"; - interrupt-parent = <0x4>; - interrupts = <0x0 0x3d 0x4 0x0 0x3d 0x4>; - reg = <0x0 0xff0d0000 0x0 0x1000>; - clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; - #address-cells = <0x1>; - #size-cells = <0x0>; - #stream-id-cells = <0x1>; - iommus = <0xa 0x876>; - power-domains = <0x11>; - clocks = <0x3 0x1f 0x3 0x6a 0x3 0x2f 0x3 0x33 0x3 0x2c>; + interrupt-parent = <0x04>; + interrupts = <0x00 0x3d 0x04 0x00 0x3d 0x04>; + reg = <0x00 0xff0d0000 0x00 0x1000>; + clock-names = "pclk\0hclk\0tx_clk\0rx_clk\0tsu_clk"; + #address-cells = <0x01>; + #size-cells = <0x00>; + #stream-id-cells = <0x01>; + iommus = <0x0e 0x876>; + power-domains = <0x0c 0x1f>; + clocks = <0x03 0x1f 0x03 0x6a 0x03 0x2f 0x03 0x33 0x03 0x2c>; + phandle = <0x74>; }; ethernet@ff0e0000 { - compatible = "cdns,zynqmp-gem", "cdns,gem"; + compatible = "cdns,zynqmp-gem\0cdns,gem"; status = "okay"; - interrupt-parent = <0x4>; - interrupts = <0x0 0x3f 0x4 0x0 0x3f 0x4>; - reg = <0x0 0xff0e0000 0x0 0x1000>; - clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; - #address-cells = <0x1>; - #size-cells = <0x0>; - #stream-id-cells = <0x1>; - iommus = <0xa 0x877>; - power-domains = <0x12>; - clocks = <0x3 0x1f 0x3 0x6b 0x3 0x30 0x3 0x34 0x3 0x2c>; - phy-handle = <0x13>; + interrupt-parent = <0x04>; + interrupts = <0x00 0x3f 0x04 0x00 0x3f 0x04>; + reg = <0x00 0xff0e0000 0x00 0x1000>; + clock-names = "pclk\0hclk\0tx_clk\0rx_clk\0tsu_clk"; + #address-cells = <0x01>; + #size-cells = <0x00>; + #stream-id-cells = <0x01>; + iommus = <0x0e 0x877>; + power-domains = <0x0c 0x20>; + clocks = <0x03 0x1f 0x03 0x6b 0x03 0x30 0x03 0x34 0x03 0x2c>; + phy-handle = <0x0f>; phy-mode = "rgmii-id"; pinctrl-names = "default"; - pinctrl-0 = <0x14>; + pinctrl-0 = <0x10>; + phandle = <0x75>; - phy@c { - reg = <0xc>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,rxctrl-strap-worka; - linux,phandle = <0x13>; - phandle = <0x13>; + ethernet-phy@c { + reg = <0x0c>; + ti,rx-internal-delay = <0x08>; + ti,tx-internal-delay = <0x0a>; + ti,fifo-depth = <0x01>; + ti,dp83867-rxctrl-strap-quirk; + phandle = <0x0f>; }; }; gpio@ff0a0000 { compatible = "xlnx,zynqmp-gpio-1.0"; status = "okay"; - #gpio-cells = <0x2>; - interrupt-parent = <0x4>; - interrupts = <0x0 0x10 0x4>; - interrupt-controller; - #interrupt-cells = <0x2>; - reg = <0x0 0xff0a0000 0x0 0x1000>; + #gpio-cells = <0x02>; gpio-controller; - power-domains = <0x15>; - clocks = <0x3 0x1f>; + interrupt-parent = <0x04>; + interrupts = <0x00 0x10 0x04>; + interrupt-controller; + #interrupt-cells = <0x02>; + reg = <0x00 0xff0a0000 0x00 0x1000>; + power-domains = <0x0c 0x2e>; + clocks = <0x03 0x1f>; pinctrl-names = "default"; - pinctrl-0 = <0x16>; - linux,phandle = <0x1a>; - phandle = <0x1a>; + pinctrl-0 = <0x11>; + phandle = <0x14>; }; i2c@ff020000 { - compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; + compatible = "cdns,i2c-r1p14"; status = "okay"; - interrupt-parent = <0x4>; - interrupts = <0x0 0x11 0x4>; - reg = <0x0 0xff020000 0x0 0x1000>; - #address-cells = <0x1>; - #size-cells = <0x0>; - power-domains = <0x17>; - clocks = <0x3 0x3d>; + interrupt-parent = <0x04>; + interrupts = <0x00 0x11 0x04>; + reg = <0x00 0xff020000 0x00 0x1000>; + #address-cells = <0x01>; + #size-cells = <0x00>; + power-domains = <0x0c 0x25>; + clocks = <0x03 0x3d>; clock-frequency = <0x61a80>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <0x18>; - pinctrl-1 = <0x19>; - scl-gpios = <0x1a 0xe 0x0>; - sda-gpios = <0x1a 0xf 0x0>; + pinctrl-names = "default\0gpio"; + pinctrl-0 = <0x12>; + pinctrl-1 = <0x13>; + scl-gpios = <0x14 0x0e 0x00>; + sda-gpios = <0x14 0x0f 0x00>; + phandle = <0x76>; gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; - #gpio-cells = <0x2>; + #gpio-cells = <0x02>; + gpio-line-names = "PS_GTR_LAN_SEL0\0PS_GTR_LAN_SEL1\0PS_GTR_LAN_SEL2\0PS_GTR_LAN_SEL3\0PCI_CLK_DIR_SEL\0IIC_MUX_RESET_B\0GEM3_EXP_RESET_B\0\0\0\0\0\0\0\0\0"; + phandle = <0x77>; - gtr_sel0 { + gtr-sel0-hog { gpio-hog; - gpios = <0x0 0x0>; + gpios = <0x00 0x00>; output-low; line-name = "sel0"; }; - gtr_sel1 { + gtr-sel1-hog { gpio-hog; - gpios = <0x1 0x0>; + gpios = <0x01 0x00>; output-high; line-name = "sel1"; }; - gtr_sel2 { + gtr-sel2-hog { gpio-hog; - gpios = <0x2 0x0>; + gpios = <0x02 0x00>; output-high; line-name = "sel2"; }; - gtr_sel3 { + gtr-sel3-hog { gpio-hog; - gpios = <0x3 0x0>; + gpios = <0x03 0x00>; output-high; line-name = "sel3"; }; @@ -1237,148 +1093,204 @@ compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; - #gpio-cells = <0x2>; + #gpio-cells = <0x02>; + gpio-line-names = "VCCPSPLL_EN\0MGTRAVCC_EN\0MGTRAVTT_EN\0VCCPSDDRPLL_EN\0MIO26_PMU_INPUT_LS\0PL_PMBUS_ALERT\0PS_PMBUS_ALERT\0MAXIM_PMBUS_ALERT\0PL_DDR4_VTERM_EN\0PL_DDR4_VPP_2V5_EN\0PS_DIMM_VDDQ_TO_PSVCCO_ON\0PS_DIMM_SUSPEND_EN\0PS_DDR4_VTERM_EN\0PS_DDR4_VPP_2V5_EN\0\0"; + phandle = <0x78>; }; i2c-mux@75 { compatible = "nxp,pca9544"; - #address-cells = <0x1>; - #size-cells = <0x0>; + #address-cells = <0x01>; + #size-cells = <0x00>; reg = <0x75>; i2c@0 { - #address-cells = <0x1>; - #size-cells = <0x0>; - reg = <0x0>; + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0x00>; ina226@40 { compatible = "ti,ina226"; + #io-channel-cells = <0x01>; + label = "ina226-u76"; reg = <0x40>; shunt-resistor = <0x1388>; + phandle = <0x2a>; }; ina226@41 { compatible = "ti,ina226"; + #io-channel-cells = <0x01>; + label = "ina226-u77"; reg = <0x41>; shunt-resistor = <0x1388>; + phandle = <0x2b>; }; ina226@42 { compatible = "ti,ina226"; + #io-channel-cells = <0x01>; + label = "ina226-u78"; reg = <0x42>; shunt-resistor = <0x1388>; + phandle = <0x2c>; }; ina226@43 { compatible = "ti,ina226"; + #io-channel-cells = <0x01>; + label = "ina226-u87"; reg = <0x43>; shunt-resistor = <0x1388>; + phandle = <0x2d>; }; ina226@44 { compatible = "ti,ina226"; + #io-channel-cells = <0x01>; + label = "ina226-u85"; reg = <0x44>; shunt-resistor = <0x1388>; + phandle = <0x2e>; }; ina226@45 { compatible = "ti,ina226"; + #io-channel-cells = <0x01>; + label = "ina226-u86"; reg = <0x45>; shunt-resistor = <0x1388>; + phandle = <0x2f>; }; ina226@46 { compatible = "ti,ina226"; + #io-channel-cells = <0x01>; + label = "ina226-u93"; reg = <0x46>; shunt-resistor = <0x1388>; + phandle = <0x30>; }; ina226@47 { compatible = "ti,ina226"; + #io-channel-cells = <0x01>; + label = "ina226-u88"; reg = <0x47>; shunt-resistor = <0x1388>; + phandle = <0x31>; }; ina226@4a { compatible = "ti,ina226"; + #io-channel-cells = <0x01>; + label = "ina226-u15"; reg = <0x4a>; shunt-resistor = <0x1388>; + phandle = <0x32>; }; ina226@4b { compatible = "ti,ina226"; + #io-channel-cells = <0x01>; + label = "ina226-u92"; reg = <0x4b>; shunt-resistor = <0x1388>; + phandle = <0x33>; }; }; i2c@1 { - #address-cells = <0x1>; - #size-cells = <0x0>; - reg = <0x1>; + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0x01>; ina226@40 { compatible = "ti,ina226"; + #io-channel-cells = <0x01>; + label = "ina226-u79"; reg = <0x40>; shunt-resistor = <0x7d0>; + phandle = <0x34>; }; ina226@41 { compatible = "ti,ina226"; + #io-channel-cells = <0x01>; + label = "ina226-u81"; reg = <0x41>; shunt-resistor = <0x1388>; + phandle = <0x35>; }; ina226@42 { compatible = "ti,ina226"; + #io-channel-cells = <0x01>; + label = "ina226-u80"; reg = <0x42>; shunt-resistor = <0x1388>; + phandle = <0x36>; }; ina226@43 { compatible = "ti,ina226"; + #io-channel-cells = <0x01>; + label = "ina226-u84"; reg = <0x43>; shunt-resistor = <0x1388>; + phandle = <0x37>; }; ina226@44 { compatible = "ti,ina226"; + #io-channel-cells = <0x01>; + label = "ina226-u16"; reg = <0x44>; shunt-resistor = <0x1388>; + phandle = <0x38>; }; ina226@45 { compatible = "ti,ina226"; + #io-channel-cells = <0x01>; + label = "ina226-u65"; reg = <0x45>; shunt-resistor = <0x1388>; + phandle = <0x39>; }; ina226@46 { compatible = "ti,ina226"; + #io-channel-cells = <0x01>; + label = "ina226-u74"; reg = <0x46>; shunt-resistor = <0x1388>; + phandle = <0x3a>; }; ina226@47 { compatible = "ti,ina226"; + #io-channel-cells = <0x01>; + label = "ina226-u75"; reg = <0x47>; shunt-resistor = <0x1388>; + phandle = <0x3b>; }; }; i2c@2 { - #address-cells = <0x1>; - #size-cells = <0x0>; - reg = <0x2>; + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0x02>; max15301@a { compatible = "maxim,max15301"; - reg = <0xa>; + reg = <0x0a>; }; max15303@b { compatible = "maxim,max15303"; - reg = <0xb>; + reg = <0x0b>; }; max15303@10 { @@ -1445,122 +1357,198 @@ }; i2c@ff030000 { - compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; + compatible = "cdns,i2c-r1p14"; status = "okay"; - interrupt-parent = <0x4>; - interrupts = <0x0 0x12 0x4>; - reg = <0x0 0xff030000 0x0 0x1000>; - #address-cells = <0x1>; - #size-cells = <0x0>; - power-domains = <0x1b>; - clocks = <0x3 0x3e>; + interrupt-parent = <0x04>; + interrupts = <0x00 0x12 0x04>; + reg = <0x00 0xff030000 0x00 0x1000>; + #address-cells = <0x01>; + #size-cells = <0x00>; + power-domains = <0x0c 0x26>; + clocks = <0x03 0x3e>; clock-frequency = <0x61a80>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <0x1c>; - pinctrl-1 = <0x1d>; - scl-gpios = <0x1a 0x10 0x0>; - sda-gpios = <0x1a 0x11 0x0>; + pinctrl-names = "default\0gpio"; + pinctrl-0 = <0x15>; + pinctrl-1 = <0x16>; + scl-gpios = <0x14 0x10 0x00>; + sda-gpios = <0x14 0x11 0x00>; + phandle = <0x79>; i2c-mux@74 { compatible = "nxp,pca9548"; - #address-cells = <0x1>; - #size-cells = <0x0>; + #address-cells = <0x01>; + #size-cells = <0x00>; reg = <0x74>; i2c@0 { - #address-cells = <0x1>; - #size-cells = <0x0>; - reg = <0x0>; + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0x00>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; - #address-cells = <0x1>; - #size-cells = <0x1>; + #address-cells = <0x01>; + #size-cells = <0x01>; + phandle = <0x7a>; board-sn@0 { - reg = <0x0 0x14>; + reg = <0x00 0x14>; + phandle = <0x7b>; }; eth-mac@20 { - reg = <0x20 0x6>; + reg = <0x20 0x06>; + phandle = <0x7c>; }; board-name@d0 { - reg = <0xd0 0x6>; + reg = <0xd0 0x06>; + phandle = <0x7d>; }; board-revision@e0 { - reg = <0xe0 0x3>; + reg = <0xe0 0x03>; + phandle = <0x7e>; }; }; }; i2c@1 { - #address-cells = <0x1>; - #size-cells = <0x0>; - reg = <0x1>; + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0x01>; clock-generator@36 { compatible = "silabs,si5341"; reg = <0x36>; + #clock-cells = <0x02>; + #address-cells = <0x01>; + #size-cells = <0x00>; + clocks = <0x17>; + clock-names = "xtal"; + clock-output-names = "si5341"; + phandle = <0x1b>; + + out@0 { + reg = <0x00>; + always-on; + phandle = <0x7f>; + }; + + out@2 { + reg = <0x02>; + always-on; + phandle = <0x80>; + }; + + out@3 { + reg = <0x03>; + always-on; + phandle = <0x81>; + }; + + out@4 { + reg = <0x04>; + always-on; + phandle = <0x82>; + }; + + out@5 { + reg = <0x05>; + always-on; + phandle = <0x83>; + }; + + out@6 { + reg = <0x06>; + always-on; + phandle = <0x84>; + }; + + out@7 { + reg = <0x07>; + always-on; + phandle = <0x85>; + }; + + out@9 { + reg = <0x09>; + always-on; + phandle = <0x86>; + }; }; }; i2c@2 { - #address-cells = <0x1>; - #size-cells = <0x0>; - reg = <0x2>; + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0x02>; clock-generator@5d { - #clock-cells = <0x0>; + #clock-cells = <0x00>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <0x32>; factory-fout = <0x11e1a300>; clock-frequency = <0x11e1a300>; clock-output-names = "si570_user"; + phandle = <0x87>; }; }; i2c@3 { - #address-cells = <0x1>; - #size-cells = <0x0>; - reg = <0x3>; + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0x03>; clock-generator@5d { - #clock-cells = <0x0>; + #clock-cells = <0x00>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <0x32>; factory-fout = <0x9502f90>; clock-frequency = <0x8d9ee20>; clock-output-names = "si570_mgt"; + phandle = <0x88>; }; }; i2c@4 { - #address-cells = <0x1>; - #size-cells = <0x0>; - reg = <0x4>; + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0x04>; clock-generator@69 { compatible = "silabs,si5328"; reg = <0x69>; + #address-cells = <0x01>; + #size-cells = <0x00>; + #clock-cells = <0x01>; + clocks = <0x18>; + clock-names = "xtal"; + clock-output-names = "si5328"; + phandle = <0x89>; + + clk0@0 { + reg = <0x00>; + clock-frequency = <0x19bfcc0>; + phandle = <0x8a>; + }; }; }; }; i2c-mux@75 { compatible = "nxp,pca9548"; - #address-cells = <0x1>; - #size-cells = <0x0>; + #address-cells = <0x01>; + #size-cells = <0x00>; reg = <0x75>; i2c@0 { - #address-cells = <0x1>; - #size-cells = <0x0>; - reg = <0x0>; + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0x00>; ad7291@2f { compatible = "adi,ad7291"; @@ -1574,104 +1562,166 @@ }; i2c@1 { - #address-cells = <0x1>; - #size-cells = <0x0>; - reg = <0x1>; + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0x01>; }; i2c@2 { - #address-cells = <0x1>; - #size-cells = <0x0>; - reg = <0x2>; + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0x02>; }; i2c@3 { - #address-cells = <0x1>; - #size-cells = <0x0>; - reg = <0x3>; + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0x03>; }; i2c@4 { - #address-cells = <0x1>; - #size-cells = <0x0>; - reg = <0x4>; + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0x04>; }; i2c@5 { - #address-cells = <0x1>; - #size-cells = <0x0>; - reg = <0x5>; + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0x05>; }; i2c@6 { - #address-cells = <0x1>; - #size-cells = <0x0>; - reg = <0x6>; + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0x06>; }; i2c@7 { - #address-cells = <0x1>; - #size-cells = <0x0>; - reg = <0x7>; + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0x07>; }; }; }; memory-controller@ff960000 { compatible = "xlnx,zynqmp-ocmc-1.0"; - reg = <0x0 0xff960000 0x0 0x1000>; - interrupt-parent = <0x4>; - interrupts = <0x0 0xa 0x4>; + reg = <0x00 0xff960000 0x00 0x1000>; + interrupt-parent = <0x04>; + interrupts = <0x00 0x0a 0x04>; + phandle = <0x8b>; }; perf-monitor@ffa00000 { compatible = "xlnx,axi-perf-monitor"; - reg = <0x0 0xffa00000 0x0 0x10000>; - interrupts = <0x0 0x19 0x4>; - interrupt-parent = <0x4>; - xlnx,enable-profile = <0x0>; - xlnx,enable-trace = <0x0>; - xlnx,num-monitor-slots = <0x4>; - xlnx,enable-event-count = <0x1>; - xlnx,enable-event-log = <0x1>; - xlnx,have-sampled-metric-cnt = <0x1>; - xlnx,num-of-counters = <0x8>; + reg = <0x00 0xffa00000 0x00 0x10000>; + interrupts = <0x00 0x19 0x04>; + interrupt-parent = <0x04>; + xlnx,enable-profile = <0x00>; + xlnx,enable-trace = <0x00>; + xlnx,num-monitor-slots = <0x01>; + xlnx,enable-event-count = <0x01>; + xlnx,enable-event-log = <0x01>; + xlnx,have-sampled-metric-cnt = <0x01>; + xlnx,num-of-counters = <0x08>; xlnx,metric-count-width = <0x20>; xlnx,metrics-sample-count-width = <0x20>; xlnx,global-count-width = <0x20>; - xlnx,metric-count-scale = <0x1>; - clocks = <0x3 0x1f>; + xlnx,metric-count-scale = <0x01>; + clocks = <0x03 0x1f>; + phandle = <0x8c>; + }; + + perf-monitor@fd0b0000 { + compatible = "xlnx,axi-perf-monitor"; + reg = <0x00 0xfd0b0000 0x00 0x10000>; + interrupts = <0x00 0x7b 0x04>; + interrupt-parent = <0x04>; + xlnx,enable-profile = <0x00>; + xlnx,enable-trace = <0x00>; + xlnx,num-monitor-slots = <0x06>; + xlnx,enable-event-count = <0x01>; + xlnx,enable-event-log = <0x00>; + xlnx,have-sampled-metric-cnt = <0x01>; + xlnx,num-of-counters = <0x0a>; + xlnx,metric-count-width = <0x20>; + xlnx,metrics-sample-count-width = <0x20>; + xlnx,global-count-width = <0x20>; + xlnx,metric-count-scale = <0x01>; + clocks = <0x03 0x1c>; + phandle = <0x8d>; + }; + + perf-monitor@fd490000 { + compatible = "xlnx,axi-perf-monitor"; + reg = <0x00 0xfd490000 0x00 0x10000>; + interrupts = <0x00 0x7b 0x04>; + interrupt-parent = <0x04>; + xlnx,enable-profile = <0x00>; + xlnx,enable-trace = <0x00>; + xlnx,num-monitor-slots = <0x01>; + xlnx,enable-event-count = <0x01>; + xlnx,enable-event-log = <0x00>; + xlnx,have-sampled-metric-cnt = <0x01>; + xlnx,num-of-counters = <0x08>; + xlnx,metric-count-width = <0x20>; + xlnx,metrics-sample-count-width = <0x20>; + xlnx,global-count-width = <0x20>; + xlnx,metric-count-scale = <0x01>; + clocks = <0x03 0x1c>; + phandle = <0x8e>; + }; + + perf-monitor@ffa10000 { + compatible = "xlnx,axi-perf-monitor"; + reg = <0x00 0xffa10000 0x00 0x10000>; + interrupts = <0x00 0x19 0x04>; + interrupt-parent = <0x04>; + xlnx,enable-profile = <0x00>; + xlnx,enable-trace = <0x00>; + xlnx,num-monitor-slots = <0x01>; + xlnx,enable-event-count = <0x01>; + xlnx,enable-event-log = <0x01>; + xlnx,have-sampled-metric-cnt = <0x01>; + xlnx,num-of-counters = <0x08>; + xlnx,metric-count-width = <0x20>; + xlnx,metrics-sample-count-width = <0x20>; + xlnx,global-count-width = <0x20>; + xlnx,metric-count-scale = <0x01>; + clocks = <0x03 0x1f>; + phandle = <0x8f>; }; pcie@fd0e0000 { compatible = "xlnx,nwl-pcie-2.11"; status = "okay"; - #address-cells = <0x3>; - #size-cells = <0x2>; - #interrupt-cells = <0x1>; + #address-cells = <0x03>; + #size-cells = <0x02>; + #interrupt-cells = <0x01>; msi-controller; device_type = "pci"; - interrupt-parent = <0x4>; - interrupts = <0x0 0x76 0x4 0x0 0x75 0x4 0x0 0x74 0x4 0x0 0x73 0x4 0x0 0x72 0x4>; - interrupt-names = "misc", "dummy", "intx", "msi1", "msi0"; - msi-parent = <0x1e>; - reg = <0x0 0xfd0e0000 0x0 0x1000 0x0 0xfd480000 0x0 0x1000 0x80 0x0 0x0 0x1000000>; - reg-names = "breg", "pcireg", "cfg"; - ranges = <0x2000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000 0x43000000 0x6 0x0 0x6 0x0 0x2 0x0>; - bus-range = <0x0 0xff>; - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0x0 0x0 0x0 0x1 0x1f 0x1 0x0 0x0 0x0 0x2 0x1f 0x2 0x0 0x0 0x0 0x3 0x1f 0x3 0x0 0x0 0x0 0x4 0x1f 0x4>; - power-domains = <0x20>; - clocks = <0x3 0x17>; - linux,phandle = <0x1e>; - phandle = <0x1e>; + interrupt-parent = <0x04>; + interrupts = <0x00 0x76 0x04 0x00 0x75 0x04 0x00 0x74 0x04 0x00 0x73 0x04 0x00 0x72 0x04>; + interrupt-names = "misc\0dummy\0intx\0msi1\0msi0"; + msi-parent = <0x19>; + reg = <0x00 0xfd0e0000 0x00 0x1000 0x00 0xfd480000 0x00 0x1000 0x80 0x00 0x00 0x1000000>; + reg-names = "breg\0pcireg\0cfg"; + ranges = <0x2000000 0x00 0xe0000000 0x00 0xe0000000 0x00 0x10000000 0x43000000 0x06 0x00 0x06 0x00 0x02 0x00>; + bus-range = <0x00 0xff>; + interrupt-map-mask = <0x00 0x00 0x00 0x07>; + interrupt-map = <0x00 0x00 0x00 0x01 0x1a 0x01 0x00 0x00 0x00 0x02 0x1a 0x02 0x00 0x00 0x00 0x03 0x1a 0x03 0x00 0x00 0x00 0x04 0x1a 0x04>; + #stream-id-cells = <0x01>; + iommus = <0x0e 0x4d0>; + power-domains = <0x0c 0x3b>; + clocks = <0x03 0x17>; + phandle = <0x19>; legacy-interrupt-controller { interrupt-controller; - #address-cells = <0x0>; - #interrupt-cells = <0x1>; - linux,phandle = <0x1f>; - phandle = <0x1f>; + #address-cells = <0x00>; + #interrupt-cells = <0x01>; + phandle = <0x1a>; }; }; @@ -1679,102 +1729,83 @@ u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-qspi-1.0"; status = "okay"; - clock-names = "ref_clk", "pclk"; - interrupts = <0x0 0xf 0x4>; - interrupt-parent = <0x4>; - num-cs = <0x1>; - reg = <0x0 0xff0f0000 0x0 0x1000 0x0 0xc0000000 0x0 0x8000000>; - #address-cells = <0x1>; - #size-cells = <0x0>; - #stream-id-cells = <0x1>; - iommus = <0xa 0x873>; - power-domains = <0x21>; - clocks = <0x3 0x35 0x3 0x1f>; - is-dual = <0x1>; + clock-names = "ref_clk\0pclk"; + interrupts = <0x00 0x0f 0x04>; + interrupt-parent = <0x04>; + num-cs = <0x01>; + reg = <0x00 0xff0f0000 0x00 0x1000 0x00 0xc0000000 0x00 0x8000000>; + #address-cells = <0x01>; + #size-cells = <0x00>; + #stream-id-cells = <0x01>; + iommus = <0x0e 0x873>; + power-domains = <0x0c 0x2d>; + clocks = <0x03 0x35 0x03 0x1f>; + is-dual = <0x01>; + phandle = <0x90>; flash@0 { - compatible = "m25p80", "spi-flash"; - #address-cells = <0x1>; - #size-cells = <0x1>; - reg = <0x0>; - spi-tx-bus-width = <0x1>; - spi-rx-bus-width = <0x4>; + compatible = "m25p80\0jedec,spi-nor"; + #address-cells = <0x01>; + #size-cells = <0x01>; + reg = <0x00>; + spi-tx-bus-width = <0x01>; + spi-rx-bus-width = <0x04>; spi-max-frequency = <0x66ff300>; - partition@qspi-fsbl-uboot { + partition@0 { label = "qspi-fsbl-uboot"; - reg = <0x0 0x100000>; + reg = <0x00 0x100000>; }; - partition@qspi-linux { + partition@100000 { label = "qspi-linux"; reg = <0x100000 0x500000>; }; - partition@qspi-device-tree { + partition@600000 { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; - partition@qspi-rootfs { + partition@620000 { label = "qspi-rootfs"; reg = <0x620000 0x5e0000>; }; }; }; + phy@fd400000 { + compatible = "xlnx,zynqmp-psgtr-v1.1"; + status = "okay"; + reg = <0x00 0xfd400000 0x00 0x40000 0x00 0xfd3d0000 0x00 0x1000>; + reg-names = "serdes\0siou"; + #phy-cells = <0x04>; + clocks = <0x1b 0x00 0x05 0x1b 0x00 0x03 0x1b 0x00 0x02 0x1b 0x00 0x00>; + clock-names = "ref0\0ref1\0ref2\0ref3"; + phandle = <0x1d>; + }; + rtc@ffa60000 { compatible = "xlnx,zynqmp-rtc"; status = "okay"; - reg = <0x0 0xffa60000 0x0 0x100>; - interrupt-parent = <0x4>; - interrupts = <0x0 0x1a 0x4 0x0 0x1b 0x4>; - interrupt-names = "alarm", "sec"; - calibration = <0x8000>; - }; - - zynqmp_phy@fd400000 { - compatible = "xlnx,zynqmp-psgtr-v1.1"; - status = "okay"; - reg = <0x0 0xfd400000 0x0 0x40000 0x0 0xfd3d0000 0x0 0x1000>; - reg-names = "serdes", "siou"; - nvmem-cells = <0x22>; - nvmem-cell-names = "soc_revision"; - resets = <0x23 0x10 0x23 0x3b 0x23 0x3c 0x23 0x3d 0x23 0x3e 0x23 0x3f 0x23 0x40 0x23 0x3 0x23 0x1d 0x23 0x1e 0x23 0x1f 0x23 0x20>; - reset-names = "sata_rst", "usb0_crst", "usb1_crst", "usb0_hibrst", "usb1_hibrst", "usb0_apbrst", "usb1_apbrst", "dp_rst", "gem0_rst", "gem1_rst", "gem2_rst", "gem3_rst"; - - lane0 { - #phy-cells = <0x4>; - }; - - lane1 { - #phy-cells = <0x4>; - linux,phandle = <0x3a>; - phandle = <0x3a>; - }; - - lane2 { - #phy-cells = <0x4>; - linux,phandle = <0x36>; - phandle = <0x36>; - }; - - lane3 { - #phy-cells = <0x4>; - linux,phandle = <0x25>; - phandle = <0x25>; - }; + reg = <0x00 0xffa60000 0x00 0x100>; + interrupt-parent = <0x04>; + interrupts = <0x00 0x1a 0x04 0x00 0x1b 0x04>; + interrupt-names = "alarm\0sec"; + calibration = <0x7fff>; + phandle = <0x91>; }; ahci@fd0c0000 { compatible = "ceva,ahci-1v84"; status = "okay"; - reg = <0x0 0xfd0c0000 0x0 0x2000>; - interrupt-parent = <0x4>; - interrupts = <0x0 0x85 0x4>; - power-domains = <0x24>; - #stream-id-cells = <0x4>; - clocks = <0x3 0x16>; + reg = <0x00 0xfd0c0000 0x00 0x2000>; + interrupt-parent = <0x04>; + interrupts = <0x00 0x85 0x04>; + power-domains = <0x0c 0x1c>; + resets = <0x1c 0x10>; + #stream-id-cells = <0x04>; + clocks = <0x03 0x16>; ceva,p0-cominit-params = <0x18401828>; ceva,p0-comwake-params = <0x614080e>; ceva,p0-burst-params = <0x13084a06>; @@ -1784,277 +1815,294 @@ ceva,p1-burst-params = <0x13084a06>; ceva,p1-retry-params = <0x96a43ffc>; phy-names = "sata-phy"; - phys = <0x25 0x1 0x1 0x1 0x7735940>; + phys = <0x1d 0x03 0x01 0x01 0x01>; + phandle = <0x92>; }; mmc@ff160000 { u-boot,dm-pre-reloc; - compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; + compatible = "xlnx,zynqmp-8.9a\0arasan,sdhci-8.9a"; status = "disabled"; - interrupt-parent = <0x4>; - interrupts = <0x0 0x30 0x4>; - reg = <0x0 0xff160000 0x0 0x1000>; - clock-names = "clk_xin", "clk_ahb"; - xlnx,device_id = <0x0>; - #stream-id-cells = <0x1>; - iommus = <0xa 0x870>; - power-domains = <0x26>; - nvmem-cells = <0x22>; + interrupt-parent = <0x04>; + interrupts = <0x00 0x30 0x04>; + reg = <0x00 0xff160000 0x00 0x1000>; + clock-names = "clk_xin\0clk_ahb"; + xlnx,device_id = <0x00>; + #stream-id-cells = <0x01>; + iommus = <0x0e 0x870>; + nvmem-cells = <0x1e>; nvmem-cell-names = "soc_revision"; - broken-mmc-highspeed; - clocks = <0x3 0x36 0x3 0x1f>; + #clock-cells = <0x01>; + clock-output-names = "clk_out_sd0\0clk_in_sd0"; + power-domains = <0x0c 0x27>; + clocks = <0x03 0x36 0x03 0x1f>; + phandle = <0x93>; }; mmc@ff170000 { u-boot,dm-pre-reloc; - compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; + compatible = "xlnx,zynqmp-8.9a\0arasan,sdhci-8.9a"; status = "okay"; - interrupt-parent = <0x4>; - interrupts = <0x0 0x31 0x4>; - reg = <0x0 0xff170000 0x0 0x1000>; - clock-names = "clk_xin", "clk_ahb"; - xlnx,device_id = <0x1>; - #stream-id-cells = <0x1>; - iommus = <0xa 0x871>; - power-domains = <0x27>; - nvmem-cells = <0x22>; + interrupt-parent = <0x04>; + interrupts = <0x00 0x31 0x04>; + reg = <0x00 0xff170000 0x00 0x1000>; + clock-names = "clk_xin\0clk_ahb"; + xlnx,device_id = <0x01>; + #stream-id-cells = <0x01>; + iommus = <0x0e 0x871>; + nvmem-cells = <0x1e>; nvmem-cell-names = "soc_revision"; - broken-mmc-highspeed; - clocks = <0x3 0x37 0x3 0x1f>; - pinctrl-names = "default"; - pinctrl-0 = <0x28>; + #clock-cells = <0x01>; + clock-output-names = "clk_out_sd1\0clk_in_sd1"; + power-domains = <0x0c 0x28>; + clocks = <0x03 0x37 0x03 0x1f>; no-1-8-v; - xlnx,mio_bank = <0x1>; + pinctrl-names = "default"; + pinctrl-0 = <0x1f>; + xlnx,mio-bank = <0x01>; + phandle = <0x94>; }; spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "okay"; - interrupt-parent = <0x4>; - interrupts = <0x0 0x13 0x4>; - reg = <0x0 0xff040000 0x0 0x1000>; - clock-names = "ref_clk", "pclk"; - #address-cells = <0x1>; - #size-cells = <0x0>; - power-domains = <0x29>; - clocks = <0x3 0x3a 0x3 0x1f>; + interrupt-parent = <0x04>; + interrupts = <0x00 0x13 0x04>; + reg = <0x00 0xff040000 0x00 0x1000>; + clock-names = "ref_clk\0pclk"; + #address-cells = <0x01>; + #size-cells = <0x00>; + power-domains = <0x0c 0x23>; + clocks = <0x03 0x3a 0x03 0x1f>; + phandle = <0x95>; ad9361-phy@0 { compatible = "adi,ad9361"; - reg = <0x0>; + reg = <0x00>; spi-cpha; spi-max-frequency = <0x989680>; - clocks = <0x2a 0x0>; + clocks = <0x20 0x00>; clock-names = "ad9361_ext_refclk"; - clock-output-names = "rx_sampl_clk", "tx_sampl_clk"; - #clock-cells = <0x1>; - adi,digital-interface-tune-skip-mode = <0x0>; + clock-output-names = "rx_sampl_clk\0tx_sampl_clk"; + #clock-cells = <0x01>; + adi,digital-interface-tune-skip-mode = <0x00>; adi,pp-tx-swap-enable; adi,pp-rx-swap-enable; adi,rx-frame-pulse-mode-enable; adi,lvds-mode-enable; adi,lvds-bias-mV = <0x96>; adi,lvds-rx-onchip-termination-enable; - adi,rx-data-delay = <0x4>; - adi,tx-fb-clock-delay = <0x7>; - adi,dcxo-coarse-and-fine-tune = <0x8 0x1720>; + adi,rx-data-delay = <0x04>; + adi,tx-fb-clock-delay = <0x07>; + adi,dcxo-coarse-and-fine-tune = <0x08 0x1720>; adi,2rx-2tx-mode-enable; adi,frequency-division-duplex-mode-enable; - adi,rx-rf-port-input-select = <0x0>; - adi,tx-rf-port-input-select = <0x0>; + adi,rx-rf-port-input-select = <0x00>; + adi,tx-rf-port-input-select = <0x00>; adi,tx-attenuation-mdB = <0x2710>; adi,tx-lo-powerdown-managed-enable; adi,rf-rx-bandwidth-hz = <0x112a880>; adi,rf-tx-bandwidth-hz = <0x112a880>; - adi,rx-synthesizer-frequency-hz = <0x0 0x8f0d1800>; - adi,tx-synthesizer-frequency-hz = <0x0 0x92080880>; + adi,rx-synthesizer-frequency-hz = <0x00 0x8f0d1800>; + adi,tx-synthesizer-frequency-hz = <0x00 0x92080880>; adi,rx-path-clock-frequencies = <0x3a980000 0xea60000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>; adi,tx-path-clock-frequencies = <0x3a980000 0x7530000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>; - adi,gc-rx1-mode = <0x2>; - adi,gc-rx2-mode = <0x2>; - adi,gc-adc-ovr-sample-size = <0x4>; + adi,gc-rx1-mode = <0x02>; + adi,gc-rx2-mode = <0x02>; + adi,gc-adc-ovr-sample-size = <0x04>; adi,gc-adc-small-overload-thresh = <0x2f>; adi,gc-adc-large-overload-thresh = <0x3a>; adi,gc-lmt-overload-high-thresh = <0x320>; adi,gc-lmt-overload-low-thresh = <0x2c0>; adi,gc-dec-pow-measurement-duration = <0x2000>; adi,gc-low-power-thresh = <0x18>; - adi,mgc-inc-gain-step = <0x2>; - adi,mgc-dec-gain-step = <0x2>; - adi,mgc-split-table-ctrl-inp-gain-mode = <0x0>; - adi,agc-attack-delay-extra-margin-us = <0x1>; - adi,agc-outer-thresh-high = <0x5>; - adi,agc-outer-thresh-high-dec-steps = <0x2>; - adi,agc-inner-thresh-high = <0xa>; - adi,agc-inner-thresh-high-dec-steps = <0x1>; - adi,agc-inner-thresh-low = <0xc>; - adi,agc-inner-thresh-low-inc-steps = <0x1>; + adi,mgc-inc-gain-step = <0x02>; + adi,mgc-dec-gain-step = <0x02>; + adi,mgc-split-table-ctrl-inp-gain-mode = <0x00>; + adi,agc-attack-delay-extra-margin-us = <0x01>; + adi,agc-outer-thresh-high = <0x05>; + adi,agc-outer-thresh-high-dec-steps = <0x02>; + adi,agc-inner-thresh-high = <0x0a>; + adi,agc-inner-thresh-high-dec-steps = <0x01>; + adi,agc-inner-thresh-low = <0x0c>; + adi,agc-inner-thresh-low-inc-steps = <0x01>; adi,agc-outer-thresh-low = <0x12>; - adi,agc-outer-thresh-low-inc-steps = <0x2>; - adi,agc-adc-small-overload-exceed-counter = <0xa>; - adi,agc-adc-large-overload-exceed-counter = <0xa>; - adi,agc-adc-large-overload-inc-steps = <0x2>; - adi,agc-lmt-overload-large-exceed-counter = <0xa>; - adi,agc-lmt-overload-small-exceed-counter = <0xa>; - adi,agc-lmt-overload-large-inc-steps = <0x2>; + adi,agc-outer-thresh-low-inc-steps = <0x02>; + adi,agc-adc-small-overload-exceed-counter = <0x0a>; + adi,agc-adc-large-overload-exceed-counter = <0x0a>; + adi,agc-adc-large-overload-inc-steps = <0x02>; + adi,agc-lmt-overload-large-exceed-counter = <0x0a>; + adi,agc-lmt-overload-small-exceed-counter = <0x0a>; + adi,agc-lmt-overload-large-inc-steps = <0x02>; adi,agc-gain-update-interval-us = <0x3e8>; adi,fagc-dec-pow-measurement-duration = <0x40>; - adi,fagc-lp-thresh-increment-steps = <0x1>; - adi,fagc-lp-thresh-increment-time = <0x5>; - adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <0x8>; - adi,fagc-final-overrange-count = <0x3>; - adi,fagc-gain-index-type-after-exit-rx-mode = <0x0>; - adi,fagc-lmt-final-settling-steps = <0x1>; - adi,fagc-lock-level = <0xa>; - adi,fagc-lock-level-gain-increase-upper-limit = <0x5>; + adi,fagc-lp-thresh-increment-steps = <0x01>; + adi,fagc-lp-thresh-increment-time = <0x05>; + adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <0x08>; + adi,fagc-final-overrange-count = <0x03>; + adi,fagc-gain-index-type-after-exit-rx-mode = <0x00>; + adi,fagc-lmt-final-settling-steps = <0x01>; + adi,fagc-lock-level = <0x0a>; + adi,fagc-lock-level-gain-increase-upper-limit = <0x05>; adi,fagc-lock-level-lmt-gain-increase-enable; - adi,fagc-lpf-final-settling-steps = <0x1>; - adi,fagc-optimized-gain-offset = <0x5>; + adi,fagc-lpf-final-settling-steps = <0x01>; + adi,fagc-optimized-gain-offset = <0x05>; adi,fagc-power-measurement-duration-in-state5 = <0x40>; adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable; - adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <0xa>; + adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <0x0a>; adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable; - adi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0x0>; + adi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0x00>; adi,fagc-rst-gla-large-adc-overload-enable; adi,fagc-rst-gla-large-lmt-overload-enable; - adi,fagc-rst-gla-stronger-sig-thresh-above-ll = <0xa>; + adi,fagc-rst-gla-stronger-sig-thresh-above-ll = <0x0a>; adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable; adi,fagc-state-wait-time-ns = <0x104>; adi,fagc-use-last-lock-level-for-set-gain-enable; - adi,rssi-restart-mode = <0x3>; - adi,rssi-delay = <0x1>; - adi,rssi-wait = <0x1>; + adi,rssi-restart-mode = <0x03>; + adi,rssi-delay = <0x01>; + adi,rssi-wait = <0x01>; adi,rssi-duration = <0x3e8>; - adi,ctrl-outs-index = <0x0>; + adi,ctrl-outs-index = <0x00>; adi,ctrl-outs-enable-mask = <0xff>; adi,temp-sense-measurement-interval-ms = <0x3e8>; adi,temp-sense-offset-signed = <0xce>; adi,temp-sense-periodic-measurement-enable; adi,aux-dac-manual-mode-enable; - adi,aux-dac1-default-value-mV = <0x0>; - adi,aux-dac1-rx-delay-us = <0x0>; - adi,aux-dac1-tx-delay-us = <0x0>; - adi,aux-dac2-default-value-mV = <0x0>; - adi,aux-dac2-rx-delay-us = <0x0>; - adi,aux-dac2-tx-delay-us = <0x0>; - en_agc-gpios = <0x1a 0x7a 0x0>; - sync-gpios = <0x1a 0x7b 0x0>; - reset-gpios = <0x1a 0x7c 0x0>; - enable-gpios = <0x1a 0x7d 0x0>; - txnrx-gpios = <0x1a 0x7e 0x0>; - linux,phandle = <0x45>; - phandle = <0x45>; + adi,aux-dac1-default-value-mV = <0x00>; + adi,aux-dac1-rx-delay-us = <0x00>; + adi,aux-dac1-tx-delay-us = <0x00>; + adi,aux-dac2-default-value-mV = <0x00>; + adi,aux-dac2-rx-delay-us = <0x00>; + adi,aux-dac2-tx-delay-us = <0x00>; + en_agc-gpios = <0x14 0x7a 0x00>; + sync-gpios = <0x14 0x7b 0x00>; + reset-gpios = <0x14 0x7c 0x00>; + enable-gpios = <0x14 0x7d 0x00>; + txnrx-gpios = <0x14 0x7e 0x00>; + phandle = <0x3d>; }; }; spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "disabled"; - interrupt-parent = <0x4>; - interrupts = <0x0 0x14 0x4>; - reg = <0x0 0xff050000 0x0 0x1000>; - clock-names = "ref_clk", "pclk"; - #address-cells = <0x1>; - #size-cells = <0x0>; - power-domains = <0x2b>; - clocks = <0x3 0x3b 0x3 0x1f>; + interrupt-parent = <0x04>; + interrupts = <0x00 0x14 0x04>; + reg = <0x00 0xff050000 0x00 0x1000>; + clock-names = "ref_clk\0pclk"; + #address-cells = <0x01>; + #size-cells = <0x00>; + power-domains = <0x0c 0x24>; + clocks = <0x03 0x3b 0x03 0x1f>; + phandle = <0x96>; }; timer@ff110000 { compatible = "cdns,ttc"; status = "disabled"; - interrupt-parent = <0x4>; - interrupts = <0x0 0x24 0x4 0x0 0x25 0x4 0x0 0x26 0x4>; - reg = <0x0 0xff110000 0x0 0x1000>; + interrupt-parent = <0x04>; + interrupts = <0x00 0x24 0x04 0x00 0x25 0x04 0x00 0x26 0x04>; + reg = <0x00 0xff110000 0x00 0x1000>; timer-width = <0x20>; - power-domains = <0x2c>; - clocks = <0x3 0x1f>; + power-domains = <0x0c 0x18>; + clocks = <0x03 0x1f>; + phandle = <0x97>; }; timer@ff120000 { compatible = "cdns,ttc"; status = "disabled"; - interrupt-parent = <0x4>; - interrupts = <0x0 0x27 0x4 0x0 0x28 0x4 0x0 0x29 0x4>; - reg = <0x0 0xff120000 0x0 0x1000>; + interrupt-parent = <0x04>; + interrupts = <0x00 0x27 0x04 0x00 0x28 0x04 0x00 0x29 0x04>; + reg = <0x00 0xff120000 0x00 0x1000>; timer-width = <0x20>; - power-domains = <0x2d>; - clocks = <0x3 0x1f>; + power-domains = <0x0c 0x19>; + clocks = <0x03 0x1f>; + phandle = <0x98>; }; timer@ff130000 { compatible = "cdns,ttc"; status = "disabled"; - interrupt-parent = <0x4>; - interrupts = <0x0 0x2a 0x4 0x0 0x2b 0x4 0x0 0x2c 0x4>; - reg = <0x0 0xff130000 0x0 0x1000>; + interrupt-parent = <0x04>; + interrupts = <0x00 0x2a 0x04 0x00 0x2b 0x04 0x00 0x2c 0x04>; + reg = <0x00 0xff130000 0x00 0x1000>; timer-width = <0x20>; - power-domains = <0x2e>; - clocks = <0x3 0x1f>; + power-domains = <0x0c 0x1a>; + clocks = <0x03 0x1f>; + phandle = <0x99>; }; timer@ff140000 { compatible = "cdns,ttc"; status = "disabled"; - interrupt-parent = <0x4>; - interrupts = <0x0 0x2d 0x4 0x0 0x2e 0x4 0x0 0x2f 0x4>; - reg = <0x0 0xff140000 0x0 0x1000>; + interrupt-parent = <0x04>; + interrupts = <0x00 0x2d 0x04 0x00 0x2e 0x04 0x00 0x2f 0x04>; + reg = <0x00 0xff140000 0x00 0x1000>; timer-width = <0x20>; - power-domains = <0x2f>; - clocks = <0x3 0x1f>; + power-domains = <0x0c 0x1b>; + clocks = <0x03 0x1f>; + phandle = <0x9a>; }; serial@ff000000 { u-boot,dm-pre-reloc; - compatible = "cdns,uart-r1p12", "xlnx,xuartps"; + compatible = "cdns,uart-r1p12\0xlnx,xuartps"; status = "okay"; - interrupt-parent = <0x4>; - interrupts = <0x0 0x15 0x4>; - reg = <0x0 0xff000000 0x0 0x1000>; - clock-names = "uart_clk", "pclk"; - power-domains = <0x30>; - clocks = <0x3 0x38 0x3 0x1f>; + interrupt-parent = <0x04>; + interrupts = <0x00 0x15 0x04>; + reg = <0x00 0xff000000 0x00 0x1000>; + clock-names = "uart_clk\0pclk"; + power-domains = <0x0c 0x21>; + clocks = <0x03 0x38 0x03 0x1f>; pinctrl-names = "default"; - pinctrl-0 = <0x31>; + pinctrl-0 = <0x21>; + phandle = <0x9b>; }; serial@ff010000 { u-boot,dm-pre-reloc; - compatible = "cdns,uart-r1p12", "xlnx,xuartps"; + compatible = "cdns,uart-r1p12\0xlnx,xuartps"; status = "okay"; - interrupt-parent = <0x4>; - interrupts = <0x0 0x16 0x4>; - reg = <0x0 0xff010000 0x0 0x1000>; - clock-names = "uart_clk", "pclk"; - power-domains = <0x32>; - clocks = <0x3 0x39 0x3 0x1f>; + interrupt-parent = <0x04>; + interrupts = <0x00 0x16 0x04>; + reg = <0x00 0xff010000 0x00 0x1000>; + clock-names = "uart_clk\0pclk"; + power-domains = <0x0c 0x22>; + clocks = <0x03 0x39 0x03 0x1f>; pinctrl-names = "default"; - pinctrl-0 = <0x33>; + pinctrl-0 = <0x22>; + phandle = <0x9c>; }; usb0@ff9d0000 { - #address-cells = <0x2>; - #size-cells = <0x2>; + #address-cells = <0x02>; + #size-cells = <0x02>; status = "okay"; compatible = "xlnx,zynqmp-dwc3"; - reg = <0x0 0xff9d0000 0x0 0x100>; - clock-names = "bus_clk", "ref_clk"; - power-domains = <0x34>; + reg = <0x00 0xff9d0000 0x00 0x100>; + clock-names = "bus_clk\0ref_clk"; + power-domains = <0x0c 0x16>; + resets = <0x1c 0x3b 0x1c 0x3d 0x1c 0x3f>; + reset-names = "usb_crst\0usb_hibrst\0usb_apbrst"; + reset-gpio = <0x23 0x01 0x00>; ranges; - nvmem-cells = <0x22>; + nvmem-cells = <0x1e>; nvmem-cell-names = "soc_revision"; - clocks = <0x3 0x20 0x3 0x22>; + clocks = <0x03 0x20 0x03 0x22>; pinctrl-names = "default"; - pinctrl-0 = <0x35>; + pinctrl-0 = <0x24>; + phandle = <0x9d>; dwc3@fe200000 { compatible = "snps,dwc3"; status = "okay"; - reg = <0x0 0xfe200000 0x0 0x40000>; - interrupt-parent = <0x4>; - interrupts = <0x0 0x41 0x4 0x0 0x45 0x4 0x0 0x4b 0x4>; - #stream-id-cells = <0x1>; - iommus = <0xa 0x860>; + reg = <0x00 0xfe200000 0x00 0x40000>; + interrupt-parent = <0x04>; + interrupt-names = "dwc_usb3\0otg\0hiber"; + interrupts = <0x00 0x41 0x04 0x00 0x45 0x04 0x00 0x4b 0x04>; + #stream-id-cells = <0x01>; + iommus = <0x0e 0x860>; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; snps,enable_guctl1_resume_quirk; @@ -2063,149 +2111,133 @@ dr_mode = "otg"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; - phys = <0x36 0x4 0x0 0x2 0x18cba80>; + phys = <0x1d 0x02 0x04 0x00 0x02>; maximum-speed = "super-speed"; + phandle = <0x9e>; }; }; usb1@ff9e0000 { - #address-cells = <0x2>; - #size-cells = <0x2>; + #address-cells = <0x02>; + #size-cells = <0x02>; status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; - reg = <0x0 0xff9e0000 0x0 0x100>; - clock-names = "bus_clk", "ref_clk"; - power-domains = <0x37>; + reg = <0x00 0xff9e0000 0x00 0x100>; + clock-names = "bus_clk\0ref_clk"; + power-domains = <0x0c 0x17>; + resets = <0x1c 0x3c 0x1c 0x3e 0x1c 0x40>; + reset-names = "usb_crst\0usb_hibrst\0usb_apbrst"; ranges; - nvmem-cells = <0x22>; + nvmem-cells = <0x1e>; nvmem-cell-names = "soc_revision"; - clocks = <0x3 0x21 0x3 0x22>; + clocks = <0x03 0x21 0x03 0x22>; + phandle = <0x9f>; dwc3@fe300000 { compatible = "snps,dwc3"; status = "disabled"; - reg = <0x0 0xfe300000 0x0 0x40000>; - interrupt-parent = <0x4>; - interrupts = <0x0 0x46 0x4 0x0 0x4a 0x4 0x0 0x4c 0x4>; - #stream-id-cells = <0x1>; - iommus = <0xa 0x861>; + reg = <0x00 0xfe300000 0x00 0x40000>; + interrupt-parent = <0x04>; + interrupt-names = "dwc_usb3\0otg\0hiber"; + interrupts = <0x00 0x46 0x04 0x00 0x4a 0x04 0x00 0x4c 0x04>; + #stream-id-cells = <0x01>; + iommus = <0x0e 0x861>; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; snps,enable_guctl1_resume_quirk; snps,enable_guctl1_ipd_quirk; snps,xhci-stream-quirk; + phandle = <0xa0>; }; }; watchdog@fd4d0000 { compatible = "cdns,wdt-r1p2"; status = "okay"; - interrupt-parent = <0x4>; - interrupts = <0x0 0x71 0x1>; - reg = <0x0 0xfd4d0000 0x0 0x1000>; + interrupt-parent = <0x04>; + interrupts = <0x00 0x71 0x01>; + reg = <0x00 0xfd4d0000 0x00 0x1000>; timeout-sec = <0x3c>; reset-on-timeout; - clocks = <0x3 0x4b>; + clocks = <0x03 0x4b>; + phandle = <0xa1>; }; watchdog@ff150000 { compatible = "cdns,wdt-r1p2"; status = "disabled"; - interrupt-parent = <0x4>; - interrupts = <0x0 0x34 0x1>; - reg = <0x0 0xff150000 0x0 0x1000>; - timeout-sec = <0xa>; - clocks = <0x3 0x4b>; + interrupt-parent = <0x04>; + interrupts = <0x00 0x34 0x01>; + reg = <0x00 0xff150000 0x00 0x1000>; + timeout-sec = <0x0a>; + clocks = <0x03 0x70>; + phandle = <0xa2>; }; ams@ffa50000 { compatible = "xlnx,zynqmp-ams"; status = "okay"; - interrupt-parent = <0x4>; - interrupts = <0x0 0x38 0x4>; + interrupt-parent = <0x04>; + interrupts = <0x00 0x38 0x04>; interrupt-names = "ams-irq"; - reg = <0x0 0xffa50000 0x0 0x800>; + reg = <0x00 0xffa50000 0x00 0x800>; reg-names = "ams-base"; - #address-cells = <0x2>; - #size-cells = <0x2>; - #io-channel-cells = <0x1>; + #address-cells = <0x02>; + #size-cells = <0x02>; + #io-channel-cells = <0x01>; ranges; - clocks = <0x3 0x46>; + clocks = <0x03 0x46>; + phandle = <0xa3>; ams_ps@ffa50800 { compatible = "xlnx,zynqmp-ams-ps"; status = "okay"; - reg = <0x0 0xffa50800 0x0 0x400>; + reg = <0x00 0xffa50800 0x00 0x400>; + phandle = <0xa4>; }; ams_pl@ffa50c00 { compatible = "xlnx,zynqmp-ams-pl"; status = "okay"; - reg = <0x0 0xffa50c00 0x0 0x400>; + reg = <0x00 0xffa50c00 0x00 0x400>; + phandle = <0xa5>; }; }; - dma@fd4c0000 { - compatible = "xlnx,dpdma"; + dma-controller@fd4c0000 { + compatible = "xlnx,zynqmp-dpdma"; status = "okay"; - reg = <0x0 0xfd4c0000 0x0 0x1000>; - interrupts = <0x0 0x7a 0x4>; - interrupt-parent = <0x4>; + reg = <0x00 0xfd4c0000 0x00 0x1000>; + interrupts = <0x00 0x7a 0x04>; + interrupt-parent = <0x04>; clock-names = "axi_clk"; - power-domains = <0x38>; - dma-channels = <0x6>; - #dma-cells = <0x1>; - clocks = <0x3 0x14>; - linux,phandle = <0x3b>; - phandle = <0x3b>; - - dma-video0channel { - compatible = "xlnx,video0"; - }; - - dma-video1channel { - compatible = "xlnx,video1"; - }; - - dma-video2channel { - compatible = "xlnx,video2"; - }; - - dma-graphicschannel { - compatible = "xlnx,graphics"; - }; - - dma-audio0channel { - compatible = "xlnx,audio0"; - }; - - dma-audio1channel { - compatible = "xlnx,audio1"; - }; + power-domains = <0x0c 0x29>; + dma-channels = <0x06>; + #stream-id-cells = <0x01>; + iommus = <0x0e 0xce4>; + #dma-cells = <0x01>; + clocks = <0x03 0x14>; + phandle = <0x25>; }; - zynqmp-display@fd4a0000 { + display@fd4a0000 { compatible = "xlnx,zynqmp-dpsub-1.7"; status = "okay"; - reg = <0x0 0xfd4a0000 0x0 0x1000 0x0 0xfd4aa000 0x0 0x1000 0x0 0xfd4ab000 0x0 0x1000 0x0 0xfd4ac000 0x0 0x1000>; - reg-names = "dp", "blend", "av_buf", "aud"; - interrupts = <0x0 0x77 0x4>; - interrupt-parent = <0x4>; - clock-names = "dp_apb_clk", "dp_aud_clk", "dp_vtc_pixel_clk_in"; - power-domains = <0x38>; - clocks = <0x39 0x3 0x11 0x3 0x10>; + reg = <0x00 0xfd4a0000 0x00 0x1000 0x00 0xfd4aa000 0x00 0x1000 0x00 0xfd4ab000 0x00 0x1000 0x00 0xfd4ac000 0x00 0x1000>; + reg-names = "dp\0blend\0av_buf\0aud"; + interrupts = <0x00 0x77 0x04>; + interrupt-parent = <0x04>; + #stream-id-cells = <0x01>; + iommus = <0x0e 0xce3>; + clock-names = "dp_apb_clk\0dp_aud_clk\0dp_vtc_pixel_clk_in"; + power-domains = <0x0c 0x29>; + resets = <0x1c 0x03>; + dma-names = "vid0\0vid1\0vid2\0gfx0"; + dmas = <0x25 0x00 0x25 0x01 0x25 0x02 0x25 0x03>; + clocks = <0x26 0x03 0x11 0x03 0x10>; phy-names = "dp-phy0"; - phys = <0x3a 0x5 0x0 0x3 0x19bfcc0>; - - vid-layer { - dma-names = "vid0", "vid1", "vid2"; - dmas = <0x3b 0x0 0x3b 0x1 0x3b 0x2>; - }; - - gfx-layer { - dma-names = "gfx0"; - dmas = <0x3b 0x3>; - }; + phys = <0x1d 0x01 0x06 0x00 0x03>; + phandle = <0xa6>; i2c-bus { }; @@ -2213,149 +2245,136 @@ zynqmp_dp_snd_codec0 { compatible = "xlnx,dp-snd-codec"; clock-names = "aud_clk"; - clocks = <0x3 0x11>; + clocks = <0x03 0x11>; status = "okay"; - linux,phandle = <0x3e>; - phandle = <0x3e>; + phandle = <0x29>; }; zynqmp_dp_snd_pcm0 { compatible = "xlnx,dp-snd-pcm"; - dmas = <0x3b 0x4>; + dmas = <0x25 0x04>; dma-names = "tx"; status = "okay"; - linux,phandle = <0x3c>; - phandle = <0x3c>; + phandle = <0x27>; }; zynqmp_dp_snd_pcm1 { compatible = "xlnx,dp-snd-pcm"; - dmas = <0x3b 0x5>; + dmas = <0x25 0x05>; dma-names = "tx"; status = "okay"; - linux,phandle = <0x3d>; - phandle = <0x3d>; + phandle = <0x28>; }; zynqmp_dp_snd_card { compatible = "xlnx,dp-snd-card"; - xlnx,dp-snd-pcm = <0x3c 0x3d>; - xlnx,dp-snd-codec = <0x3e>; + xlnx,dp-snd-pcm = <0x27 0x28>; + xlnx,dp-snd-codec = <0x29>; status = "okay"; + phandle = <0xa7>; }; }; }; fclk0 { - status = "disabled"; + status = "okay"; compatible = "xlnx,fclk"; - clocks = <0x3 0x47>; + clocks = <0x03 0x47>; + phandle = <0xa8>; }; fclk1 { - status = "disabled"; + status = "okay"; compatible = "xlnx,fclk"; - clocks = <0x3 0x48>; + clocks = <0x03 0x48>; + phandle = <0xa9>; }; fclk2 { - status = "disabled"; + status = "okay"; compatible = "xlnx,fclk"; - clocks = <0x3 0x49>; + clocks = <0x03 0x49>; + phandle = <0xaa>; }; fclk3 { - status = "disabled"; + status = "okay"; compatible = "xlnx,fclk"; - clocks = <0x3 0x4a>; + clocks = <0x03 0x4a>; + phandle = <0xab>; }; pss_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; - #clock-cells = <0x0>; + #clock-cells = <0x00>; clock-frequency = <0x1fca055>; - linux,phandle = <0x3f>; - phandle = <0x3f>; + phandle = <0x06>; }; video_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; - #clock-cells = <0x0>; + #clock-cells = <0x00>; clock-frequency = <0x19bfcc0>; - linux,phandle = <0x40>; - phandle = <0x40>; + phandle = <0x07>; }; pss_alt_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; - #clock-cells = <0x0>; - clock-frequency = <0x0>; - linux,phandle = <0x41>; - phandle = <0x41>; + #clock-cells = <0x00>; + clock-frequency = <0x00>; + phandle = <0x08>; }; gt_crx_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; - #clock-cells = <0x0>; + #clock-cells = <0x00>; clock-frequency = <0x66ff300>; - linux,phandle = <0x43>; - phandle = <0x43>; + phandle = <0x0a>; }; aux_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; - #clock-cells = <0x0>; + #clock-cells = <0x00>; clock-frequency = <0x19bfcc0>; - linux,phandle = <0x42>; - phandle = <0x42>; - }; - - clk { - u-boot,dm-pre-reloc; - #clock-cells = <0x1>; - compatible = "xlnx,zynqmp-clk"; - clocks = <0x3f 0x40 0x41 0x42 0x43>; - clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", "aux_ref_clk", "gt_crx_ref_clk"; - linux,phandle = <0x3>; - phandle = <0x3>; + phandle = <0x09>; }; dp_aclk { compatible = "fixed-clock"; - #clock-cells = <0x0>; + #clock-cells = <0x00>; clock-frequency = <0x5f5e100>; clock-accuracy = <0x64>; - linux,phandle = <0x39>; - phandle = <0x39>; + phandle = <0x26>; }; aliases { - ethernet0 = "/amba/ethernet@ff0e0000"; - gpio0 = "/amba/gpio@ff0a0000"; - i2c0 = "/amba/i2c@ff020000"; - i2c1 = "/amba/i2c@ff030000"; - mmc0 = "/amba/mmc@ff170000"; - rtc0 = "/amba/rtc@ffa60000"; - serial0 = "/amba/serial@ff000000"; - serial1 = "/amba/serial@ff010000"; + ethernet0 = "/axi/ethernet@ff0e0000"; + gpio0 = "/axi/gpio@ff0a0000"; + i2c0 = "/axi/i2c@ff020000"; + i2c1 = "/axi/i2c@ff030000"; + mmc0 = "/axi/mmc@ff170000"; + rtc0 = "/axi/rtc@ffa60000"; + serial0 = "/axi/serial@ff000000"; + serial1 = "/axi/serial@ff010000"; serial2 = "/dcc"; - spi0 = "/amba/spi@ff0f0000"; - usb0 = "/amba/usb0@ff9d0000"; + spi0 = "/axi/spi@ff0f0000"; + usb0 = "/axi/usb0@ff9d0000"; }; chosen { bootargs = "earlycon"; stdout-path = "serial0:115200n8"; + xlnx,eeprom = "/axi/i2c@ff030000/i2c-mux@74/i2c@0/eeprom@54"; }; memory@0 { device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000 0x8 0x0 0x0 0x80000000>; + reg = <0x00 0x00 0x00 0x80000000 0x08 0x00 0x00 0x80000000>; }; gpio-keys { @@ -2364,9 +2383,9 @@ sw19 { label = "sw19"; - gpios = <0x1a 0x16 0x0>; + gpios = <0x14 0x16 0x00>; linux,code = <0x6c>; - gpio-key,wakeup; + wakeup-source; autorepeat; }; }; @@ -2374,40 +2393,144 @@ leds { compatible = "gpio-leds"; - heartbeat_led { + heartbeat-led { label = "heartbeat"; - gpios = <0x1a 0x17 0x0>; + gpios = <0x14 0x17 0x00>; linux,default-trigger = "heartbeat"; }; }; + ina226-u76 { + compatible = "iio-hwmon"; + io-channels = <0x2a 0x00 0x2a 0x01 0x2a 0x02 0x2a 0x03>; + }; + + ina226-u77 { + compatible = "iio-hwmon"; + io-channels = <0x2b 0x00 0x2b 0x01 0x2b 0x02 0x2b 0x03>; + }; + + ina226-u78 { + compatible = "iio-hwmon"; + io-channels = <0x2c 0x00 0x2c 0x01 0x2c 0x02 0x2c 0x03>; + }; + + ina226-u87 { + compatible = "iio-hwmon"; + io-channels = <0x2d 0x00 0x2d 0x01 0x2d 0x02 0x2d 0x03>; + }; + + ina226-u85 { + compatible = "iio-hwmon"; + io-channels = <0x2e 0x00 0x2e 0x01 0x2e 0x02 0x2e 0x03>; + }; + + ina226-u86 { + compatible = "iio-hwmon"; + io-channels = <0x2f 0x00 0x2f 0x01 0x2f 0x02 0x2f 0x03>; + }; + + ina226-u93 { + compatible = "iio-hwmon"; + io-channels = <0x30 0x00 0x30 0x01 0x30 0x02 0x30 0x03>; + }; + + ina226-u88 { + compatible = "iio-hwmon"; + io-channels = <0x31 0x00 0x31 0x01 0x31 0x02 0x31 0x03>; + }; + + ina226-u15 { + compatible = "iio-hwmon"; + io-channels = <0x32 0x00 0x32 0x01 0x32 0x02 0x32 0x03>; + }; + + ina226-u92 { + compatible = "iio-hwmon"; + io-channels = <0x33 0x00 0x33 0x01 0x33 0x02 0x33 0x03>; + }; + + ina226-u79 { + compatible = "iio-hwmon"; + io-channels = <0x34 0x00 0x34 0x01 0x34 0x02 0x34 0x03>; + }; + + ina226-u81 { + compatible = "iio-hwmon"; + io-channels = <0x35 0x00 0x35 0x01 0x35 0x02 0x35 0x03>; + }; + + ina226-u80 { + compatible = "iio-hwmon"; + io-channels = <0x36 0x00 0x36 0x01 0x36 0x02 0x36 0x03>; + }; + + ina226-u84 { + compatible = "iio-hwmon"; + io-channels = <0x37 0x00 0x37 0x01 0x37 0x02 0x37 0x03>; + }; + + ina226-u16 { + compatible = "iio-hwmon"; + io-channels = <0x38 0x00 0x38 0x01 0x38 0x02 0x38 0x03>; + }; + + ina226-u65 { + compatible = "iio-hwmon"; + io-channels = <0x39 0x00 0x39 0x01 0x39 0x02 0x39 0x03>; + }; + + ina226-u74 { + compatible = "iio-hwmon"; + io-channels = <0x3a 0x00 0x3a 0x01 0x3a 0x02 0x3a 0x03>; + }; + + ina226-u75 { + compatible = "iio-hwmon"; + io-channels = <0x3b 0x00 0x3b 0x01 0x3b 0x02 0x3b 0x03>; + }; + + ref48M { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0x2dc6c00>; + phandle = <0x17>; + }; + + refhdmi { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0x6cfd9c8>; + phandle = <0x18>; + }; + fpga-axi@0 { - interrupt-parent = <0x4>; + interrupt-parent = <0x04>; compatible = "simple-bus"; - #address-cells = <0x1>; - #size-cells = <0x1>; - ranges = <0x0 0x0 0x0 0xffffffff>; + #address-cells = <0x01>; + #size-cells = <0x01>; + ranges = <0x00 0x00 0x00 0xffffffff>; + phandle = <0xac>; // dma@9c400000 { // compatible = "adi,axi-dmac-1.00.a"; // reg = <0x9c400000 0x10000>; - // #dma-cells = <0x1>; - // #clock-cells = <0x0>; - // interrupts = <0x0 0x6d 0x0>; - // clocks = <0x3 0x47>; - // linux,phandle = <0x44>; - // phandle = <0x44>; + // #dma-cells = <0x01>; + // #clock-cells = <0x00>; + // interrupts = <0x00 0x6d 0x04>; + // clocks = <0x03 0x47>; + // phandle = <0x3c>; // adi,channels { - // #size-cells = <0x0>; - // #address-cells = <0x1>; + // #size-cells = <0x00>; + // #address-cells = <0x01>; // dma-channel@0 { - // reg = <0x0>; + // reg = <0x00>; // adi,source-bus-width = <0x40>; - // adi,source-bus-type = <0x2>; + // adi,source-bus-type = <0x02>; // adi,destination-bus-width = <0x40>; - // adi,destination-bus-type = <0x0>; + // adi,destination-bus-type = <0x00>; // }; // }; // }; @@ -2415,23 +2538,22 @@ // dma@9c420000 { // compatible = "adi,axi-dmac-1.00.a"; // reg = <0x9c420000 0x10000>; - // #dma-cells = <0x1>; - // #clock-cells = <0x0>; - // interrupts = <0x0 0x6c 0x0>; - // clocks = <0x3 0x47>; - // linux,phandle = <0x46>; - // phandle = <0x46>; + // #dma-cells = <0x01>; + // #clock-cells = <0x00>; + // interrupts = <0x00 0x6c 0x04>; + // clocks = <0x03 0x47>; + // phandle = <0x3e>; // adi,channels { - // #size-cells = <0x0>; - // #address-cells = <0x1>; + // #size-cells = <0x00>; + // #address-cells = <0x01>; // dma-channel@0 { - // reg = <0x0>; + // reg = <0x00>; // adi,source-bus-width = <0x40>; - // adi,source-bus-type = <0x0>; + // adi,source-bus-type = <0x00>; // adi,destination-bus-width = <0x40>; - // adi,destination-bus-type = <0x2>; + // adi,destination-bus-type = <0x02>; // }; // }; // }; @@ -2452,6 +2574,27 @@ dma-names = "axidma0", "axidma1"; } ; + openwifi_ip_axi_bram_ctrl_0: axi_bram_ctrl@b0000000 { + clock-names = "s_axi_aclk"; + clocks = <0x3 0x49>; + compatible = "xlnx,axi-bram-ctrl-4.1"; + reg = <0x0 0xb0000000 0x0 0x80000>; + xlnx,bram-addr-width = <0x10>; + xlnx,bram-inst-mode = "EXTERNAL"; + xlnx,ecc = <0x0>; + xlnx,ecc-onoff-reset-value = <0x0>; + xlnx,ecc-type = <0x0>; + xlnx,fault-inject = <0x0>; + xlnx,memory-depth = <0x10000>; + xlnx,rd-cmd-optimization = <0x1>; + xlnx,read-latency = <0x1>; + xlnx,s-axi-ctrl-addr-width = <0x20>; + xlnx,s-axi-ctrl-data-width = <0x20>; + xlnx,s-axi-id-width = <0x10>; + xlnx,s-axi-supports-narrow-burst = <0x1>; + xlnx,single-port-bram = <0x1>; + }; + tx_dma: dma@a0000000 { #dma-cells = <1>; clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk"; @@ -2459,7 +2602,7 @@ compatible = "xlnx,axi-dma-1.00.a"; interrupt-names = "mm2s_introut", "s2mm_introut"; interrupts = <0 95 4 0 96 4>; - reg = <0xA0000000 0x1000>; + reg = <0xA0000000 0x10000>; xlnx,addrwidth = <0x28>; xlnx,include-sg ; xlnx,sg-length-width = <0xe>; @@ -2479,7 +2622,7 @@ }; }; - rx_dma: dma@a0001000 { + rx_dma: dma@a0010000 { #dma-cells = <1>; clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk"; clocks = <0x3 0x49>, <0x3 0x49>, <0x3 0x49>, <0x3 0x49>; @@ -2487,11 +2630,11 @@ //dma-coherent ; interrupt-names = "mm2s_introut", "s2mm_introut"; interrupts = <0 91 4 0 92 4>; - reg = <0xA0001000 0x1000>; + reg = <0xa0010000 0x10000>; xlnx,addrwidth = <0x28>; xlnx,include-sg ; xlnx,sg-length-width = <0xe>; - dma-channel@a0001000 { + dma-channel@a0010000 { compatible = "xlnx,axi-dma-mm2s-channel"; dma-channels = <0x1>; interrupts = <0 91 4>; @@ -2507,54 +2650,54 @@ }; }; - tx_intf_0: tx_intf@a0005000 { + tx_intf_0: tx_intf@a0060000 { clock-names = "s00_axi_aclk", "s00_axis_aclk";//, "s01_axis_aclk", "m00_axis_aclk"; clocks = <0x3 0x49>, <0x3 0x49>;//, <0x3 0x49>, <0x3 0x49>; compatible = "sdr,tx_intf"; interrupt-names = "tx_itrpt"; interrupts = <0 94 1>; - reg = <0xA0005000 0x1000>; + reg = <0xa0060000 0x10000>; xlnx,s00-axi-addr-width = <0x7>; xlnx,s00-axi-data-width = <0x20>; }; - rx_intf_0: rx_intf@a0004000 { + rx_intf_0: rx_intf@a0040000 { clock-names = "s00_axi_aclk", "m00_axis_aclk";//, "s00_axis_aclk"; clocks = <0x3 0x49>, <0x3 0x49>;//, <0x3 0x49>; compatible = "sdr,rx_intf"; interrupt-names = "not_valid_anymore", "rx_pkt_intr"; interrupts = <0 89 1 0 90 1>; - reg = <0xA0004000 0x1000>; + reg = <0xa0040000 0x10000>; xlnx,s00-axi-addr-width = <0x7>; xlnx,s00-axi-data-width = <0x20>; }; - openofdm_tx_0: openofdm_tx@a0003000 { + openofdm_tx_0: openofdm_tx@a0030000 { clock-names = "clk"; clocks = <0x3 0x49>; compatible = "sdr,openofdm_tx"; - reg = <0xA0003000 0x1000>; + reg = <0xa0030000 0x10000>; }; - openofdm_rx_0: openofdm_rx@a0002000 { + openofdm_rx_0: openofdm_rx@a0020000 { clock-names = "clk"; clocks = <0x3 0x49>; compatible = "sdr,openofdm_rx"; - reg = <0xA0002000 0x1000>; + reg = <0xa0020000 0x10000>; }; - xpu_0: xpu@a0006000 { + xpu_0: xpu@a0070000 { clock-names = "s00_axi_aclk"; clocks = <0x3 0x49>; compatible = "sdr,xpu"; - reg = <0xA0006000 0x1000>; + reg = <0xa0070000 0x10000>; }; - side_ch_0: side_ch@a0007000 { + side_ch_0: side_ch@a0050000 { clock-names = "s00_axi_aclk"; clocks = <0x3 0x49>; compatible = "sdr,side_ch"; - reg = <0xA0007000 0x1000>; + reg = <0xa0050000 0x10000>; dmas = <&rx_dma 0 &tx_dma 1>; dma-names = "rx_dma_mm2s", "tx_dma_s2mm"; @@ -2563,24 +2706,27 @@ cf-ad9361-lpc@99020000 { compatible = "adi,axi-ad9361-6.00.a"; reg = <0x99020000 0x6000>; - // dmas = <0x44 0x0>; + // dmas = <0x3c 0x00>; // dma-names = "rx"; - spibus-connected = <0x45>; + spibus-connected = <0x3d>; + phandle = <0xad>; }; cf-ad9361-dds-core-lpc@99024000 { compatible = "adi,axi-ad9361-dds-6.00.a"; reg = <0x99024000 0x1000>; - clocks = <0x45 0xd>; + clocks = <0x3d 0x0d>; clock-names = "sampl_clk"; - // dmas = <0x46 0x0>; + // dmas = <0x3e 0x00>; // dma-names = "tx"; + phandle = <0xae>; }; - /*axi-sysid-0@85000000 { - compatible = "adi,axi-sysid-1.00.a"; - reg = <0x85000000 0x10000>; - };*/ + // axi-sysid-0@85000000 { + // compatible = "adi,axi-sysid-1.00.a"; + // reg = <0x85000000 0x10000>; + // phandle = <0xaf>; + // }; }; clocks { @@ -2589,9 +2735,186 @@ compatible = "fixed-clock"; clock-frequency = <0x2625a00>; clock-output-names = "ad9361_ext_refclk"; - #clock-cells = <0x0>; - linux,phandle = <0x2a>; - phandle = <0x2a>; + #clock-cells = <0x00>; + phandle = <0x20>; }; }; + + __symbols__ { + cpu0 = "/cpus/cpu@0"; + cpu1 = "/cpus/cpu@1"; + cpu2 = "/cpus/cpu@2"; + cpu3 = "/cpus/cpu@3"; + CPU_SLEEP_0 = "/cpus/idle-states/cpu-sleep-0"; + cpu_opp_table = "/cpu-opp-table"; + zynqmp_ipi = "/zynqmp_ipi"; + ipi_mailbox_pmu1 = "/zynqmp_ipi/mailbox@ff990400"; + dcc = "/dcc"; + zynqmp_firmware = "/firmware/zynqmp-firmware"; + zynqmp_power = "/firmware/zynqmp-firmware/zynqmp-power"; + soc_revision = "/firmware/zynqmp-firmware/nvmem_firmware/soc_revision@0"; + efuse_dna = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_dna@c"; + efuse_usr0 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr0@20"; + efuse_usr1 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr1@24"; + efuse_usr2 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr2@28"; + efuse_usr3 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr3@2c"; + efuse_usr4 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr4@30"; + efuse_usr5 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr5@34"; + efuse_usr6 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr6@38"; + efuse_usr7 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr7@3c"; + efuse_miscusr = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_miscusr@40"; + efuse_chash = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_chash@50"; + efuse_pufmisc = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_pufmisc@54"; + efuse_sec = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_sec@58"; + efuse_spkid = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_spkid@5c"; + efuse_ppk0hash = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_ppk0hash@a0"; + efuse_ppk1hash = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_ppk1hash@d0"; + zynqmp_pcap = "/firmware/zynqmp-firmware/pcap"; + xlnx_aes = "/firmware/zynqmp-firmware/zynqmp-aes"; + zynqmp_reset = "/firmware/zynqmp-firmware/reset-controller"; + pinctrl0 = "/firmware/zynqmp-firmware/pinctrl"; + pinctrl_i2c0_default = "/firmware/zynqmp-firmware/pinctrl/i2c0-default"; + pinctrl_i2c0_gpio = "/firmware/zynqmp-firmware/pinctrl/i2c0-gpio"; + pinctrl_i2c1_default = "/firmware/zynqmp-firmware/pinctrl/i2c1-default"; + pinctrl_i2c1_gpio = "/firmware/zynqmp-firmware/pinctrl/i2c1-gpio"; + pinctrl_uart0_default = "/firmware/zynqmp-firmware/pinctrl/uart0-default"; + pinctrl_uart1_default = "/firmware/zynqmp-firmware/pinctrl/uart1-default"; + pinctrl_usb0_default = "/firmware/zynqmp-firmware/pinctrl/usb0-default"; + pinctrl_gem3_default = "/firmware/zynqmp-firmware/pinctrl/gem3-default"; + pinctrl_can1_default = "/firmware/zynqmp-firmware/pinctrl/can1-default"; + pinctrl_sdhci1_default = "/firmware/zynqmp-firmware/pinctrl/sdhci1-default"; + pinctrl_gpio_default = "/firmware/zynqmp-firmware/pinctrl/gpio-default"; + xlnx_keccak_384 = "/firmware/zynqmp-firmware/sha384"; + xlnx_rsa = "/firmware/zynqmp-firmware/zynqmp-rsa"; + modepin_gpio = "/firmware/zynqmp-firmware/gpio"; + zynqmp_clk = "/firmware/zynqmp-firmware/clock-controller"; + fpga_full = "/fpga-full"; + smmu = "/smmu@fd800000"; + amba = "/axi"; + can0 = "/axi/can@ff060000"; + can1 = "/axi/can@ff070000"; + cci = "/axi/cci@fd6e0000"; + fpd_dma_chan1 = "/axi/dma@fd500000"; + fpd_dma_chan2 = "/axi/dma@fd510000"; + fpd_dma_chan3 = "/axi/dma@fd520000"; + fpd_dma_chan4 = "/axi/dma@fd530000"; + fpd_dma_chan5 = "/axi/dma@fd540000"; + fpd_dma_chan6 = "/axi/dma@fd550000"; + fpd_dma_chan7 = "/axi/dma@fd560000"; + fpd_dma_chan8 = "/axi/dma@fd570000"; + gic = "/axi/interrupt-controller@f9010000"; + gpu = "/axi/gpu@fd4b0000"; + lpd_dma_chan1 = "/axi/dma@ffa80000"; + lpd_dma_chan2 = "/axi/dma@ffa90000"; + lpd_dma_chan3 = "/axi/dma@ffaa0000"; + lpd_dma_chan4 = "/axi/dma@ffab0000"; + lpd_dma_chan5 = "/axi/dma@ffac0000"; + lpd_dma_chan6 = "/axi/dma@ffad0000"; + lpd_dma_chan7 = "/axi/dma@ffae0000"; + lpd_dma_chan8 = "/axi/dma@ffaf0000"; + mc = "/axi/memory-controller@fd070000"; + nand0 = "/axi/nand-controller@ff100000"; + gem0 = "/axi/ethernet@ff0b0000"; + gem1 = "/axi/ethernet@ff0c0000"; + gem2 = "/axi/ethernet@ff0d0000"; + gem3 = "/axi/ethernet@ff0e0000"; + phyc = "/axi/ethernet@ff0e0000/ethernet-phy@c"; + gpio = "/axi/gpio@ff0a0000"; + i2c0 = "/axi/i2c@ff020000"; + tca6416_u97 = "/axi/i2c@ff020000/gpio@20"; + tca6416_u61 = "/axi/i2c@ff020000/gpio@21"; + u76 = "/axi/i2c@ff020000/i2c-mux@75/i2c@0/ina226@40"; + u77 = "/axi/i2c@ff020000/i2c-mux@75/i2c@0/ina226@41"; + u78 = "/axi/i2c@ff020000/i2c-mux@75/i2c@0/ina226@42"; + u87 = "/axi/i2c@ff020000/i2c-mux@75/i2c@0/ina226@43"; + u85 = "/axi/i2c@ff020000/i2c-mux@75/i2c@0/ina226@44"; + u86 = "/axi/i2c@ff020000/i2c-mux@75/i2c@0/ina226@45"; + u93 = "/axi/i2c@ff020000/i2c-mux@75/i2c@0/ina226@46"; + u88 = "/axi/i2c@ff020000/i2c-mux@75/i2c@0/ina226@47"; + u15 = "/axi/i2c@ff020000/i2c-mux@75/i2c@0/ina226@4a"; + u92 = "/axi/i2c@ff020000/i2c-mux@75/i2c@0/ina226@4b"; + u79 = "/axi/i2c@ff020000/i2c-mux@75/i2c@1/ina226@40"; + u81 = "/axi/i2c@ff020000/i2c-mux@75/i2c@1/ina226@41"; + u80 = "/axi/i2c@ff020000/i2c-mux@75/i2c@1/ina226@42"; + u84 = "/axi/i2c@ff020000/i2c-mux@75/i2c@1/ina226@43"; + u16 = "/axi/i2c@ff020000/i2c-mux@75/i2c@1/ina226@44"; + u65 = "/axi/i2c@ff020000/i2c-mux@75/i2c@1/ina226@45"; + u74 = "/axi/i2c@ff020000/i2c-mux@75/i2c@1/ina226@46"; + u75 = "/axi/i2c@ff020000/i2c-mux@75/i2c@1/ina226@47"; + i2c1 = "/axi/i2c@ff030000"; + eeprom = "/axi/i2c@ff030000/i2c-mux@74/i2c@0/eeprom@54"; + board_sn = "/axi/i2c@ff030000/i2c-mux@74/i2c@0/eeprom@54/board-sn@0"; + eth_mac = "/axi/i2c@ff030000/i2c-mux@74/i2c@0/eeprom@54/eth-mac@20"; + board_name = "/axi/i2c@ff030000/i2c-mux@74/i2c@0/eeprom@54/board-name@d0"; + board_revision = "/axi/i2c@ff030000/i2c-mux@74/i2c@0/eeprom@54/board-revision@e0"; + si5341 = "/axi/i2c@ff030000/i2c-mux@74/i2c@1/clock-generator@36"; + si5341_0 = "/axi/i2c@ff030000/i2c-mux@74/i2c@1/clock-generator@36/out@0"; + si5341_2 = "/axi/i2c@ff030000/i2c-mux@74/i2c@1/clock-generator@36/out@2"; + si5341_3 = "/axi/i2c@ff030000/i2c-mux@74/i2c@1/clock-generator@36/out@3"; + si5341_4 = "/axi/i2c@ff030000/i2c-mux@74/i2c@1/clock-generator@36/out@4"; + si5341_5 = "/axi/i2c@ff030000/i2c-mux@74/i2c@1/clock-generator@36/out@5"; + si5341_6 = "/axi/i2c@ff030000/i2c-mux@74/i2c@1/clock-generator@36/out@6"; + si5341_7 = "/axi/i2c@ff030000/i2c-mux@74/i2c@1/clock-generator@36/out@7"; + si5341_9 = "/axi/i2c@ff030000/i2c-mux@74/i2c@1/clock-generator@36/out@9"; + si570_1 = "/axi/i2c@ff030000/i2c-mux@74/i2c@2/clock-generator@5d"; + si570_2 = "/axi/i2c@ff030000/i2c-mux@74/i2c@3/clock-generator@5d"; + si5328 = "/axi/i2c@ff030000/i2c-mux@74/i2c@4/clock-generator@69"; + si5328_clk = "/axi/i2c@ff030000/i2c-mux@74/i2c@4/clock-generator@69/clk0@0"; + ocm = "/axi/memory-controller@ff960000"; + perf_monitor_ocm = "/axi/perf-monitor@ffa00000"; + perf_monitor_ddr = "/axi/perf-monitor@fd0b0000"; + perf_monitor_cci = "/axi/perf-monitor@fd490000"; + perf_monitor_lpd = "/axi/perf-monitor@ffa10000"; + pcie = "/axi/pcie@fd0e0000"; + pcie_intc = "/axi/pcie@fd0e0000/legacy-interrupt-controller"; + qspi = "/axi/spi@ff0f0000"; + psgtr = "/axi/phy@fd400000"; + rtc = "/axi/rtc@ffa60000"; + sata = "/axi/ahci@fd0c0000"; + sdhci0 = "/axi/mmc@ff160000"; + sdhci1 = "/axi/mmc@ff170000"; + spi0 = "/axi/spi@ff040000"; + adc0_ad9361 = "/axi/spi@ff040000/ad9361-phy@0"; + spi1 = "/axi/spi@ff050000"; + ttc0 = "/axi/timer@ff110000"; + ttc1 = "/axi/timer@ff120000"; + ttc2 = "/axi/timer@ff130000"; + ttc3 = "/axi/timer@ff140000"; + uart0 = "/axi/serial@ff000000"; + uart1 = "/axi/serial@ff010000"; + usb0 = "/axi/usb0@ff9d0000"; + dwc3_0 = "/axi/usb0@ff9d0000/dwc3@fe200000"; + usb1 = "/axi/usb1@ff9e0000"; + dwc3_1 = "/axi/usb1@ff9e0000/dwc3@fe300000"; + watchdog0 = "/axi/watchdog@fd4d0000"; + lpd_watchdog = "/axi/watchdog@ff150000"; + xilinx_ams = "/axi/ams@ffa50000"; + ams_ps = "/axi/ams@ffa50000/ams_ps@ffa50800"; + ams_pl = "/axi/ams@ffa50000/ams_pl@ffa50c00"; + zynqmp_dpdma = "/axi/dma-controller@fd4c0000"; + zynqmp_dpsub = "/axi/display@fd4a0000"; + zynqmp_dp_snd_codec0 = "/axi/display@fd4a0000/zynqmp_dp_snd_codec0"; + zynqmp_dp_snd_pcm0 = "/axi/display@fd4a0000/zynqmp_dp_snd_pcm0"; + zynqmp_dp_snd_pcm1 = "/axi/display@fd4a0000/zynqmp_dp_snd_pcm1"; + zynqmp_dp_snd_card0 = "/axi/display@fd4a0000/zynqmp_dp_snd_card"; + fclk0 = "/fclk0"; + fclk1 = "/fclk1"; + fclk2 = "/fclk2"; + fclk3 = "/fclk3"; + pss_ref_clk = "/pss_ref_clk"; + video_clk = "/video_clk"; + pss_alt_ref_clk = "/pss_alt_ref_clk"; + gt_crx_ref_clk = "/gt_crx_ref_clk"; + aux_ref_clk = "/aux_ref_clk"; + dp_aclk = "/dp_aclk"; + ref48 = "/ref48M"; + refhdmi = "/refhdmi"; + fpga_axi = "/fpga-axi@0"; + rx_dma = "/fpga-axi@0/dma@9c400000"; + tx_dma = "/fpga-axi@0/dma@9c420000"; + cf_ad9361_adc_core_0 = "/fpga-axi@0/cf-ad9361-lpc@99020000"; + cf_ad9361_dac_core_0 = "/fpga-axi@0/cf-ad9361-dds-core-lpc@99024000"; + axi_sysid_0 = "/fpga-axi@0/axi-sysid-0@85000000"; + ad9361_clkin = "/clocks/clock@0"; + }; }; diff --git a/kernel_boot/boards/zcu102_fmcs2/u-boot-zcu.elf b/kernel_boot/boards/zcu102_fmcs2/u-boot-zcu.elf deleted file mode 100644 index d4edf69..0000000 Binary files a/kernel_boot/boards/zcu102_fmcs2/u-boot-zcu.elf and /dev/null differ diff --git a/kernel_boot/boards/zcu102_fmcs2/u-boot_xilinx_zynqmp_zcu102_revA.elf b/kernel_boot/boards/zcu102_fmcs2/u-boot_xilinx_zynqmp_zcu102_revA.elf new file mode 100644 index 0000000..b651e27 Binary files /dev/null and b/kernel_boot/boards/zcu102_fmcs2/u-boot_xilinx_zynqmp_zcu102_revA.elf differ diff --git a/kernel_boot/boards/zed_fmcs2/u-boot.elf b/kernel_boot/boards/zed_fmcs2/u-boot.elf index d074293..e2822e9 100644 Binary files a/kernel_boot/boards/zed_fmcs2/u-boot.elf and b/kernel_boot/boards/zed_fmcs2/u-boot.elf differ diff --git a/kernel_boot/build_boot_bin.sh b/kernel_boot/build_boot_bin.sh index 4639167..c3f2212 100755 --- a/kernel_boot/build_boot_bin.sh +++ b/kernel_boot/build_boot_bin.sh @@ -1,60 +1,38 @@ #!/bin/bash - -# Author: Xianjun Jiao -# SPDX-FileCopyrightText: 2019 UGent -# SPDX-License-Identifier: AGPL-3.0-or-later -# https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/software/linux/zynq_2014r2 - -if [ "$#" -ne 2 ]; then - echo "You must enter the \$OPENWIFI_HW_DIR \$BOARD_NAME as argument" - echo "BOARD_NAME Like: sdrpi antsdr adrv9364z7020 adrv9361z7035 zc706_fmcs2 zed_fmcs2 zc702_fmcs2 zcu102_fmcs2 zcu102_9371" - exit 1 -fi - -OPENWIFI_HW_DIR=$1 -BOARD_NAME=$2 - -if [ "$BOARD_NAME" != "antsdr" ] && [ "$BOARD_NAME" != "antsdr_e200" ] && [ "$BOARD_NAME" != "sdrpi" ] && [ "$BOARD_NAME" != "zc706_fmcs2" ] && [ "$BOARD_NAME" != "zc702_fmcs2" ] && [ "$BOARD_NAME" != "zed_fmcs2" ] && [ "$BOARD_NAME" != "adrv9361z7035" ] && [ "$BOARD_NAME" != "adrv9364z7020" ] && [ "$BOARD_NAME" != "zcu102_fmcs2" ] && [ "$BOARD_NAME" != "zcu102_9371" ]; then - echo "\$BOARD_NAME is not correct. Please check!" - exit 1 -else - echo "\$BOARD_NAME is found!" -fi - set -ex -HDF_FILE=$OPENWIFI_HW_DIR/boards/$BOARD_NAME/sdk/system_top_hw_platform_0/system.hdf -UBOOT_FILE=./boards/$BOARD_NAME/u-boot.elf -BUILD_DIR=./boards/$BOARD_NAME/build_boot_bin -OUTPUT_DIR=./boards/$BOARD_NAME/output_boot_bin +HDF_FILE=$1 +UBOOT_FILE=$2 +BUILD_DIR=build_boot_bin +OUTPUT_DIR=output_boot_bin -# usage () { -# echo usage: $0 system_top.hdf u-boot.elf [output-archive] -# exit 1 -# } +usage () { + echo "usage: $0 system_top. u-boot.elf [output-archive]" + exit 1 +} -# depends () { -# echo Xilinx $1 must be installed and in your PATH -# echo try: source /opt/Xilinx/Vivado/201x.x/settings64.sh -# exit 1 -# } +depends () { + echo Xilinx $1 must be installed and in your PATH + echo try: source /opt/Xilinx/Vivado/201x.x/settings64.sh + exit 1 +} ### Check command line parameters -echo $HDF_FILE | grep -q ".hdf" || usage -echo $UBOOT_FILE | grep -q -e ".elf" -e "uboot" || usage +echo $HDF_FILE | grep -q ".hdf\|.xsa" || usage +echo $UBOOT_FILE | grep -q -e ".elf" -e "uboot" -e "u-boot"|| usage if [ ! -f $HDF_FILE ]; then - echo $HDF_FILE: File not found! - usage + echo $HDF_FILE: File not found! + usage fi if [ ! -f $UBOOT_FILE ]; then - echo $UBOOT_FILE: File not found! - usage + echo $UBOOT_FILE: File not found! + usage fi -### Check for required Xilinx tools -command -v xsdk >/dev/null 2>&1 || depends xsdk +### Check for required Xilinx tools (xcst is equivalent with 'xsdk -batch') +command -v xsct >/dev/null 2>&1 || depends xsct command -v bootgen >/dev/null 2>&1 || depends bootgen rm -Rf $BUILD_DIR $OUTPUT_DIR @@ -65,14 +43,26 @@ cp $HDF_FILE $BUILD_DIR/ cp $UBOOT_FILE $OUTPUT_DIR/u-boot.elf cp $HDF_FILE $OUTPUT_DIR/ -### Create create_fsbl_project.tcl file used by xsdk to create the fsbl +### Create create_fsbl_project.tcl file used by xsct to create the fsbl. echo "hsi open_hw_design `basename $HDF_FILE`" > $BUILD_DIR/create_fsbl_project.tcl echo 'set cpu_name [lindex [hsi get_cells -filter {IP_TYPE==PROCESSOR}] 0]' >> $BUILD_DIR/create_fsbl_project.tcl -echo 'sdk setws ./build/sdk' >> $BUILD_DIR/create_fsbl_project.tcl -echo "sdk createhw -name hw_0 -hwspec `basename $HDF_FILE`" >> $BUILD_DIR/create_fsbl_project.tcl -echo 'sdk createapp -name fsbl -hwproject hw_0 -proc $cpu_name -os standalone -lang C -app {Zynq FSBL}' >> $BUILD_DIR/create_fsbl_project.tcl -echo 'configapp -app fsbl build-config release' >> $BUILD_DIR/create_fsbl_project.tcl -echo 'sdk projects -build -type all' >> $BUILD_DIR/create_fsbl_project.tcl +### The fsbl creating flow is different starting with 2019.2 Xilinx version +if [[ "$HDF_FILE" =~ ".hdf" ]];then + echo 'sdk setws ./build/sdk' >> $BUILD_DIR/create_fsbl_project.tcl + echo "sdk createhw -name hw_0 -hwspec `basename $HDF_FILE`" >> $BUILD_DIR/create_fsbl_project.tcl + echo 'sdk createapp -name fsbl -hwproject hw_0 -proc $cpu_name -os standalone -lang C -app {Zynq FSBL}' >> $BUILD_DIR/create_fsbl_project.tcl + echo 'configapp -app fsbl build-config release' >> $BUILD_DIR/create_fsbl_project.tcl + echo 'sdk projects -build -type all' >> $BUILD_DIR/create_fsbl_project.tcl + + FSBL_PATH="$BUILD_DIR/build/sdk/fsbl/Release/fsbl.elf" + SYSTEM_TOP_BIT_PATH="$BUILD_DIR/build/sdk/hw_0/system_top.bit" +else + echo 'platform create -name hw0 -hw system_top.xsa -os standalone -out ./build/sdk -proc $cpu_name' >> $BUILD_DIR/create_fsbl_project.tcl + echo 'platform generate' >> $BUILD_DIR/create_fsbl_project.tcl + + FSBL_PATH="$BUILD_DIR/build/sdk/hw0/export/hw0/sw/hw0/boot/fsbl.elf" + SYSTEM_TOP_BIT_PATH="$BUILD_DIR/build/sdk/hw0/hw/system_top.bit" +fi ### Create zynq.bif file used by bootgen echo 'the_ROM_image:' > $OUTPUT_DIR/zynq.bif @@ -85,12 +75,12 @@ echo '}' >> $OUTPUT_DIR/zynq.bif ### Build fsbl.elf ( cd $BUILD_DIR - xsdk -batch -source create_fsbl_project.tcl + xsct create_fsbl_project.tcl ) ### Copy fsbl and system_top.bit into the output folder -cp $BUILD_DIR/build/sdk/fsbl/Release/fsbl.elf $OUTPUT_DIR/fsbl.elf -cp $BUILD_DIR/build/sdk/hw_0/system_top.bit $OUTPUT_DIR/system_top.bit +cp $FSBL_PATH $OUTPUT_DIR/fsbl.elf +cp $SYSTEM_TOP_BIT_PATH $OUTPUT_DIR/system_top.bit ### Build BOOT.BIN ( @@ -98,12 +88,7 @@ cp $BUILD_DIR/build/sdk/hw_0/system_top.bit $OUTPUT_DIR/system_top.bit bootgen -arch zynq -image zynq.bif -o BOOT.BIN -w ) -### clean up BUILD_DIR and copy ILA definition together with .bit into OUTPUT_DIR -( - rm $BUILD_DIR -rf -) - -# ### Optionally tar.gz the entire output folder with the name given in argument 3 -# if [ ${#3} -ne 0 ]; then -# tar czvf $3.tar.gz $OUTPUT_DIR -# fi +### Optionally tar.gz the entire output folder with the name given in argument 3 +if [ ${#3} -ne 0 ]; then + tar czvf $3.tar.gz $OUTPUT_DIR +fi diff --git a/kernel_boot/build_zynqmp_boot_bin.sh b/kernel_boot/build_zynqmp_boot_bin.sh index abe3448..60a9ce7 100755 --- a/kernel_boot/build_zynqmp_boot_bin.sh +++ b/kernel_boot/build_zynqmp_boot_bin.sh @@ -1,10 +1,4 @@ #!/bin/bash - -# Author: Xianjun Jiao -# SPDX-FileCopyrightText: 2019 UGent -# SPDX-License-Identifier: AGPL-3.0-or-later -# https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/software/linux/zynqmp - set -ex HDF_FILE=$1 @@ -14,7 +8,7 @@ BUILD_DIR=build_boot_bin OUTPUT_DIR=output_boot_bin usage () { - echo "usage: $0 system_top.hdf u-boot.elf (download | bl31.elf | ) [output-archive]" + echo "usage: $0 system_top. u-boot.elf (download | bl31.elf | ) [output-archive]" exit 1 } @@ -25,12 +19,14 @@ depends () { } ### Check command line parameters -echo $HDF_FILE | grep -q ".hdf" || usage -echo $UBOOT_FILE | grep -q -e ".elf" -e "uboot" || usage +echo $HDF_FILE | grep -q ".hdf\|.xsa" || usage +echo $UBOOT_FILE | grep -q -e ".elf" -e "uboot" -e "u-boot" || usage if [ ! -f $HDF_FILE ]; then - echo $HDF_FILE: File not found! - usage + echo $HDF_FILE: File not found! + usage +else + if [[ "$HDF_FILE" =~ ".hdf" ]]; then TOOL="xsdk";else TOOL="vitis";fi fi if [ ! -f $UBOOT_FILE ]; then @@ -38,10 +34,10 @@ if [ ! -f $UBOOT_FILE ]; then usage fi -### Check for required Xilinx tools -command -v xsdk >/dev/null 2>&1 || depends xsdk +### Check for required Xilinx tools (starting with 2019.2 there is no hsi anymore) +command -v xsct >/dev/null 2>&1 || depends xsct command -v bootgen >/dev/null 2>&1 || depends bootgen -command -v hsi >/dev/null 2>&1 || depends hsi +if [[ "$HDF_FILE" =~ ".hdf" ]];then (command -v hsi >/dev/null 2>&1 || depends hsi);fi rm -Rf $BUILD_DIR $OUTPUT_DIR mkdir -p $OUTPUT_DIR @@ -51,13 +47,22 @@ mkdir -p $BUILD_DIR # 2018.1 use df4a7e97d57494c7d79de51b1e0e450d982cea98 # 2018.2 use 93a69a5a3bc318027da4af5911124537f4907642 # 2018.3 use 08560c36ea5b6f48b962cb4bd9a79b35bb3d95ce +# 2019.3 use 713dace94b259845fd8eede11061fbd8f039011e +# 2020.1 use bf72e4d494f3be10665b94c0e88766eb2096ef71 +# 2021.2 use 799131a3b063f6f24f87baa74e46906c076aebcd -hsi_ver=$(hsi -version | head -1 | cut -d' ' -f2) -if [ -z "$hsi_ver" ] ; then +tool_version=$($TOOL -version | sed -n '3p' | cut -d' ' -f 3) +if [ -z "$tool_version" ] ; then echo "Could not determine Vivado version" exit 1 fi -atf_version=xilinx-$hsi_ver +atf_version=xilinx-$tool_version + +if [[ "$atf_version" == "xilinx-v2021.1" ]];then atf_version="xlnx_rebase_v2.4_2021.1";fi +if [[ "$atf_version" == "xilinx-v2021.1.1" ]];then atf_version="xlnx_rebase_v2.4_2021.1_update1";fi +if [[ "$atf_version" == "xilinx-v2021.2" ]];then atf_version="xlnx-v2021.2";fi + +if [[ "$4" == "uart1" ]];then console="cadence1";else console="cadence0";fi ### Check if ATF_FILE is .elf or path to arm-trusted-firmware if [ "$ATF_FILE" != "" ] && [ -d $ATF_FILE ]; then @@ -66,7 +71,7 @@ if [ "$ATF_FILE" != "" ] && [ -d $ATF_FILE ]; then cd $ATF_FILE make distclean git checkout $atf_version - make CROSS_COMPILE=aarch64-linux-gnu- PLAT=zynqmp RESET_TO_BL31=1 + make CROSS_COMPILE=aarch64-linux-gnu- PLAT=zynqmp RESET_TO_BL31=1 ZYNQMP_CONSOLE=$console ) cp $ATF_FILE/build/zynqmp/release/bl31/bl31.elf $OUTPUT_DIR/bl31.elf elif [ "$ATF_FILE" == "download" ]; then @@ -76,7 +81,7 @@ elif [ "$ATF_FILE" == "download" ]; then git clone https://github.com/Xilinx/arm-trusted-firmware.git cd arm-trusted-firmware git checkout $atf_version - make CROSS_COMPILE=aarch64-linux-gnu- PLAT=zynqmp RESET_TO_BL31=1 + make CROSS_COMPILE=aarch64-linux-gnu- PLAT=zynqmp RESET_TO_BL31=1 ZYNQMP_CONSOLE=$console ) cp $BUILD_DIR/arm-trusted-firmware/build/zynqmp/release/bl31/bl31.elf $OUTPUT_DIR/bl31.elf else @@ -88,45 +93,52 @@ else cp $ATF_FILE $OUTPUT_DIR/bl31.elf fi -cp $HDF_FILE $BUILD_DIR/ -cp $UBOOT_FILE $OUTPUT_DIR/u-boot.elf -cp $HDF_FILE $OUTPUT_DIR/ +cp "$HDF_FILE" "$BUILD_DIR/" +cp "$UBOOT_FILE" "$OUTPUT_DIR/u-boot.elf" +cp "$HDF_FILE" "$OUTPUT_DIR/" -# get the tools version (e.g., v2018.3) -tool_version=$(hsi -version) -tool_version=${tool_version#hsi\ } -tool_version=${tool_version%\ (64-bit)*} - -# Work-arownd for MPSoC ZCU102 and ZCU106 Evaluation Kits - DDR4 SODIMM change +# Work-around for MPSoC ZCU102 and ZCU106 Evaluation Kits - DDR4 SODIMM change # (https://www.xilinx.com/support/answers/71961.html) if [ $tool_version == "v2018.3" ];then ( -# wget https://www.xilinx.com/Attachment/72113-files.zip -P $BUILD_DIR - cp -P 72113-files.zip $BUILD_DIR + wget https://www.xilinx.com/Attachment/72113-files.zip -P $BUILD_DIR unzip $BUILD_DIR/72113-files.zip -d $BUILD_DIR ) fi -### Create create_fsbl_project.tcl file used by xsdk to create the fsbl +### Create create_fsbl_project.tcl file used by xsct to create the fsbl. echo "hsi open_hw_design `basename $HDF_FILE`" > $BUILD_DIR/create_fsbl_project.tcl echo 'set cpu_name [lindex [hsi get_cells -filter {IP_TYPE==PROCESSOR}] 0]' >> $BUILD_DIR/create_fsbl_project.tcl -echo 'sdk setws ./build/sdk' >> $BUILD_DIR/create_fsbl_project.tcl -echo "sdk createhw -name hw_0 -hwspec `basename $HDF_FILE`" >> $BUILD_DIR/create_fsbl_project.tcl -echo 'sdk createapp -name fsbl -hwproject hw_0 -proc $cpu_name -os standalone -lang C -app {Zynq MP FSBL}' >> $BUILD_DIR/create_fsbl_project.tcl -echo 'configapp -app fsbl build-config release' >> $BUILD_DIR/create_fsbl_project.tcl -if [ $tool_version == "v2018.3" ];then -( - echo "file copy -force xfsbl_ddr_init.c ./build/sdk/fsbl/src" >> $BUILD_DIR/create_fsbl_project.tcl - echo "file copy -force xfsbl_hooks.c ./build/sdk/fsbl/src" >> $BUILD_DIR/create_fsbl_project.tcl - echo "file copy -force xfsbl_hooks.h ./build/sdk/fsbl/src" >> $BUILD_DIR/create_fsbl_project.tcl -) -fi -echo 'sdk projects -build -type all' >> $BUILD_DIR/create_fsbl_project.tcl +### The fsbl creating flow is different starting with 2019.2 Xilinx version +if [[ "$HDF_FILE" =~ ".hdf" ]];then + echo 'sdk setws ./build/sdk' >> $BUILD_DIR/create_fsbl_project.tcl + echo "sdk createhw -name hw_0 -hwspec `basename $HDF_FILE`" >> $BUILD_DIR/create_fsbl_project.tcl + echo 'sdk createapp -name fsbl -hwproject hw_0 -proc $cpu_name -os standalone -lang C -app {Zynq MP FSBL}' >> $BUILD_DIR/create_fsbl_project.tcl + echo 'configapp -app fsbl build-config release' >> $BUILD_DIR/create_fsbl_project.tcl + if [ $tool_version == "v2018.3" ];then + echo "file copy -force xfsbl_ddr_init.c ./build/sdk/fsbl/src" >> $BUILD_DIR/create_fsbl_project.tcl + echo "file copy -force xfsbl_hooks.c ./build/sdk/fsbl/src" >> $BUILD_DIR/create_fsbl_project.tcl + echo "file copy -force xfsbl_hooks.h ./build/sdk/fsbl/src" >> $BUILD_DIR/create_fsbl_project.tcl + fi + echo 'sdk projects -build -type all' >> $BUILD_DIR/create_fsbl_project.tcl -### Create create_pmufw_project.tcl -echo "set hwdsgn [open_hw_design `basename $HDF_FILE`]" > $BUILD_DIR/create_pmufw_project.tcl -echo 'generate_app -hw $hwdsgn -os standalone -proc psu_pmu_0 -app zynqmp_pmufw -sw pmufw -dir pmufw' >> $BUILD_DIR/create_pmufw_project.tcl -echo 'quit' >> $BUILD_DIR/create_pmufw_project.tcl + ### Create create_pmufw_project.tcl + echo "set hwdsgn [open_hw_design `basename $HDF_FILE`]" > $BUILD_DIR/create_pmufw_project.tcl + echo 'generate_app -hw $hwdsgn -os standalone -proc psu_pmu_0 -app zynqmp_pmufw -compile -sw pmufw -dir pmufw' >> $BUILD_DIR/create_pmufw_project.tcl + echo 'quit' >> $BUILD_DIR/create_pmufw_project.tcl + + FSBL_PATH="$BUILD_DIR/build/sdk/fsbl/Release/fsbl.elf" + SYSTEM_TOP_BIT_PATH="$BUILD_DIR/build/sdk/hw_0/system_top.bit" + PMUFW_PATH="$BUILD_DIR/pmufw/executable.elf" +else + # Flow got changed starting with 2019.2 version (when Vitis replaced SDK) and pmufw is generated automatically with fsbl + echo 'platform create -name hw0 -hw system_top.xsa -os standalone -out ./build/sdk -proc $cpu_name' >> $BUILD_DIR/create_fsbl_project.tcl + echo 'platform generate' >> $BUILD_DIR/create_fsbl_project.tcl + + FSBL_PATH="$BUILD_DIR/build/sdk/hw0/export/hw0/sw/hw0/boot/fsbl.elf" + SYSTEM_TOP_BIT_PATH="$BUILD_DIR/build/sdk/hw0/hw/system_top.bit" + PMUFW_PATH="$BUILD_DIR/build/sdk/hw0/export/hw0/sw/hw0/boot/pmufw.elf" +fi ### Create zynq.bif file used by bootgen echo "the_ROM_image:" > $OUTPUT_DIR/zynq.bif @@ -138,22 +150,22 @@ echo "[destination_cpu=a53-0,exception_level=el-3,trustzone] bl31.elf" >> $OUTPU echo "[destination_cpu=a53-0, exception_level=el-2] u-boot.elf" >> $OUTPUT_DIR/zynq.bif echo "}" >> $OUTPUT_DIR/zynq.bif - ### Build fsbl.elf & pmufw.elf ( cd $BUILD_DIR - xsdk -batch -source create_fsbl_project.tcl - hsi -source create_pmufw_project.tcl - ### There was a bug in some vivado version where they build would fail -> check CC_FLAGS - grep "CC_FLAGS :=" pmufw/Makefile | grep -e "-Os" || sed -i '/-mxl-soft-mul/ s/$/ -Os -flto -ffat-lto-objects/' pmufw/Makefile - cd pmufw - make + xsct create_fsbl_project.tcl + if [[ "$HDF_FILE" =~ ".hdf" ]];then + hsi -source create_pmufw_project.tcl + ### There was a bug in some vivado version where they build would fail -> check CC_FLAGS + grep "CC_FLAGS :=" pmufw/Makefile | grep -e "-Os" || sed -i '/-mxl-soft-mul/ s/$/ -Os -flto -ffat-lto-objects/' pmufw/Makefile + cd pmufw + make + fi ) - ### Copy fsbl and system_top.bit into the output folder -cp $BUILD_DIR/build/sdk/fsbl/Release/fsbl.elf $OUTPUT_DIR/fsbl.elf -cp $BUILD_DIR/build/sdk/hw_0/system_top.bit $OUTPUT_DIR/system_top.bit -cp $BUILD_DIR/pmufw/executable.elf $OUTPUT_DIR/pmufw.elf +cp "$FSBL_PATH" "$OUTPUT_DIR/fsbl.elf" +cp "$SYSTEM_TOP_BIT_PATH" "$OUTPUT_DIR/system_top.bit" +cp "$PMUFW_PATH" "$OUTPUT_DIR/pmufw.elf" ### Build BOOT.BIN ( @@ -161,7 +173,11 @@ cp $BUILD_DIR/pmufw/executable.elf $OUTPUT_DIR/pmufw.elf bootgen -arch zynqmp -image zynq.bif -o BOOT.BIN -w ) -### Optionally tar.gz the entire output folder with the name given in argument 3 -if [ ${#4} -ne 0 ]; then - tar czvf $4.tar.gz $OUTPUT_DIR +### Optionally tar.gz the entire output folder with the name given in argument 4/5 +if [[ ( $4 == "uart"* && ${#5} -ne 0 ) ]]; then + tar czvf $5.tar.gz $OUTPUT_DIR +fi + +if [[ ( ${#4} -ne 0 && $4 != "uart"* && ${#5} -eq 0 ) ]]; then + tar czvf $4.tar.gz $OUTPUT_DIR fi diff --git a/kernel_boot/kernel_config b/kernel_boot/kernel_config index 2d072c6..5101414 100644 --- a/kernel_boot/kernel_config +++ b/kernel_boot/kernel_config @@ -1,37 +1,36 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm 4.14.0 Kernel Configuration +# Linux/arm 5.10.0 Kernel Configuration # -CONFIG_ARM=y -CONFIG_ARM_HAS_SG_CHAIN=y -CONFIG_MIGHT_HAVE_PCI=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_HAVE_PROC_CPU=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -CONFIG_RWSEM_XCHGADD_ALGORITHM=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_ARCH_SUPPORTS_UPROBES=y -CONFIG_VECTORS_BASE=0xffff0000 -CONFIG_ARM_PATCH_PHYS_VIRT=y -CONFIG_GENERIC_BUG=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +# CONFIG_KERNEL_ALL_ADI_DRIVERS is not set +# CONFIG_CLK_ALL_ADI_DRIVERS is not set +# CONFIG_HWMON_ALL_ADI_DRIVERS is not set +# CONFIG_IIO_ALL_ADI_DRIVERS is not set +# CONFIG_INPUT_ALL_ADI_DRIVERS is not set +# CONFIG_MEDIA_ALL_ADI_DRIVERS is not set +# CONFIG_USB_ALL_ADI_DRIVERS is not set +# CONFIG_SND_SOC_ALL_ADI_CODECS is not set +CONFIG_CC_VERSION_TEXT="arm-xilinx-linux-gnueabi-gcc.real (GCC) 10.2.0" +CONFIG_CC_IS_GCC=y +CONFIG_GCC_VERSION=100200 +CONFIG_LD_VERSION=235000000 +CONFIG_CLANG_VERSION=0 +CONFIG_LLD_VERSION=0 +CONFIG_CC_CAN_LINK=y +CONFIG_CC_CAN_LINK_STATIC=y +CONFIG_CC_HAS_ASM_GOTO=y +CONFIG_CC_HAS_ASM_INLINE=y CONFIG_IRQ_WORK=y -CONFIG_BUILDTIME_EXTABLE_SORT=y +CONFIG_BUILDTIME_TABLE_SORT=y # # General setup # CONFIG_INIT_ENV_ARG_LIMIT=32 -CONFIG_CROSS_COMPILE="" # CONFIG_COMPILE_TEST is not set CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y +CONFIG_BUILD_SALT="" CONFIG_HAVE_KERNEL_GZIP=y CONFIG_HAVE_KERNEL_LZMA=y CONFIG_HAVE_KERNEL_XZ=y @@ -42,13 +41,14 @@ CONFIG_KERNEL_GZIP=y # CONFIG_KERNEL_XZ is not set # CONFIG_KERNEL_LZO is not set # CONFIG_KERNEL_LZ4 is not set +CONFIG_DEFAULT_INIT="" CONFIG_DEFAULT_HOSTNAME="(none)" CONFIG_SWAP=y CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y # CONFIG_POSIX_MQUEUE is not set +# CONFIG_WATCH_QUEUE is not set CONFIG_CROSS_MEMORY_ATTACH=y -CONFIG_FHANDLE=y CONFIG_USELIB=y # CONFIG_AUDIT is not set CONFIG_HAVE_ARCH_AUDITSYSCALL=y @@ -60,15 +60,18 @@ CONFIG_GENERIC_IRQ_PROBE=y CONFIG_GENERIC_IRQ_SHOW=y CONFIG_GENERIC_IRQ_SHOW_LEVEL=y CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_MIGRATION=y CONFIG_HARDIRQS_SW_RESEND=y CONFIG_IRQ_DOMAIN=y CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_GENERIC_IRQ_IPI=y CONFIG_HANDLE_DOMAIN_IRQ=y -# CONFIG_IRQ_DOMAIN_DEBUG is not set CONFIG_IRQ_FORCED_THREADING=y CONFIG_SPARSE_IRQ=y # CONFIG_GENERIC_IRQ_DEBUGFS is not set -CONFIG_ARCH_CLOCKSOURCE_DATA=y +# end of IRQ subsystem + +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_ARCH_HAS_TICK_BROADCAST=y CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y @@ -82,6 +85,13 @@ CONFIG_HZ_PERIODIC=y # CONFIG_NO_HZ_FULL is not set # CONFIG_NO_HZ is not set CONFIG_HIGH_RES_TIMERS=y +# end of Timers subsystem + +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREEMPT=y +CONFIG_PREEMPT_COUNT=y +CONFIG_PREEMPTION=y # # CPU/Task time and stats accounting @@ -91,24 +101,38 @@ CONFIG_TICK_CPU_ACCOUNTING=y # CONFIG_IRQ_TIME_ACCOUNTING is not set # CONFIG_BSD_PROCESS_ACCT is not set # CONFIG_TASKSTATS is not set +# CONFIG_PSI is not set +# end of CPU/Task time and stats accounting + +CONFIG_CPU_ISOLATION=y # # RCU Subsystem # +CONFIG_TREE_RCU=y CONFIG_PREEMPT_RCU=y # CONFIG_RCU_EXPERT is not set CONFIG_SRCU=y CONFIG_TREE_SRCU=y +CONFIG_TASKS_RCU_GENERIC=y CONFIG_TASKS_RCU=y CONFIG_RCU_STALL_COMMON=y CONFIG_RCU_NEED_SEGCBLIST=y -CONFIG_BUILD_BIN2C=y +# end of RCU Subsystem + CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y +# CONFIG_IKHEADERS is not set CONFIG_LOG_BUF_SHIFT=15 CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 CONFIG_GENERIC_SCHED_CLOCK=y + +# +# Scheduler features +# +# end of Scheduler features + CONFIG_CGROUPS=y # CONFIG_MEMCG is not set # CONFIG_BLK_CGROUP is not set @@ -122,8 +146,8 @@ CONFIG_CGROUPS=y # CONFIG_CGROUP_PERF is not set # CONFIG_CGROUP_DEBUG is not set CONFIG_SOCK_CGROUP_DATA=y -# CONFIG_CHECKPOINT_RESTORE is not set # CONFIG_NAMESPACES is not set +# CONFIG_CHECKPOINT_RESTORE is not set # CONFIG_SCHED_AUTOGROUP is not set # CONFIG_SYSFS_DEPRECATED is not set # CONFIG_RELAY is not set @@ -135,10 +159,12 @@ CONFIG_RD_GZIP=y # CONFIG_RD_XZ is not set # CONFIG_RD_LZO is not set # CONFIG_RD_LZ4 is not set +CONFIG_RD_ZSTD=y +# CONFIG_BOOT_CONFIG is not set CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_LD_ORPHAN_WARN=y CONFIG_SYSCTL=y -CONFIG_ANON_INODES=y CONFIG_HAVE_UID16=y CONFIG_BPF=y CONFIG_EXPERT=y @@ -146,12 +172,8 @@ CONFIG_UID16=y CONFIG_MULTIUSER=y # CONFIG_SGETMASK_SYSCALL is not set CONFIG_SYSFS_SYSCALL=y -CONFIG_SYSCTL_SYSCALL=y +CONFIG_FHANDLE=y CONFIG_POSIX_TIMERS=y -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_ALL is not set -# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set -CONFIG_KALLSYMS_BASE_RELATIVE=y CONFIG_PRINTK=y CONFIG_PRINTK_NMI=y CONFIG_BUG=y @@ -163,12 +185,19 @@ CONFIG_EPOLL=y CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y -# CONFIG_BPF_SYSCALL is not set CONFIG_SHMEM=y CONFIG_AIO=y +CONFIG_IO_URING=y CONFIG_ADVISE_SYSCALLS=y -# CONFIG_USERFAULTFD is not set CONFIG_MEMBARRIER=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +CONFIG_KALLSYMS_BASE_RELATIVE=y +# CONFIG_BPF_SYSCALL is not set +# CONFIG_USERFAULTFD is not set +CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y +CONFIG_RSEQ=y +# CONFIG_DEBUG_RSEQ is not set CONFIG_EMBEDDED=y CONFIG_HAVE_PERF_EVENTS=y CONFIG_PERF_USE_VMALLOC=y @@ -179,6 +208,8 @@ CONFIG_PERF_USE_VMALLOC=y # CONFIG_PERF_EVENTS=y # CONFIG_DEBUG_PERF_USE_VMALLOC is not set +# end of Kernel Performance Events And Counters + CONFIG_VM_EVENT_COUNTERS=y CONFIG_COMPAT_BRK=y CONFIG_SLAB=y @@ -186,147 +217,44 @@ CONFIG_SLAB=y # CONFIG_SLOB is not set CONFIG_SLAB_MERGE_DEFAULT=y # CONFIG_SLAB_FREELIST_RANDOM is not set -# CONFIG_SYSTEM_DATA_VERIFICATION is not set +# CONFIG_SLAB_FREELIST_HARDENED is not set +# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set +CONFIG_SYSTEM_DATA_VERIFICATION=y # CONFIG_PROFILING is not set -CONFIG_HAVE_OPROFILE=y -# CONFIG_KPROBES is not set -# CONFIG_JUMP_LABEL is not set -# CONFIG_UPROBES is not set -# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set -CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y -CONFIG_ARCH_USE_BUILTIN_BSWAP=y -CONFIG_HAVE_KPROBES=y -CONFIG_HAVE_KRETPROBES=y -CONFIG_HAVE_OPTPROBES=y -CONFIG_HAVE_NMI=y -CONFIG_HAVE_ARCH_TRACEHOOK=y -CONFIG_HAVE_DMA_CONTIGUOUS=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_ARCH_HAS_SET_MEMORY=y -CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y -CONFIG_HAVE_CLK=y -CONFIG_HAVE_DMA_API_DEBUG=y -CONFIG_HAVE_HW_BREAKPOINT=y -CONFIG_HAVE_PERF_REGS=y -CONFIG_HAVE_PERF_USER_STACK_DUMP=y -CONFIG_HAVE_ARCH_JUMP_LABEL=y -CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y -CONFIG_HAVE_ARCH_SECCOMP_FILTER=y -CONFIG_HAVE_GCC_PLUGINS=y -# CONFIG_GCC_PLUGINS is not set -CONFIG_HAVE_CC_STACKPROTECTOR=y -# CONFIG_CC_STACKPROTECTOR is not set -CONFIG_CC_STACKPROTECTOR_NONE=y -# CONFIG_CC_STACKPROTECTOR_REGULAR is not set -# CONFIG_CC_STACKPROTECTOR_STRONG is not set -CONFIG_THIN_ARCHIVES=y -CONFIG_HAVE_CONTEXT_TRACKING=y -CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y -CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y -CONFIG_HAVE_MOD_ARCH_SPECIFIC=y -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_ARCH_HAS_ELF_RANDOMIZE=y -CONFIG_HAVE_ARCH_MMAP_RND_BITS=y -CONFIG_HAVE_EXIT_THREAD=y -CONFIG_ARCH_MMAP_RND_BITS_MIN=8 -CONFIG_ARCH_MMAP_RND_BITS_MAX=16 -CONFIG_ARCH_MMAP_RND_BITS=8 -# CONFIG_HAVE_ARCH_HASH is not set -# CONFIG_ISA_BUS_API is not set -CONFIG_CLONE_BACKWARDS=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_OLD_SIGACTION=y -# CONFIG_CPU_NO_EFFICIENT_FFS is not set -# CONFIG_HAVE_ARCH_VMAP_STACK is not set -CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y -CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y -CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y -CONFIG_STRICT_KERNEL_RWX=y -CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y -CONFIG_STRICT_MODULE_RWX=y -# CONFIG_REFCOUNT_FULL is not set +# end of General setup -# -# GCOV-based kernel profiling -# -# CONFIG_GCOV_KERNEL is not set -CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y -CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_SLABINFO=y -CONFIG_RT_MUTEXES=y -CONFIG_BASE_SMALL=0 -CONFIG_MODULES=y -# CONFIG_MODULE_FORCE_LOAD is not set -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_MODVERSIONS=y -# CONFIG_MODULE_SRCVERSION_ALL is not set -# CONFIG_MODULE_SIG is not set -# CONFIG_MODULE_COMPRESS is not set -# CONFIG_TRIM_UNUSED_KSYMS is not set -CONFIG_MODULES_TREE_LOOKUP=y -CONFIG_BLOCK=y -CONFIG_LBDAF=y -CONFIG_BLK_SCSI_REQUEST=y -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_BLK_DEV_BSGLIB is not set -# CONFIG_BLK_DEV_INTEGRITY is not set -# CONFIG_BLK_DEV_ZONED is not set -# CONFIG_BLK_CMDLINE_PARSER is not set -# CONFIG_BLK_WBT is not set -CONFIG_BLK_DEBUG_FS=y -# CONFIG_BLK_SED_OPAL is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y -CONFIG_EFI_PARTITION=y - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -# CONFIG_DEFAULT_DEADLINE is not set -CONFIG_DEFAULT_CFQ=y -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="cfq" -CONFIG_MQ_IOSCHED_DEADLINE=y -CONFIG_MQ_IOSCHED_KYBER=y -# CONFIG_IOSCHED_BFQ is not set -CONFIG_UNINLINE_SPIN_UNLOCK=y -CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_FREEZER=y +CONFIG_ARM=y +CONFIG_ARM_HAS_SG_CHAIN=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_GENERIC_BUG=y +CONFIG_PGTABLE_LEVELS=2 # # System Type # CONFIG_MMU=y +CONFIG_ARCH_MMAP_RND_BITS_MIN=8 +CONFIG_ARCH_MMAP_RND_BITS_MAX=16 CONFIG_ARCH_MULTIPLATFORM=y # CONFIG_ARCH_EBSA110 is not set # CONFIG_ARCH_EP93XX is not set # CONFIG_ARCH_FOOTBRIDGE is not set -# CONFIG_ARCH_NETX is not set -# CONFIG_ARCH_IOP13XX is not set # CONFIG_ARCH_IOP32X is not set -# CONFIG_ARCH_IOP33X is not set # CONFIG_ARCH_IXP4XX is not set # CONFIG_ARCH_DOVE is not set -# CONFIG_ARCH_KS8695 is not set -# CONFIG_ARCH_W90X900 is not set -# CONFIG_ARCH_LPC32XX is not set # CONFIG_ARCH_PXA is not set # CONFIG_ARCH_RPC is not set # CONFIG_ARCH_SA1100 is not set # CONFIG_ARCH_S3C24XX is not set -# CONFIG_ARCH_DAVINCI is not set # CONFIG_ARCH_OMAP1 is not set # @@ -339,22 +267,29 @@ CONFIG_ARCH_MULTIPLATFORM=y # CONFIG_ARCH_MULTI_V6 is not set CONFIG_ARCH_MULTI_V7=y CONFIG_ARCH_MULTI_V6_V7=y -# CONFIG_ARCH_MULTI_CPU_AUTO is not set +# end of Multiple platform selection + # CONFIG_ARCH_VIRT is not set -# CONFIG_ARCH_MVEBU is not set # CONFIG_ARCH_ACTIONS is not set # CONFIG_ARCH_ALPINE is not set # CONFIG_ARCH_ARTPEC is not set +# CONFIG_ARCH_ASPEED is not set # CONFIG_ARCH_AT91 is not set # CONFIG_ARCH_BCM is not set # CONFIG_ARCH_BERLIN is not set # CONFIG_ARCH_DIGICOLOR is not set +# CONFIG_ARCH_EXYNOS is not set # CONFIG_ARCH_HIGHBANK is not set # CONFIG_ARCH_HISI is not set -# CONFIG_ARCH_KEYSTONE is not set -# CONFIG_ARCH_MESON is not set # CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_KEYSTONE is not set # CONFIG_ARCH_MEDIATEK is not set +# CONFIG_ARCH_MESON is not set +# CONFIG_ARCH_MILBEAUT is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_MSTARV7 is not set +# CONFIG_ARCH_MVEBU is not set +# CONFIG_ARCH_NPCM is not set # # TI OMAP/AM/DM/DRA Family @@ -365,18 +300,21 @@ CONFIG_ARCH_MULTI_V6_V7=y # CONFIG_SOC_AM33XX is not set # CONFIG_SOC_AM43XX is not set # CONFIG_SOC_DRA7XX is not set -# CONFIG_ARCH_MMP is not set +# end of TI OMAP/AM/DM/DRA Family + +# CONFIG_ARCH_SIRF is not set # CONFIG_ARCH_QCOM is not set +# CONFIG_ARCH_RDA is not set +# CONFIG_ARCH_REALTEK is not set # CONFIG_ARCH_REALVIEW is not set # CONFIG_ARCH_ROCKCHIP is not set +# CONFIG_ARCH_S5PV210 is not set +# CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SOCFPGA is not set # CONFIG_PLAT_SPEAR is not set # CONFIG_ARCH_STI is not set -# CONFIG_ARCH_S5PV210 is not set -# CONFIG_ARCH_EXYNOS is not set -# CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_STM32 is not set # CONFIG_ARCH_SUNXI is not set -# CONFIG_ARCH_SIRF is not set # CONFIG_ARCH_TANGO is not set # CONFIG_ARCH_TEGRA is not set # CONFIG_ARCH_UNIPHIER is not set @@ -391,6 +329,7 @@ CONFIG_ARCH_ZYNQ=y # CONFIG_XILINX_PREFETCH=y # CONFIG_XILINX_RESET_CODE is not set +# end of Xilinx Specific Options # # Processor Type @@ -413,14 +352,16 @@ CONFIG_CPU_CP15_MMU=y # Processor Features # # CONFIG_ARM_LPAE is not set -# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_ARM_THUMB=y # CONFIG_ARM_THUMBEE is not set CONFIG_ARM_VIRT_EXT=y CONFIG_SWP_EMULATE=y # CONFIG_CPU_BIG_ENDIAN is not set # CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND is not set # CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_CPU_SPECTRE=y +CONFIG_HARDEN_BRANCH_PREDICTOR=y CONFIG_KUSER_HELPERS=y # CONFIG_VDSO is not set CONFIG_OUTER_CACHE=y @@ -438,7 +379,6 @@ CONFIG_ARM_DMA_MEM_BUFFERABLE=y CONFIG_ARM_HEAVY_MB=y CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y CONFIG_DEBUG_ALIGN_RODATA=y -CONFIG_MULTI_IRQ_HANDLER=y # CONFIG_ARM_ERRATA_430973 is not set # CONFIG_ARM_ERRATA_643719 is not set # CONFIG_ARM_ERRATA_720789 is not set @@ -451,25 +391,17 @@ CONFIG_ARM_ERRATA_775420=y # CONFIG_ARM_ERRATA_818325_852422 is not set # CONFIG_ARM_ERRATA_821420 is not set # CONFIG_ARM_ERRATA_825619 is not set +# CONFIG_ARM_ERRATA_857271 is not set # CONFIG_ARM_ERRATA_852421 is not set # CONFIG_ARM_ERRATA_852423 is not set +# CONFIG_ARM_ERRATA_857272 is not set +# end of System Type # # Bus support # -# CONFIG_PCI is not set -# CONFIG_PCI_DOMAINS_GENERIC is not set -# CONFIG_PCI_SYSCALL is not set - -# -# DesignWare PCI Core Support -# - -# -# PCI Endpoint -# -# CONFIG_PCI_ENDPOINT is not set -# CONFIG_PCCARD is not set +# CONFIG_ARM_ERRATA_814220 is not set +# end of Bus support # # Kernel Features @@ -494,10 +426,6 @@ CONFIG_NR_CPUS=4 CONFIG_HOTPLUG_CPU=y # CONFIG_ARM_PSCI is not set CONFIG_ARCH_NR_GPIO=1024 -# CONFIG_PREEMPT_NONE is not set -# CONFIG_PREEMPT_VOLUNTARY is not set -CONFIG_PREEMPT=y -CONFIG_PREEMPT_COUNT=y CONFIG_HZ_FIXED=0 CONFIG_HZ_100=y # CONFIG_HZ_200 is not set @@ -511,8 +439,9 @@ CONFIG_SCHED_HRTICK=y CONFIG_ARM_PATCH_IDIV=y CONFIG_AEABI=y # CONFIG_OABI_COMPAT is not set -# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set -# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y CONFIG_HAVE_ARCH_PFN_VALID=y CONFIG_HIGHMEM=y # CONFIG_HIGHPTE is not set @@ -520,42 +449,13 @@ CONFIG_CPU_SW_DOMAIN_PAN=y CONFIG_HW_PERF_EVENTS=y CONFIG_ARCH_WANT_GENERAL_HUGETLB=y # CONFIG_ARM_MODULE_PLTS is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -CONFIG_HAVE_MEMBLOCK=y -CONFIG_NO_BOOTMEM=y -CONFIG_MEMORY_ISOLATION=y -# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set -CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_COMPACTION is not set -CONFIG_MIGRATION=y -# CONFIG_PHYS_ADDR_T_64BIT is not set -CONFIG_BOUNCE=y -# CONFIG_KSM is not set -CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 -# CONFIG_ARCH_WANTS_THP_SWAP is not set -# CONFIG_CLEANCACHE is not set -# CONFIG_FRONTSWAP is not set -CONFIG_CMA=y -# CONFIG_CMA_DEBUG is not set -# CONFIG_CMA_DEBUGFS is not set -CONFIG_CMA_AREAS=7 -# CONFIG_ZPOOL is not set -# CONFIG_ZBUD is not set -# CONFIG_ZSMALLOC is not set -CONFIG_GENERIC_EARLY_IOREMAP=y -# CONFIG_IDLE_PAGE_TRACKING is not set -CONFIG_FRAME_VECTOR=y -# CONFIG_PERCPU_STATS is not set CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_ALIGNMENT_TRAP=y # CONFIG_UACCESS_WITH_MEMCPY is not set -# CONFIG_SECCOMP is not set -CONFIG_SWIOTLB=y -CONFIG_IOMMU_HELPER=y # CONFIG_PARAVIRT is not set # CONFIG_PARAVIRT_TIME_ACCOUNTING is not set # CONFIG_XEN is not set +# end of Kernel Features # # Boot options @@ -574,6 +474,7 @@ CONFIG_CMDLINE_FROM_BOOTLOADER=y # CONFIG_CRASH_DUMP is not set CONFIG_AUTO_ZRELADDR=y # CONFIG_EFI is not set +# end of Boot options # # CPU Power Management @@ -583,6 +484,7 @@ CONFIG_AUTO_ZRELADDR=y # CPU Frequency scaling # # CONFIG_CPU_FREQ is not set +# end of CPU Frequency scaling # # CPU Idle @@ -590,13 +492,16 @@ CONFIG_AUTO_ZRELADDR=y CONFIG_CPU_IDLE=y CONFIG_CPU_IDLE_GOV_LADDER=y CONFIG_CPU_IDLE_GOV_MENU=y +# CONFIG_CPU_IDLE_GOV_TEO is not set # # ARM CPU Idle Drivers # # CONFIG_ARM_CPUIDLE is not set CONFIG_ARM_ZYNQ_CPUIDLE=y -# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set +# end of ARM CPU Idle Drivers +# end of CPU Idle +# end of CPU Power Management # # Floating point emulation @@ -609,18 +514,7 @@ CONFIG_VFP=y CONFIG_VFPv3=y CONFIG_NEON=y # CONFIG_KERNEL_MODE_NEON is not set - -# -# Userspace binary formats -# -CONFIG_BINFMT_ELF=y -CONFIG_ELFCORE=y -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -CONFIG_BINFMT_SCRIPT=y -# CONFIG_BINFMT_FLAT is not set -# CONFIG_HAVE_AOUT is not set -# CONFIG_BINFMT_MISC is not set -CONFIG_COREDUMP=y +# end of Floating point emulation # # Power management options @@ -642,8 +536,200 @@ CONFIG_CPU_PM=y CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_ARM_CPU_SUSPEND=y CONFIG_ARCH_HIBERNATION_POSSIBLE=y +# end of Power management options + +# +# Firmware Drivers +# +# CONFIG_FIRMWARE_MEMMAP is not set +# CONFIG_FW_CFG_SYSFS is not set +# CONFIG_TRUSTED_FOUNDATIONS is not set +# CONFIG_GOOGLE_FIRMWARE is not set +CONFIG_HAVE_ARM_SMCCC=y + +# +# Tegra firmware driver +# +# end of Tegra firmware driver +# end of Firmware Drivers + +# CONFIG_ARM_CRYPTO is not set +CONFIG_AS_VFP_VMRS_FPINST=y + +# +# General architecture-dependent options +# +CONFIG_SET_FS=y +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +# CONFIG_JUMP_LABEL is not set +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_OPTPROBES=y +CONFIG_HAVE_NMI=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_ARCH_HAS_FORTIFY_SOURCE=y +CONFIG_ARCH_HAS_KEEPINITRD=y +CONFIG_ARCH_HAS_SET_MEMORY=y +CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y +CONFIG_ARCH_32BIT_OFF_T=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_RSEQ=y +CONFIG_HAVE_HW_BREAKPOINT=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_HAVE_ARCH_SECCOMP=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +# CONFIG_SECCOMP is not set +CONFIG_HAVE_STACKPROTECTOR=y +CONFIG_STACKPROTECTOR=y +CONFIG_STACKPROTECTOR_STRONG=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_HAVE_ARCH_MMAP_RND_BITS=y +CONFIG_HAVE_EXIT_THREAD=y +CONFIG_ARCH_MMAP_RND_BITS=8 +CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_OLD_SIGACTION=y +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y +CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y +CONFIG_STRICT_KERNEL_RWX=y +CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y +CONFIG_STRICT_MODULE_RWX=y +CONFIG_ARCH_HAS_PHYS_TO_DMA=y +# CONFIG_LOCK_EVENT_COUNTS is not set +CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +# end of GCOV-based kernel profiling + +CONFIG_HAVE_GCC_PLUGINS=y +# end of General architecture-dependent options + +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_MODULE_SIG is not set +# CONFIG_MODULE_COMPRESS is not set +# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_TRIM_UNUSED_KSYMS is not set +CONFIG_MODULES_TREE_LOOKUP=y +CONFIG_BLOCK=y +CONFIG_BLK_SCSI_REQUEST=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_BSGLIB is not set +# CONFIG_BLK_DEV_INTEGRITY is not set +# CONFIG_BLK_DEV_ZONED is not set +# CONFIG_BLK_CMDLINE_PARSER is not set +# CONFIG_BLK_WBT is not set +CONFIG_BLK_DEBUG_FS=y +# CONFIG_BLK_SED_OPAL is not set +# CONFIG_BLK_INLINE_ENCRYPTION is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_EFI_PARTITION=y +# end of Partition Types + +CONFIG_BLK_PM=y + +# +# IO Schedulers +# +CONFIG_MQ_IOSCHED_DEADLINE=y +CONFIG_MQ_IOSCHED_KYBER=y +# CONFIG_IOSCHED_BFQ is not set +# end of IO Schedulers + +CONFIG_ASN1=y +CONFIG_UNINLINE_SPIN_UNLOCK=y +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y +CONFIG_FREEZER=y + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_ELF_FDPIC is not set +CONFIG_ELFCORE=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_BINFMT_SCRIPT=y +CONFIG_ARCH_HAS_BINFMT_FLAT=y +# CONFIG_BINFMT_FLAT is not set +CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y +# CONFIG_BINFMT_MISC is not set +CONFIG_COREDUMP=y +# end of Executable file formats + +# +# Memory Management options +# +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_MEMORY_ISOLATION=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_COMPACTION is not set +# CONFIG_PAGE_REPORTING is not set +CONFIG_MIGRATION=y +CONFIG_CONTIG_ALLOC=y +CONFIG_BOUNCE=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +# CONFIG_CLEANCACHE is not set +# CONFIG_FRONTSWAP is not set +CONFIG_CMA=y +# CONFIG_CMA_DEBUG is not set +# CONFIG_CMA_DEBUGFS is not set +CONFIG_CMA_AREAS=7 +# CONFIG_ZPOOL is not set +# CONFIG_ZBUD is not set +# CONFIG_ZSMALLOC is not set +CONFIG_GENERIC_EARLY_IOREMAP=y +# CONFIG_IDLE_PAGE_TRACKING is not set +CONFIG_FRAME_VECTOR=y +# CONFIG_PERCPU_STATS is not set +# CONFIG_GUP_BENCHMARK is not set +# end of Memory Management options + CONFIG_NET=y CONFIG_NET_INGRESS=y +CONFIG_SKB_EXTENSIONS=y # # Networking options @@ -651,10 +737,12 @@ CONFIG_NET_INGRESS=y CONFIG_PACKET=y # CONFIG_PACKET_DIAG is not set CONFIG_UNIX=y +CONFIG_UNIX_SCM=y # CONFIG_UNIX_DIAG is not set # CONFIG_TLS is not set CONFIG_XFRM=y # CONFIG_XFRM_USER is not set +# CONFIG_XFRM_INTERFACE is not set # CONFIG_XFRM_SUB_POLICY is not set # CONFIG_XFRM_MIGRATE is not set # CONFIG_XFRM_STATISTICS is not set @@ -670,22 +758,18 @@ CONFIG_IP_PNP_RARP=y CONFIG_NET_IPIP=m # CONFIG_NET_IPGRE_DEMUX is not set CONFIG_NET_IP_TUNNEL=m +CONFIG_IP_MROUTE_COMMON=y CONFIG_IP_MROUTE=y CONFIG_IP_PIMSM_V1=y CONFIG_IP_PIMSM_V2=y CONFIG_SYN_COOKIES=y CONFIG_NET_IPVTI=m -# CONFIG_NET_UDP_TUNNEL is not set # CONFIG_NET_FOU is not set # CONFIG_NET_FOU_IP_TUNNELS is not set # CONFIG_INET_AH is not set # CONFIG_INET_ESP is not set # CONFIG_INET_IPCOMP is not set -# CONFIG_INET_XFRM_TUNNEL is not set CONFIG_INET_TUNNEL=m -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y CONFIG_INET_DIAG=y CONFIG_INET_TCP_DIAG=y CONFIG_INET_UDP_DIAG=m @@ -720,25 +804,19 @@ CONFIG_IPV6=m # CONFIG_INET6_IPCOMP is not set # CONFIG_IPV6_MIP6 is not set # CONFIG_IPV6_ILA is not set -# CONFIG_INET6_XFRM_TUNNEL is not set -# CONFIG_INET6_TUNNEL is not set -CONFIG_INET6_XFRM_MODE_TRANSPORT=m -CONFIG_INET6_XFRM_MODE_TUNNEL=m -CONFIG_INET6_XFRM_MODE_BEET=m -# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set # CONFIG_IPV6_VTI is not set CONFIG_IPV6_SIT=m # CONFIG_IPV6_SIT_6RD is not set CONFIG_IPV6_NDISC_NODETYPE=y # CONFIG_IPV6_TUNNEL is not set -# CONFIG_IPV6_FOU is not set -# CONFIG_IPV6_FOU_TUNNEL is not set # CONFIG_IPV6_MULTIPLE_TABLES is not set CONFIG_IPV6_MROUTE=y CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y CONFIG_IPV6_PIMSM_V2=y # CONFIG_IPV6_SEG6_LWTUNNEL is not set # CONFIG_IPV6_SEG6_HMAC is not set +# CONFIG_IPV6_RPL_LWTUNNEL is not set +# CONFIG_MPTCP is not set # CONFIG_NETWORK_SECMARK is not set CONFIG_NET_PTP_CLASSIFY=y # CONFIG_NETWORK_PHY_TIMESTAMPING is not set @@ -751,12 +829,16 @@ CONFIG_BRIDGE_NETFILTER=m # CONFIG_NETFILTER_INGRESS=y CONFIG_NETFILTER_NETLINK=y +CONFIG_NETFILTER_FAMILY_BRIDGE=y +CONFIG_NETFILTER_FAMILY_ARP=y CONFIG_NETFILTER_NETLINK_ACCT=y CONFIG_NETFILTER_NETLINK_QUEUE=y CONFIG_NETFILTER_NETLINK_LOG=y +CONFIG_NETFILTER_NETLINK_OSF=y CONFIG_NF_CONNTRACK=y CONFIG_NF_LOG_COMMON=y CONFIG_NF_LOG_NETDEV=y +CONFIG_NETFILTER_CONNCOUNT=y CONFIG_NF_CONNTRACK_MARK=y # CONFIG_NF_CONNTRACK_ZONES is not set CONFIG_NF_CONNTRACK_PROCFS=y @@ -784,34 +866,27 @@ CONFIG_NF_CT_NETLINK_TIMEOUT=y CONFIG_NF_CT_NETLINK_HELPER=y CONFIG_NETFILTER_NETLINK_GLUE_CT=y CONFIG_NF_NAT=y -CONFIG_NF_NAT_NEEDED=y -CONFIG_NF_NAT_PROTO_DCCP=y -CONFIG_NF_NAT_PROTO_UDPLITE=y -CONFIG_NF_NAT_PROTO_SCTP=y CONFIG_NF_NAT_AMANDA=y CONFIG_NF_NAT_FTP=y CONFIG_NF_NAT_IRC=y CONFIG_NF_NAT_SIP=y CONFIG_NF_NAT_TFTP=y CONFIG_NF_NAT_REDIRECT=y +CONFIG_NF_NAT_MASQUERADE=y CONFIG_NETFILTER_SYNPROXY=y CONFIG_NF_TABLES=y # CONFIG_NF_TABLES_INET is not set CONFIG_NF_TABLES_NETDEV=y -CONFIG_NFT_EXTHDR=y -CONFIG_NFT_META=y -CONFIG_NFT_RT=y CONFIG_NFT_NUMGEN=y CONFIG_NFT_CT=y -CONFIG_NFT_SET_RBTREE=y -CONFIG_NFT_SET_HASH=y -CONFIG_NFT_SET_BITMAP=y CONFIG_NFT_COUNTER=y +# CONFIG_NFT_CONNLIMIT is not set CONFIG_NFT_LOG=y CONFIG_NFT_LIMIT=y CONFIG_NFT_MASQ=y CONFIG_NFT_REDIR=y CONFIG_NFT_NAT=y +# CONFIG_NFT_TUNNEL is not set CONFIG_NFT_OBJREF=y CONFIG_NFT_QUEUE=m CONFIG_NFT_QUOTA=y @@ -819,10 +894,15 @@ CONFIG_NFT_REJECT=y CONFIG_NFT_COMPAT=y CONFIG_NFT_HASH=y CONFIG_NFT_FIB=y +# CONFIG_NFT_XFRM is not set +# CONFIG_NFT_SOCKET is not set +# CONFIG_NFT_OSF is not set +# CONFIG_NFT_TPROXY is not set +# CONFIG_NFT_SYNPROXY is not set CONFIG_NF_DUP_NETDEV=y CONFIG_NFT_DUP_NETDEV=y CONFIG_NFT_FWD_NETDEV=y -# CONFIG_NFT_FIB_NETDEV is not set +# CONFIG_NF_FLOW_TABLE is not set CONFIG_NETFILTER_XTABLES=y # @@ -852,6 +932,7 @@ CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y CONFIG_NETFILTER_XT_TARGET_NOTRACK=y CONFIG_NETFILTER_XT_TARGET_RATEEST=y CONFIG_NETFILTER_XT_TARGET_REDIRECT=y +CONFIG_NETFILTER_XT_TARGET_MASQUERADE=y CONFIG_NETFILTER_XT_TARGET_TEE=m CONFIG_NETFILTER_XT_TARGET_TPROXY=m CONFIG_NETFILTER_XT_TARGET_TRACE=y @@ -906,6 +987,8 @@ CONFIG_NETFILTER_XT_MATCH_STRING=y CONFIG_NETFILTER_XT_MATCH_TCPMSS=y CONFIG_NETFILTER_XT_MATCH_TIME=y CONFIG_NETFILTER_XT_MATCH_U32=y +# end of Core Netfilter Configuration + # CONFIG_IP_SET is not set # CONFIG_IP_VS is not set @@ -913,10 +996,9 @@ CONFIG_NETFILTER_XT_MATCH_U32=y # IP: Netfilter Configuration # CONFIG_NF_DEFRAG_IPV4=y -CONFIG_NF_CONNTRACK_IPV4=y CONFIG_NF_SOCKET_IPV4=y +CONFIG_NF_TPROXY_IPV4=m CONFIG_NF_TABLES_IPV4=y -CONFIG_NFT_CHAIN_ROUTE_IPV4=y CONFIG_NFT_REJECT_IPV4=y CONFIG_NFT_DUP_IPV4=y CONFIG_NFT_FIB_IPV4=y @@ -925,13 +1007,7 @@ CONFIG_NF_DUP_IPV4=y CONFIG_NF_LOG_ARP=y CONFIG_NF_LOG_IPV4=y CONFIG_NF_REJECT_IPV4=y -CONFIG_NF_NAT_IPV4=y -CONFIG_NFT_CHAIN_NAT_IPV4=y -CONFIG_NF_NAT_MASQUERADE_IPV4=y -CONFIG_NFT_MASQ_IPV4=y -CONFIG_NFT_REDIR_IPV4=y CONFIG_NF_NAT_SNMP_BASIC=y -CONFIG_NF_NAT_PROTO_GRE=y CONFIG_NF_NAT_PPTP=y CONFIG_NF_NAT_H323=m CONFIG_IP_NF_IPTABLES=y @@ -954,22 +1030,17 @@ CONFIG_IP_NF_RAW=y CONFIG_IP_NF_ARPTABLES=y CONFIG_IP_NF_ARPFILTER=y CONFIG_IP_NF_ARP_MANGLE=y +# end of IP: Netfilter Configuration # # IPv6: Netfilter Configuration # -CONFIG_NF_DEFRAG_IPV6=m -CONFIG_NF_CONNTRACK_IPV6=m CONFIG_NF_SOCKET_IPV6=m -CONFIG_NF_TABLES_IPV6=m -CONFIG_NFT_CHAIN_ROUTE_IPV6=m -CONFIG_NFT_REJECT_IPV6=m -CONFIG_NFT_DUP_IPV6=m -CONFIG_NFT_FIB_IPV6=m +CONFIG_NF_TPROXY_IPV6=m +# CONFIG_NF_TABLES_IPV6 is not set CONFIG_NF_DUP_IPV6=m CONFIG_NF_REJECT_IPV6=m CONFIG_NF_LOG_IPV6=m -# CONFIG_NF_NAT_IPV6 is not set CONFIG_IP6_NF_IPTABLES=m CONFIG_IP6_NF_MATCH_AH=m CONFIG_IP6_NF_MATCH_EUI64=m @@ -980,6 +1051,7 @@ CONFIG_IP6_NF_MATCH_IPV6HEADER=m CONFIG_IP6_NF_MATCH_MH=m # CONFIG_IP6_NF_MATCH_RPFILTER is not set CONFIG_IP6_NF_MATCH_RT=m +# CONFIG_IP6_NF_MATCH_SRH is not set # CONFIG_IP6_NF_TARGET_HL is not set CONFIG_IP6_NF_FILTER=m # CONFIG_IP6_NF_TARGET_REJECT is not set @@ -987,8 +1059,13 @@ CONFIG_IP6_NF_TARGET_SYNPROXY=m CONFIG_IP6_NF_MANGLE=m CONFIG_IP6_NF_RAW=m # CONFIG_IP6_NF_NAT is not set +# end of IPv6: Netfilter Configuration + +CONFIG_NF_DEFRAG_IPV6=y # CONFIG_NF_TABLES_BRIDGE is not set +# CONFIG_NF_CONNTRACK_BRIDGE is not set # CONFIG_BRIDGE_NF_EBTABLES is not set +# CONFIG_BPFILTER is not set # CONFIG_IP_DCCP is not set # CONFIG_IP_SCTP is not set # CONFIG_RDS is not set @@ -999,6 +1076,7 @@ CONFIG_STP=m CONFIG_BRIDGE=m CONFIG_BRIDGE_IGMP_SNOOPING=y CONFIG_BRIDGE_VLAN_FILTERING=y +# CONFIG_BRIDGE_MRP is not set CONFIG_HAVE_NET_DSA=y # CONFIG_NET_DSA is not set CONFIG_VLAN_8021Q=m @@ -1007,7 +1085,6 @@ CONFIG_VLAN_8021Q=m # CONFIG_DECNET is not set CONFIG_LLC=m # CONFIG_LLC2 is not set -# CONFIG_IPX is not set # CONFIG_ATALK is not set # CONFIG_X25 is not set # CONFIG_LAPB is not set @@ -1016,6 +1093,7 @@ CONFIG_LLC=m # CONFIG_IEEE802154 is not set # CONFIG_NET_SCHED is not set # CONFIG_DCB is not set +# CONFIG_DNS_RESOLVER is not set # CONFIG_BATMAN_ADV is not set # CONFIG_OPENVSWITCH is not set # CONFIG_VSOCKETS is not set @@ -1025,6 +1103,7 @@ CONFIG_LLC=m # CONFIG_HSR is not set # CONFIG_NET_SWITCHDEV is not set # CONFIG_NET_L3_MASTER_DEV is not set +# CONFIG_QRTR is not set # CONFIG_NET_NCSI is not set CONFIG_RPS=y CONFIG_RFS_ACCEL=y @@ -1040,12 +1119,14 @@ CONFIG_NET_FLOW_LIMIT=y # Network testing # # CONFIG_NET_PKTGEN is not set +# end of Network testing +# end of Networking options + # CONFIG_HAMRADIO is not set # CONFIG_CAN is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set # CONFIG_AF_KCM is not set -# CONFIG_STREAM_PARSER is not set CONFIG_FIB_RULES=y CONFIG_WIRELESS=y CONFIG_WEXT_CORE=y @@ -1054,17 +1135,15 @@ CONFIG_CFG80211=m CONFIG_NL80211_TESTMODE=y CONFIG_CFG80211_DEVELOPER_WARNINGS=y # CONFIG_CFG80211_CERTIFICATION_ONUS is not set +CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y +CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y CONFIG_CFG80211_DEFAULT_PS=y CONFIG_CFG80211_DEBUGFS=y -# CONFIG_CFG80211_INTERNAL_REGDB is not set CONFIG_CFG80211_CRDA_SUPPORT=y CONFIG_CFG80211_WEXT=y -# CONFIG_LIB80211 is not set CONFIG_MAC80211=m CONFIG_MAC80211_HAS_RC=y CONFIG_MAC80211_RC_MINSTREL=y -CONFIG_MAC80211_RC_MINSTREL_HT=y -CONFIG_MAC80211_RC_MINSTREL_VHT=y CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y CONFIG_MAC80211_RC_DEFAULT="minstrel_ht" CONFIG_MAC80211_MESH=y @@ -1103,14 +1182,17 @@ CONFIG_RFKILL_LEDS=y # CONFIG_LWTUNNEL is not set CONFIG_DST_CACHE=y CONFIG_GRO_CELLS=y -# CONFIG_NET_DEVLINK is not set -CONFIG_MAY_USE_DEVLINK=y +# CONFIG_FAILOVER is not set +CONFIG_ETHTOOL_NETLINK=y CONFIG_HAVE_EBPF_JIT=y # # Device Drivers # CONFIG_ARM_AMBA=y +CONFIG_HAVE_PCI=y +# CONFIG_PCI is not set +# CONFIG_PCCARD is not set # # Generic Driver Options @@ -1121,18 +1203,23 @@ CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y + +# +# Firmware loader +# CONFIG_FW_LOADER=y -CONFIG_FIRMWARE_IN_KERNEL=y CONFIG_EXTRA_FIRMWARE="ad9467_intbypass_ad9517.stp ad9517.stp ad9517_fmcomms6.stp adau1761.bin imageon_edid.bin pzsdr-fmc-ad9517.stp Mykonos_M3.bin" CONFIG_EXTRA_FIRMWARE_DIR="./firmware" -# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set +# CONFIG_FW_LOADER_USER_HELPER is not set +# CONFIG_FW_LOADER_COMPRESS is not set +CONFIG_FW_CACHE=y +# end of Firmware loader + CONFIG_ALLOW_DEV_COREDUMP=y # CONFIG_DEBUG_DRIVER is not set # CONFIG_DEBUG_DEVRES is not set # CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set # CONFIG_TEST_ASYNC_DRIVER_PROBE is not set -# CONFIG_SYS_HYPERVISOR is not set -# CONFIG_GENERIC_CPU_DEVICES is not set CONFIG_GENERIC_CPU_AUTOPROBE=y CONFIG_SOC_BUS=y CONFIG_REGMAP=y @@ -1141,41 +1228,34 @@ CONFIG_REGMAP_SPI=y CONFIG_REGMAP_MMIO=y CONFIG_DMA_SHARED_BUFFER=y # CONFIG_DMA_FENCE_TRACE is not set -CONFIG_DMA_CMA=y - -# -# Default contiguous memory area size: -# -CONFIG_CMA_SIZE_MBYTES=128 -CONFIG_CMA_SIZE_SEL_MBYTES=y -# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set -# CONFIG_CMA_SIZE_SEL_MIN is not set -# CONFIG_CMA_SIZE_SEL_MAX is not set -CONFIG_CMA_ALIGNMENT=8 CONFIG_GENERIC_ARCH_TOPOLOGY=y +# end of Generic Driver Options # # Bus devices # -# CONFIG_ARM_CCI400_PMU is not set -# CONFIG_ARM_CCI5xx_PMU is not set -# CONFIG_ARM_CCN is not set # CONFIG_BRCMSTB_GISB_ARB is not set +# CONFIG_MOXTET is not set # CONFIG_SIMPLE_PM_BUS is not set # CONFIG_VEXPRESS_CONFIG is not set +# CONFIG_MHI_BUS is not set +# end of Bus devices + CONFIG_CONNECTOR=y CONFIG_PROC_EVENTS=y +# CONFIG_GNSS is not set CONFIG_MTD=y # CONFIG_MTD_TESTS is not set -# CONFIG_MTD_REDBOOT_PARTS is not set -CONFIG_MTD_CMDLINE_PARTS=y -# CONFIG_MTD_AFS_PARTS is not set -CONFIG_MTD_OF_PARTS=y -# CONFIG_MTD_AR7_PARTS is not set # # Partition parsers # +# CONFIG_MTD_AR7_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_OF_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +# end of Partition parsers # # User Modules And Translation Layers @@ -1202,13 +1282,8 @@ CONFIG_MTD_GEN_PROBE=y CONFIG_MTD_MAP_BANK_WIDTH_1=y CONFIG_MTD_MAP_BANK_WIDTH_2=y CONFIG_MTD_MAP_BANK_WIDTH_4=y -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set CONFIG_MTD_CFI_I1=y CONFIG_MTD_CFI_I2=y -# CONFIG_MTD_CFI_I4 is not set -# CONFIG_MTD_CFI_I8 is not set # CONFIG_MTD_CFI_INTELEXT is not set CONFIG_MTD_CFI_AMDSTD=y # CONFIG_MTD_CFI_STAA is not set @@ -1216,6 +1291,7 @@ CONFIG_MTD_CFI_UTIL=y # CONFIG_MTD_RAM is not set # CONFIG_MTD_ROM is not set # CONFIG_MTD_ABSENT is not set +# end of RAM/ROM/Flash chip drivers # # Mapping drivers for chip access @@ -1224,15 +1300,16 @@ CONFIG_MTD_CFI_UTIL=y CONFIG_MTD_PHYSMAP=y # CONFIG_MTD_PHYSMAP_COMPAT is not set CONFIG_MTD_PHYSMAP_OF=y -# CONFIG_MTD_PHYSMAP_OF_VERSATILE is not set -# CONFIG_MTD_PHYSMAP_OF_GEMINI is not set +# CONFIG_MTD_PHYSMAP_VERSATILE is not set +# CONFIG_MTD_PHYSMAP_GEMINI is not set +# CONFIG_MTD_PHYSMAP_IXP4XX is not set # CONFIG_MTD_PLATRAM is not set +# end of Mapping drivers for chip access # # Self-contained MTD device drivers # # CONFIG_MTD_DATAFLASH is not set -CONFIG_MTD_M25P80=y # CONFIG_MTD_MCHP23K256 is not set # CONFIG_MTD_SST25L is not set # CONFIG_MTD_SLRAM is not set @@ -1244,49 +1321,47 @@ CONFIG_MTD_M25P80=y # Disk-On-Chip Device Drivers # # CONFIG_MTD_DOCG3 is not set -CONFIG_MTD_NAND_ECC=y -# CONFIG_MTD_NAND_ECC_SMC is not set -CONFIG_MTD_NAND=y -# CONFIG_MTD_NAND_ECC_BCH is not set -# CONFIG_MTD_SM_COMMON is not set -# CONFIG_MTD_NAND_DENALI_DT is not set -# CONFIG_MTD_NAND_GPIO is not set -# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set -# CONFIG_MTD_NAND_DISKONCHIP is not set -# CONFIG_MTD_NAND_DOCG4 is not set -# CONFIG_MTD_NAND_NANDSIM is not set -# CONFIG_MTD_NAND_BRCMNAND is not set -# CONFIG_MTD_NAND_PLATFORM is not set -CONFIG_MTD_NAND_PL35X=y -# CONFIG_MTD_NAND_ARASAN is not set +# end of Self-contained MTD device drivers + +# +# NAND +# # CONFIG_MTD_ONENAND is not set +# CONFIG_MTD_RAW_NAND is not set +# CONFIG_MTD_SPI_NAND is not set + +# +# ECC engine support +# +# end of ECC engine support +# end of NAND # # LPDDR & LPDDR2 PCM memory drivers # # CONFIG_MTD_LPDDR is not set # CONFIG_MTD_LPDDR2_NVM is not set +# end of LPDDR & LPDDR2 PCM memory drivers + CONFIG_MTD_SPI_NOR=y -# CONFIG_MTD_MT81xx_NOR is not set CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y -# CONFIG_SPI_CADENCE_QUADSPI is not set # CONFIG_MTD_UBI is not set +# CONFIG_MTD_HYPERBUS is not set CONFIG_DTC=y CONFIG_OF=y # CONFIG_OF_UNITTEST is not set CONFIG_OF_FLATTREE=y CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_KOBJ=y CONFIG_OF_ADDRESS=y CONFIG_OF_IRQ=y CONFIG_OF_NET=y -CONFIG_OF_MDIO=y CONFIG_OF_RESERVED_MEM=y # CONFIG_OF_OVERLAY is not set CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y # CONFIG_PARPORT is not set CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_NULL_BLK is not set -# CONFIG_BLK_DEV_COW_COMMON is not set CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 # CONFIG_BLK_DEV_CRYPTOLOOP is not set @@ -1298,16 +1373,21 @@ CONFIG_BLK_DEV_RAM_SIZE=16384 # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set # CONFIG_BLK_DEV_RBD is not set + +# +# NVME Support +# # CONFIG_NVME_FC is not set # CONFIG_NVME_TARGET is not set +# end of NVME Support # # Misc devices # -# CONFIG_SENSORS_LIS3LV02D is not set CONFIG_AD525X_DPOT=y # CONFIG_AD525X_DPOT_I2C is not set CONFIG_AD525X_DPOT_SPI=y +# CONFIG_ADI_AXI_DATA_OFFLOAD is not set # CONFIG_DUMMY_IRQ is not set # CONFIG_ICS932S401 is not set # CONFIG_ENCLOSURE_SERVICES is not set @@ -1319,12 +1399,13 @@ CONFIG_AD525X_DPOT_SPI=y # CONFIG_SENSORS_APDS990X is not set # CONFIG_HMC6352 is not set # CONFIG_DS1682 is not set -# CONFIG_TI_DAC7512 is not set -# CONFIG_USB_SWITCH_FSA9480 is not set # CONFIG_LATTICE_ECP3_CONFIG is not set # CONFIG_SRAM is not set # CONFIG_XILINX_SDFEC is not set +# CONFIG_XILINX_FLEX_PM is not set # CONFIG_XILINX_TRAFGEN is not set +# CONFIG_PVPANIC is not set +# CONFIG_HISI_HIKEY_USB is not set # CONFIG_XILINX_JESD204B is not set # CONFIG_C2PORT is not set @@ -1338,17 +1419,17 @@ CONFIG_EEPROM_AT25=y # CONFIG_EEPROM_93CX6 is not set # CONFIG_EEPROM_93XX46 is not set # CONFIG_EEPROM_IDT_89HPESX is not set +# CONFIG_EEPROM_EE1004 is not set +# end of EEPROM support # # Texas Instruments shared transport line discipline # # CONFIG_TI_ST is not set +# end of Texas Instruments shared transport line discipline + # CONFIG_SENSORS_LIS3_SPI is not set # CONFIG_SENSORS_LIS3_I2C is not set - -# -# Altera FPGA firmware download module -# # CONFIG_ALTERA_STAPL is not set # @@ -1359,42 +1440,11 @@ CONFIG_MWIPCORE=m CONFIG_MWIPCORE_DMA_STREAMING=m CONFIG_MWIPCORE_IIO_STREAMING=m CONFIG_MATHWORKS_GENERIC_OF=m +# end of MathWorks IP Drivers -# -# Intel MIC Bus Driver -# - -# -# SCIF Bus Driver -# - -# -# VOP Bus Driver -# - -# -# Intel MIC Host Driver -# - -# -# Intel MIC Card Driver -# - -# -# SCIF Driver -# - -# -# Intel MIC Coprocessor State Management (COSM) Drivers -# - -# -# VOP Driver -# # CONFIG_ECHO is not set -# CONFIG_CXL_BASE is not set -# CONFIG_CXL_AFU_DRIVER_OPS is not set -# CONFIG_CXL_LIB is not set +# CONFIG_MISC_RTSX_USB is not set +# end of Misc devices # # SCSI device support @@ -1403,8 +1453,6 @@ CONFIG_SCSI_MOD=y # CONFIG_RAID_ATTRS is not set CONFIG_SCSI=y CONFIG_SCSI_DMA=y -# CONFIG_SCSI_NETLINK is not set -# CONFIG_SCSI_MQ_DEFAULT is not set CONFIG_SCSI_PROC_FS=y # @@ -1412,7 +1460,6 @@ CONFIG_SCSI_PROC_FS=y # CONFIG_BLK_DEV_SD=y # CONFIG_CHR_DEV_ST is not set -# CONFIG_CHR_DEV_OSST is not set # CONFIG_BLK_DEV_SR is not set CONFIG_CHR_DEV_SG=y # CONFIG_CHR_DEV_SCH is not set @@ -1429,13 +1476,16 @@ CONFIG_CHR_DEV_SG=y # CONFIG_SCSI_SAS_ATTRS is not set # CONFIG_SCSI_SAS_LIBSAS is not set # CONFIG_SCSI_SRP_ATTRS is not set +# end of SCSI Transports + CONFIG_SCSI_LOWLEVEL=y # CONFIG_ISCSI_TCP is not set # CONFIG_ISCSI_BOOT_SYSFS is not set # CONFIG_SCSI_UFSHCD is not set # CONFIG_SCSI_DEBUG is not set # CONFIG_SCSI_DH is not set -# CONFIG_SCSI_OSD_INITIATOR is not set +# end of SCSI device support + # CONFIG_ATA is not set # CONFIG_MD is not set # CONFIG_TARGET_CORE is not set @@ -1443,26 +1493,27 @@ CONFIG_NETDEVICES=y CONFIG_NET_CORE=y # CONFIG_BONDING is not set # CONFIG_DUMMY is not set +# CONFIG_WIREGUARD is not set # CONFIG_EQUALIZER is not set # CONFIG_NET_TEAM is not set # CONFIG_MACVLAN is not set +# CONFIG_IPVLAN is not set # CONFIG_VXLAN is not set +# CONFIG_GENEVE is not set +# CONFIG_BAREUDP is not set +# CONFIG_GTP is not set CONFIG_MACSEC=y # CONFIG_NETCONSOLE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set CONFIG_TUN=y # CONFIG_TUN_VNET_CROSS_LE is not set # CONFIG_VETH is not set # CONFIG_NLMON is not set -# -# CAIF transport drivers -# - # # Distributed Switch Architecture drivers # +# end of Distributed Switch Architecture drivers + CONFIG_ETHERNET=y CONFIG_NET_VENDOR_ALACRITECH=y # CONFIG_ALTERA_TSE is not set @@ -1470,34 +1521,43 @@ CONFIG_NET_VENDOR_AMAZON=y CONFIG_NET_VENDOR_AQUANTIA=y CONFIG_NET_VENDOR_ARC=y # CONFIG_NET_VENDOR_AURORA is not set -CONFIG_NET_CADENCE=y +# CONFIG_NET_VENDOR_BROADCOM is not set +CONFIG_NET_VENDOR_CADENCE=y CONFIG_MACB=y CONFIG_MACB_USE_HWSTAMP=y -# CONFIG_NET_VENDOR_BROADCOM is not set +CONFIG_NET_VENDOR_CAVIUM=y # CONFIG_NET_VENDOR_CIRRUS is not set +CONFIG_NET_VENDOR_CORTINA=y +# CONFIG_GEMINI_ETHERNET is not set # CONFIG_DM9000 is not set # CONFIG_DNET is not set CONFIG_NET_VENDOR_EZCHIP=y # CONFIG_EZCHIP_NPS_MANAGEMENT_ENET is not set # CONFIG_NET_VENDOR_FARADAY is not set +CONFIG_NET_VENDOR_GOOGLE=y CONFIG_NET_VENDOR_HISILICON=y # CONFIG_HIX5HD2_GMAC is not set # CONFIG_HISI_FEMAC is not set # CONFIG_HIP04_ETH is not set -# CONFIG_HNS is not set # CONFIG_HNS_DSAF is not set # CONFIG_HNS_ENET is not set CONFIG_NET_VENDOR_HUAWEI=y # CONFIG_NET_VENDOR_INTEL is not set +CONFIG_NET_VENDOR_ADI=y +# CONFIG_ADIN1110 is not set # CONFIG_NET_VENDOR_MARVELL is not set CONFIG_NET_VENDOR_MELLANOX=y # CONFIG_MLXSW_CORE is not set # CONFIG_MLXFW is not set # CONFIG_NET_VENDOR_MICREL is not set # CONFIG_NET_VENDOR_MICROCHIP is not set +CONFIG_NET_VENDOR_MICROSEMI=y # CONFIG_NET_VENDOR_NATSEMI is not set CONFIG_NET_VENDOR_NETRONOME=y +CONFIG_NET_VENDOR_NI=y +# CONFIG_NI_XGE_MANAGEMENT_ENET is not set # CONFIG_ETHOC is not set +CONFIG_NET_VENDOR_PENSANDO=y CONFIG_NET_VENDOR_QUALCOMM=y # CONFIG_QCA7000_SPI is not set # CONFIG_QCOM_EMAC is not set @@ -1509,63 +1569,95 @@ CONFIG_NET_VENDOR_SAMSUNG=y # CONFIG_NET_VENDOR_SEEQ is not set CONFIG_NET_VENDOR_SOLARFLARE=y # CONFIG_NET_VENDOR_SMSC is not set +CONFIG_NET_VENDOR_SOCIONEXT=y # CONFIG_NET_VENDOR_STMICRO is not set +CONFIG_NET_VENDOR_SYNOPSYS=y +# CONFIG_DWC_XLGMAC is not set # CONFIG_NET_VENDOR_VIA is not set # CONFIG_NET_VENDOR_WIZNET is not set CONFIG_NET_VENDOR_XILINX=y # CONFIG_XILINX_EMACLITE is not set # CONFIG_XILINX_AXI_EMAC is not set +# CONFIG_XILINX_LL_TEMAC is not set # CONFIG_XILINX_TSN is not set -CONFIG_NET_VENDOR_SYNOPSYS=y -# CONFIG_DWC_XLGMAC is not set -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_BUS=y -# CONFIG_MDIO_BCM_UNIMAC is not set -CONFIG_MDIO_BITBANG=y -# CONFIG_MDIO_BUS_MUX_GPIO is not set -# CONFIG_MDIO_BUS_MUX_MMIOREG is not set -# CONFIG_MDIO_GPIO is not set -# CONFIG_MDIO_HISI_FEMAC is not set +CONFIG_PHYLINK=y CONFIG_PHYLIB=y CONFIG_SWPHY=y # CONFIG_LED_TRIGGER_PHY is not set +CONFIG_FIXED_PHY=y +# CONFIG_SFP is not set # # MII PHY device drivers # -# CONFIG_ADIN_PHY is not set # CONFIG_AMD_PHY is not set +# CONFIG_ADIN_PHY is not set +# CONFIG_ADIN1100_PHY is not set # CONFIG_AQUANTIA_PHY is not set -# CONFIG_AT803X_PHY is not set -# CONFIG_BCM7XXX_PHY is not set -# CONFIG_BCM87XX_PHY is not set +# CONFIG_AX88796B_PHY is not set # CONFIG_BROADCOM_PHY is not set +# CONFIG_BCM54140_PHY is not set +# CONFIG_BCM7XXX_PHY is not set +# CONFIG_BCM84881_PHY is not set +# CONFIG_BCM87XX_PHY is not set # CONFIG_CICADA_PHY is not set # CONFIG_CORTINA_PHY is not set # CONFIG_DAVICOM_PHY is not set -# CONFIG_DP83848_PHY is not set -# CONFIG_DP83867_PHY is not set -CONFIG_FIXED_PHY=y # CONFIG_ICPLUS_PHY is not set +# CONFIG_LXT_PHY is not set # CONFIG_INTEL_XWAY_PHY is not set # CONFIG_LSI_ET1011C_PHY is not set -# CONFIG_LXT_PHY is not set CONFIG_MARVELL_PHY=y # CONFIG_MARVELL_10G_PHY is not set # CONFIG_MICREL_PHY is not set # CONFIG_MICROCHIP_PHY is not set +# CONFIG_MICROCHIP_T1_PHY is not set # CONFIG_MICROSEMI_PHY is not set # CONFIG_NATIONAL_PHY is not set +# CONFIG_NXP_TJA11XX_PHY is not set +# CONFIG_AT803X_PHY is not set # CONFIG_QSEMI_PHY is not set CONFIG_REALTEK_PHY=y +# CONFIG_RENESAS_PHY is not set # CONFIG_ROCKCHIP_PHY is not set # CONFIG_SMSC_PHY is not set # CONFIG_STE10XP is not set # CONFIG_TERANETICS_PHY is not set +# CONFIG_DP83822_PHY is not set +# CONFIG_DP83TC811_PHY is not set +# CONFIG_DP83848_PHY is not set +# CONFIG_DP83867_PHY is not set +# CONFIG_DP83869_PHY is not set # CONFIG_VITESSE_PHY is not set # CONFIG_XILINX_PHY is not set CONFIG_XILINX_GMII2RGMII=y # CONFIG_MICREL_KS8995MA is not set +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_BUS=y +CONFIG_OF_MDIO=y +CONFIG_MDIO_DEVRES=y +CONFIG_MDIO_BITBANG=y +# CONFIG_MDIO_BCM_UNIMAC is not set +# CONFIG_MDIO_GPIO is not set +# CONFIG_MDIO_HISI_FEMAC is not set +# CONFIG_MDIO_MVUSB is not set +# CONFIG_MDIO_MSCC_MIIM is not set +# CONFIG_MDIO_IPQ4019 is not set +# CONFIG_MDIO_IPQ8064 is not set + +# +# MDIO Multiplexers +# +# CONFIG_MDIO_BUS_MUX_GPIO is not set +# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set +# CONFIG_MDIO_BUS_MUX_MMIOREG is not set + +# +# PCS device drivers +# +# CONFIG_PCS_XPCS is not set +# end of PCS device drivers + # CONFIG_PPP is not set # CONFIG_SLIP is not set CONFIG_USB_NET_DRIVERS=y @@ -1584,6 +1676,8 @@ CONFIG_USB_NET_DRIVERS=y # Enable WiMAX (Networking options) to see the WiMAX drivers # # CONFIG_WAN is not set +# CONFIG_NETDEVSIM is not set +# CONFIG_NET_FAILOVER is not set # CONFIG_ISDN is not set # CONFIG_NVM is not set @@ -1613,6 +1707,7 @@ CONFIG_INPUT_KEYBOARD=y # CONFIG_KEYBOARD_ADP5588 is not set # CONFIG_KEYBOARD_ADP5589 is not set CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_QT1050 is not set # CONFIG_KEYBOARD_QT1070 is not set # CONFIG_KEYBOARD_QT2160 is not set # CONFIG_KEYBOARD_DLINK_DIR685 is not set @@ -1669,10 +1764,9 @@ CONFIG_INPUT_MISC=y # CONFIG_INPUT_BMA150 is not set # CONFIG_INPUT_E3X0_BUTTON is not set # CONFIG_INPUT_MMA8450 is not set -# CONFIG_INPUT_GP2A is not set # CONFIG_INPUT_GPIO_BEEPER is not set -# CONFIG_INPUT_GPIO_TILT_POLLED is not set # CONFIG_INPUT_GPIO_DECODER is not set +# CONFIG_INPUT_GPIO_VIBRA is not set # CONFIG_INPUT_ATI_REMOTE2 is not set # CONFIG_INPUT_KEYSPAN_REMOTE is not set # CONFIG_INPUT_KXTJ9 is not set @@ -1685,8 +1779,8 @@ CONFIG_INPUT_MISC=y CONFIG_INPUT_GPIO_ROTARY_ENCODER=y # CONFIG_INPUT_ADXL34X is not set # CONFIG_INPUT_IMS_PCU is not set +# CONFIG_INPUT_IQS269A is not set # CONFIG_INPUT_CMA3000 is not set -# CONFIG_INPUT_SOC_BUTTON_ARRAY is not set # CONFIG_INPUT_DRV260X_HAPTICS is not set # CONFIG_INPUT_DRV2665_HAPTICS is not set # CONFIG_INPUT_DRV2667_HAPTICS is not set @@ -1707,6 +1801,8 @@ CONFIG_SERIO_LIBPS2=y # CONFIG_SERIO_GPIO_PS2 is not set # CONFIG_USERIO is not set # CONFIG_GAMEPORT is not set +# end of Hardware I/O ports +# end of Input device support # # Character devices @@ -1720,11 +1816,7 @@ CONFIG_HW_CONSOLE=y CONFIG_VT_HW_CONSOLE_BINDING=y CONFIG_UNIX98_PTYS=y # CONFIG_LEGACY_PTYS is not set -# CONFIG_SERIAL_NONSTANDARD is not set -# CONFIG_N_GSM is not set -# CONFIG_TRACE_SINK is not set -CONFIG_DEVMEM=y -# CONFIG_DEVKMEM is not set +CONFIG_LDISC_AUTOLOAD=y # # Serial drivers @@ -1743,6 +1835,7 @@ CONFIG_SERIAL_EARLYCON=y # CONFIG_SERIAL_UARTLITE is not set CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_SIFIVE is not set # CONFIG_SERIAL_SCCNXP is not set # CONFIG_SERIAL_SC16IS7XX is not set # CONFIG_SERIAL_BCM63XX is not set @@ -1753,18 +1846,31 @@ CONFIG_SERIAL_XILINX_PS_UART=y CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y # CONFIG_SERIAL_ARC is not set # CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_FSL_LINFLEXUART is not set # CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set # CONFIG_SERIAL_ST_ASC is not set +# CONFIG_SERIAL_SPRD is not set +# end of Serial drivers + +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_N_GSM is not set +# CONFIG_NULL_TTY is not set +# CONFIG_TRACE_SINK is not set +# CONFIG_HVC_DCC is not set # CONFIG_SERIAL_DEV_BUS is not set # CONFIG_TTY_PRINTK is not set -# CONFIG_HVC_DCC is not set +# CONFIG_VIRTIO_CONSOLE is not set # CONFIG_IPMI_HANDLER is not set # CONFIG_HW_RANDOM is not set -# CONFIG_R3964 is not set +CONFIG_DEVMEM=y +# CONFIG_DEVKMEM is not set # CONFIG_RAW_DRIVER is not set # CONFIG_TCG_TPM is not set # CONFIG_XILLYBUS is not set CONFIG_AXI_INTR_MONITOR=y +# end of Character devices + +# CONFIG_RANDOM_TRUST_BOOTLOADER is not set # # I2C support @@ -1788,6 +1894,8 @@ CONFIG_I2C_MUX_PCA954x=y # CONFIG_I2C_MUX_REG is not set # CONFIG_I2C_DEMUX_PINCTRL is not set # CONFIG_I2C_MUX_MLXCPLD is not set +# end of Multiplexer I2C Chip support + CONFIG_I2C_HELPER_AUTO=y CONFIG_I2C_ALGOBIT=y @@ -1803,10 +1911,10 @@ CONFIG_I2C_CADENCE=y # CONFIG_I2C_DESIGNWARE_PLATFORM is not set # CONFIG_I2C_EMEV2 is not set CONFIG_I2C_GPIO=y +# CONFIG_I2C_GPIO_FAULT_INJECTOR is not set # CONFIG_I2C_NOMADIK is not set # CONFIG_I2C_OCORES is not set # CONFIG_I2C_PCA_PLATFORM is not set -# CONFIG_I2C_PXA_PCI is not set # CONFIG_I2C_RK3X is not set # CONFIG_I2C_SIMTEC is not set CONFIG_I2C_XILINX=y @@ -1815,7 +1923,6 @@ CONFIG_I2C_XILINX=y # External I2C/SMBus adapter drivers # # CONFIG_I2C_DIOLAN_U2C is not set -# CONFIG_I2C_PARPORT_LIGHT is not set # CONFIG_I2C_ROBOTFUZZ_OSIF is not set # CONFIG_I2C_TAOS_EVM is not set # CONFIG_I2C_TINY_USB is not set @@ -1823,14 +1930,20 @@ CONFIG_I2C_XILINX=y # # Other I2C/SMBus bus drivers # +# end of I2C Hardware Bus support + # CONFIG_I2C_STUB is not set # CONFIG_I2C_SLAVE is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set # CONFIG_I2C_DEBUG_BUS is not set +# end of I2C support + +# CONFIG_I3C is not set CONFIG_SPI=y # CONFIG_SPI_DEBUG is not set CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y # # SPI Master Controller Drivers @@ -1839,20 +1952,29 @@ CONFIG_SPI_MASTER=y CONFIG_SPI_AXI_SPI_ENGINE=y CONFIG_SPI_BITBANG=y CONFIG_SPI_CADENCE=y +# CONFIG_SPI_CADENCE_QUADSPI is not set # CONFIG_SPI_DESIGNWARE is not set +# CONFIG_SPI_NXP_FLEXSPI is not set # CONFIG_SPI_GPIO is not set # CONFIG_SPI_FSL_SPI is not set # CONFIG_SPI_OC_TINY is not set # CONFIG_SPI_PL022 is not set -# CONFIG_SPI_PXA2XX_PCI is not set # CONFIG_SPI_ROCKCHIP is not set # CONFIG_SPI_SC18IS602 is not set +# CONFIG_SPI_SIFIVE is not set +# CONFIG_SPI_MXIC is not set CONFIG_SPI_XCOMM=y CONFIG_SPI_AD9250FMC=y CONFIG_SPI_XILINX=y CONFIG_SPI_ZYNQ_QSPI=y # CONFIG_SPI_ZYNQ_QSPI_DUAL_STACKED is not set # CONFIG_SPI_ZYNQMP_GQSPI is not set +# CONFIG_SPI_AMD is not set + +# +# SPI Multiplexer support +# +# CONFIG_SPI_MUX is not set # # SPI Protocol Masters @@ -1886,77 +2008,103 @@ CONFIG_PTP_1588_CLOCK=y # # Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. # -CONFIG_PINCTRL=y +# CONFIG_PTP_1588_CLOCK_IDT82P33 is not set +# CONFIG_PTP_1588_CLOCK_IDTCM is not set +# CONFIG_PTP_1588_CLOCK_XILINX is not set +# end of PTP clock support -# -# Pin controllers -# +CONFIG_PINCTRL=y CONFIG_PINMUX=y CONFIG_PINCONF=y CONFIG_GENERIC_PINCONF=y # CONFIG_DEBUG_PINCTRL is not set -# CONFIG_PINCTRL_AMD is not set # CONFIG_PINCTRL_MCP23S08 is not set # CONFIG_PINCTRL_SINGLE is not set # CONFIG_PINCTRL_SX150X is not set +# CONFIG_PINCTRL_STMFX is not set CONFIG_PINCTRL_ZYNQ=y +# CONFIG_PINCTRL_OCELOT is not set + +# +# Renesas pinctrl drivers +# +# end of Renesas pinctrl drivers + CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y CONFIG_GPIOLIB=y +CONFIG_GPIOLIB_FASTPATH_LIMIT=512 CONFIG_OF_GPIO=y CONFIG_GPIOLIB_IRQCHIP=y # CONFIG_DEBUG_GPIO is not set CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_CDEV=y +CONFIG_GPIO_CDEV_V1=y # # Memory mapped GPIO drivers # # CONFIG_GPIO_74XX_MMIO is not set # CONFIG_GPIO_ALTERA is not set +# CONFIG_GPIO_CADENCE is not set # CONFIG_GPIO_DWAPB is not set # CONFIG_GPIO_FTGPIO010 is not set # CONFIG_GPIO_GENERIC_PLATFORM is not set # CONFIG_GPIO_GRGPIO is not set -# CONFIG_GPIO_MOCKUP is not set +# CONFIG_GPIO_HLWD is not set +# CONFIG_GPIO_LOGICVC is not set +# CONFIG_GPIO_MB86S7X is not set # CONFIG_GPIO_MPC8XXX is not set # CONFIG_GPIO_PL061 is not set +# CONFIG_GPIO_SAMA5D2_PIOBU is not set +# CONFIG_GPIO_SIFIVE is not set # CONFIG_GPIO_SYSCON is not set CONFIG_GPIO_XILINX=y # CONFIG_GPIO_ZEVIO is not set CONFIG_GPIO_ZYNQ=y +# CONFIG_GPIO_AMD_FCH is not set +# end of Memory mapped GPIO drivers # # I2C GPIO expanders # # CONFIG_GPIO_ADP5588 is not set # CONFIG_GPIO_ADNP is not set +# CONFIG_GPIO_GW_PLD is not set # CONFIG_GPIO_MAX7300 is not set # CONFIG_GPIO_MAX732X is not set CONFIG_GPIO_PCA953X=y # CONFIG_GPIO_PCA953X_IRQ is not set +# CONFIG_GPIO_PCA9570 is not set # CONFIG_GPIO_PCF857X is not set -# CONFIG_GPIO_SX150X is not set # CONFIG_GPIO_TPIC2810 is not set +# end of I2C GPIO expanders # # MFD GPIO expanders # # CONFIG_HTC_EGPIO is not set +# end of MFD GPIO expanders # # SPI GPIO expanders # # CONFIG_GPIO_74X164 is not set CONFIG_GPIO_ADI_DAQ1=y +# CONFIG_GPIO_MAX3191X is not set # CONFIG_GPIO_MAX7301 is not set # CONFIG_GPIO_MC33880 is not set # CONFIG_GPIO_PISOSR is not set # CONFIG_GPIO_XRA1403 is not set +# end of SPI GPIO expanders # # USB GPIO expanders # +# end of USB GPIO expanders + +# CONFIG_GPIO_AGGREGATOR is not set +# CONFIG_GPIO_MOCKUP is not set # CONFIG_W1 is not set -# CONFIG_POWER_AVS is not set CONFIG_POWER_RESET=y # CONFIG_POWER_RESET_BRCMKONA is not set # CONFIG_POWER_RESET_BRCMSTB is not set @@ -1968,18 +2116,21 @@ CONFIG_POWER_RESET_RESTART=y # CONFIG_POWER_RESET_SYSCON is not set # CONFIG_POWER_RESET_SYSCON_POWEROFF is not set # CONFIG_SYSCON_REBOOT_MODE is not set +# CONFIG_NVMEM_REBOOT_MODE is not set CONFIG_POWER_SUPPLY=y # CONFIG_POWER_SUPPLY_DEBUG is not set +CONFIG_POWER_SUPPLY_HWMON=y # CONFIG_PDA_POWER is not set # CONFIG_GENERIC_ADC_BATTERY is not set # CONFIG_TEST_POWER is not set CONFIG_CHARGER_ADP5061=y +# CONFIG_BATTERY_CW2015 is not set # CONFIG_BATTERY_DS2780 is not set # CONFIG_BATTERY_DS2781 is not set # CONFIG_BATTERY_DS2782 is not set -# CONFIG_BATTERY_LEGO_EV3 is not set # CONFIG_BATTERY_SBS is not set # CONFIG_CHARGER_SBS is not set +# CONFIG_MANAGER_SBS is not set # CONFIG_BATTERY_BQ27XXX is not set # CONFIG_BATTERY_MAX17040 is not set # CONFIG_BATTERY_MAX17042 is not set @@ -1987,18 +2138,21 @@ CONFIG_CHARGER_ADP5061=y # CONFIG_CHARGER_LP8727 is not set # CONFIG_CHARGER_GPIO is not set # CONFIG_CHARGER_MANAGER is not set -# CONFIG_CHARGER_LTC3651 is not set +# CONFIG_CHARGER_LT3651 is not set # CONFIG_CHARGER_DETECTOR_MAX14656 is not set # CONFIG_CHARGER_BQ2415X is not set # CONFIG_CHARGER_BQ24190 is not set # CONFIG_CHARGER_BQ24257 is not set # CONFIG_CHARGER_BQ24735 is not set +# CONFIG_CHARGER_BQ2515X is not set # CONFIG_CHARGER_BQ25890 is not set +# CONFIG_CHARGER_BQ25980 is not set # CONFIG_CHARGER_SMB347 is not set CONFIG_BATTERY_GAUGE_LTC2941=y # CONFIG_CHARGER_RT9455 is not set +# CONFIG_CHARGER_UCS1002 is not set +# CONFIG_CHARGER_BD99954 is not set CONFIG_HWMON=y -# CONFIG_HWMON_VID is not set # CONFIG_HWMON_DEBUG_CHIP is not set # @@ -2006,13 +2160,13 @@ CONFIG_HWMON=y # # CONFIG_SENSORS_AD7314 is not set # CONFIG_SENSORS_AD7414 is not set -# CONFIG_SENSORS_AXI_FAN_CONTROL is not set # CONFIG_SENSORS_AD7418 is not set # CONFIG_SENSORS_ADM1021 is not set # CONFIG_SENSORS_ADM1025 is not set # CONFIG_SENSORS_ADM1026 is not set # CONFIG_SENSORS_ADM1029 is not set # CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM1177 is not set # CONFIG_SENSORS_ADM9240 is not set # CONFIG_SENSORS_ADT7310 is not set # CONFIG_SENSORS_ADT7410 is not set @@ -2020,9 +2174,12 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ADT7462 is not set # CONFIG_SENSORS_ADT7470 is not set # CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_AS370 is not set # CONFIG_SENSORS_ASC7621 is not set +# CONFIG_SENSORS_AXI_FAN_CONTROL is not set # CONFIG_SENSORS_ASPEED is not set # CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_CORSAIR_CPRO is not set # CONFIG_SENSORS_DS620 is not set # CONFIG_SENSORS_DS1621 is not set # CONFIG_SENSORS_F71805F is not set @@ -2044,6 +2201,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_LTC2947_I2C is not set # CONFIG_SENSORS_LTC2947_SPI is not set # CONFIG_SENSORS_LTC2990 is not set +# CONFIG_SENSORS_LTC2992 is not set # CONFIG_SENSORS_LTC4151 is not set # CONFIG_SENSORS_LTC4215 is not set # CONFIG_SENSORS_LTC4222 is not set @@ -2056,6 +2214,8 @@ CONFIG_HWMON=y # CONFIG_SENSORS_MAX1668 is not set # CONFIG_SENSORS_MAX197 is not set # CONFIG_SENSORS_MAX31722 is not set +# CONFIG_SENSORS_MAX31730 is not set +# CONFIG_SENSORS_MAX6621 is not set # CONFIG_SENSORS_MAX6639 is not set # CONFIG_SENSORS_MAX6642 is not set # CONFIG_SENSORS_MAX6650 is not set @@ -2063,6 +2223,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_MAX31790 is not set # CONFIG_SENSORS_MCP3021 is not set # CONFIG_SENSORS_TC654 is not set +# CONFIG_SENSORS_MR75203 is not set # CONFIG_SENSORS_ADCXX is not set # CONFIG_SENSORS_LM63 is not set # CONFIG_SENSORS_LM70 is not set @@ -2087,23 +2248,38 @@ CONFIG_HWMON=y # CONFIG_SENSORS_NCT6775 is not set # CONFIG_SENSORS_NCT7802 is not set # CONFIG_SENSORS_NCT7904 is not set +# CONFIG_SENSORS_NPCM7XX is not set +# CONFIG_SENSORS_OCC_P8_I2C is not set # CONFIG_SENSORS_PCF8591 is not set CONFIG_PMBUS=y CONFIG_SENSORS_PMBUS=y +# CONFIG_SENSORS_ADM1266 is not set # CONFIG_SENSORS_ADM1275 is not set +# CONFIG_SENSORS_BEL_PFE is not set # CONFIG_SENSORS_IBM_CFFPS is not set +# CONFIG_SENSORS_INSPUR_IPSPS is not set # CONFIG_SENSORS_IR35221 is not set +# CONFIG_SENSORS_IR38064 is not set +# CONFIG_SENSORS_IRPS5401 is not set +# CONFIG_SENSORS_ISL68137 is not set # CONFIG_SENSORS_LM25066 is not set # CONFIG_SENSORS_LTC2978 is not set # CONFIG_SENSORS_LTC3815 is not set # CONFIG_SENSORS_MAX16064 is not set +# CONFIG_SENSORS_MAX16601 is not set +# CONFIG_SENSORS_MAX20730 is not set # CONFIG_SENSORS_MAX20751 is not set +# CONFIG_SENSORS_MAX31785 is not set # CONFIG_SENSORS_MAX34440 is not set # CONFIG_SENSORS_MAX8688 is not set +# CONFIG_SENSORS_MP2975 is not set +# CONFIG_SENSORS_PXE1610 is not set # CONFIG_SENSORS_TPS40422 is not set # CONFIG_SENSORS_TPS53679 is not set +# CONFIG_SENSORS_TPS544 is not set CONFIG_SENSORS_UCD9000=y CONFIG_SENSORS_UCD9200=y +# CONFIG_SENSORS_XDPE122 is not set # CONFIG_SENSORS_ZL6100 is not set # CONFIG_SENSORS_SHT15 is not set # CONFIG_SENSORS_SHT21 is not set @@ -2116,13 +2292,11 @@ CONFIG_SENSORS_UCD9200=y # CONFIG_SENSORS_SMSC47M1 is not set # CONFIG_SENSORS_SMSC47M192 is not set # CONFIG_SENSORS_SMSC47B397 is not set -# CONFIG_SENSORS_SCH56XX_COMMON is not set # CONFIG_SENSORS_SCH5627 is not set # CONFIG_SENSORS_SCH5636 is not set # CONFIG_SENSORS_STTS751 is not set # CONFIG_SENSORS_SMM665 is not set # CONFIG_SENSORS_ADC128D818 is not set -# CONFIG_SENSORS_ADS1015 is not set # CONFIG_SENSORS_ADS7828 is not set # CONFIG_SENSORS_ADS7871 is not set # CONFIG_SENSORS_AMC6821 is not set @@ -2136,7 +2310,9 @@ CONFIG_SENSORS_UCD9200=y # CONFIG_SENSORS_TMP108 is not set # CONFIG_SENSORS_TMP401 is not set # CONFIG_SENSORS_TMP421 is not set +# CONFIG_SENSORS_TMP513 is not set # CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_W83773G is not set # CONFIG_SENSORS_W83781D is not set # CONFIG_SENSORS_W83791D is not set # CONFIG_SENSORS_W83792D is not set @@ -2147,6 +2323,8 @@ CONFIG_SENSORS_UCD9200=y # CONFIG_SENSORS_W83627HF is not set # CONFIG_SENSORS_W83627EHF is not set CONFIG_THERMAL=y +# CONFIG_THERMAL_NETLINK is not set +# CONFIG_THERMAL_STATISTICS is not set CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 CONFIG_THERMAL_HWMON=y CONFIG_THERMAL_OF=y @@ -2154,25 +2332,26 @@ CONFIG_THERMAL_OF=y CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y # CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set # CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set -# CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR is not set # CONFIG_THERMAL_GOV_FAIR_SHARE is not set CONFIG_THERMAL_GOV_STEP_WISE=y # CONFIG_THERMAL_GOV_BANG_BANG is not set # CONFIG_THERMAL_GOV_USER_SPACE is not set -# CONFIG_THERMAL_GOV_POWER_ALLOCATOR is not set +# CONFIG_CPU_THERMAL is not set # CONFIG_THERMAL_EMULATION is not set -# CONFIG_QORIQ_THERMAL is not set - -# -# ACPI INT340X thermal drivers -# +# CONFIG_THERMAL_MMIO is not set # CONFIG_GENERIC_ADC_THERMAL is not set CONFIG_WATCHDOG=y CONFIG_WATCHDOG_CORE=y # CONFIG_WATCHDOG_NOWAYOUT is not set CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y +CONFIG_WATCHDOG_OPEN_TIMEOUT=0 # CONFIG_WATCHDOG_SYSFS is not set +# +# Watchdog Pretimeout Governors +# +# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set + # # Watchdog Device Drivers # @@ -2182,24 +2361,17 @@ CONFIG_XILINX_WATCHDOG=y # CONFIG_ZIIRAVE_WATCHDOG is not set # CONFIG_ARM_SP805_WATCHDOG is not set CONFIG_CADENCE_WATCHDOG=y +# CONFIG_FTWDT010_WATCHDOG is not set # CONFIG_DW_WATCHDOG is not set # CONFIG_MAX63XX_WATCHDOG is not set +# CONFIG_ARM_SMC_WATCHDOG is not set # CONFIG_MEN_A21_WDT is not set # # USB-based Watchdog Cards # # CONFIG_USBPCWATCHDOG is not set - -# -# Watchdog Pretimeout Governors -# -# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set CONFIG_SSB_POSSIBLE=y - -# -# Sonics Silicon Backplane -# # CONFIG_SSB is not set CONFIG_BCMA_POSSIBLE=y # CONFIG_BCMA is not set @@ -2207,7 +2379,6 @@ CONFIG_BCMA_POSSIBLE=y # # Multifunction device drivers # -# CONFIG_MFD_CORE is not set # CONFIG_MFD_ACT8945A is not set # CONFIG_MFD_AS3711 is not set # CONFIG_MFD_AS3722 is not set @@ -2218,7 +2389,7 @@ CONFIG_BCMA_POSSIBLE=y # CONFIG_MFD_BCM590XX is not set # CONFIG_MFD_BD9571MWV is not set # CONFIG_MFD_AXP20X_I2C is not set -# CONFIG_MFD_CROS_EC is not set +# CONFIG_MFD_MADERA is not set # CONFIG_MFD_ASIC3 is not set # CONFIG_PMIC_DA903X is not set # CONFIG_MFD_DA9052_SPI is not set @@ -2228,17 +2399,21 @@ CONFIG_BCMA_POSSIBLE=y # CONFIG_MFD_DA9063 is not set # CONFIG_MFD_DA9150 is not set # CONFIG_MFD_DLN2 is not set +# CONFIG_MFD_GATEWORKS_GSC is not set # CONFIG_MFD_MC13XXX_SPI is not set # CONFIG_MFD_MC13XXX_I2C is not set +# CONFIG_MFD_MP2629 is not set # CONFIG_MFD_HI6421_PMIC is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_HTC_I2CPLD is not set +# CONFIG_MFD_IQS62X is not set # CONFIG_MFD_KEMPLD is not set # CONFIG_MFD_88PM800 is not set # CONFIG_MFD_88PM805 is not set # CONFIG_MFD_88PM860X is not set # CONFIG_MFD_MAX14577 is not set # CONFIG_MFD_MAX77620 is not set +# CONFIG_MFD_MAX77650 is not set # CONFIG_MFD_MAX77686 is not set # CONFIG_MFD_MAX77693 is not set # CONFIG_MFD_MAX77843 is not set @@ -2246,6 +2421,7 @@ CONFIG_BCMA_POSSIBLE=y # CONFIG_MFD_MAX8925 is not set # CONFIG_MFD_MAX8997 is not set # CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_MT6360 is not set # CONFIG_MFD_MT6397 is not set # CONFIG_MFD_MENF21BMC is not set # CONFIG_EZX_PCAP is not set @@ -2255,15 +2431,14 @@ CONFIG_BCMA_POSSIBLE=y # CONFIG_MFD_PCF50633 is not set # CONFIG_MFD_PM8XXX is not set # CONFIG_MFD_RT5033 is not set -# CONFIG_MFD_RTSX_USB is not set # CONFIG_MFD_RC5T583 is not set # CONFIG_MFD_RK808 is not set # CONFIG_MFD_RN5T618 is not set # CONFIG_MFD_SEC_CORE is not set # CONFIG_MFD_SI476X_CORE is not set +# CONFIG_MFD_SL28CPLD is not set # CONFIG_MFD_SM501 is not set # CONFIG_MFD_SKY81452 is not set -# CONFIG_MFD_SMSC is not set # CONFIG_ABX500_CORE is not set # CONFIG_MFD_STMPE is not set CONFIG_MFD_SYSCON=y @@ -2291,10 +2466,11 @@ CONFIG_MFD_SYSCON=y # CONFIG_MFD_WL1273_CORE is not set # CONFIG_MFD_LM3533 is not set # CONFIG_MFD_TC3589X is not set -# CONFIG_MFD_TMIO is not set # CONFIG_MFD_T7L66XB is not set # CONFIG_MFD_TC6387XB is not set # CONFIG_MFD_TC6393XB is not set +# CONFIG_MFD_TQMX86 is not set +# CONFIG_MFD_LOCHNAGAR is not set # CONFIG_MFD_ARIZONA_I2C is not set # CONFIG_MFD_ARIZONA_SPI is not set # CONFIG_MFD_WM8400 is not set @@ -2302,17 +2478,27 @@ CONFIG_MFD_SYSCON=y # CONFIG_MFD_WM831X_SPI is not set # CONFIG_MFD_WM8350_I2C is not set # CONFIG_MFD_WM8994 is not set +# CONFIG_MFD_ROHM_BD718XX is not set +# CONFIG_MFD_ROHM_BD70528 is not set +# CONFIG_MFD_ROHM_BD71828 is not set +# CONFIG_MFD_STPMIC1 is not set +# CONFIG_MFD_STMFX is not set +# CONFIG_MFD_INTEL_M10_BMC is not set +# end of Multifunction device drivers + CONFIG_REGULATOR=y # CONFIG_REGULATOR_DEBUG is not set CONFIG_REGULATOR_FIXED_VOLTAGE=y # CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set # CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +# CONFIG_REGULATOR_88PG86X is not set # CONFIG_REGULATOR_ACT8865 is not set # CONFIG_REGULATOR_AD5398 is not set -# CONFIG_REGULATOR_ANATOP is not set +# CONFIG_REGULATOR_DA9121 is not set # CONFIG_REGULATOR_DA9210 is not set # CONFIG_REGULATOR_DA9211 is not set # CONFIG_REGULATOR_FAN53555 is not set +# CONFIG_REGULATOR_FAN53880 is not set # CONFIG_REGULATOR_GPIO is not set # CONFIG_REGULATOR_ISL9305 is not set # CONFIG_REGULATOR_ISL6271A is not set @@ -2327,11 +2513,25 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y # CONFIG_REGULATOR_MAX8660 is not set # CONFIG_REGULATOR_MAX8952 is not set # CONFIG_REGULATOR_MAX8973 is not set +# CONFIG_REGULATOR_MAX77826 is not set +# CONFIG_REGULATOR_MCP16502 is not set +# CONFIG_REGULATOR_MP5416 is not set +# CONFIG_REGULATOR_MP8859 is not set +# CONFIG_REGULATOR_MP886X is not set +# CONFIG_REGULATOR_MPQ7920 is not set # CONFIG_REGULATOR_MT6311 is not set +# CONFIG_REGULATOR_PCA9450 is not set # CONFIG_REGULATOR_PFUZE100 is not set # CONFIG_REGULATOR_PV88060 is not set # CONFIG_REGULATOR_PV88080 is not set # CONFIG_REGULATOR_PV88090 is not set +# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set +# CONFIG_REGULATOR_RT4801 is not set +# CONFIG_REGULATOR_RTMV20 is not set +# CONFIG_REGULATOR_SLG51000 is not set +# CONFIG_REGULATOR_SY8106A is not set +# CONFIG_REGULATOR_SY8824X is not set +# CONFIG_REGULATOR_SY8827N is not set # CONFIG_REGULATOR_TPS51632 is not set # CONFIG_REGULATOR_TPS62360 is not set # CONFIG_REGULATOR_TPS65023 is not set @@ -2341,8 +2541,8 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y # CONFIG_REGULATOR_VCTRL is not set CONFIG_RC_CORE=y CONFIG_RC_MAP=y -CONFIG_RC_DECODERS=y # CONFIG_LIRC is not set +CONFIG_RC_DECODERS=y CONFIG_IR_NEC_DECODER=y CONFIG_IR_RC5_DECODER=y CONFIG_IR_RC6_DECODER=y @@ -2352,30 +2552,63 @@ CONFIG_IR_SANYO_DECODER=y CONFIG_IR_SHARP_DECODER=y CONFIG_IR_MCE_KBD_DECODER=y CONFIG_IR_XMP_DECODER=y +# CONFIG_IR_IMON_DECODER is not set +# CONFIG_IR_RCMM_DECODER is not set # CONFIG_RC_DEVICES is not set +CONFIG_CEC_CORE=y +# CONFIG_MEDIA_CEC_RC is not set +# CONFIG_MEDIA_CEC_SUPPORT is not set CONFIG_MEDIA_SUPPORT=y +# CONFIG_MEDIA_SUPPORT_FILTER is not set +CONFIG_MEDIA_SUBDRV_AUTOSELECT=y # -# Multimedia core support +# Media device types # CONFIG_MEDIA_CAMERA_SUPPORT=y -# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set -# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set -# CONFIG_MEDIA_RADIO_SUPPORT is not set -# CONFIG_MEDIA_SDR_SUPPORT is not set -# CONFIG_MEDIA_CEC_SUPPORT is not set -CONFIG_MEDIA_CONTROLLER=y +CONFIG_MEDIA_ANALOG_TV_SUPPORT=y +CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y +CONFIG_MEDIA_RADIO_SUPPORT=y +CONFIG_MEDIA_SDR_SUPPORT=y +CONFIG_MEDIA_PLATFORM_SUPPORT=y +CONFIG_MEDIA_TEST_SUPPORT=y +# end of Media device types + +# +# Media core support +# CONFIG_VIDEO_DEV=y -CONFIG_VIDEO_V4L2_SUBDEV_API=y +CONFIG_MEDIA_CONTROLLER=y +CONFIG_DVB_CORE=y +# end of Media core support + +# +# Video4Linux options +# CONFIG_VIDEO_V4L2=y +CONFIG_VIDEO_V4L2_I2C=y +CONFIG_VIDEO_V4L2_SUBDEV_API=y CONFIG_VIDEO_ADV_DEBUG=y # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set CONFIG_V4L2_FWNODE=y -CONFIG_VIDEOBUF2_CORE=y -CONFIG_VIDEOBUF2_MEMOPS=y -CONFIG_VIDEOBUF2_DMA_CONTIG=y -CONFIG_VIDEOBUF2_VMALLOC=y -# CONFIG_TTPCI_EEPROM is not set +# end of Video4Linux options + +# +# Media controller options +# +# CONFIG_MEDIA_CONTROLLER_DVB is not set +# end of Media controller options + +# +# Digital TV options +# +# CONFIG_DVB_MMAP is not set +CONFIG_DVB_NET=y +CONFIG_DVB_MAX_ADAPTERS=16 +CONFIG_DVB_DYNAMIC_MINORS=y +# CONFIG_DVB_DEMUX_SECTION_LOSS_LOG is not set +# CONFIG_DVB_ULE_DEBUG is not set +# end of Digital TV options # # Media drivers @@ -2444,98 +2677,512 @@ CONFIG_USB_GSPCA=y # CONFIG_USB_S2255 is not set # CONFIG_VIDEO_USBTV is not set +# +# Analog TV USB devices +# +# CONFIG_VIDEO_PVRUSB2 is not set +# CONFIG_VIDEO_HDPVR is not set +# CONFIG_VIDEO_STK1160_COMMON is not set +# CONFIG_VIDEO_GO7007 is not set + +# +# Analog/digital TV USB devices +# +# CONFIG_VIDEO_AU0828 is not set +# CONFIG_VIDEO_CX231XX is not set +# CONFIG_VIDEO_TM6000 is not set + +# +# Digital TV USB devices +# +# CONFIG_DVB_USB is not set +# CONFIG_DVB_USB_V2 is not set +# CONFIG_SMS_USB_DRV is not set +# CONFIG_DVB_B2C2_FLEXCOP_USB is not set +# CONFIG_DVB_AS102 is not set + # # Webcam, TV (analog/digital) USB devices # # CONFIG_VIDEO_EM28XX is not set + +# +# Software defined radio USB devices +# +# CONFIG_USB_AIRSPY is not set +# CONFIG_USB_HACKRF is not set +# CONFIG_USB_MSI2500 is not set +CONFIG_RADIO_ADAPTERS=y +# CONFIG_RADIO_SI470X is not set +# CONFIG_RADIO_SI4713 is not set +# CONFIG_USB_MR800 is not set +# CONFIG_USB_DSBR is not set +# CONFIG_RADIO_SHARK is not set +# CONFIG_RADIO_SHARK2 is not set +# CONFIG_USB_KEENE is not set +# CONFIG_USB_RAREMONO is not set +# CONFIG_USB_MA901 is not set +# CONFIG_RADIO_TEA5764 is not set +# CONFIG_RADIO_SAA7706H is not set +# CONFIG_RADIO_TEF6862 is not set +# CONFIG_RADIO_WL1273 is not set +CONFIG_VIDEOBUF2_CORE=y +CONFIG_VIDEOBUF2_V4L2=y +CONFIG_VIDEOBUF2_MEMOPS=y +CONFIG_VIDEOBUF2_DMA_CONTIG=y +CONFIG_VIDEOBUF2_VMALLOC=y CONFIG_V4L_PLATFORM_DRIVERS=y +# CONFIG_VIDEO_CADENCE is not set +# CONFIG_VIDEO_ASPEED is not set # CONFIG_VIDEO_MUX is not set CONFIG_VIDEO_AXI_HDMI_RX=y CONFIG_VIDEO_IMAGEON_BRIDGE=y -# CONFIG_SOC_CAMERA is not set # CONFIG_VIDEO_XILINX is not set # CONFIG_V4L_MEM2MEM_DRIVERS is not set # CONFIG_ADI_AXI_VIDEO_FRAME_BUFFER is not set +# CONFIG_DVB_PLATFORM_DRIVERS is not set +# CONFIG_SDR_PLATFORM_DRIVERS is not set + +# +# MMC/SDIO DVB adapters +# +# CONFIG_SMS_SDIO_DRV is not set # CONFIG_V4L_TEST_DRIVERS is not set +# CONFIG_DVB_TEST_DRIVERS is not set +# end of Media drivers # -# Supported MMC/SDIO adapters +# Media ancillary drivers # -# CONFIG_CYPRESS_FIRMWARE is not set +CONFIG_MEDIA_ATTACH=y # -# Media ancillary drivers (tuners, sensors, i2c, spi, frontends) +# IR I2C driver auto-selected by 'Autoselect ancillary drivers' # -CONFIG_MEDIA_SUBDRV_AUTOSELECT=y CONFIG_VIDEO_IR_I2C=y # # Audio decoders, processors and mixers # +# CONFIG_VIDEO_TVAUDIO is not set +# CONFIG_VIDEO_TDA7432 is not set +# CONFIG_VIDEO_TDA9840 is not set +# CONFIG_VIDEO_TDA1997X is not set +# CONFIG_VIDEO_TEA6415C is not set +# CONFIG_VIDEO_TEA6420 is not set +# CONFIG_VIDEO_MSP3400 is not set +# CONFIG_VIDEO_CS3308 is not set +# CONFIG_VIDEO_CS5345 is not set +# CONFIG_VIDEO_CS53L32A is not set +# CONFIG_VIDEO_TLV320AIC23B is not set +# CONFIG_VIDEO_UDA1342 is not set +# CONFIG_VIDEO_WM8775 is not set +# CONFIG_VIDEO_WM8739 is not set +# CONFIG_VIDEO_VP27SMPX is not set +# CONFIG_VIDEO_SONY_BTF_MPX is not set +# end of Audio decoders, processors and mixers # # RDS decoders # +# CONFIG_VIDEO_SAA6588 is not set +# end of RDS decoders # # Video decoders # +# CONFIG_VIDEO_ADV7180 is not set +# CONFIG_VIDEO_ADV7183 is not set +# CONFIG_VIDEO_ADV748X is not set CONFIG_VIDEO_ADV7604=y +# CONFIG_VIDEO_ADV7604_CEC is not set +# CONFIG_VIDEO_ADV7842 is not set +# CONFIG_VIDEO_BT819 is not set +# CONFIG_VIDEO_BT856 is not set +# CONFIG_VIDEO_BT866 is not set +# CONFIG_VIDEO_KS0127 is not set +# CONFIG_VIDEO_ML86V7667 is not set +# CONFIG_VIDEO_SAA7110 is not set +# CONFIG_VIDEO_SAA711X is not set +# CONFIG_VIDEO_TC358743 is not set +# CONFIG_VIDEO_TVP514X is not set +# CONFIG_VIDEO_TVP5150 is not set +# CONFIG_VIDEO_TVP7002 is not set +# CONFIG_VIDEO_TW2804 is not set +# CONFIG_VIDEO_TW9903 is not set +# CONFIG_VIDEO_TW9906 is not set +# CONFIG_VIDEO_TW9910 is not set +# CONFIG_VIDEO_VPX3220 is not set +# CONFIG_VIDEO_MAX9286 is not set # # Video and audio decoders # +# CONFIG_VIDEO_SAA717X is not set +# CONFIG_VIDEO_CX25840 is not set +# end of Video decoders # # Video encoders # +# CONFIG_VIDEO_SAA7127 is not set +# CONFIG_VIDEO_SAA7185 is not set +# CONFIG_VIDEO_ADV7170 is not set +# CONFIG_VIDEO_ADV7175 is not set +# CONFIG_VIDEO_ADV7343 is not set +# CONFIG_VIDEO_ADV7393 is not set CONFIG_VIDEO_ADV7511=y - -# -# Camera sensor devices -# - -# -# Flash devices -# +# CONFIG_VIDEO_ADV7511_CEC is not set +# CONFIG_VIDEO_AD9389B is not set +# CONFIG_VIDEO_AK881X is not set +# CONFIG_VIDEO_THS8200 is not set +# end of Video encoders # # Video improvement chips # +# CONFIG_VIDEO_UPD64031A is not set +# CONFIG_VIDEO_UPD64083 is not set +# end of Video improvement chips + +# CONFIG_VIDEO_AP1302 is not set # # Audio/Video compression chips # +# CONFIG_VIDEO_SAA6752HS is not set +# end of Audio/Video compression chips # # SDR tuner chips # +# CONFIG_SDR_MAX2175 is not set +# end of SDR tuner chips # # Miscellaneous helper chips # +# CONFIG_VIDEO_THS7303 is not set +# CONFIG_VIDEO_M52790 is not set +# CONFIG_VIDEO_I2C is not set +# CONFIG_VIDEO_ST_MIPID02 is not set +# end of Miscellaneous helper chips # -# Sensors used on soc_camera driver +# Camera sensor devices # +# CONFIG_VIDEO_ADDI9036 is not set +# CONFIG_VIDEO_HI556 is not set +# CONFIG_VIDEO_IMX214 is not set +# CONFIG_VIDEO_IMX219 is not set +# CONFIG_VIDEO_IMX258 is not set +# CONFIG_VIDEO_IMX274 is not set +# CONFIG_VIDEO_IMX290 is not set +# CONFIG_VIDEO_IMX319 is not set +# CONFIG_VIDEO_IMX355 is not set +# CONFIG_VIDEO_OV2640 is not set +# CONFIG_VIDEO_OV2659 is not set +# CONFIG_VIDEO_OV2680 is not set +# CONFIG_VIDEO_OV2685 is not set +# CONFIG_VIDEO_OV5640 is not set +# CONFIG_VIDEO_OV5645 is not set +# CONFIG_VIDEO_OV5647 is not set +# CONFIG_VIDEO_OV6650 is not set +# CONFIG_VIDEO_OV5670 is not set +# CONFIG_VIDEO_OV5675 is not set +# CONFIG_VIDEO_OV5695 is not set +# CONFIG_VIDEO_OV7251 is not set +# CONFIG_VIDEO_OV772X is not set +# CONFIG_VIDEO_OV7640 is not set +# CONFIG_VIDEO_OV7670 is not set +# CONFIG_VIDEO_OV7740 is not set +# CONFIG_VIDEO_OV8856 is not set +# CONFIG_VIDEO_OV9640 is not set +# CONFIG_VIDEO_OV9650 is not set +# CONFIG_VIDEO_OV13858 is not set +# CONFIG_VIDEO_VS6624 is not set +# CONFIG_VIDEO_MT9M001 is not set +# CONFIG_VIDEO_MT9M032 is not set +# CONFIG_VIDEO_MT9M111 is not set +# CONFIG_VIDEO_MT9P031 is not set +# CONFIG_VIDEO_MT9T001 is not set +# CONFIG_VIDEO_MT9T112 is not set +# CONFIG_VIDEO_MT9V011 is not set +# CONFIG_VIDEO_MT9V032 is not set +# CONFIG_VIDEO_MT9V111 is not set +# CONFIG_VIDEO_SR030PC30 is not set +# CONFIG_VIDEO_NOON010PC30 is not set +# CONFIG_VIDEO_M5MOLS is not set +# CONFIG_VIDEO_RDACM20 is not set +# CONFIG_VIDEO_RJ54N1 is not set +# CONFIG_VIDEO_S5K6AA is not set +# CONFIG_VIDEO_S5K6A3 is not set +# CONFIG_VIDEO_S5K4ECGX is not set +# CONFIG_VIDEO_S5K5BAF is not set +# CONFIG_VIDEO_SMIAPP is not set +# CONFIG_VIDEO_ET8EK8 is not set +# CONFIG_VIDEO_S5C73M3 is not set +# end of Camera sensor devices + +# +# Lens drivers +# +# CONFIG_VIDEO_AD5820 is not set +# CONFIG_VIDEO_AK7375 is not set +# CONFIG_VIDEO_DW9714 is not set +# CONFIG_VIDEO_DW9768 is not set +# CONFIG_VIDEO_DW9807_VCM is not set +# end of Lens drivers + +# +# Flash devices +# +# CONFIG_VIDEO_ADP1653 is not set +# CONFIG_VIDEO_LM3560 is not set +# CONFIG_VIDEO_LM3646 is not set +# end of Flash devices + +# +# SPI helper chips +# +# CONFIG_VIDEO_GS1662 is not set +# end of SPI helper chips + +# +# Media SPI Adapters +# +# CONFIG_CXD2880_SPI_DRV is not set +# end of Media SPI Adapters + +CONFIG_MEDIA_TUNER=y + +# +# Customize TV tuners +# +CONFIG_MEDIA_TUNER_SIMPLE=y +# CONFIG_MEDIA_TUNER_TDA18250 is not set +CONFIG_MEDIA_TUNER_TDA8290=y +CONFIG_MEDIA_TUNER_TDA827X=y +CONFIG_MEDIA_TUNER_TDA18271=y +CONFIG_MEDIA_TUNER_TDA9887=y +CONFIG_MEDIA_TUNER_TEA5761=y +CONFIG_MEDIA_TUNER_TEA5767=y +# CONFIG_MEDIA_TUNER_MSI001 is not set +CONFIG_MEDIA_TUNER_MT20XX=y +# CONFIG_MEDIA_TUNER_MT2060 is not set +# CONFIG_MEDIA_TUNER_MT2063 is not set +# CONFIG_MEDIA_TUNER_MT2266 is not set +# CONFIG_MEDIA_TUNER_MT2131 is not set +# CONFIG_MEDIA_TUNER_QT1010 is not set +CONFIG_MEDIA_TUNER_XC2028=y +CONFIG_MEDIA_TUNER_XC5000=y +CONFIG_MEDIA_TUNER_XC4000=y +# CONFIG_MEDIA_TUNER_MXL5005S is not set +# CONFIG_MEDIA_TUNER_MXL5007T is not set +CONFIG_MEDIA_TUNER_MC44S803=y +# CONFIG_MEDIA_TUNER_MAX2165 is not set +# CONFIG_MEDIA_TUNER_TDA18218 is not set +# CONFIG_MEDIA_TUNER_FC0011 is not set +# CONFIG_MEDIA_TUNER_FC0012 is not set +# CONFIG_MEDIA_TUNER_FC0013 is not set +# CONFIG_MEDIA_TUNER_TDA18212 is not set +# CONFIG_MEDIA_TUNER_E4000 is not set +# CONFIG_MEDIA_TUNER_FC2580 is not set +# CONFIG_MEDIA_TUNER_M88RS6000T is not set +# CONFIG_MEDIA_TUNER_TUA9001 is not set +# CONFIG_MEDIA_TUNER_SI2157 is not set +# CONFIG_MEDIA_TUNER_IT913X is not set +# CONFIG_MEDIA_TUNER_R820T is not set +# CONFIG_MEDIA_TUNER_MXL301RF is not set +# CONFIG_MEDIA_TUNER_QM1D1C0042 is not set +# CONFIG_MEDIA_TUNER_QM1D1B0004 is not set +# end of Customize TV tuners + +# +# Customise DVB Frontends +# + +# +# Multistandard (satellite) frontends +# +# CONFIG_DVB_STB0899 is not set +# CONFIG_DVB_STB6100 is not set +# CONFIG_DVB_STV090x is not set +# CONFIG_DVB_STV0910 is not set +# CONFIG_DVB_STV6110x is not set +# CONFIG_DVB_STV6111 is not set +# CONFIG_DVB_MXL5XX is not set +# CONFIG_DVB_M88DS3103 is not set + +# +# Multistandard (cable + terrestrial) frontends +# +# CONFIG_DVB_DRXK is not set +# CONFIG_DVB_TDA18271C2DD is not set +# CONFIG_DVB_SI2165 is not set +# CONFIG_DVB_MN88472 is not set +# CONFIG_DVB_MN88473 is not set + +# +# DVB-S (satellite) frontends +# +# CONFIG_DVB_CX24110 is not set +# CONFIG_DVB_CX24123 is not set +# CONFIG_DVB_MT312 is not set +# CONFIG_DVB_ZL10036 is not set +# CONFIG_DVB_ZL10039 is not set +# CONFIG_DVB_S5H1420 is not set +# CONFIG_DVB_STV0288 is not set +# CONFIG_DVB_STB6000 is not set +# CONFIG_DVB_STV0299 is not set +# CONFIG_DVB_STV6110 is not set +# CONFIG_DVB_STV0900 is not set +# CONFIG_DVB_TDA8083 is not set +# CONFIG_DVB_TDA10086 is not set +# CONFIG_DVB_TDA8261 is not set +# CONFIG_DVB_VES1X93 is not set +# CONFIG_DVB_TUNER_ITD1000 is not set +# CONFIG_DVB_TUNER_CX24113 is not set +# CONFIG_DVB_TDA826X is not set +# CONFIG_DVB_TUA6100 is not set +# CONFIG_DVB_CX24116 is not set +# CONFIG_DVB_CX24117 is not set +# CONFIG_DVB_CX24120 is not set +# CONFIG_DVB_SI21XX is not set +# CONFIG_DVB_TS2020 is not set +# CONFIG_DVB_DS3000 is not set +# CONFIG_DVB_MB86A16 is not set +# CONFIG_DVB_TDA10071 is not set + +# +# DVB-T (terrestrial) frontends +# +# CONFIG_DVB_SP8870 is not set +# CONFIG_DVB_SP887X is not set +# CONFIG_DVB_CX22700 is not set +# CONFIG_DVB_CX22702 is not set +# CONFIG_DVB_S5H1432 is not set +# CONFIG_DVB_DRXD is not set +# CONFIG_DVB_L64781 is not set +# CONFIG_DVB_TDA1004X is not set +# CONFIG_DVB_NXT6000 is not set +# CONFIG_DVB_MT352 is not set +# CONFIG_DVB_ZL10353 is not set +# CONFIG_DVB_DIB3000MB is not set +# CONFIG_DVB_DIB3000MC is not set +# CONFIG_DVB_DIB7000M is not set +# CONFIG_DVB_DIB7000P is not set +# CONFIG_DVB_DIB9000 is not set +# CONFIG_DVB_TDA10048 is not set +# CONFIG_DVB_AF9013 is not set +# CONFIG_DVB_EC100 is not set +# CONFIG_DVB_STV0367 is not set +# CONFIG_DVB_CXD2820R is not set +# CONFIG_DVB_CXD2841ER is not set +# CONFIG_DVB_RTL2830 is not set +# CONFIG_DVB_RTL2832 is not set +# CONFIG_DVB_RTL2832_SDR is not set +# CONFIG_DVB_SI2168 is not set +# CONFIG_DVB_ZD1301_DEMOD is not set +# CONFIG_DVB_CXD2880 is not set + +# +# DVB-C (cable) frontends +# +# CONFIG_DVB_VES1820 is not set +# CONFIG_DVB_TDA10021 is not set +# CONFIG_DVB_TDA10023 is not set +# CONFIG_DVB_STV0297 is not set + +# +# ATSC (North American/Korean Terrestrial/Cable DTV) frontends +# +# CONFIG_DVB_NXT200X is not set +# CONFIG_DVB_OR51211 is not set +# CONFIG_DVB_OR51132 is not set +# CONFIG_DVB_BCM3510 is not set +# CONFIG_DVB_LGDT330X is not set +# CONFIG_DVB_LGDT3305 is not set +# CONFIG_DVB_LGDT3306A is not set +# CONFIG_DVB_LG2160 is not set +# CONFIG_DVB_S5H1409 is not set +# CONFIG_DVB_AU8522_DTV is not set +# CONFIG_DVB_AU8522_V4L is not set +# CONFIG_DVB_S5H1411 is not set + +# +# ISDB-T (terrestrial) frontends +# +# CONFIG_DVB_S921 is not set +# CONFIG_DVB_DIB8000 is not set +# CONFIG_DVB_MB86A20S is not set + +# +# ISDB-S (satellite) & ISDB-T (terrestrial) frontends +# +# CONFIG_DVB_TC90522 is not set +# CONFIG_DVB_MN88443X is not set + +# +# Digital terrestrial only tuners/PLL +# +# CONFIG_DVB_PLL is not set +# CONFIG_DVB_TUNER_DIB0070 is not set +# CONFIG_DVB_TUNER_DIB0090 is not set + +# +# SEC control devices for DVB-S +# +# CONFIG_DVB_DRX39XYJ is not set +# CONFIG_DVB_LNBH25 is not set +# CONFIG_DVB_LNBH29 is not set +# CONFIG_DVB_LNBP21 is not set +# CONFIG_DVB_LNBP22 is not set +# CONFIG_DVB_ISL6405 is not set +# CONFIG_DVB_ISL6421 is not set +# CONFIG_DVB_ISL6423 is not set +# CONFIG_DVB_A8293 is not set +# CONFIG_DVB_LGS8GL5 is not set +# CONFIG_DVB_LGS8GXX is not set +# CONFIG_DVB_ATBM8830 is not set +# CONFIG_DVB_TDA665x is not set +# CONFIG_DVB_IX2505V is not set +# CONFIG_DVB_M88RS2000 is not set +# CONFIG_DVB_AF9033 is not set +# CONFIG_DVB_HORUS3A is not set +# CONFIG_DVB_ASCOT2E is not set +# CONFIG_DVB_HELENE is not set + +# +# Common Interface (EN50221) controller drivers +# +# CONFIG_DVB_CXD2099 is not set +# CONFIG_DVB_SP2 is not set +# end of Customise DVB Frontends # # Tools to develop new frontends # +# CONFIG_DVB_DUMMY_FE is not set +# end of Media ancillary drivers # # Graphics support # # CONFIG_IMX_IPUV3_CORE is not set CONFIG_DRM=y +CONFIG_DRM_MIPI_DSI=y # CONFIG_DRM_DP_AUX_CHARDEV is not set # CONFIG_DRM_DEBUG_MM is not set -# CONFIG_DRM_DEBUG_MM_SELFTEST is not set +# CONFIG_DRM_DEBUG_SELFTEST is not set CONFIG_DRM_KMS_HELPER=y CONFIG_DRM_KMS_FB_HELPER=y +# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set CONFIG_DRM_FBDEV_EMULATION=y CONFIG_DRM_FBDEV_OVERALLOC=100 +# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set # CONFIG_DRM_LOAD_EDID_FIRMWARE is not set +# CONFIG_DRM_DP_CEC is not set CONFIG_DRM_GEM_CMA_HELPER=y CONFIG_DRM_KMS_CMA_HELPER=y @@ -2545,18 +3192,25 @@ CONFIG_DRM_KMS_CMA_HELPER=y # CONFIG_DRM_I2C_CH7006 is not set # CONFIG_DRM_I2C_SIL164 is not set # CONFIG_DRM_I2C_NXP_TDA998X is not set -# CONFIG_DRM_HDLCD is not set -# CONFIG_DRM_MALI_DISPLAY is not set +# CONFIG_DRM_I2C_NXP_TDA9950 is not set +# end of I2C encoder or helper chips # -# ACP (Audio CoProcessor) Configuration +# ARM devices # -# CONFIG_DRM_VGEM is not set +# CONFIG_DRM_HDLCD is not set +# CONFIG_DRM_MALI_DISPLAY is not set +# CONFIG_DRM_KOMEDA is not set +# end of ARM devices + CONFIG_DRM_ADI_AXI_HDMI=m +# CONFIG_DRM_VGEM is not set +# CONFIG_DRM_VKMS is not set # CONFIG_DRM_EXYNOS is not set # CONFIG_DRM_UDL is not set # CONFIG_DRM_ARMADA is not set # CONFIG_DRM_RCAR_DW_HDMI is not set +# CONFIG_DRM_RCAR_LVDS is not set # CONFIG_DRM_OMAP is not set # CONFIG_DRM_TILCDC is not set # CONFIG_DRM_FSL_DCU is not set @@ -2566,64 +3220,136 @@ CONFIG_DRM_PANEL=y # # Display Panels # +# CONFIG_DRM_PANEL_ARM_VERSATILE is not set +# CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596 is not set +# CONFIG_DRM_PANEL_BOE_HIMAX8279D is not set +# CONFIG_DRM_PANEL_BOE_TV101WUM_NL6 is not set # CONFIG_DRM_PANEL_LVDS is not set # CONFIG_DRM_PANEL_SIMPLE is not set +# CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set +# CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set +# CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set +# CONFIG_DRM_PANEL_ILITEK_IL9322 is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set +# CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set +# CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set +# CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04 is not set +# CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W is not set +# CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 is not set # CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set +# CONFIG_DRM_PANEL_LG_LB035Q02 is not set # CONFIG_DRM_PANEL_LG_LG4573 is not set +# CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set +# CONFIG_DRM_PANEL_NOVATEK_NT35510 is not set +# CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set +# CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set +# CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set +# CONFIG_DRM_PANEL_ORISETECH_OTM8009A is not set +# CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS is not set +# CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00 is not set +# CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN is not set +# CONFIG_DRM_PANEL_RAYDIUM_RM67191 is not set +# CONFIG_DRM_PANEL_RAYDIUM_RM68200 is not set +# CONFIG_DRM_PANEL_RONBO_RB070D30 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set +# CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set +# CONFIG_DRM_PANEL_SHARP_LQ101R1SX01 is not set +# CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set +# CONFIG_DRM_PANEL_SHARP_LS043T1LE01 is not set +# CONFIG_DRM_PANEL_SITRONIX_ST7701 is not set +# CONFIG_DRM_PANEL_SITRONIX_ST7703 is not set # CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set +# CONFIG_DRM_PANEL_SONY_ACX424AKP is not set +# CONFIG_DRM_PANEL_SONY_ACX565AKM is not set +# CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set +# CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set +# CONFIG_DRM_PANEL_TPO_TPG110 is not set +# CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA is not set +# CONFIG_DRM_PANEL_VISIONOX_RM69299 is not set +# CONFIG_DRM_PANEL_XINPENG_XPP055C272 is not set +# end of Display Panels + CONFIG_DRM_BRIDGE=y CONFIG_DRM_PANEL_BRIDGE=y # # Display Interface Bridges # -# CONFIG_DRM_ANALOGIX_ANX78XX is not set -# CONFIG_DRM_DUMB_VGA_DAC is not set -# CONFIG_DRM_LVDS_ENCODER is not set +# CONFIG_DRM_CDNS_DSI is not set +# CONFIG_DRM_CHRONTEL_CH7033 is not set +# CONFIG_DRM_DISPLAY_CONNECTOR is not set +# CONFIG_DRM_LONTIUM_LT9611 is not set +# CONFIG_DRM_LVDS_CODEC is not set # CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set +# CONFIG_DRM_NWL_MIPI_DSI is not set # CONFIG_DRM_NXP_PTN3460 is not set # CONFIG_DRM_PARADE_PS8622 is not set +# CONFIG_DRM_PARADE_PS8640 is not set # CONFIG_DRM_SIL_SII8620 is not set # CONFIG_DRM_SII902X is not set +# CONFIG_DRM_SII9234 is not set +# CONFIG_DRM_SIMPLE_BRIDGE is not set +# CONFIG_DRM_THINE_THC63LVD1024 is not set +# CONFIG_DRM_TOSHIBA_TC358762 is not set +# CONFIG_DRM_TOSHIBA_TC358764 is not set # CONFIG_DRM_TOSHIBA_TC358767 is not set +# CONFIG_DRM_TOSHIBA_TC358768 is not set +# CONFIG_DRM_TOSHIBA_TC358775 is not set # CONFIG_DRM_TI_TFP410 is not set +# CONFIG_DRM_TI_SN65DSI86 is not set +# CONFIG_DRM_TI_TPD12S015 is not set +# CONFIG_DRM_ANALOGIX_ANX6345 is not set +# CONFIG_DRM_ANALOGIX_ANX78XX is not set CONFIG_DRM_I2C_ADV7511=y CONFIG_DRM_I2C_ADV7511_AUDIO=y -# CONFIG_DRM_I2C_ADV7533 is not set +CONFIG_DRM_I2C_ADV7511_CEC=y +# CONFIG_DRM_CDNS_MHDP8546 is not set +# end of Display Interface Bridges + # CONFIG_DRM_STI is not set -# CONFIG_DRM_XILINX is not set -# CONFIG_DRM_ZOCL is not set +# CONFIG_DRM_ETNAVIV is not set # CONFIG_DRM_ARCPGU is not set # CONFIG_DRM_MXSFB is not set -# CONFIG_DRM_TINYDRM is not set +# CONFIG_DRM_GM12U320 is not set +# CONFIG_TINYDRM_HX8357D is not set +# CONFIG_TINYDRM_ILI9225 is not set +# CONFIG_TINYDRM_ILI9341 is not set +# CONFIG_TINYDRM_ILI9486 is not set +# CONFIG_TINYDRM_MI0283QT is not set +# CONFIG_TINYDRM_REPAPER is not set +# CONFIG_TINYDRM_ST7586 is not set +# CONFIG_TINYDRM_ST7735R is not set # CONFIG_DRM_PL111 is not set +# CONFIG_DRM_TVE200 is not set +# CONFIG_DRM_LIMA is not set +# CONFIG_DRM_PANFROST is not set +# CONFIG_DRM_MCDE is not set +# CONFIG_DRM_TIDSS is not set # CONFIG_DRM_XLNX is not set # CONFIG_DRM_LEGACY is not set -# CONFIG_DRM_LIB_RANDOM is not set +CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y # # Frame buffer Devices # -CONFIG_FB=y -# CONFIG_FIRMWARE_EDID is not set CONFIG_FB_CMDLINE=y CONFIG_FB_NOTIFY=y -# CONFIG_FB_DDC is not set -# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set CONFIG_FB_CFB_FILLRECT=y CONFIG_FB_CFB_COPYAREA=y CONFIG_FB_CFB_IMAGEBLIT=y -# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set CONFIG_FB_SYS_FILLRECT=y CONFIG_FB_SYS_COPYAREA=y CONFIG_FB_SYS_IMAGEBLIT=y -# CONFIG_FB_PROVIDE_GET_FB_UNMAPPED_AREA is not set # CONFIG_FB_FOREIGN_ENDIAN is not set CONFIG_FB_SYS_FOPS=y CONFIG_FB_DEFERRED_IO=y -# CONFIG_FB_SVGALIB is not set -# CONFIG_FB_MACMODES is not set CONFIG_FB_BACKLIGHT=y # CONFIG_FB_MODE_HELPERS is not set # CONFIG_FB_TILEBLITTING is not set @@ -2631,6 +3357,7 @@ CONFIG_FB_BACKLIGHT=y # # Frame buffer hardware drivers # +# CONFIG_FB_ALTERA_VIP is not set # CONFIG_FB_ARMCLCD is not set # CONFIG_FB_UVESA is not set # CONFIG_FB_OPENCORES is not set @@ -2641,11 +3368,13 @@ CONFIG_FB_BACKLIGHT=y # CONFIG_FB_XILINX is not set # CONFIG_FB_VIRTUAL is not set # CONFIG_FB_METRONOME is not set -# CONFIG_FB_BROADSHEET is not set -# CONFIG_FB_AUO_K190X is not set # CONFIG_FB_SIMPLE is not set # CONFIG_FB_SSD1307 is not set -CONFIG_BACKLIGHT_LCD_SUPPORT=y +# end of Frame buffer Devices + +# +# Backlight & LCD device support +# CONFIG_LCD_CLASS_DEVICE=m # CONFIG_LCD_L4F00242T03 is not set # CONFIG_LCD_LMS283GF05 is not set @@ -2655,14 +3384,13 @@ CONFIG_LCD_CLASS_DEVICE=m # CONFIG_LCD_TDO24M is not set # CONFIG_LCD_VGG2432A4 is not set # CONFIG_LCD_PLATFORM is not set -# CONFIG_LCD_S6E63M0 is not set -# CONFIG_LCD_LD9040 is not set # CONFIG_LCD_AMS369FG06 is not set # CONFIG_LCD_LMS501KF03 is not set # CONFIG_LCD_HX8357 is not set +# CONFIG_LCD_OTM3225A is not set CONFIG_BACKLIGHT_CLASS_DEVICE=y -CONFIG_BACKLIGHT_GENERIC=y -# CONFIG_BACKLIGHT_PM8941_WLED is not set +# CONFIG_BACKLIGHT_KTD253 is not set +# CONFIG_BACKLIGHT_QCOM_WLED is not set # CONFIG_BACKLIGHT_ADP8860 is not set # CONFIG_BACKLIGHT_ADP8870 is not set # CONFIG_BACKLIGHT_LM3639 is not set @@ -2670,7 +3398,9 @@ CONFIG_BACKLIGHT_GENERIC=y # CONFIG_BACKLIGHT_LV5207LP is not set # CONFIG_BACKLIGHT_BD6107 is not set # CONFIG_BACKLIGHT_ARCXCNN is not set -# CONFIG_VGASTATE is not set +# CONFIG_BACKLIGHT_LED is not set +# end of Backlight & LCD device support + CONFIG_HDMI=y # @@ -2680,12 +3410,16 @@ CONFIG_DUMMY_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y # CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +# CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set +# end of Console display driver support + CONFIG_LOGO=y CONFIG_LOGO_LINUX_MONO=y CONFIG_LOGO_LINUX_VGA16=y CONFIG_LOGO_LINUX_CLUT224=y +# end of Graphics support + CONFIG_SOUND=y -# CONFIG_SOUND_OSS_CORE is not set CONFIG_SND=y CONFIG_SND_TIMER=y CONFIG_SND_PCM=y @@ -2705,13 +3439,13 @@ CONFIG_SND_PROC_FS=y # CONFIG_SND_VERBOSE_PRINTK is not set # CONFIG_SND_DEBUG is not set # CONFIG_SND_SEQUENCER is not set -# CONFIG_SND_OPL3_LIB_SEQ is not set -# CONFIG_SND_OPL4_LIB_SEQ is not set # CONFIG_SND_DRIVERS is not set # # HD-Audio # +# end of HD-Audio + CONFIG_SND_HDA_PREALLOC_SIZE=64 # CONFIG_SND_ARM is not set # CONFIG_SND_SPI is not set @@ -2724,6 +3458,7 @@ CONFIG_SND_SOC_ADI_AXI_SPDIF=y CONFIG_SND_SOC_ADRV936X_BOX=y # CONFIG_SND_SOC_AMD_ACP is not set # CONFIG_SND_ATMEL_SOC is not set +# CONFIG_SND_BCM63XX_I2S_WHISTLER is not set # CONFIG_SND_DESIGNWARE_I2S is not set # @@ -2735,19 +3470,28 @@ CONFIG_SND_SOC_ADRV936X_BOX=y # # CONFIG_SND_SOC_FSL_ASRC is not set # CONFIG_SND_SOC_FSL_SAI is not set +# CONFIG_SND_SOC_FSL_AUDMIX is not set # CONFIG_SND_SOC_FSL_SSI is not set # CONFIG_SND_SOC_FSL_SPDIF is not set # CONFIG_SND_SOC_FSL_ESAI is not set +# CONFIG_SND_SOC_FSL_MICFIL is not set # CONFIG_SND_SOC_IMX_AUDMUX is not set +# end of SoC Audio for Freescale CPUs + # CONFIG_SND_I2S_HI6210_I2S is not set # CONFIG_SND_SOC_IMG is not set +# CONFIG_SND_SOC_MTK_BTCVSD is not set +# CONFIG_SND_SOC_SOF_TOPLEVEL is not set # # STMicroelectronics STM32 SOC audio support # +# end of STMicroelectronics STM32 SOC audio support + # CONFIG_SND_SOC_XILINX_DP is not set # CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set # CONFIG_SND_SOC_XILINX_I2S is not set +# CONFIG_SND_SOC_XILINX_SPDIF is not set # CONFIG_SND_SOC_XTFPGA_I2S is not set # CONFIG_ZX_TDM is not set CONFIG_SND_SOC_I2C_AND_SPI=y @@ -2764,58 +3508,82 @@ CONFIG_SND_SOC_ADAU1761=y CONFIG_SND_SOC_ADAU1761_I2C=y # CONFIG_SND_SOC_ADAU1761_SPI is not set # CONFIG_SND_SOC_ADAU7002 is not set +# CONFIG_SND_SOC_ADAU7118_HW is not set +# CONFIG_SND_SOC_ADAU7118_I2C is not set # CONFIG_SND_SOC_AK4104 is not set +# CONFIG_SND_SOC_AK4118 is not set +# CONFIG_SND_SOC_AK4458 is not set # CONFIG_SND_SOC_AK4554 is not set # CONFIG_SND_SOC_AK4613 is not set # CONFIG_SND_SOC_AK4642 is not set # CONFIG_SND_SOC_AK5386 is not set +# CONFIG_SND_SOC_AK5558 is not set # CONFIG_SND_SOC_ALC5623 is not set +# CONFIG_SND_SOC_BD28623 is not set # CONFIG_SND_SOC_BT_SCO is not set # CONFIG_SND_SOC_CS35L32 is not set # CONFIG_SND_SOC_CS35L33 is not set # CONFIG_SND_SOC_CS35L34 is not set # CONFIG_SND_SOC_CS35L35 is not set +# CONFIG_SND_SOC_CS35L36 is not set # CONFIG_SND_SOC_CS42L42 is not set # CONFIG_SND_SOC_CS42L51_I2C is not set # CONFIG_SND_SOC_CS42L52 is not set # CONFIG_SND_SOC_CS42L56 is not set # CONFIG_SND_SOC_CS42L73 is not set +# CONFIG_SND_SOC_CS4234 is not set # CONFIG_SND_SOC_CS4265 is not set # CONFIG_SND_SOC_CS4270 is not set # CONFIG_SND_SOC_CS4271_I2C is not set # CONFIG_SND_SOC_CS4271_SPI is not set # CONFIG_SND_SOC_CS42XX8_I2C is not set # CONFIG_SND_SOC_CS43130 is not set +# CONFIG_SND_SOC_CS4341 is not set # CONFIG_SND_SOC_CS4349 is not set # CONFIG_SND_SOC_CS53L30 is not set -# CONFIG_SND_SOC_DIO2125 is not set +# CONFIG_SND_SOC_CX2072X is not set +# CONFIG_SND_SOC_DA7213 is not set +# CONFIG_SND_SOC_DMIC is not set CONFIG_SND_SOC_HDMI_CODEC=y # CONFIG_SND_SOC_ES7134 is not set +# CONFIG_SND_SOC_ES7241 is not set # CONFIG_SND_SOC_ES8316 is not set # CONFIG_SND_SOC_ES8328_I2C is not set # CONFIG_SND_SOC_ES8328_SPI is not set # CONFIG_SND_SOC_GTM601 is not set # CONFIG_SND_SOC_INNO_RK3036 is not set +# CONFIG_SND_SOC_MAX98088 is not set +# CONFIG_SND_SOC_MAX98357A is not set # CONFIG_SND_SOC_MAX98504 is not set +# CONFIG_SND_SOC_MAX9867 is not set # CONFIG_SND_SOC_MAX98927 is not set +# CONFIG_SND_SOC_MAX98373_I2C is not set +# CONFIG_SND_SOC_MAX98390 is not set # CONFIG_SND_SOC_MAX9860 is not set # CONFIG_SND_SOC_MSM8916_WCD_DIGITAL is not set # CONFIG_SND_SOC_PCM1681 is not set +# CONFIG_SND_SOC_PCM1789_I2C is not set # CONFIG_SND_SOC_PCM179X_I2C is not set # CONFIG_SND_SOC_PCM179X_SPI is not set +# CONFIG_SND_SOC_PCM186X_I2C is not set +# CONFIG_SND_SOC_PCM186X_SPI is not set +# CONFIG_SND_SOC_PCM3060_I2C is not set +# CONFIG_SND_SOC_PCM3060_SPI is not set # CONFIG_SND_SOC_PCM3168A_I2C is not set # CONFIG_SND_SOC_PCM3168A_SPI is not set # CONFIG_SND_SOC_PCM512x_I2C is not set # CONFIG_SND_SOC_PCM512x_SPI is not set +# CONFIG_SND_SOC_RK3328 is not set # CONFIG_SND_SOC_RT5616 is not set # CONFIG_SND_SOC_RT5631 is not set -# CONFIG_SND_SOC_RT5677_SPI is not set # CONFIG_SND_SOC_SGTL5000 is not set CONFIG_SND_SOC_SIGMADSP=y CONFIG_SND_SOC_SIGMADSP_I2C=y CONFIG_SND_SOC_SIGMADSP_REGMAP=y +# CONFIG_SND_SOC_SIMPLE_AMPLIFIER is not set # CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set # CONFIG_SND_SOC_SPDIF is not set +# CONFIG_SND_SOC_SSM2305 is not set # CONFIG_SND_SOC_SSM2602_SPI is not set # CONFIG_SND_SOC_SSM2602_I2C is not set # CONFIG_SND_SOC_SSM4567 is not set @@ -2823,15 +3591,26 @@ CONFIG_SND_SOC_SIGMADSP_REGMAP=y # CONFIG_SND_SOC_STA350 is not set # CONFIG_SND_SOC_STI_SAS is not set # CONFIG_SND_SOC_TAS2552 is not set +# CONFIG_SND_SOC_TAS2562 is not set +# CONFIG_SND_SOC_TAS2764 is not set +# CONFIG_SND_SOC_TAS2770 is not set # CONFIG_SND_SOC_TAS5086 is not set # CONFIG_SND_SOC_TAS571X is not set # CONFIG_SND_SOC_TAS5720 is not set +# CONFIG_SND_SOC_TAS6424 is not set +# CONFIG_SND_SOC_TDA7419 is not set # CONFIG_SND_SOC_TFA9879 is not set # CONFIG_SND_SOC_TLV320AIC23_I2C is not set # CONFIG_SND_SOC_TLV320AIC23_SPI is not set # CONFIG_SND_SOC_TLV320AIC31XX is not set +# CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set +# CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set # CONFIG_SND_SOC_TLV320AIC3X is not set +# CONFIG_SND_SOC_TLV320ADCX140 is not set CONFIG_SND_SOC_TS3A227E=y +# CONFIG_SND_SOC_TSCS42XX is not set +# CONFIG_SND_SOC_TSCS454 is not set +# CONFIG_SND_SOC_UDA1334 is not set # CONFIG_SND_SOC_WM8510 is not set # CONFIG_SND_SOC_WM8523 is not set # CONFIG_SND_SOC_WM8524 is not set @@ -2845,24 +3624,32 @@ CONFIG_SND_SOC_TS3A227E=y # CONFIG_SND_SOC_WM8753 is not set # CONFIG_SND_SOC_WM8770 is not set # CONFIG_SND_SOC_WM8776 is not set +# CONFIG_SND_SOC_WM8782 is not set # CONFIG_SND_SOC_WM8804_I2C is not set # CONFIG_SND_SOC_WM8804_SPI is not set # CONFIG_SND_SOC_WM8903 is not set +# CONFIG_SND_SOC_WM8904 is not set # CONFIG_SND_SOC_WM8960 is not set # CONFIG_SND_SOC_WM8962 is not set # CONFIG_SND_SOC_WM8974 is not set # CONFIG_SND_SOC_WM8978 is not set # CONFIG_SND_SOC_WM8985 is not set +# CONFIG_SND_SOC_ZL38060 is not set # CONFIG_SND_SOC_ZX_AUD96P22 is not set +# CONFIG_SND_SOC_MAX9759 is not set +# CONFIG_SND_SOC_MT6351 is not set +# CONFIG_SND_SOC_MT6358 is not set +# CONFIG_SND_SOC_MT6660 is not set # CONFIG_SND_SOC_NAU8540 is not set # CONFIG_SND_SOC_NAU8810 is not set +# CONFIG_SND_SOC_NAU8822 is not set # CONFIG_SND_SOC_NAU8824 is not set # CONFIG_SND_SOC_TPA6130A2 is not set +# end of CODEC drivers + CONFIG_SND_SIMPLE_CARD_UTILS=y CONFIG_SND_SIMPLE_CARD=y -# CONFIG_SND_SIMPLE_SCU_CARD is not set # CONFIG_SND_AUDIO_GRAPH_CARD is not set -# CONFIG_SND_AUDIO_GRAPH_SCU_CARD is not set # # HID support @@ -2886,31 +3673,40 @@ CONFIG_HID_APPLE=y # CONFIG_HID_AUREAL is not set CONFIG_HID_BELKIN=y # CONFIG_HID_BETOP_FF is not set +# CONFIG_HID_BIGBEN_FF is not set CONFIG_HID_CHERRY=y CONFIG_HID_CHICONY=y # CONFIG_HID_CORSAIR is not set +# CONFIG_HID_COUGAR is not set +# CONFIG_HID_MACALLY is not set CONFIG_HID_PRODIKEYS=y # CONFIG_HID_CMEDIA is not set # CONFIG_HID_CP2112 is not set +# CONFIG_HID_CREATIVE_SB0540 is not set CONFIG_HID_CYPRESS=y CONFIG_HID_DRAGONRISE=y # CONFIG_DRAGONRISE_FF is not set CONFIG_HID_EMS_FF=y +# CONFIG_HID_ELAN is not set # CONFIG_HID_ELECOM is not set # CONFIG_HID_ELO is not set CONFIG_HID_EZKEY=y # CONFIG_HID_GEMBIRD is not set # CONFIG_HID_GFRM is not set +# CONFIG_HID_GLORIOUS is not set CONFIG_HID_HOLTEK=y CONFIG_HOLTEK_FF=y +# CONFIG_HID_VIVALDI is not set # CONFIG_HID_GT683R is not set CONFIG_HID_KEYTOUCH=y CONFIG_HID_KYE=y CONFIG_HID_UCLOGIC=y CONFIG_HID_WALTOP=y +# CONFIG_HID_VIEWSONIC is not set CONFIG_HID_GYRATION=y # CONFIG_HID_ICADE is not set # CONFIG_HID_ITE is not set +# CONFIG_HID_JABRA is not set CONFIG_HID_TWINHAN=y CONFIG_HID_KENSINGTON=y CONFIG_HID_LCPOWER=y @@ -2924,7 +3720,9 @@ CONFIG_LOGIRUMBLEPAD2_FF=y CONFIG_LOGIG940_FF=y CONFIG_LOGIWHEELS_FF=y # CONFIG_HID_MAGICMOUSE is not set +# CONFIG_HID_MALTRON is not set # CONFIG_HID_MAYFLASH is not set +# CONFIG_HID_REDRAGON is not set CONFIG_HID_MICROSOFT=y CONFIG_HID_MONTEREY=y CONFIG_HID_MULTITOUCH=y @@ -2949,6 +3747,7 @@ CONFIG_HID_SAMSUNG=y CONFIG_HID_SONY=y # CONFIG_SONY_FF is not set CONFIG_HID_SPEEDLINK=y +# CONFIG_HID_STEAM is not set # CONFIG_HID_STEELSERIES is not set CONFIG_HID_SUNPLUS=y # CONFIG_HID_RMI is not set @@ -2970,6 +3769,8 @@ CONFIG_ZEROPLUS_FF=y CONFIG_HID_ZYDACRON=y # CONFIG_HID_SENSOR_HUB is not set # CONFIG_HID_ALPS is not set +# CONFIG_HID_MCP2221 is not set +# end of Special HID drivers # # USB HID support @@ -2977,14 +3778,21 @@ CONFIG_HID_ZYDACRON=y CONFIG_USB_HID=y # CONFIG_HID_PID is not set CONFIG_USB_HIDDEV=y +# end of USB HID support # # I2C HID support # # CONFIG_I2C_HID is not set +# end of I2C HID support +# end of HID support + CONFIG_USB_OHCI_LITTLE_ENDIAN=y CONFIG_USB_SUPPORT=y CONFIG_USB_COMMON=y +# CONFIG_USB_LED_TRIG is not set +CONFIG_USB_ULPI_BUS=y +# CONFIG_USB_CONN_GPIO is not set CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB=y # CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set @@ -2993,14 +3801,15 @@ CONFIG_USB=y # Miscellaneous USB options # CONFIG_USB_DEFAULT_PERSIST=y +# CONFIG_USB_FEW_INIT_RETRIES is not set # CONFIG_USB_DYNAMIC_MINORS is not set CONFIG_USB_OTG=y -# CONFIG_USB_OTG_WHITELIST is not set -# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_OTG_PRODUCTLIST is not set +# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set # CONFIG_USB_OTG_FSM is not set # CONFIG_USB_LEDS_TRIGGER_USBPORT is not set +CONFIG_USB_AUTOSUSPEND_DELAY=2 # CONFIG_USB_MON is not set -# CONFIG_USB_WUSB_CBAF is not set # # USB Host Controller Drivers @@ -3010,10 +3819,10 @@ CONFIG_USB_OTG=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_ROOT_HUB_TT=y # CONFIG_USB_EHCI_TT_NEWSCHED is not set +# CONFIG_USB_EHCI_FSL is not set # CONFIG_USB_EHCI_HCD_PLATFORM is not set # CONFIG_USB_OXU210HP_HCD is not set # CONFIG_USB_ISP116X_HCD is not set -# CONFIG_USB_ISP1362_HCD is not set # CONFIG_USB_FOTG210_HCD is not set # CONFIG_USB_MAX3421_HCD is not set # CONFIG_USB_OHCI_HCD is not set @@ -3059,14 +3868,17 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_MDC800 is not set # CONFIG_USB_MICROTEK is not set # CONFIG_USBIP_CORE is not set +# CONFIG_USB_CDNS3 is not set # CONFIG_USB_MUSB_HDRC is not set # CONFIG_USB_DWC3 is not set # CONFIG_USB_DWC2 is not set CONFIG_USB_CHIPIDEA=y -CONFIG_USB_CHIPIDEA_OF=y CONFIG_USB_CHIPIDEA_UDC=y CONFIG_USB_CHIPIDEA_HOST=y -# CONFIG_USB_CHIPIDEA_ULPI is not set +CONFIG_USB_CHIPIDEA_MSM=y +CONFIG_USB_CHIPIDEA_IMX=y +CONFIG_USB_CHIPIDEA_GENERIC=y +CONFIG_USB_CHIPIDEA_TEGRA=y # CONFIG_USB_ISP1760 is not set # @@ -3134,7 +3946,6 @@ CONFIG_USB_SERIAL_FTDI_SIO=y # CONFIG_USB_EMI26 is not set # CONFIG_USB_ADUTUX is not set # CONFIG_USB_SEVSEG is not set -# CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set # CONFIG_USB_CYPRESS_CY7C63 is not set @@ -3142,6 +3953,7 @@ CONFIG_USB_SERIAL_FTDI_SIO=y # CONFIG_USB_IDMOUSE is not set # CONFIG_USB_FTDI_ELAN is not set # CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_APPLE_MFI_FASTCHARGE is not set # CONFIG_USB_SISUSBVGA is not set # CONFIG_USB_LD is not set # CONFIG_USB_TRANCEVIBRATOR is not set @@ -3152,6 +3964,7 @@ CONFIG_USB_SERIAL_FTDI_SIO=y # CONFIG_USB_YUREX is not set # CONFIG_USB_EZUSB_FX2 is not set # CONFIG_USB_HUB_USB251XB is not set +# CONFIG_USB_USB5744 is not set # CONFIG_USB_HSIC_USB3503 is not set # CONFIG_USB_HSIC_USB4604 is not set # CONFIG_USB_LINK_LAYER_TEST is not set @@ -3159,12 +3972,13 @@ CONFIG_USB_SERIAL_FTDI_SIO=y # # USB Physical Layer drivers # -# CONFIG_USB_PHY is not set # CONFIG_NOP_USB_XCEIV is not set # CONFIG_USB_GPIO_VBUS is not set # CONFIG_USB_ISP1301 is not set CONFIG_USB_ULPI=y CONFIG_USB_ULPI_VIEWPORT=y +# end of USB Physical Layer drivers + CONFIG_USB_GADGET=y # CONFIG_USB_GADGET_DEBUG is not set # CONFIG_USB_GADGET_DEBUG_FILES is not set @@ -3188,7 +4002,10 @@ CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 # CONFIG_USB_BDC_UDC is not set # CONFIG_USB_NET2272 is not set CONFIG_USB_GADGET_XILINX=y +# CONFIG_USB_MAX3420_UDC is not set # CONFIG_USB_DUMMY_HCD is not set +# end of USB Peripheral Controller + CONFIG_USB_LIBCOMPOSITE=y CONFIG_USB_F_ACM=y CONFIG_USB_U_SERIAL=y @@ -3214,12 +4031,29 @@ CONFIG_USB_CONFIGFS_F_FS=y # CONFIG_USB_CONFIGFS_F_PRINTER is not set # -# USB Power Delivery and Type-C drivers +# USB Gadget precomposed configurations # -# CONFIG_TYPEC_UCSI is not set -# CONFIG_USB_LED_TRIG is not set -CONFIG_USB_ULPI_BUS=y -# CONFIG_UWB is not set +# CONFIG_USB_ZERO is not set +# CONFIG_USB_AUDIO is not set +# CONFIG_USB_ETH is not set +# CONFIG_USB_G_NCM is not set +# CONFIG_USB_GADGETFS is not set +# CONFIG_USB_FUNCTIONFS is not set +# CONFIG_USB_MASS_STORAGE is not set +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_G_PRINTER is not set +# CONFIG_USB_CDC_COMPOSITE is not set +# CONFIG_USB_G_ACM_MS is not set +# CONFIG_USB_G_MULTI is not set +# CONFIG_USB_G_HID is not set +# CONFIG_USB_G_DBGP is not set +# CONFIG_USB_G_WEBCAM is not set +# CONFIG_USB_RAW_GADGET is not set +# end of USB Gadget precomposed configurations + +# CONFIG_TYPEC is not set +CONFIG_USB_ROLE_SWITCH=y CONFIG_MMC=y CONFIG_PWRSEQ_EMMC=y CONFIG_PWRSEQ_SIMPLE=y @@ -3236,37 +4070,49 @@ CONFIG_MMC_BLOCK_MINORS=8 CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SDHCI_OF_ARASAN=y +# CONFIG_MMC_SDHCI_OF_ASPEED is not set # CONFIG_MMC_SDHCI_OF_AT91 is not set +# CONFIG_MMC_SDHCI_OF_DWCMSHC is not set # CONFIG_MMC_SDHCI_CADENCE is not set # CONFIG_MMC_SDHCI_F_SDH30 is not set +# CONFIG_MMC_SDHCI_MILBEAUT is not set # CONFIG_MMC_SPI is not set # CONFIG_MMC_DW is not set # CONFIG_MMC_VUB300 is not set # CONFIG_MMC_USHC is not set # CONFIG_MMC_USDHI6ROL0 is not set +CONFIG_MMC_CQHCI=y +# CONFIG_MMC_HSQ is not set # CONFIG_MMC_MTK is not set # CONFIG_MMC_SDHCI_XENON is not set +# CONFIG_MMC_SDHCI_OMAP is not set +# CONFIG_MMC_SDHCI_AM654 is not set # CONFIG_MEMSTICK is not set CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y # CONFIG_LEDS_CLASS_FLASH is not set +# CONFIG_LEDS_CLASS_MULTICOLOR is not set # CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set # # LED drivers # +# CONFIG_LEDS_AN30259A is not set +# CONFIG_LEDS_AW2013 is not set # CONFIG_LEDS_BCM6328 is not set # CONFIG_LEDS_BCM6358 is not set +# CONFIG_LEDS_CR0014114 is not set +# CONFIG_LEDS_EL15203000 is not set # CONFIG_LEDS_LM3530 is not set +# CONFIG_LEDS_LM3532 is not set # CONFIG_LEDS_LM3642 is not set +# CONFIG_LEDS_LM3692X is not set # CONFIG_LEDS_PCA9532 is not set CONFIG_LEDS_GPIO=y # CONFIG_LEDS_LP3944 is not set # CONFIG_LEDS_LP3952 is not set -# CONFIG_LEDS_LP5521 is not set -# CONFIG_LEDS_LP5523 is not set -# CONFIG_LEDS_LP5562 is not set -# CONFIG_LEDS_LP8501 is not set +# CONFIG_LEDS_LP50XX is not set +# CONFIG_LEDS_LP55XX_COMMON is not set # CONFIG_LEDS_LP8860 is not set # CONFIG_LEDS_PCA955X is not set # CONFIG_LEDS_PCA963X is not set @@ -3285,7 +4131,10 @@ CONFIG_LEDS_GPIO=y # # CONFIG_LEDS_BLINKM is not set # CONFIG_LEDS_SYSCON is not set +# CONFIG_LEDS_MLXREG is not set CONFIG_LEDS_USER=y +# CONFIG_LEDS_SPI_BYTE is not set +# CONFIG_LEDS_TI_LMU_COMMON is not set # # LED Triggers @@ -3297,6 +4146,7 @@ CONFIG_LEDS_TRIGGER_ONESHOT=y CONFIG_LEDS_TRIGGER_HEARTBEAT=y # CONFIG_LEDS_TRIGGER_BACKLIGHT is not set CONFIG_LEDS_TRIGGER_CPU=y +# CONFIG_LEDS_TRIGGER_ACTIVITY is not set CONFIG_LEDS_TRIGGER_GPIO=y # CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set @@ -3306,7 +4156,11 @@ CONFIG_LEDS_TRIGGER_GPIO=y # CONFIG_LEDS_TRIGGER_TRANSIENT is not set # CONFIG_LEDS_TRIGGER_CAMERA is not set # CONFIG_LEDS_TRIGGER_PANIC is not set +# CONFIG_LEDS_TRIGGER_NETDEV is not set +# CONFIG_LEDS_TRIGGER_PATTERN is not set +# CONFIG_LEDS_TRIGGER_AUDIO is not set # CONFIG_ACCESSIBILITY is not set +# CONFIG_INFINIBAND is not set CONFIG_EDAC_ATOMIC_SCRUB=y CONFIG_EDAC_SUPPORT=y CONFIG_RTC_LIB=y @@ -3331,6 +4185,7 @@ CONFIG_RTC_INTF_DEV=y # I2C RTC drivers # # CONFIG_RTC_DRV_ABB5ZES3 is not set +# CONFIG_RTC_DRV_ABEOZ9 is not set # CONFIG_RTC_DRV_ABX80X is not set # CONFIG_RTC_DRV_DS1307 is not set # CONFIG_RTC_DRV_DS1374 is not set @@ -3340,9 +4195,11 @@ CONFIG_RTC_INTF_DEV=y # CONFIG_RTC_DRV_RS5C372 is not set # CONFIG_RTC_DRV_ISL1208 is not set # CONFIG_RTC_DRV_ISL12022 is not set +# CONFIG_RTC_DRV_ISL12026 is not set # CONFIG_RTC_DRV_X1205 is not set # CONFIG_RTC_DRV_PCF8523 is not set # CONFIG_RTC_DRV_PCF85063 is not set +# CONFIG_RTC_DRV_PCF85363 is not set CONFIG_RTC_DRV_PCF8563=y # CONFIG_RTC_DRV_PCF8583 is not set # CONFIG_RTC_DRV_M41T80 is not set @@ -3353,7 +4210,10 @@ CONFIG_RTC_DRV_PCF8563=y # CONFIG_RTC_DRV_RX8581 is not set # CONFIG_RTC_DRV_RX8025 is not set # CONFIG_RTC_DRV_EM3027 is not set +# CONFIG_RTC_DRV_RV3028 is not set +# CONFIG_RTC_DRV_RV3032 is not set # CONFIG_RTC_DRV_RV8803 is not set +# CONFIG_RTC_DRV_SD3078 is not set # # SPI RTC drivers @@ -3408,14 +4268,13 @@ CONFIG_RTC_DRV_DS3232_HWMON=y # # CONFIG_RTC_DRV_PL030 is not set # CONFIG_RTC_DRV_PL031 is not set +# CONFIG_RTC_DRV_CADENCE is not set # CONFIG_RTC_DRV_FTRTC010 is not set -# CONFIG_RTC_DRV_SNVS is not set # CONFIG_RTC_DRV_R7301 is not set # # HID Sensor RTC drivers # -# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set CONFIG_DMADEVICES=y # CONFIG_DMADEVICES_DEBUG is not set @@ -3428,52 +4287,62 @@ CONFIG_DMA_OF=y # CONFIG_ALTERA_MSGDMA is not set # CONFIG_AMBA_PL08X is not set CONFIG_AXI_DMAC=y +# CONFIG_DW_AXI_DMAC is not set # CONFIG_FSL_EDMA is not set +# CONFIG_FSL_QDMA is not set # CONFIG_INTEL_IDMA64 is not set # CONFIG_NBPFAXI_DMA is not set CONFIG_PL330_DMA=y -CONFIG_XILINX_DMA_ENGINES=y -CONFIG_XILINX_DMATEST=m -# CONFIG_XILINX_VDMATEST is not set -# CONFIG_XILINX_CDMATEST is not set -# CONFIG_XILINX_DPDMA is not set -# CONFIG_XILINX_FRMBUF is not set CONFIG_XILINX_DMA=m # CONFIG_XILINX_ZYNQMP_DMA is not set +# CONFIG_XILINX_ZYNQMP_DPDMA is not set +# CONFIG_XILINX_FRMBUF is not set # CONFIG_QCOM_HIDMA_MGMT is not set # CONFIG_QCOM_HIDMA is not set # CONFIG_DW_DMAC is not set +# CONFIG_SF_PDMA is not set # # DMA Clients # # CONFIG_ASYNC_TX_DMA is not set # CONFIG_DMATEST is not set +CONFIG_XILINX_DMATEST=m +# CONFIG_XILINX_VDMATEST is not set # # DMABUF options # CONFIG_SYNC_FILE=y # CONFIG_SW_SYNC is not set +# CONFIG_UDMABUF is not set +# CONFIG_DMABUF_MOVE_NOTIFY is not set +# CONFIG_DMABUF_SELFTESTS is not set +# CONFIG_DMABUF_HEAPS is not set +# end of DMABUF options + # CONFIG_AUXDISPLAY is not set CONFIG_UIO=y CONFIG_UIO_PDRV_GENIRQ=y CONFIG_UIO_DMEM_GENIRQ=y # CONFIG_UIO_PRUSS is not set CONFIG_UIO_XILINX_APM=y +# CONFIG_UIO_XILINX_AI_ENGINE is not set # CONFIG_VIRT_DRIVERS is not set - -# -# Virtio drivers -# +CONFIG_VIRTIO_MENU=y # CONFIG_VIRTIO_MMIO is not set +# CONFIG_VDPA is not set +CONFIG_VHOST_MENU=y +# CONFIG_VHOST_NET is not set +# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set # # Microsoft Hyper-V guest support # -# CONFIG_HYPERV_TSCPAGE is not set +# end of Microsoft Hyper-V guest support + +# CONFIG_GREYBUS is not set CONFIG_STAGING=y -# CONFIG_IRDA is not set # CONFIG_COMEDI is not set # @@ -3483,88 +4352,68 @@ CONFIG_STAGING=y # # Accelerometers # -CONFIG_ADIS16201=y CONFIG_ADIS16203=y -CONFIG_ADIS16209=y CONFIG_ADIS16240=y +# end of Accelerometers # # Analog to digital converters # -CONFIG_AD7780=y CONFIG_AD7816=y -CONFIG_AD7192=y CONFIG_AD7280=y +# end of Analog to digital converters # # Analog digital bi-direction converters # # CONFIG_ADT7316 is not set +# end of Analog digital bi-direction converters # # Capacitance to digital converters # # CONFIG_AD7150 is not set -# CONFIG_AD7152 is not set # CONFIG_AD7746 is not set +# end of Capacitance to digital converters # # Direct Digital Synthesis # # CONFIG_AD9832 is not set # CONFIG_AD9834 is not set - -# -# Digital gyroscope sensors -# -CONFIG_ADIS16060=y +# end of Direct Digital Synthesis # # Network Analyzer, Impedance Converters # # CONFIG_AD5933 is not set - -# -# Light sensors -# -# CONFIG_TSL2x7x is not set +# end of Network Analyzer, Impedance Converters # # Active energy metering IC # -# CONFIG_ADE7753 is not set -# CONFIG_ADE7754 is not set -# CONFIG_ADE7758 is not set -# CONFIG_ADE7759 is not set # CONFIG_ADE7854 is not set +# end of Active energy metering IC # # Resolver to digital converters # -# CONFIG_AD2S90 is not set -# CONFIG_AD2S1200 is not set CONFIG_AD2S1210=y +# end of Resolver to digital converters +# end of IIO staging drivers -# -# Triggers - standalone -# - -# -# Speakup console speech -# -# CONFIG_SPEAKUP is not set # CONFIG_STAGING_MEDIA is not set # # Android # +# end of Android + # CONFIG_STAGING_BOARD is not set # CONFIG_LTE_GDM724X is not set -# CONFIG_MTD_SPINAND_MT29F is not set -# CONFIG_LNET is not set # CONFIG_GS_FPGABOOT is not set +# CONFIG_UNISYSSPAR is not set # CONFIG_XILINX_APF is not set -# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set CONFIG_FB_TFT=y # CONFIG_FB_TFT_AGM1264K_FL is not set # CONFIG_FB_TFT_BD663474 is not set @@ -3588,7 +4437,6 @@ CONFIG_FB_TFT_SEPS525=y # CONFIG_FB_TFT_SSD1289 is not set # CONFIG_FB_TFT_SSD1305 is not set # CONFIG_FB_TFT_SSD1306 is not set -# CONFIG_FB_TFT_SSD1325 is not set # CONFIG_FB_TFT_SSD1331 is not set # CONFIG_FB_TFT_SSD1351 is not set # CONFIG_FB_TFT_ST7735R is not set @@ -3599,35 +4447,33 @@ CONFIG_FB_TFT_SEPS525=y # CONFIG_FB_TFT_UC1701 is not set # CONFIG_FB_TFT_UPD161704 is not set # CONFIG_FB_TFT_WATTEROTT is not set -CONFIG_FB_FLEX=y -# CONFIG_FB_TFT_FBTFT_DEVICE is not set -# CONFIG_WILC1000_SDIO is not set -# CONFIG_WILC1000_SPI is not set -# CONFIG_MOST is not set # CONFIG_KS7010 is not set -# CONFIG_GREYBUS is not set -# CONFIG_CRYPTO_DEV_CCREE is not set +# CONFIG_PI433 is not set # -# USB Power Delivery and Type-C drivers +# Gasket devices # -# CONFIG_TYPEC_TCPM is not set -# CONFIG_PI433 is not set +# end of Gasket devices + +# CONFIG_XIL_AXIS_FIFO is not set +# CONFIG_FIELDBUS_DEV is not set +# CONFIG_WFX is not set # CONFIG_XILINX_FCLK is not set +# CONFIG_XLNX_TSMUX is not set # CONFIG_XROE_FRAMER is not set +# CONFIG_XROE_TRAFFIC_GEN is not set # CONFIG_GOLDFISH is not set # CONFIG_CHROME_PLATFORMS is not set +# CONFIG_MELLANOX_PLATFORM is not set +CONFIG_HAVE_CLK=y CONFIG_CLKDEV_LOOKUP=y CONFIG_HAVE_CLK_PREPARE=y CONFIG_COMMON_CLK=y - -# -# Common Clock Framework -# -CONFIG_ICST=y -# CONFIG_CLK_HSDK is not set +# CONFIG_COMMON_CLK_MAX9485 is not set +# CONFIG_COMMON_CLK_SI5341 is not set # CONFIG_COMMON_CLK_SI5351 is not set # CONFIG_COMMON_CLK_SI514 is not set +# CONFIG_COMMON_CLK_SI544 is not set CONFIG_COMMON_CLK_SI570=y # CONFIG_COMMON_CLK_SI5324 is not set # CONFIG_COMMON_CLK_IDT8T49N24X is not set @@ -3636,10 +4482,19 @@ CONFIG_COMMON_CLK_SI570=y # CONFIG_COMMON_CLK_CS2000_CP is not set CONFIG_COMMON_CLK_AXI_CLKGEN=y # CONFIG_CLK_QORIQ is not set -# CONFIG_COMMON_CLK_NXP is not set -# CONFIG_COMMON_CLK_PXA is not set -# CONFIG_COMMON_CLK_PIC32 is not set +CONFIG_COMMON_CLK_ADI=y # CONFIG_COMMON_CLK_VC5 is not set +# CONFIG_COMMON_CLK_FIXED_MMIO is not set +# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set +# CONFIG_COMMON_CLK_XLNX_CLKWZRD_V is not set + +# +# Analog Devices Clock Drivers +# +# CONFIG_COMMON_CLK_AD9545_I2C is not set +# CONFIG_COMMON_CLK_AD9545_SPI is not set +# end of Analog Devices Clock Drivers + # CONFIG_HWSPINLOCK is not set # @@ -3649,13 +4504,10 @@ CONFIG_TIMER_OF=y CONFIG_TIMER_PROBE=y CONFIG_CADENCE_TTC_TIMER=y CONFIG_ARM_GLOBAL_TIMER=y -# CONFIG_ARM_TIMER_SP804 is not set CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y -# CONFIG_ATMEL_PIT is not set -# CONFIG_SH_TIMER_CMT is not set -# CONFIG_SH_TIMER_MTU2 is not set -# CONFIG_SH_TIMER_TMU is not set -# CONFIG_EM_TIMER_STI is not set +# CONFIG_MICROCHIP_PIT64B is not set +# end of Clock Source drivers + # CONFIG_MAILBOX is not set # CONFIG_IOMMU_SUPPORT is not set @@ -3663,10 +4515,15 @@ CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y # Remoteproc drivers # # CONFIG_REMOTEPROC is not set +# end of Remoteproc drivers # # Rpmsg drivers # +# CONFIG_RPMSG_VIRTIO is not set +# end of Rpmsg drivers + +# CONFIG_SOUNDWIRE is not set # # SOC (System On Chip) specific Drivers @@ -3675,26 +4532,45 @@ CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y # # Amlogic SoC drivers # +# end of Amlogic SoC drivers + +# +# Aspeed SoC drivers +# +# end of Aspeed SoC drivers # # Broadcom SoC drivers # # CONFIG_SOC_BRCMSTB is not set +# end of Broadcom SoC drivers + +# +# NXP/Freescale QorIQ SoC drivers +# +# CONFIG_QUICC_ENGINE is not set +# CONFIG_FSL_RCPM is not set +# end of NXP/Freescale QorIQ SoC drivers # # i.MX SoC drivers # +# end of i.MX SoC drivers # # Qualcomm SoC drivers # -# CONFIG_SUNXI_SRAM is not set +# end of Qualcomm SoC drivers + # CONFIG_SOC_TI is not set # # Xilinx SoC drivers # # CONFIG_XILINX_VCU is not set +# end of Xilinx SoC drivers +# end of SOC (System On Chip) specific Drivers + # CONFIG_PM_DEVFREQ is not set CONFIG_EXTCON=y @@ -3702,38 +4578,50 @@ CONFIG_EXTCON=y # Extcon Device Drivers # # CONFIG_EXTCON_ADC_JACK is not set +# CONFIG_EXTCON_FSA9480 is not set # CONFIG_EXTCON_GPIO is not set # CONFIG_EXTCON_MAX3355 is not set +# CONFIG_EXTCON_PTN5150 is not set # CONFIG_EXTCON_RT8973A is not set # CONFIG_EXTCON_SM5502 is not set # CONFIG_EXTCON_USB_GPIO is not set CONFIG_MEMORY=y # CONFIG_ARM_PL172_MPMC is not set -CONFIG_PL35X_SMC=y +CONFIG_PL353_SMC=y CONFIG_IIO=y CONFIG_IIO_BUFFER=y # CONFIG_IIO_BUFFER_CB is not set CONFIG_IIO_BUFFER_DMA=y CONFIG_IIO_BUFFER_DMAENGINE=y +CONFIG_IIO_BUFFER_HW_CONSUMER=y CONFIG_IIO_KFIFO_BUF=y CONFIG_IIO_TRIGGERED_BUFFER=y -CONFIG_IIO_HW_CONSUMER=y CONFIG_IIO_CONFIGFS=y CONFIG_IIO_TRIGGER=y CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_IIO_SW_DEVICE is not set CONFIG_IIO_SW_TRIGGER=y +# CONFIG_IIO_TRIGGERED_EVENT is not set # # Accelerometers # +CONFIG_ADIS16201=y +CONFIG_ADIS16209=y +# CONFIG_ADXL313_I2C is not set +# CONFIG_ADXL313_SPI is not set CONFIG_ADXL345=y CONFIG_ADXL345_I2C=y CONFIG_ADXL345_SPI=y +# CONFIG_ADXL355_I2C is not set +# CONFIG_ADXL355_SPI is not set +# CONFIG_ADXL367_SPI is not set +# CONFIG_ADXL367_I2C is not set # CONFIG_ADXL372_SPI is not set # CONFIG_ADXL372_I2C is not set # CONFIG_BMA180 is not set # CONFIG_BMA220 is not set +# CONFIG_BMA400 is not set # CONFIG_BMC150_ACCEL is not set # CONFIG_DA280 is not set # CONFIG_DA311 is not set @@ -3755,17 +4643,21 @@ CONFIG_ADXL345_SPI=y # CONFIG_SCA3000 is not set # CONFIG_STK8312 is not set # CONFIG_STK8BA50 is not set +# end of Accelerometers # # Analog to digital converters # CONFIG_AD_SIGMA_DELTA=y # CONFIG_AD400X is not set +# CONFIG_AD4630 is not set CONFIG_AD7091R5=y # CONFIG_AD7124 is not set CONFIG_AD7173=y +CONFIG_AD7192=y CONFIG_AD7266=y CONFIG_AD7291=y +# CONFIG_AD7292 is not set CONFIG_AD7298=y CONFIG_AD738X=y CONFIG_AD7476=y @@ -3775,18 +4667,24 @@ CONFIG_AD7606_IFACE_SPI=y CONFIG_AD7766=y CONFIG_AD7768=y # CONFIG_AD7768_1 is not set +CONFIG_AD7780=y CONFIG_AD7791=y CONFIG_AD7793=y CONFIG_AD7887=y CONFIG_AD7923=y +# CONFIG_AD7949 is not set CONFIG_AD799X=y CONFIG_AD9963=y CONFIG_ADM1177=y +# CONFIG_ADI_AXI_ADC is not set CONFIG_CF_AXI_ADC=y +# CONFIG_AD9081 is not set +# CONFIG_AD9083 is not set # CONFIG_AD9208 is not set CONFIG_AD9361=m # CONFIG_AD9361_EXT_BAND_CONTROL is not set CONFIG_AD9371=y +# CONFIG_ADRV9001 is not set # CONFIG_ADRV9009 is not set CONFIG_AD6676=y CONFIG_AD9467=y @@ -3800,17 +4698,23 @@ CONFIG_CF_AXI_TDD=y # CONFIG_HI8435 is not set # CONFIG_HX711 is not set # CONFIG_INA2XX_ADC is not set +# CONFIG_INA260_ADC is not set +# CONFIG_LTC2308 is not set # CONFIG_LTC2471 is not set # CONFIG_LTC2485 is not set +# CONFIG_LTC2496 is not set # CONFIG_LTC2497 is not set # CONFIG_MAX1027 is not set # CONFIG_MAX11100 is not set # CONFIG_MAX1118 is not set +# CONFIG_MAX1241 is not set # CONFIG_MAX1363 is not set # CONFIG_MAX9611 is not set # CONFIG_MCP320X is not set # CONFIG_MCP3422 is not set +# CONFIG_MCP3911 is not set # CONFIG_NAU7802 is not set +# CONFIG_SD_ADC_MODULATOR is not set # CONFIG_TI_ADC081C is not set # CONFIG_TI_ADC0832 is not set # CONFIG_TI_ADC084S021 is not set @@ -3820,40 +4724,73 @@ CONFIG_CF_AXI_TDD=y # CONFIG_TI_ADC161S626 is not set # CONFIG_TI_ADS1015 is not set # CONFIG_TI_ADS7950 is not set +# CONFIG_TI_ADS8344 is not set # CONFIG_TI_ADS8688 is not set +# CONFIG_TI_ADS124S08 is not set # CONFIG_TI_TLC4541 is not set # CONFIG_VF610_ADC is not set CONFIG_XILINX_XADC=y +# CONFIG_VERSAL_SYSMON is not set +# end of Analog to digital converters + +# +# Analog to digital and digital to analog converters +# +# CONFIG_AD74413R is not set +# CONFIG_ONE_BIT_ADC_DAC is not set +# end of Analog to digital and digital to analog converters + +# +# Analog Front Ends +# +# CONFIG_IIO_RESCALE is not set +# end of Analog Front Ends # # Amplifiers # CONFIG_AD8366=y +# CONFIG_AD916X_AMP is not set +# CONFIG_ADA4250 is not set +# CONFIG_HMC425 is not set +# end of Amplifiers + +# +# Beamformers +# +# CONFIG_ADAR1000 is not set +# CONFIG_ADAR3000 is not set +# end of Beamformers # # Chemical Sensors # # CONFIG_ATLAS_PH_SENSOR is not set +# CONFIG_ATLAS_EZO_SENSOR is not set +# CONFIG_BME680 is not set # CONFIG_CCS811 is not set # CONFIG_IAQCORE is not set +# CONFIG_SCD30_CORE is not set +# CONFIG_SENSIRION_SGP30 is not set +# CONFIG_SPS30 is not set # CONFIG_VZ89X is not set +# end of Chemical Sensors # # Hid Sensor IIO Common # +# end of Hid Sensor IIO Common # # SSP Sensor Common # # CONFIG_IIO_SSP_SENSORHUB is not set - -# -# Counters -# +# end of SSP Sensor Common # # Digital to analog converters # +# CONFIG_AD3552R is not set CONFIG_AD5064=y CONFIG_AD5270=y CONFIG_AD5360=y @@ -3866,28 +4803,45 @@ CONFIG_AD5592R=y CONFIG_AD5593R=y CONFIG_AD5504=y CONFIG_AD5624R_SPI=y -CONFIG_LTC2632=y +# CONFIG_LTC2688 is not set # CONFIG_AD5686_SPI is not set # CONFIG_AD5696_I2C is not set CONFIG_AD5755=y # CONFIG_AD5758 is not set CONFIG_AD5761=y CONFIG_AD5764=y +# CONFIG_AD5766 is not set # CONFIG_AD5770R is not set CONFIG_AD5791=y +# CONFIG_AD7293 is not set CONFIG_AD7303=y CONFIG_AD8801=y # CONFIG_DPOT_DAC is not set +# CONFIG_DS4424 is not set +# CONFIG_LTC1660 is not set +CONFIG_LTC2632=y # CONFIG_M62332 is not set # CONFIG_MAX517 is not set # CONFIG_MAX5821 is not set # CONFIG_MCP4725 is not set # CONFIG_MCP4922 is not set +# CONFIG_TI_DAC082S085 is not set +# CONFIG_TI_DAC5571 is not set +# CONFIG_TI_DAC7311 is not set +# CONFIG_TI_DAC7612 is not set # CONFIG_VF610_DAC is not set +# end of Digital to analog converters # # IIO dummy driver # +# end of IIO dummy driver + +# +# Filters +# +# CONFIG_ADMV8818 is not set +# end of Filters # # Frequency Synthesizers DDS/PLL @@ -3901,7 +4855,13 @@ CONFIG_AD9523=y CONFIG_AD9528=y CONFIG_AD9548=y CONFIG_AD9517=y +# CONFIG_ADMV1013 is not set +# CONFIG_ADMV1014 is not set +# CONFIG_ADMV4420 is not set +# CONFIG_ADRF6780 is not set CONFIG_HMC7044=y +# CONFIG_LTC6952 is not set +# end of Clock Generator/Distribution # # Direct Digital Synthesis @@ -3912,15 +4872,27 @@ CONFIG_CF_AXI_DDS_AD9144=y CONFIG_CF_AXI_DDS_AD9162=y # CONFIG_CF_AXI_DDS_AD9172 is not set CONFIG_CF_AXI_DDS_AD9739A=y +# CONFIG_CF_AXI_DDS_AD9783 is not set # CONFIG_M2K_DAC is not set +# end of Direct Digital Synthesis # # Phase-Locked Loop (PLL) frequency synthesizers # +# CONFIG_ADF4159 is not set CONFIG_ADF4350=y -CONFIG_ADF5355=y -# CONFIG_ADF4371 is not set # CONFIG_ADF4360 is not set +# CONFIG_ADF4371 is not set +# CONFIG_ADF4377 is not set +CONFIG_ADF5355=y +# end of Phase-Locked Loop (PLL) frequency synthesizers + +# +# RF Font-Ends +# +# CONFIG_ADL5960 is not set +# end of RF Font-Ends +# end of Frequency Synthesizers DDS/PLL # # Digital gyroscope sensors @@ -3929,11 +4901,14 @@ CONFIG_ADIS16080=y CONFIG_ADIS16130=y CONFIG_ADIS16136=y CONFIG_ADIS16260=y +# CONFIG_ADXRS290 is not set CONFIG_ADXRS450=y # CONFIG_BMG160 is not set +# CONFIG_FXAS21002C is not set # CONFIG_MPU3050_I2C is not set # CONFIG_IIO_ST_GYRO_3AXIS is not set # CONFIG_ITG3200 is not set +# end of Digital gyroscope sensors # # Health Sensors @@ -3946,6 +4921,8 @@ CONFIG_ADXRS450=y # CONFIG_AFE4404 is not set # CONFIG_MAX30100 is not set # CONFIG_MAX30102 is not set +# end of Heart Rate Monitors +# end of Health Sensors # # Humidity sensors @@ -3953,40 +4930,52 @@ CONFIG_ADXRS450=y # CONFIG_AM2315 is not set # CONFIG_DHT11 is not set # CONFIG_HDC100X is not set +# CONFIG_HDC2010 is not set # CONFIG_HTS221 is not set # CONFIG_HTU21 is not set # CONFIG_SI7005 is not set # CONFIG_SI7020 is not set +# end of Humidity sensors # # Inertial measurement units # CONFIG_ADIS16400=y CONFIG_ADIS16460=y +# CONFIG_ADIS16475 is not set CONFIG_ADIS16480=y # CONFIG_BMI160_I2C is not set # CONFIG_BMI160_SPI is not set +# CONFIG_FXOS8700_I2C is not set +# CONFIG_FXOS8700_SPI is not set # CONFIG_KMX61 is not set +# CONFIG_INV_ICM42600_I2C is not set +# CONFIG_INV_ICM42600_SPI is not set # CONFIG_INV_MPU6050_I2C is not set # CONFIG_INV_MPU6050_SPI is not set # CONFIG_IIO_ST_LSM6DSX is not set +# end of Inertial measurement units + CONFIG_IIO_ADIS_LIB=y CONFIG_IIO_ADIS_LIB_BUFFER=y -CONFIG_JESD204=y # CONFIG_ALTERA_ARRIA10_JESD204_PHY is not set CONFIG_AXI_ADXCVR=y CONFIG_AXI_JESD204B=y CONFIG_AXI_JESD204_TX=y CONFIG_AXI_JESD204_RX=y CONFIG_XILINX_TRANSCEIVER=y +# CONFIG_ADI_IIO_FAKEDEV is not set # # Light sensors # # CONFIG_ADJD_S311 is not set +# CONFIG_ADUX1020 is not set +# CONFIG_AL3010 is not set # CONFIG_AL3320A is not set # CONFIG_APDS9300 is not set # CONFIG_APDS9960 is not set +# CONFIG_AS73211 is not set # CONFIG_BH1750 is not set # CONFIG_BH1780 is not set # CONFIG_CM32181 is not set @@ -3994,6 +4983,7 @@ CONFIG_XILINX_TRANSCEIVER=y # CONFIG_CM3323 is not set # CONFIG_CM3605 is not set # CONFIG_CM36651 is not set +# CONFIG_GP2AP002 is not set # CONFIG_GP2AP020A00F is not set # CONFIG_SENSORS_ISL29018 is not set # CONFIG_SENSORS_ISL29028 is not set @@ -4001,25 +4991,36 @@ CONFIG_XILINX_TRANSCEIVER=y # CONFIG_JSA1212 is not set # CONFIG_RPR0521 is not set # CONFIG_LTR501 is not set +# CONFIG_LV0104CS is not set # CONFIG_MAX44000 is not set +# CONFIG_MAX44009 is not set +# CONFIG_NOA1305 is not set # CONFIG_OPT3001 is not set # CONFIG_PA12203001 is not set +# CONFIG_SI1133 is not set # CONFIG_SI1145 is not set # CONFIG_STK3310 is not set +# CONFIG_ST_UVIS25 is not set # CONFIG_TCS3414 is not set # CONFIG_TCS3472 is not set # CONFIG_SENSORS_TSL2563 is not set # CONFIG_TSL2583 is not set +# CONFIG_TSL2772 is not set # CONFIG_TSL4531 is not set # CONFIG_US5182D is not set # CONFIG_VCNL4000 is not set +# CONFIG_VCNL4035 is not set +# CONFIG_VEML6030 is not set # CONFIG_VEML6070 is not set # CONFIG_VL6180 is not set +# CONFIG_ZOPT2201 is not set +# end of Light sensors # # Logic Analyzers # # CONFIG_M2K_LOGIC_ANALYZER is not set +# end of Logic Analyzers # # Magnetometer sensors @@ -4034,15 +5035,28 @@ CONFIG_XILINX_TRANSCEIVER=y # CONFIG_IIO_ST_MAGN_3AXIS is not set # CONFIG_SENSORS_HMC5843_I2C is not set # CONFIG_SENSORS_HMC5843_SPI is not set +# CONFIG_SENSORS_RM3100_I2C is not set +# CONFIG_SENSORS_RM3100_SPI is not set +# end of Magnetometer sensors # # Multiplexers # # CONFIG_IIO_MUX is not set +# CONFIG_IIO_GEN_MUX is not set +# end of Multiplexers + +# +# IIO Regmap Access Drivers +# +# CONFIG_IIO_REGMAP_I2C is not set +# CONFIG_IIO_REGMAP_SPI is not set +# end of IIO Regmap Access Drivers # # Inclinometer sensors # +# end of Inclinometer sensors # # Triggers - standalone @@ -4051,28 +5065,43 @@ CONFIG_IIO_HRTIMER_TRIGGER=y CONFIG_IIO_INTERRUPT_TRIGGER=y CONFIG_IIO_TIGHTLOOP_TRIGGER=y CONFIG_IIO_SYSFS_TRIGGER=y +# end of Triggers - standalone + +# +# Linear and angular position sensors +# +# end of Linear and angular position sensors # # Digital potentiometers # +# CONFIG_AD5272 is not set # CONFIG_DS1803 is not set +# CONFIG_MAX5432 is not set # CONFIG_MAX5481 is not set # CONFIG_MAX5487 is not set +# CONFIG_MCP4018 is not set # CONFIG_MCP4131 is not set # CONFIG_MCP4531 is not set +# CONFIG_MCP41010 is not set # CONFIG_TPL0102 is not set +# end of Digital potentiometers # # Digital potentiostats # # CONFIG_LMP91000 is not set +# end of Digital potentiostats # # Pressure sensors # # CONFIG_ABP060MG is not set # CONFIG_BMP280 is not set +# CONFIG_DLHL60D is not set +# CONFIG_DPS310 is not set # CONFIG_HP03 is not set +# CONFIG_ICP10100 is not set # CONFIG_MPL115_I2C is not set # CONFIG_MPL115_SPI is not set # CONFIG_MPL3115 is not set @@ -4082,121 +5111,158 @@ CONFIG_IIO_SYSFS_TRIGGER=y # CONFIG_T5403 is not set # CONFIG_HP206C is not set # CONFIG_ZPA2326 is not set +# end of Pressure sensors # # Lightning sensors # # CONFIG_AS3935 is not set +# end of Lightning sensors # # Proximity and distance sensors # +# CONFIG_ISL29501 is not set # CONFIG_LIDAR_LITE_V2 is not set +# CONFIG_MB1232 is not set +# CONFIG_PING is not set +# CONFIG_RFD77402 is not set # CONFIG_SRF04 is not set +# CONFIG_SX9310 is not set # CONFIG_SX9500 is not set # CONFIG_SRF08 is not set +# CONFIG_VCNL3020 is not set +# CONFIG_VL53L0X_I2C is not set +# end of Proximity and distance sensors + +# +# Resolver to digital converters +# +# CONFIG_AD2S90 is not set +# CONFIG_AD2S1200 is not set +# end of Resolver to digital converters # # Temperature sensors # -# CONFIG_MAXIM_THERMOCOUPLE is not set # CONFIG_LTC2983 is not set +# CONFIG_MAXIM_THERMOCOUPLE is not set # CONFIG_MLX90614 is not set +# CONFIG_MLX90632 is not set # CONFIG_TMP006 is not set # CONFIG_TMP007 is not set # CONFIG_TSYS01 is not set # CONFIG_TSYS02D is not set +# CONFIG_MAX31856 is not set +# end of Temperature sensors + +CONFIG_JESD204=y +# CONFIG_JESD204_TOP_DEVICE is not set # CONFIG_PWM is not set + +# +# IRQ chip support +# CONFIG_IRQCHIP=y CONFIG_ARM_GIC=y CONFIG_ARM_GIC_MAX_NR=1 +# CONFIG_AL_FIC is not set # CONFIG_XILINX_INTC is not set +# end of IRQ chip support + # CONFIG_IPACK_BUS is not set CONFIG_ARCH_HAS_RESET_CONTROLLER=y CONFIG_RESET_CONTROLLER=y -# CONFIG_RESET_ATH79 is not set -# CONFIG_RESET_BERLIN is not set -# CONFIG_RESET_IMX7 is not set -# CONFIG_RESET_LANTIQ is not set -# CONFIG_RESET_LPC18XX is not set -# CONFIG_RESET_MESON is not set -# CONFIG_RESET_PISTACHIO is not set -# CONFIG_RESET_SOCFPGA is not set -# CONFIG_RESET_STM32 is not set -# CONFIG_RESET_SUNXI is not set +# CONFIG_RESET_BRCMSTB_RESCAL is not set +# CONFIG_RESET_INTEL_GW is not set # CONFIG_RESET_TI_SYSCON is not set CONFIG_RESET_ZYNQ=y -# CONFIG_RESET_TEGRA_BPMP is not set -# CONFIG_FMC is not set # # PHY Subsystem # # CONFIG_GENERIC_PHY is not set +# CONFIG_USB_LGM_PHY is not set # CONFIG_BCM_KONA_USB2_PHY is not set +# CONFIG_PHY_CADENCE_TORRENT is not set +# CONFIG_PHY_CADENCE_DPHY is not set +# CONFIG_PHY_CADENCE_SIERRA is not set +# CONFIG_PHY_CADENCE_SALVO is not set +# CONFIG_PHY_FSL_IMX8MQ_USB is not set +# CONFIG_PHY_MIXEL_MIPI_DPHY is not set # CONFIG_PHY_PXA_28NM_HSIC is not set # CONFIG_PHY_PXA_28NM_USB2 is not set # CONFIG_PHY_CPCAP_USB is not set +# CONFIG_PHY_MAPPHONE_MDM6600 is not set +# CONFIG_PHY_OCELOT_SERDES is not set # CONFIG_PHY_QCOM_USB_HS is not set # CONFIG_PHY_QCOM_USB_HSIC is not set # CONFIG_PHY_TUSB1210 is not set +# end of PHY Subsystem + # CONFIG_POWERCAP is not set # CONFIG_MCB is not set # # Performance monitor support # +# CONFIG_ARM_CCI_PMU is not set +# CONFIG_ARM_CCN is not set CONFIG_ARM_PMU=y +# end of Performance monitor support + # CONFIG_RAS is not set # # Android # # CONFIG_ANDROID is not set +# end of Android + # CONFIG_DAX is not set CONFIG_NVMEM=y +CONFIG_NVMEM_SYSFS=y # CONFIG_NVMEM_AXI_SYSID is not set + +# +# HW tracing support +# # CONFIG_STM is not set # CONFIG_INTEL_TH is not set +# end of HW tracing support + CONFIG_FPGA=y # CONFIG_FPGA_MGR_DEBUG_FS is not set -# CONFIG_FPGA_MGR_ICE40_SPI is not set +# CONFIG_ALTERA_PR_IP_CORE is not set # CONFIG_FPGA_MGR_ALTERA_PS_SPI is not set -# CONFIG_FPGA_MGR_XILINX_SPI is not set CONFIG_FPGA_MGR_ZYNQ_FPGA=y +# CONFIG_FPGA_MGR_XILINX_SPI is not set +# CONFIG_FPGA_MGR_ICE40_SPI is not set +# CONFIG_FPGA_MGR_MACHXO2_SPI is not set # CONFIG_FPGA_MGR_ZYNQ_AFI_FPGA is not set # CONFIG_FPGA_BRIDGE is not set -# CONFIG_ALTERA_PR_IP_CORE is not set - -# -# FSI support -# +# CONFIG_FPGA_DFL is not set # CONFIG_FSI is not set # CONFIG_TEE is not set - -# -# Firmware Drivers -# -# CONFIG_FIRMWARE_MEMMAP is not set -# CONFIG_FW_CFG_SYSFS is not set -CONFIG_HAVE_ARM_SMCCC=y -# CONFIG_GOOGLE_FIRMWARE is not set - -# -# Tegra firmware driver -# +# CONFIG_SIOX is not set +# CONFIG_SLIMBUS is not set +# CONFIG_INTERCONNECT is not set +# CONFIG_COUNTER is not set +# CONFIG_MOST is not set +# end of Device Drivers # # File systems # CONFIG_DCACHE_WORD_ACCESS=y +# CONFIG_VALIDATE_FS_PARSER is not set +CONFIG_FS_IOMAP=y # CONFIG_EXT2_FS is not set # CONFIG_EXT3_FS is not set CONFIG_EXT4_FS=y CONFIG_EXT4_USE_FOR_EXT2=y CONFIG_EXT4_FS_POSIX_ACL=y # CONFIG_EXT4_FS_SECURITY is not set -# CONFIG_EXT4_ENCRYPTION is not set # CONFIG_EXT4_DEBUG is not set CONFIG_JBD2=y # CONFIG_JBD2_DEBUG is not set @@ -4215,13 +5281,14 @@ CONFIG_EXPORTFS=y CONFIG_FILE_LOCKING=y CONFIG_MANDATORY_FILE_LOCKING=y # CONFIG_FS_ENCRYPTION is not set +# CONFIG_FS_VERITY is not set CONFIG_FSNOTIFY=y # CONFIG_DNOTIFY is not set CONFIG_INOTIFY_USER=y # CONFIG_FANOTIFY is not set # CONFIG_QUOTA is not set -# CONFIG_QUOTACTL is not set # CONFIG_AUTOFS4_FS is not set +# CONFIG_AUTOFS_FS is not set # CONFIG_FUSE_FS is not set # CONFIG_OVERLAY_FS is not set @@ -4229,15 +5296,17 @@ CONFIG_INOTIFY_USER=y # Caches # # CONFIG_FSCACHE is not set +# end of Caches # # CD-ROM/DVD Filesystems # # CONFIG_ISO9660_FS is not set # CONFIG_UDF_FS is not set +# end of CD-ROM/DVD Filesystems # -# DOS/FAT/NT Filesystems +# DOS/FAT/EXFAT/NT Filesystems # CONFIG_FAT_FS=y CONFIG_MSDOS_FS=y @@ -4245,7 +5314,9 @@ CONFIG_VFAT_FS=y CONFIG_FAT_DEFAULT_CODEPAGE=437 CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" # CONFIG_FAT_DEFAULT_UTF8 is not set +# CONFIG_EXFAT_FS is not set # CONFIG_NTFS_FS is not set +# end of DOS/FAT/EXFAT/NT Filesystems # # Pseudo filesystems @@ -4259,12 +5330,15 @@ CONFIG_SYSFS=y CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y CONFIG_TMPFS_XATTR=y -# CONFIG_HUGETLB_PAGE is not set +CONFIG_MEMFD_CREATE=y CONFIG_CONFIGFS_FS=y +# end of Pseudo filesystems + CONFIG_MISC_FILESYSTEMS=y # CONFIG_ORANGEFS_FS is not set # CONFIG_ADFS_FS is not set # CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set # CONFIG_HFS_FS is not set # CONFIG_HFSPLUS_FS is not set # CONFIG_BEFS_FS is not set @@ -4283,6 +5357,7 @@ CONFIG_MISC_FILESYSTEMS=y # CONFIG_PSTORE is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set +# CONFIG_EROFS_FS is not set # CONFIG_NETWORK_FILESYSTEMS is not set CONFIG_NLS=y CONFIG_NLS_DEFAULT="iso8859-1" @@ -4336,199 +5411,42 @@ CONFIG_NLS_ISO8859_1=y # CONFIG_NLS_MAC_TURKISH is not set # CONFIG_NLS_UTF8 is not set # CONFIG_DLM is not set - -# -# Kernel hacking -# - -# -# printk and dmesg options -# -# CONFIG_PRINTK_TIME is not set -CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 -CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 -# CONFIG_BOOT_PRINTK_DELAY is not set -# CONFIG_DYNAMIC_DEBUG is not set - -# -# Compile-time checks and compiler options -# -CONFIG_DEBUG_INFO=y -# CONFIG_DEBUG_INFO_REDUCED is not set -# CONFIG_DEBUG_INFO_SPLIT is not set -# CONFIG_DEBUG_INFO_DWARF4 is not set -# CONFIG_GDB_SCRIPTS is not set -# CONFIG_ENABLE_WARN_DEPRECATED is not set -# CONFIG_ENABLE_MUST_CHECK is not set -CONFIG_FRAME_WARN=1024 -# CONFIG_STRIP_ASM_SYMS is not set -# CONFIG_READABLE_ASM is not set -# CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_PAGE_OWNER is not set -CONFIG_DEBUG_FS=y -# CONFIG_HEADERS_CHECK is not set -# CONFIG_DEBUG_SECTION_MISMATCH is not set -CONFIG_SECTION_MISMATCH_WARN_ONLY=y -# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set -# CONFIG_MAGIC_SYSRQ is not set -CONFIG_DEBUG_KERNEL=y - -# -# Memory Debugging -# -# CONFIG_PAGE_EXTENSION is not set -# CONFIG_DEBUG_PAGEALLOC is not set -# CONFIG_PAGE_POISONING is not set -# CONFIG_DEBUG_RODATA_TEST is not set -# CONFIG_DEBUG_OBJECTS is not set -# CONFIG_DEBUG_SLAB is not set -CONFIG_HAVE_DEBUG_KMEMLEAK=y -# CONFIG_DEBUG_KMEMLEAK is not set -# CONFIG_DEBUG_STACK_USAGE is not set -# CONFIG_DEBUG_VM is not set -CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y -# CONFIG_DEBUG_VIRTUAL is not set -# CONFIG_DEBUG_MEMORY_INIT is not set -# CONFIG_DEBUG_PER_CPU_MAPS is not set -# CONFIG_DEBUG_HIGHMEM is not set -# CONFIG_DEBUG_SHIRQ is not set - -# -# Debug Lockups and Hangs -# -# CONFIG_SOFTLOCKUP_DETECTOR is not set -CONFIG_DETECT_HUNG_TASK=y -CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=20 -# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set -CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 -# CONFIG_WQ_WATCHDOG is not set -# CONFIG_PANIC_ON_OOPS is not set -CONFIG_PANIC_ON_OOPS_VALUE=0 -CONFIG_PANIC_TIMEOUT=0 -# CONFIG_SCHED_DEBUG is not set -# CONFIG_SCHED_INFO is not set -# CONFIG_SCHEDSTATS is not set -# CONFIG_SCHED_STACK_END_CHECK is not set -# CONFIG_DEBUG_TIMEKEEPING is not set -# CONFIG_DEBUG_PREEMPT is not set - -# -# Lock Debugging (spinlocks, mutexes, etc...) -# -# CONFIG_DEBUG_RT_MUTEXES is not set -# CONFIG_DEBUG_SPINLOCK is not set -# CONFIG_DEBUG_MUTEXES is not set -# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set -# CONFIG_DEBUG_LOCK_ALLOC is not set -# CONFIG_PROVE_LOCKING is not set -# CONFIG_LOCK_STAT is not set -# CONFIG_DEBUG_ATOMIC_SLEEP is not set -# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set -# CONFIG_LOCK_TORTURE_TEST is not set -# CONFIG_WW_MUTEX_SELFTEST is not set -# CONFIG_STACKTRACE is not set -# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set -# CONFIG_DEBUG_KOBJECT is not set -CONFIG_DEBUG_BUGVERBOSE=y -# CONFIG_DEBUG_LIST is not set -# CONFIG_DEBUG_PI_LIST is not set -# CONFIG_DEBUG_SG is not set -# CONFIG_DEBUG_NOTIFIERS is not set -# CONFIG_DEBUG_CREDENTIALS is not set - -# -# RCU Debugging -# -# CONFIG_PROVE_RCU is not set -# CONFIG_TORTURE_TEST is not set -# CONFIG_RCU_PERF_TEST is not set -# CONFIG_RCU_TORTURE_TEST is not set -CONFIG_RCU_CPU_STALL_TIMEOUT=60 -# CONFIG_RCU_TRACE is not set -# CONFIG_RCU_EQS_DEBUG is not set -# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set -# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set -# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set -# CONFIG_NOTIFIER_ERROR_INJECTION is not set -# CONFIG_FAULT_INJECTION is not set -# CONFIG_LATENCYTOP is not set -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y -CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y -CONFIG_HAVE_SYSCALL_TRACEPOINTS=y -CONFIG_HAVE_C_RECORDMCOUNT=y -CONFIG_TRACING_SUPPORT=y -# CONFIG_FTRACE is not set -# CONFIG_DMA_API_DEBUG is not set - -# -# Runtime Testing -# -# CONFIG_LKDTM is not set -# CONFIG_TEST_LIST_SORT is not set -# CONFIG_TEST_SORT is not set -# CONFIG_BACKTRACE_SELF_TEST is not set -# CONFIG_RBTREE_TEST is not set -# CONFIG_INTERVAL_TREE_TEST is not set -# CONFIG_PERCPU_TEST is not set -# CONFIG_ATOMIC64_SELFTEST is not set -# CONFIG_TEST_HEXDUMP is not set -# CONFIG_TEST_STRING_HELPERS is not set -# CONFIG_TEST_KSTRTOX is not set -# CONFIG_TEST_PRINTF is not set -# CONFIG_TEST_BITMAP is not set -# CONFIG_TEST_UUID is not set -# CONFIG_TEST_RHASHTABLE is not set -# CONFIG_TEST_HASH is not set -# CONFIG_TEST_LKM is not set -# CONFIG_TEST_USER_COPY is not set -# CONFIG_TEST_BPF is not set -# CONFIG_TEST_FIRMWARE is not set -# CONFIG_TEST_SYSCTL is not set -# CONFIG_TEST_UDELAY is not set -# CONFIG_TEST_STATIC_KEYS is not set -# CONFIG_TEST_KMOD is not set -# CONFIG_MEMTEST is not set -# CONFIG_BUG_ON_DATA_CORRUPTION is not set -# CONFIG_SAMPLES is not set -CONFIG_HAVE_ARCH_KGDB=y -# CONFIG_KGDB is not set -# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set -# CONFIG_UBSAN is not set -CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y -# CONFIG_STRICT_DEVMEM is not set -# CONFIG_ARM_PTDUMP is not set -CONFIG_ARM_UNWIND=y -# CONFIG_DEBUG_USER is not set -CONFIG_DEBUG_LL=y -# CONFIG_DEBUG_ZYNQ_UART0 is not set -CONFIG_DEBUG_ZYNQ_UART1=y -# CONFIG_DEBUG_ICEDCC is not set -# CONFIG_DEBUG_SEMIHOSTING is not set -# CONFIG_DEBUG_LL_UART_8250 is not set -# CONFIG_DEBUG_LL_UART_PL01X is not set -CONFIG_DEBUG_LL_INCLUDE="debug/zynq.S" -# CONFIG_DEBUG_UART_8250 is not set -CONFIG_DEBUG_UNCOMPRESS=y -CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" -CONFIG_EARLY_PRINTK=y -# CONFIG_PID_IN_CONTEXTIDR is not set -# CONFIG_CORESIGHT is not set +# CONFIG_UNICODE is not set +CONFIG_IO_WQ=y +# end of File systems # # Security options # -# CONFIG_KEYS is not set +CONFIG_KEYS=y +# CONFIG_KEYS_REQUEST_CACHE is not set +# CONFIG_PERSISTENT_KEYRINGS is not set +# CONFIG_ENCRYPTED_KEYS is not set +# CONFIG_KEY_DH_OPERATIONS is not set # CONFIG_SECURITY_DMESG_RESTRICT is not set # CONFIG_SECURITY is not set # CONFIG_SECURITYFS is not set CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y # CONFIG_HARDENED_USERCOPY is not set +# CONFIG_FORTIFY_SOURCE is not set # CONFIG_STATIC_USERMODEHELPER is not set CONFIG_DEFAULT_SECURITY_DAC=y -CONFIG_DEFAULT_SECURITY="" +CONFIG_LSM="lockdown,yama,loadpin,safesetid,integrity,bpf" + +# +# Kernel hardening options +# + +# +# Memory initialization +# +CONFIG_INIT_STACK_NONE=y +# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set +# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set +# end of Memory initialization +# end of Kernel hardening options +# end of Security options + CONFIG_CRYPTO=y # @@ -4538,19 +5456,17 @@ CONFIG_CRYPTO_ALGAPI=y CONFIG_CRYPTO_ALGAPI2=y CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_BLKCIPHER=y -CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_SKCIPHER=y +CONFIG_CRYPTO_SKCIPHER2=y CONFIG_CRYPTO_HASH=y CONFIG_CRYPTO_HASH2=y CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_RNG2=y CONFIG_CRYPTO_RNG_DEFAULT=y CONFIG_CRYPTO_AKCIPHER2=y +CONFIG_CRYPTO_AKCIPHER=y CONFIG_CRYPTO_KPP2=y CONFIG_CRYPTO_ACOMP2=y -# CONFIG_CRYPTO_RSA is not set -# CONFIG_CRYPTO_DH is not set -# CONFIG_CRYPTO_ECDH is not set CONFIG_CRYPTO_MANAGER=y CONFIG_CRYPTO_MANAGER2=y # CONFIG_CRYPTO_USER is not set @@ -4559,18 +5475,27 @@ CONFIG_CRYPTO_GF128MUL=y CONFIG_CRYPTO_NULL=y CONFIG_CRYPTO_NULL2=y # CONFIG_CRYPTO_PCRYPT is not set -CONFIG_CRYPTO_WORKQUEUE=y # CONFIG_CRYPTO_CRYPTD is not set -# CONFIG_CRYPTO_MCRYPTD is not set # CONFIG_CRYPTO_AUTHENC is not set # CONFIG_CRYPTO_TEST is not set +# +# Public-key cryptography +# +CONFIG_CRYPTO_RSA=y +# CONFIG_CRYPTO_DH is not set +# CONFIG_CRYPTO_ECDH is not set +# CONFIG_CRYPTO_ECRDSA is not set +# CONFIG_CRYPTO_SM2 is not set +# CONFIG_CRYPTO_CURVE25519 is not set + # # Authenticated Encryption with Associated Data # CONFIG_CRYPTO_CCM=m CONFIG_CRYPTO_GCM=y # CONFIG_CRYPTO_CHACHA20POLY1305 is not set +# CONFIG_CRYPTO_AEGIS128 is not set CONFIG_CRYPTO_SEQIV=y CONFIG_CRYPTO_ECHAINIV=m @@ -4578,13 +5503,17 @@ CONFIG_CRYPTO_ECHAINIV=m # Block modes # # CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CFB is not set CONFIG_CRYPTO_CTR=y # CONFIG_CRYPTO_CTS is not set # CONFIG_CRYPTO_ECB is not set # CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_OFB is not set # CONFIG_CRYPTO_PCBC is not set # CONFIG_CRYPTO_XTS is not set # CONFIG_CRYPTO_KEYWRAP is not set +# CONFIG_CRYPTO_ADIANTUM is not set +# CONFIG_CRYPTO_ESSIV is not set # # Hash modes @@ -4599,6 +5528,9 @@ CONFIG_CRYPTO_HMAC=y # CONFIG_CRYPTO_CRC32C=y # CONFIG_CRYPTO_CRC32 is not set +# CONFIG_CRYPTO_XXHASH is not set +# CONFIG_CRYPTO_BLAKE2B is not set +# CONFIG_CRYPTO_BLAKE2S is not set # CONFIG_CRYPTO_CRCT10DIF is not set CONFIG_CRYPTO_GHASH=y # CONFIG_CRYPTO_POLY1305 is not set @@ -4613,6 +5545,8 @@ CONFIG_CRYPTO_GHASH=y CONFIG_CRYPTO_SHA256=y # CONFIG_CRYPTO_SHA512 is not set # CONFIG_CRYPTO_SHA3 is not set +# CONFIG_CRYPTO_SM3 is not set +# CONFIG_CRYPTO_STREEBOG is not set # CONFIG_CRYPTO_TGR192 is not set # CONFIG_CRYPTO_WP512 is not set @@ -4621,20 +5555,16 @@ CONFIG_CRYPTO_SHA256=y # CONFIG_CRYPTO_AES=y # CONFIG_CRYPTO_AES_TI is not set -# CONFIG_CRYPTO_ANUBIS is not set -CONFIG_CRYPTO_ARC4=m # CONFIG_CRYPTO_BLOWFISH is not set # CONFIG_CRYPTO_CAMELLIA is not set # CONFIG_CRYPTO_CAST5 is not set # CONFIG_CRYPTO_CAST6 is not set # CONFIG_CRYPTO_DES is not set # CONFIG_CRYPTO_FCRYPT is not set -# CONFIG_CRYPTO_KHAZAD is not set # CONFIG_CRYPTO_SALSA20 is not set # CONFIG_CRYPTO_CHACHA20 is not set -# CONFIG_CRYPTO_SEED is not set # CONFIG_CRYPTO_SERPENT is not set -# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_SM4 is not set # CONFIG_CRYPTO_TWOFISH is not set # @@ -4645,6 +5575,7 @@ CONFIG_CRYPTO_ARC4=m # CONFIG_CRYPTO_842 is not set # CONFIG_CRYPTO_LZ4 is not set # CONFIG_CRYPTO_LZ4HC is not set +# CONFIG_CRYPTO_ZSTD is not set # # Random Number Generation @@ -4660,26 +5591,58 @@ CONFIG_CRYPTO_JITTERENTROPY=y # CONFIG_CRYPTO_USER_API_SKCIPHER is not set # CONFIG_CRYPTO_USER_API_RNG is not set # CONFIG_CRYPTO_USER_API_AEAD is not set +CONFIG_CRYPTO_HASH_INFO=y + +# +# Crypto library routines +# +CONFIG_CRYPTO_LIB_AES=y +CONFIG_CRYPTO_LIB_ARC4=m +# CONFIG_CRYPTO_LIB_BLAKE2S is not set +# CONFIG_CRYPTO_LIB_CHACHA is not set +# CONFIG_CRYPTO_LIB_CURVE25519 is not set +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9 +# CONFIG_CRYPTO_LIB_POLY1305 is not set +# CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set +CONFIG_CRYPTO_LIB_SHA256=y CONFIG_CRYPTO_HW=y -# CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC is not set +# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set +# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set +# CONFIG_CRYPTO_DEV_SAFEXCEL is not set +# CONFIG_CRYPTO_DEV_CCREE is not set +# CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set +CONFIG_ASYMMETRIC_KEY_TYPE=y +CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y +CONFIG_X509_CERTIFICATE_PARSER=y +# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set +CONFIG_PKCS7_MESSAGE_PARSER=y +# CONFIG_PKCS7_TEST_KEY is not set +# CONFIG_SIGNED_PE_FILE_VERIFICATION is not set # # Certificates for signature checking # -# CONFIG_ARM_CRYPTO is not set -# CONFIG_BINARY_PRINTF is not set +CONFIG_SYSTEM_TRUSTED_KEYRING=y +CONFIG_SYSTEM_TRUSTED_KEYS="" +# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set +# CONFIG_SECONDARY_TRUSTED_KEYRING is not set +# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set +# end of Certificates for signature checking # # Library routines # +CONFIG_LINEAR_RANGES=y +# CONFIG_PACKING is not set CONFIG_BITREVERSE=y CONFIG_HAVE_ARCH_BITREVERSE=y -CONFIG_RATIONAL=y CONFIG_GENERIC_STRNCPY_FROM_USER=y CONFIG_GENERIC_STRNLEN_USER=y CONFIG_GENERIC_NET_UTILS=y +# CONFIG_CORDIC is not set +# CONFIG_PRIME_NUMBERS is not set +CONFIG_RATIONAL=y CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_IO=y CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y # CONFIG_CRC_CCITT is not set CONFIG_CRC16=y @@ -4691,35 +5654,58 @@ CONFIG_CRC32_SLICEBY8=y # CONFIG_CRC32_SLICEBY4 is not set # CONFIG_CRC32_SARWATE is not set # CONFIG_CRC32_BIT is not set +# CONFIG_CRC64 is not set # CONFIG_CRC4 is not set # CONFIG_CRC7 is not set CONFIG_LIBCRC32C=y -# CONFIG_CRC8 is not set -# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set +CONFIG_CRC8=y +CONFIG_XXHASH=y # CONFIG_RANDOM32_SELFTEST is not set CONFIG_ZLIB_INFLATE=y +CONFIG_ZSTD_DECOMPRESS=y # CONFIG_XZ_DEC is not set -# CONFIG_XZ_DEC_BCJ is not set CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_ZSTD=y CONFIG_GENERIC_ALLOCATOR=y CONFIG_TEXTSEARCH=y CONFIG_TEXTSEARCH_KMP=y CONFIG_TEXTSEARCH_BM=y CONFIG_TEXTSEARCH_FSM=y +CONFIG_ASSOCIATIVE_ARRAY=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT_MAP=y CONFIG_HAS_DMA=y -# CONFIG_DMA_NOOP_OPS is not set -# CONFIG_DMA_VIRT_OPS is not set +CONFIG_DMA_OPS=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_DMA_DECLARE_COHERENT=y +CONFIG_ARCH_HAS_SETUP_DMA_OPS=y +CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y +CONFIG_DMA_NONCOHERENT_MMAP=y +CONFIG_DMA_REMAP=y +CONFIG_DMA_CMA=y +# CONFIG_DMA_PERNUMA_CMA is not set + +# +# Default contiguous memory area size: +# +CONFIG_CMA_SIZE_MBYTES=128 +CONFIG_CMA_SIZE_SEL_MBYTES=y +# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set +# CONFIG_CMA_SIZE_SEL_MIN is not set +# CONFIG_CMA_SIZE_SEL_MAX is not set +CONFIG_CMA_ALIGNMENT=8 +# CONFIG_DMA_API_DEBUG is not set +CONFIG_SGL_ALLOC=y CONFIG_CPU_RMAP=y CONFIG_DQL=y CONFIG_GLOB=y # CONFIG_GLOB_SELFTEST is not set CONFIG_NLATTR=y -# CONFIG_CORDIC is not set -# CONFIG_DDR is not set +CONFIG_CLZ_TAB=y # CONFIG_IRQ_POLL is not set +CONFIG_MPILIB=y CONFIG_LIBFDT=y +CONFIG_OID_REGISTRY=y CONFIG_FONT_SUPPORT=y CONFIG_FONTS=y CONFIG_FONT_8x8=y @@ -4733,9 +5719,256 @@ CONFIG_FONT_8x16=y # CONFIG_FONT_10x18 is not set # CONFIG_FONT_SUN8x16 is not set # CONFIG_FONT_SUN12x22 is not set -# CONFIG_SG_SPLIT is not set +# CONFIG_FONT_TER16x32 is not set +# CONFIG_FONT_6x8 is not set CONFIG_SG_POOL=y -CONFIG_ARCH_HAS_SG_CHAIN=y CONFIG_SBITMAP=y # CONFIG_STRING_SELFTEST is not set -# CONFIG_VIRTUALIZATION is not set +# end of Library routines + +# +# Kernel hacking +# + +# +# printk and dmesg options +# +# CONFIG_PRINTK_TIME is not set +# CONFIG_PRINTK_CALLER is not set +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 +CONFIG_CONSOLE_LOGLEVEL_QUIET=4 +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_DYNAMIC_DEBUG_CORE is not set +CONFIG_SYMBOLIC_ERRNAME=y +CONFIG_DEBUG_BUGVERBOSE=y +# end of printk and dmesg options + +# +# Compile-time checks and compiler options +# +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_INFO_REDUCED is not set +# CONFIG_DEBUG_INFO_COMPRESSED is not set +# CONFIG_DEBUG_INFO_SPLIT is not set +# CONFIG_DEBUG_INFO_DWARF4 is not set +# CONFIG_DEBUG_INFO_BTF is not set +# CONFIG_GDB_SCRIPTS is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=1024 +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_READABLE_ASM is not set +# CONFIG_HEADERS_INSTALL is not set +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_SECTION_MISMATCH_WARN_ONLY=y +# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_32B is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# end of Compile-time checks and compiler options + +# +# Generic Kernel Debugging Instruments +# +# CONFIG_MAGIC_SYSRQ is not set +CONFIG_DEBUG_FS=y +CONFIG_DEBUG_FS_ALLOW_ALL=y +# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set +# CONFIG_DEBUG_FS_ALLOW_NONE is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_UBSAN is not set +# end of Generic Kernel Debugging Instruments + +CONFIG_DEBUG_KERNEL=y +CONFIG_DEBUG_MISC=y + +# +# Memory Debugging +# +# CONFIG_PAGE_EXTENSION is not set +# CONFIG_DEBUG_PAGEALLOC is not set +# CONFIG_PAGE_OWNER is not set +# CONFIG_PAGE_POISONING is not set +# CONFIG_DEBUG_RODATA_TEST is not set +# CONFIG_DEBUG_WX is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_SLAB is not set +CONFIG_HAVE_DEBUG_KMEMLEAK=y +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_SCHED_STACK_END_CHECK is not set +# CONFIG_DEBUG_VM is not set +CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y +# CONFIG_DEBUG_VIRTUAL is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_PER_CPU_MAPS is not set +# CONFIG_DEBUG_HIGHMEM is not set +CONFIG_CC_HAS_KASAN_GENERIC=y +CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y +# end of Memory Debugging + +# CONFIG_DEBUG_SHIRQ is not set + +# +# Debug Oops, Lockups and Hangs +# +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=0 +# CONFIG_SOFTLOCKUP_DETECTOR is not set +CONFIG_DETECT_HUNG_TASK=y +CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=20 +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +# CONFIG_WQ_WATCHDOG is not set +# CONFIG_TEST_LOCKUP is not set +# end of Debug Oops, Lockups and Hangs + +# +# Scheduler Debugging +# +# CONFIG_SCHED_DEBUG is not set +# CONFIG_SCHEDSTATS is not set +# end of Scheduler Debugging + +# CONFIG_DEBUG_TIMEKEEPING is not set +# CONFIG_DEBUG_PREEMPT is not set + +# +# Lock Debugging (spinlocks, mutexes, etc...) +# +CONFIG_LOCK_DEBUGGING_SUPPORT=y +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set +# CONFIG_DEBUG_RWSEMS is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_DEBUG_ATOMIC_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_LOCK_TORTURE_TEST is not set +# CONFIG_WW_MUTEX_SELFTEST is not set +# CONFIG_SCF_TORTURE_TEST is not set +# end of Lock Debugging (spinlocks, mutexes, etc...) + +# CONFIG_STACKTRACE is not set +# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set +# CONFIG_DEBUG_KOBJECT is not set + +# +# Debug kernel data structures +# +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_PLIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_BUG_ON_DATA_CORRUPTION is not set +# end of Debug kernel data structures + +# CONFIG_DEBUG_CREDENTIALS is not set + +# +# RCU Debugging +# +# CONFIG_RCU_SCALE_TEST is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_REF_SCALE_TEST is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +# CONFIG_RCU_TRACE is not set +# CONFIG_RCU_EQS_DEBUG is not set +# end of RCU Debugging + +# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set +# CONFIG_LATENCYTOP is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_SAMPLES is not set +CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y +# CONFIG_STRICT_DEVMEM is not set + +# +# arm Debugging +# +# CONFIG_ARM_PTDUMP_DEBUGFS is not set +# CONFIG_UNWINDER_FRAME_POINTER is not set +CONFIG_UNWINDER_ARM=y +CONFIG_ARM_UNWIND=y +# CONFIG_DEBUG_USER is not set +CONFIG_DEBUG_LL=y +# CONFIG_DEBUG_ZYNQ_UART0 is not set +CONFIG_DEBUG_ZYNQ_UART1=y +# CONFIG_DEBUG_ICEDCC is not set +# CONFIG_DEBUG_SEMIHOSTING is not set +# CONFIG_DEBUG_LL_UART_8250 is not set +# CONFIG_DEBUG_LL_UART_PL01X is not set +# CONFIG_DEBUG_UART_FLOW_CONTROL is not set +CONFIG_DEBUG_LL_INCLUDE="debug/zynq.S" +CONFIG_DEBUG_UNCOMPRESS=y +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +CONFIG_EARLY_PRINTK=y +# CONFIG_PID_IN_CONTEXTIDR is not set +# CONFIG_CORESIGHT is not set +# end of arm Debugging + +# +# Kernel Testing and Coverage +# +# CONFIG_KUNIT is not set +# CONFIG_NOTIFIER_ERROR_INJECTION is not set +# CONFIG_FAULT_INJECTION is not set +CONFIG_ARCH_HAS_KCOV=y +CONFIG_CC_HAS_SANCOV_TRACE_PC=y +# CONFIG_KCOV is not set +CONFIG_RUNTIME_TESTING_MENU=y +# CONFIG_LKDTM is not set +# CONFIG_TEST_LIST_SORT is not set +# CONFIG_TEST_MIN_HEAP is not set +# CONFIG_TEST_SORT is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_RBTREE_TEST is not set +# CONFIG_REED_SOLOMON_TEST is not set +# CONFIG_INTERVAL_TREE_TEST is not set +# CONFIG_PERCPU_TEST is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_TEST_HEXDUMP is not set +# CONFIG_TEST_STRING_HELPERS is not set +# CONFIG_TEST_STRSCPY is not set +# CONFIG_TEST_KSTRTOX is not set +# CONFIG_TEST_PRINTF is not set +# CONFIG_TEST_BITMAP is not set +# CONFIG_TEST_UUID is not set +# CONFIG_TEST_XARRAY is not set +# CONFIG_TEST_OVERFLOW is not set +# CONFIG_TEST_RHASHTABLE is not set +# CONFIG_TEST_HASH is not set +# CONFIG_TEST_IDA is not set +# CONFIG_TEST_LKM is not set +# CONFIG_TEST_BITOPS is not set +# CONFIG_TEST_VMALLOC is not set +# CONFIG_TEST_USER_COPY is not set +# CONFIG_TEST_BPF is not set +# CONFIG_TEST_BLACKHOLE_DEV is not set +# CONFIG_FIND_BIT_BENCHMARK is not set +# CONFIG_TEST_FIRMWARE is not set +# CONFIG_TEST_SYSCTL is not set +# CONFIG_TEST_UDELAY is not set +# CONFIG_TEST_STATIC_KEYS is not set +# CONFIG_TEST_KMOD is not set +# CONFIG_TEST_MEMCAT_P is not set +# CONFIG_TEST_STACKINIT is not set +# CONFIG_TEST_MEMINIT is not set +# CONFIG_TEST_FREE_PAGES is not set +# CONFIG_MEMTEST is not set +# end of Kernel Testing and Coverage +# end of Kernel hacking diff --git a/kernel_boot/kernel_config_zynqmp b/kernel_boot/kernel_config_zynqmp index 389fecc..6668ba4 100644 --- a/kernel_boot/kernel_config_zynqmp +++ b/kernel_boot/kernel_config_zynqmp @@ -1,67 +1,50 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 4.14.0 Kernel Configuration +# Linux/arm64 5.10.0 Kernel Configuration # -CONFIG_ARM64=y -CONFIG_64BIT=y -CONFIG_ARCH_PHYS_ADDR_T_64BIT=y -CONFIG_MMU=y -CONFIG_ARM64_PAGE_SHIFT=12 -CONFIG_ARM64_CONT_SHIFT=4 -CONFIG_ARCH_MMAP_RND_BITS_MIN=18 -CONFIG_ARCH_MMAP_RND_BITS_MAX=24 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16 -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -CONFIG_RWSEM_XCHGADD_ALGORITHM=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CSUM=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_ZONE_DMA=y -CONFIG_HAVE_GENERIC_GUP=y -CONFIG_ARCH_DMA_ADDR_T_64BIT=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_SG_DMA_LENGTH=y -CONFIG_SMP=y -CONFIG_SWIOTLB=y -CONFIG_IOMMU_HELPER=y -CONFIG_KERNEL_MODE_NEON=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_PGTABLE_LEVELS=3 -CONFIG_ARCH_SUPPORTS_UPROBES=y -CONFIG_ARCH_PROC_KCORE_TEXT=y -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_KERNEL_ALL_ADI_DRIVERS=y +CONFIG_CLK_ALL_ADI_DRIVERS=y +CONFIG_HWMON_ALL_ADI_DRIVERS=y +CONFIG_IIO_ALL_ADI_DRIVERS=y +CONFIG_INPUT_ALL_ADI_DRIVERS=y +CONFIG_MEDIA_ALL_ADI_DRIVERS=y +CONFIG_USB_ALL_ADI_DRIVERS=y +CONFIG_SND_SOC_ALL_ADI_CODECS=y +CONFIG_CC_VERSION_TEXT="aarch64-xilinx-linux-gcc.real (GCC) 10.2.0" +CONFIG_CC_IS_GCC=y +CONFIG_GCC_VERSION=100200 +CONFIG_LD_VERSION=235000000 +CONFIG_CLANG_VERSION=0 +CONFIG_LLD_VERSION=0 +CONFIG_CC_CAN_LINK=y +CONFIG_CC_CAN_LINK_STATIC=y +CONFIG_CC_HAS_ASM_GOTO=y +CONFIG_CC_HAS_ASM_INLINE=y CONFIG_IRQ_WORK=y -CONFIG_BUILDTIME_EXTABLE_SORT=y +CONFIG_BUILDTIME_TABLE_SORT=y CONFIG_THREAD_INFO_IN_TASK=y # # General setup # CONFIG_INIT_ENV_ARG_LIMIT=32 -CONFIG_CROSS_COMPILE="" # CONFIG_COMPILE_TEST is not set CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y +CONFIG_BUILD_SALT="" +CONFIG_DEFAULT_INIT="" CONFIG_DEFAULT_HOSTNAME="(none)" CONFIG_SWAP=y CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y CONFIG_POSIX_MQUEUE=y CONFIG_POSIX_MQUEUE_SYSCTL=y +# CONFIG_WATCH_QUEUE is not set CONFIG_CROSS_MEMORY_ATTACH=y -CONFIG_FHANDLE=y # CONFIG_USELIB is not set CONFIG_AUDIT=y CONFIG_HAVE_ARCH_AUDITSYSCALL=y CONFIG_AUDITSYSCALL=y -CONFIG_AUDIT_WATCH=y -CONFIG_AUDIT_TREE=y # # IRQ subsystem @@ -74,14 +57,17 @@ CONFIG_GENERIC_IRQ_MIGRATION=y CONFIG_HARDIRQS_SW_RESEND=y CONFIG_IRQ_DOMAIN=y CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_GENERIC_IRQ_IPI=y CONFIG_GENERIC_MSI_IRQ=y CONFIG_GENERIC_MSI_IRQ_DOMAIN=y +CONFIG_IRQ_MSI_IOMMU=y CONFIG_HANDLE_DOMAIN_IRQ=y -# CONFIG_IRQ_DOMAIN_DEBUG is not set CONFIG_IRQ_FORCED_THREADING=y CONFIG_SPARSE_IRQ=y # CONFIG_GENERIC_IRQ_DEBUGFS is not set -CONFIG_ARCH_CLOCKSOURCE_DATA=y +# end of IRQ subsystem + +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_ARCH_HAS_TICK_BROADCAST=y @@ -97,6 +83,11 @@ CONFIG_NO_HZ_IDLE=y # CONFIG_NO_HZ_FULL is not set CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y +# end of Timers subsystem + +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set # # CPU/Task time and stats accounting @@ -110,6 +101,10 @@ CONFIG_TASKSTATS=y CONFIG_TASK_DELAY_ACCT=y CONFIG_TASK_XACCT=y CONFIG_TASK_IO_ACCOUNTING=y +# CONFIG_PSI is not set +# end of CPU/Task time and stats accounting + +CONFIG_CPU_ISOLATION=y # # RCU Subsystem @@ -118,17 +113,26 @@ CONFIG_TREE_RCU=y # CONFIG_RCU_EXPERT is not set CONFIG_SRCU=y CONFIG_TREE_SRCU=y -# CONFIG_TASKS_RCU is not set CONFIG_RCU_STALL_COMMON=y CONFIG_RCU_NEED_SEGCBLIST=y -CONFIG_BUILD_BIN2C=y +# end of RCU Subsystem + CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y +# CONFIG_IKHEADERS is not set CONFIG_LOG_BUF_SHIFT=16 CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 CONFIG_GENERIC_SCHED_CLOCK=y + +# +# Scheduler features +# +# end of Scheduler features + CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y +CONFIG_CC_HAS_INT128=y +CONFIG_ARCH_SUPPORTS_INT128=y CONFIG_CGROUPS=y # CONFIG_MEMCG is not set # CONFIG_BLK_CGROUP is not set @@ -142,9 +146,14 @@ CONFIG_CGROUPS=y # CONFIG_CGROUP_CPUACCT is not set # CONFIG_CGROUP_PERF is not set # CONFIG_CGROUP_DEBUG is not set -# CONFIG_SOCK_CGROUP_DATA is not set +CONFIG_NAMESPACES=y +CONFIG_UTS_NS=y +CONFIG_TIME_NS=y +CONFIG_IPC_NS=y +CONFIG_USER_NS=y +CONFIG_PID_NS=y +CONFIG_NET_NS=y # CONFIG_CHECKPOINT_RESTORE is not set -# CONFIG_NAMESPACES is not set # CONFIG_SCHED_AUTOGROUP is not set # CONFIG_SYSFS_DEPRECATED is not set # CONFIG_RELAY is not set @@ -156,10 +165,12 @@ CONFIG_RD_LZMA=y CONFIG_RD_XZ=y CONFIG_RD_LZO=y CONFIG_RD_LZ4=y +CONFIG_RD_ZSTD=y +# CONFIG_BOOT_CONFIG is not set CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_LD_ORPHAN_WARN=y CONFIG_SYSCTL=y -CONFIG_ANON_INODES=y CONFIG_HAVE_UID16=y CONFIG_SYSCTL_EXCEPTION_TRACE=y CONFIG_BPF=y @@ -168,29 +179,35 @@ CONFIG_UID16=y CONFIG_MULTIUSER=y # CONFIG_SGETMASK_SYSCALL is not set CONFIG_SYSFS_SYSCALL=y -# CONFIG_SYSCTL_SYSCALL is not set +CONFIG_FHANDLE=y CONFIG_POSIX_TIMERS=y -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_ALL is not set -# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set -CONFIG_KALLSYMS_BASE_RELATIVE=y CONFIG_PRINTK=y +CONFIG_PRINTK_NMI=y CONFIG_BUG=y CONFIG_ELF_CORE=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_FUTEX_PI=y +CONFIG_HAVE_FUTEX_CMPXCHG=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y -# CONFIG_BPF_SYSCALL is not set CONFIG_SHMEM=y CONFIG_AIO=y +CONFIG_IO_URING=y CONFIG_ADVISE_SYSCALLS=y -# CONFIG_USERFAULTFD is not set -CONFIG_PCI_QUIRKS=y CONFIG_MEMBARRIER=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +CONFIG_KALLSYMS_BASE_RELATIVE=y +# CONFIG_BPF_SYSCALL is not set +CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y +CONFIG_USERMODE_DRIVER=y +# CONFIG_USERFAULTFD is not set +CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y +CONFIG_RSEQ=y +# CONFIG_DEBUG_RSEQ is not set CONFIG_EMBEDDED=y CONFIG_HAVE_PERF_EVENTS=y # CONFIG_PC104 is not set @@ -200,6 +217,8 @@ CONFIG_HAVE_PERF_EVENTS=y # CONFIG_PERF_EVENTS=y # CONFIG_DEBUG_PERF_USE_VMALLOC is not set +# end of Kernel Performance Events And Counters + CONFIG_VM_EVENT_COUNTERS=y # CONFIG_COMPAT_BRK is not set CONFIG_SLAB=y @@ -207,210 +226,84 @@ CONFIG_SLAB=y # CONFIG_SLOB is not set CONFIG_SLAB_MERGE_DEFAULT=y # CONFIG_SLAB_FREELIST_RANDOM is not set -# CONFIG_SYSTEM_DATA_VERIFICATION is not set +# CONFIG_SLAB_FREELIST_HARDENED is not set +# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set +CONFIG_SYSTEM_DATA_VERIFICATION=y CONFIG_PROFILING=y -# CONFIG_KPROBES is not set -# CONFIG_JUMP_LABEL is not set -# CONFIG_UPROBES is not set -# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set -CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y -CONFIG_HAVE_KPROBES=y -CONFIG_HAVE_KRETPROBES=y -CONFIG_HAVE_ARCH_TRACEHOOK=y -CONFIG_HAVE_DMA_CONTIGUOUS=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_ARCH_HAS_FORTIFY_SOURCE=y -CONFIG_ARCH_HAS_SET_MEMORY=y -CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y -CONFIG_HAVE_CLK=y -CONFIG_HAVE_DMA_API_DEBUG=y -CONFIG_HAVE_HW_BREAKPOINT=y -CONFIG_HAVE_PERF_REGS=y -CONFIG_HAVE_PERF_USER_STACK_DUMP=y -CONFIG_HAVE_ARCH_JUMP_LABEL=y -CONFIG_HAVE_RCU_TABLE_FREE=y -CONFIG_HAVE_CMPXCHG_LOCAL=y -CONFIG_HAVE_CMPXCHG_DOUBLE=y -CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y -CONFIG_HAVE_ARCH_SECCOMP_FILTER=y -CONFIG_HAVE_GCC_PLUGINS=y -# CONFIG_GCC_PLUGINS is not set -CONFIG_HAVE_CC_STACKPROTECTOR=y -# CONFIG_CC_STACKPROTECTOR is not set -CONFIG_CC_STACKPROTECTOR_NONE=y -# CONFIG_CC_STACKPROTECTOR_REGULAR is not set -# CONFIG_CC_STACKPROTECTOR_STRONG is not set -CONFIG_THIN_ARCHIVES=y -CONFIG_HAVE_CONTEXT_TRACKING=y -CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y -CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y -CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y -CONFIG_HAVE_ARCH_HUGE_VMAP=y -CONFIG_MODULES_USE_ELF_RELA=y -CONFIG_ARCH_HAS_ELF_RANDOMIZE=y -CONFIG_HAVE_ARCH_MMAP_RND_BITS=y -CONFIG_ARCH_MMAP_RND_BITS=18 -CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y -CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11 -# CONFIG_HAVE_ARCH_HASH is not set -# CONFIG_ISA_BUS_API is not set -CONFIG_CLONE_BACKWARDS=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_COMPAT_OLD_SIGACTION=y -# CONFIG_CPU_NO_EFFICIENT_FFS is not set -CONFIG_HAVE_ARCH_VMAP_STACK=y -CONFIG_VMAP_STACK=y -# CONFIG_ARCH_OPTIONAL_KERNEL_RWX is not set -# CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT is not set -CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y -CONFIG_STRICT_KERNEL_RWX=y -CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y -CONFIG_STRICT_MODULE_RWX=y -# CONFIG_REFCOUNT_FULL is not set +# end of General setup -# -# GCOV-based kernel profiling -# -# CONFIG_GCOV_KERNEL is not set -CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y -CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_SLABINFO=y -CONFIG_RT_MUTEXES=y -CONFIG_BASE_SMALL=0 -CONFIG_MODULES=y -# CONFIG_MODULE_FORCE_LOAD is not set -CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set -# CONFIG_MODVERSIONS is not set -# CONFIG_MODULE_SRCVERSION_ALL is not set -# CONFIG_MODULE_SIG is not set -# CONFIG_MODULE_COMPRESS is not set -# CONFIG_TRIM_UNUSED_KSYMS is not set -CONFIG_MODULES_TREE_LOOKUP=y -CONFIG_BLOCK=y -CONFIG_BLK_SCSI_REQUEST=y -CONFIG_BLK_DEV_BSG=y -# CONFIG_BLK_DEV_BSGLIB is not set -# CONFIG_BLK_DEV_INTEGRITY is not set -# CONFIG_BLK_DEV_ZONED is not set -# CONFIG_BLK_CMDLINE_PARSER is not set -# CONFIG_BLK_WBT is not set -CONFIG_BLK_DEBUG_FS=y -# CONFIG_BLK_SED_OPAL is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y -CONFIG_EFI_PARTITION=y -CONFIG_BLOCK_COMPAT=y -CONFIG_BLK_MQ_PCI=y - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -# CONFIG_DEFAULT_DEADLINE is not set -CONFIG_DEFAULT_CFQ=y -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="cfq" -CONFIG_MQ_IOSCHED_DEADLINE=y -CONFIG_MQ_IOSCHED_KYBER=y -# CONFIG_IOSCHED_BFQ is not set -CONFIG_INLINE_SPIN_UNLOCK_IRQ=y -CONFIG_INLINE_READ_UNLOCK=y -CONFIG_INLINE_READ_UNLOCK_IRQ=y -CONFIG_INLINE_WRITE_UNLOCK=y -CONFIG_INLINE_WRITE_UNLOCK_IRQ=y -CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_FREEZER=y +CONFIG_ARM64=y +CONFIG_64BIT=y +CONFIG_MMU=y +CONFIG_ARM64_PAGE_SHIFT=12 +CONFIG_ARM64_CONT_PTE_SHIFT=4 +CONFIG_ARM64_CONT_PMD_SHIFT=4 +CONFIG_ARCH_MMAP_RND_BITS_MIN=18 +CONFIG_ARCH_MMAP_RND_BITS_MAX=24 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16 +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CSUM=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_ZONE_DMA32=y +CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y +CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y +CONFIG_SMP=y +CONFIG_KERNEL_MODE_NEON=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_PGTABLE_LEVELS=3 +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARCH_PROC_KCORE_TEXT=y # # Platform selection # # CONFIG_ARCH_ACTIONS is not set +# CONFIG_ARCH_AGILEX is not set # CONFIG_ARCH_SUNXI is not set # CONFIG_ARCH_ALPINE is not set # CONFIG_ARCH_BCM2835 is not set # CONFIG_ARCH_BCM_IPROC is not set # CONFIG_ARCH_BERLIN is not set +# CONFIG_ARCH_BITMAIN is not set # CONFIG_ARCH_BRCMSTB is not set # CONFIG_ARCH_EXYNOS is not set +# CONFIG_ARCH_SPARX5 is not set +# CONFIG_ARCH_K3 is not set # CONFIG_ARCH_LAYERSCAPE is not set # CONFIG_ARCH_LG1K is not set # CONFIG_ARCH_HISI is not set +# CONFIG_ARCH_KEEMBAY is not set # CONFIG_ARCH_MEDIATEK is not set # CONFIG_ARCH_MESON is not set # CONFIG_ARCH_MVEBU is not set +# CONFIG_ARCH_MXC is not set # CONFIG_ARCH_QCOM is not set # CONFIG_ARCH_REALTEK is not set -# CONFIG_ARCH_ROCKCHIP is not set -# CONFIG_ARCH_SEATTLE is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_ROCKCHIP is not set +# CONFIG_ARCH_S32 is not set +# CONFIG_ARCH_SEATTLE is not set # CONFIG_ARCH_STRATIX10 is not set +# CONFIG_ARCH_SYNQUACER is not set # CONFIG_ARCH_TEGRA is not set # CONFIG_ARCH_SPRD is not set # CONFIG_ARCH_THUNDER is not set # CONFIG_ARCH_THUNDER2 is not set # CONFIG_ARCH_UNIPHIER is not set # CONFIG_ARCH_VEXPRESS is not set -# CONFIG_ARCH_VULCAN is not set +# CONFIG_ARCH_VISCONTI is not set # CONFIG_ARCH_XGENE is not set # CONFIG_ARCH_ZX is not set CONFIG_ARCH_ZYNQMP=y - -# -# Bus support -# -CONFIG_PCI=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_SYSCALL=y -# CONFIG_PCIEPORTBUS is not set -CONFIG_PCI_BUS_ADDR_T_64BIT=y -CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y -# CONFIG_PCI_DEBUG is not set -# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set -# CONFIG_PCI_STUB is not set -# CONFIG_PCI_IOV is not set -# CONFIG_PCI_PRI is not set -# CONFIG_PCI_PASID is not set -# CONFIG_HOTPLUG_PCI is not set - -# -# DesignWare PCI Core Support -# -# CONFIG_PCIE_DW_PLAT is not set -# CONFIG_PCI_HISI is not set -# CONFIG_PCIE_KIRIN is not set - -# -# PCI host controller drivers -# -CONFIG_PCIE_XILINX_NWL=y -# CONFIG_PCI_HOST_GENERIC is not set -# CONFIG_PCIE_XDMA_PL is not set -# CONFIG_PCI_XGENE is not set -# CONFIG_PCI_HOST_THUNDER_PEM is not set -# CONFIG_PCI_HOST_THUNDER_ECAM is not set - -# -# PCI Endpoint -# -# CONFIG_PCI_ENDPOINT is not set - -# -# PCI switch controller drivers -# -# CONFIG_PCI_SW_SWITCHTEC is not set +# end of Platform selection # # Kernel Features @@ -419,6 +312,7 @@ CONFIG_PCIE_XILINX_NWL=y # # ARM errata workarounds via the alternatives framework # +CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y CONFIG_ARM64_ERRATUM_826319=y CONFIG_ARM64_ERRATUM_827319=y CONFIG_ARM64_ERRATUM_824069=y @@ -426,28 +320,47 @@ CONFIG_ARM64_ERRATUM_819472=y CONFIG_ARM64_ERRATUM_832075=y CONFIG_ARM64_ERRATUM_845719=y CONFIG_ARM64_ERRATUM_843419=y +CONFIG_ARM64_ERRATUM_1024718=y +CONFIG_ARM64_ERRATUM_1418040=y +CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y +CONFIG_ARM64_ERRATUM_1165522=y +CONFIG_ARM64_ERRATUM_1319367=y +CONFIG_ARM64_ERRATUM_1530923=y +CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y +CONFIG_ARM64_ERRATUM_1286807=y +CONFIG_ARM64_ERRATUM_1463225=y +CONFIG_ARM64_ERRATUM_1542419=y +CONFIG_ARM64_ERRATUM_1508412=y CONFIG_CAVIUM_ERRATUM_22375=y CONFIG_CAVIUM_ERRATUM_23154=y CONFIG_CAVIUM_ERRATUM_27456=y CONFIG_CAVIUM_ERRATUM_30115=y +CONFIG_CAVIUM_TX2_ERRATUM_219=y +CONFIG_FUJITSU_ERRATUM_010001=y +CONFIG_HISILICON_ERRATUM_161600802=y CONFIG_QCOM_FALKOR_ERRATUM_1003=y CONFIG_QCOM_FALKOR_ERRATUM_1009=y CONFIG_QCOM_QDF2400_ERRATUM_0065=y +CONFIG_QCOM_FALKOR_ERRATUM_E1041=y +CONFIG_SOCIONEXT_SYNQUACER_PREITS=y +# end of ARM errata workarounds via the alternatives framework + CONFIG_ARM64_4K_PAGES=y # CONFIG_ARM64_16K_PAGES is not set # CONFIG_ARM64_64K_PAGES is not set CONFIG_ARM64_VA_BITS_39=y # CONFIG_ARM64_VA_BITS_48 is not set CONFIG_ARM64_VA_BITS=39 +CONFIG_ARM64_PA_BITS_48=y +CONFIG_ARM64_PA_BITS=48 # CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_CPU_LITTLE_ENDIAN=y # CONFIG_SCHED_MC is not set # CONFIG_SCHED_SMT is not set CONFIG_NR_CPUS=8 CONFIG_HOTPLUG_CPU=y # CONFIG_NUMA is not set -CONFIG_PREEMPT_NONE=y -# CONFIG_PREEMPT_VOLUNTARY is not set -# CONFIG_PREEMPT is not set +CONFIG_HOLES_IN_ZONE=y # CONFIG_HZ_100 is not set CONFIG_HZ_250=y # CONFIG_HZ_300 is not set @@ -455,101 +368,102 @@ CONFIG_HZ_250=y CONFIG_HZ=250 CONFIG_SCHED_HRTICK=y CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y -CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y CONFIG_ARCH_SPARSEMEM_ENABLE=y CONFIG_ARCH_SPARSEMEM_DEFAULT=y CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_FLATMEM_ENABLE=y CONFIG_HAVE_ARCH_PFN_VALID=y CONFIG_HW_PERF_EVENTS=y CONFIG_SYS_SUPPORTS_HUGETLBFS=y CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_SPARSEMEM_MANUAL=y -CONFIG_SPARSEMEM=y -CONFIG_HAVE_MEMORY_PRESENT=y -CONFIG_SPARSEMEM_EXTREME=y -CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y -CONFIG_SPARSEMEM_VMEMMAP=y -CONFIG_HAVE_MEMBLOCK=y -CONFIG_NO_BOOTMEM=y -CONFIG_MEMORY_ISOLATION=y -# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set -CONFIG_SPLIT_PTLOCK_CPUS=4 -CONFIG_COMPACTION=y -CONFIG_MIGRATION=y -CONFIG_PHYS_ADDR_T_64BIT=y -CONFIG_BOUNCE=y -# CONFIG_KSM is not set -CONFIG_DEFAULT_MMAP_MIN_ADDR=32768 -CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y -# CONFIG_MEMORY_FAILURE is not set -CONFIG_TRANSPARENT_HUGEPAGE=y -# CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS is not set -CONFIG_TRANSPARENT_HUGEPAGE_MADVISE=y -# CONFIG_ARCH_WANTS_THP_SWAP is not set -CONFIG_TRANSPARENT_HUGE_PAGECACHE=y -# CONFIG_CLEANCACHE is not set -# CONFIG_FRONTSWAP is not set -CONFIG_CMA=y -# CONFIG_CMA_DEBUG is not set -# CONFIG_CMA_DEBUGFS is not set -CONFIG_CMA_AREAS=7 -# CONFIG_ZPOOL is not set -# CONFIG_ZBUD is not set -# CONFIG_ZSMALLOC is not set -CONFIG_GENERIC_EARLY_IOREMAP=y -# CONFIG_IDLE_PAGE_TRACKING is not set -CONFIG_FRAME_VECTOR=y -# CONFIG_PERCPU_STATS is not set -# CONFIG_SECCOMP is not set +CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y # CONFIG_PARAVIRT is not set # CONFIG_PARAVIRT_TIME_ACCOUNTING is not set # CONFIG_KEXEC is not set +# CONFIG_KEXEC_FILE is not set # CONFIG_CRASH_DUMP is not set # CONFIG_XEN is not set CONFIG_FORCE_MAX_ZONEORDER=11 -# CONFIG_ARMV8_DEPRECATED is not set +CONFIG_UNMAP_KERNEL_AT_EL0=y +CONFIG_RODATA_FULL_DEFAULT_ENABLED=y # CONFIG_ARM64_SW_TTBR0_PAN is not set +CONFIG_ARM64_TAGGED_ADDR_ABI=y +CONFIG_COMPAT=y +CONFIG_KUSER_HELPERS=y +CONFIG_ARMV8_DEPRECATED=y +CONFIG_SWP_EMULATION=y +CONFIG_CP15_BARRIER_EMULATION=y +CONFIG_SETEND_EMULATION=y # # ARMv8.1 architectural features # CONFIG_ARM64_HW_AFDBM=y CONFIG_ARM64_PAN=y -# CONFIG_ARM64_LSE_ATOMICS is not set CONFIG_ARM64_VHE=y +# end of ARMv8.1 architectural features # # ARMv8.2 architectural features # CONFIG_ARM64_UAO=y # CONFIG_ARM64_PMEM is not set -CONFIG_ARM64_MODULE_CMODEL_LARGE=y +CONFIG_ARM64_RAS_EXTN=y +CONFIG_ARM64_CNP=y +# end of ARMv8.2 architectural features + +# +# ARMv8.3 architectural features +# +CONFIG_ARM64_PTR_AUTH=y +CONFIG_CC_HAS_BRANCH_PROT_PAC_RET=y +CONFIG_CC_HAS_SIGN_RETURN_ADDRESS=y +CONFIG_AS_HAS_PAC=y +CONFIG_AS_HAS_CFI_NEGATE_RA_STATE=y +# end of ARMv8.3 architectural features + +# +# ARMv8.4 architectural features +# +CONFIG_ARM64_AMU_EXTN=y +CONFIG_AS_HAS_ARMV8_4=y +CONFIG_ARM64_TLB_RANGE=y +# end of ARMv8.4 architectural features + +# +# ARMv8.5 architectural features +# +CONFIG_ARM64_BTI=y +CONFIG_ARM64_BTI_KERNEL=y +CONFIG_CC_HAS_BRANCH_PROT_PAC_RET_BTI=y +CONFIG_ARM64_E0PD=y +CONFIG_ARCH_RANDOM=y +CONFIG_ARM64_AS_HAS_MTE=y +CONFIG_ARM64_MTE=y +# end of ARMv8.5 architectural features + +CONFIG_ARM64_SVE=y +CONFIG_ARM64_MODULE_PLTS=y +# CONFIG_ARM64_PSEUDO_NMI is not set +CONFIG_RELOCATABLE=y # CONFIG_RANDOMIZE_BASE is not set +CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y +CONFIG_STACKPROTECTOR_PER_TASK=y +# end of Kernel Features # # Boot options # CONFIG_CMDLINE="" -# CONFIG_CMDLINE_FORCE is not set CONFIG_EFI_STUB=y CONFIG_EFI=y # CONFIG_DMI is not set +# end of Boot options -# -# Userspace binary formats -# -CONFIG_BINFMT_ELF=y -CONFIG_COMPAT_BINFMT_ELF=y -CONFIG_ELFCORE=y -CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y -CONFIG_BINFMT_SCRIPT=y -# CONFIG_HAVE_AOUT is not set -# CONFIG_BINFMT_MISC is not set -CONFIG_COREDUMP=y -CONFIG_COMPAT=y CONFIG_SYSVIPC_COMPAT=y +CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y +CONFIG_ARCH_ENABLE_THP_MIGRATION=y # # Power management options @@ -564,15 +478,16 @@ CONFIG_PM_SLEEP_SMP=y # CONFIG_PM_WAKELOCKS is not set CONFIG_PM=y # CONFIG_PM_DEBUG is not set -CONFIG_PM_OPP=y CONFIG_PM_CLK=y CONFIG_PM_GENERIC_DOMAINS=y # CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set CONFIG_PM_GENERIC_DOMAINS_SLEEP=y CONFIG_PM_GENERIC_DOMAINS_OF=y CONFIG_CPU_PM=y +# CONFIG_ENERGY_MODEL is not set CONFIG_ARCH_HIBERNATION_POSSIBLE=y CONFIG_ARCH_SUSPEND_POSSIBLE=y +# end of Power management options # # CPU Power Management @@ -585,13 +500,16 @@ CONFIG_CPU_IDLE=y CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y # CONFIG_CPU_IDLE_GOV_LADDER is not set CONFIG_CPU_IDLE_GOV_MENU=y +# CONFIG_CPU_IDLE_GOV_TEO is not set CONFIG_DT_IDLE_STATES=y # # ARM CPU Idle Drivers # CONFIG_ARM_CPUIDLE=y -# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set +# CONFIG_ARM_PSCI_CPUIDLE is not set +# end of ARM CPU Idle Drivers +# end of CPU Idle # # CPU Frequency scaling @@ -616,12 +534,324 @@ CONFIG_CPU_FREQ_GOV_USERSPACE=y # CONFIG_CPUFREQ_DT=y CONFIG_CPUFREQ_DT_PLATDEV=y -# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set -# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set -# CONFIG_QORIQ_CPUFREQ is not set +# end of CPU Frequency scaling +# end of CPU Power Management + +# +# Firmware Drivers +# +# CONFIG_ARM_SCMI_PROTOCOL is not set +# CONFIG_ARM_SCPI_PROTOCOL is not set +# CONFIG_ARM_SDE_INTERFACE is not set +# CONFIG_FIRMWARE_MEMMAP is not set +# CONFIG_FW_CFG_SYSFS is not set +# CONFIG_GOOGLE_FIRMWARE is not set + +# +# EFI (Extensible Firmware Interface) Support +# +CONFIG_EFI_ESRT=y +CONFIG_EFI_PARAMS_FROM_FDT=y +CONFIG_EFI_RUNTIME_WRAPPERS=y +CONFIG_EFI_GENERIC_STUB=y +CONFIG_EFI_ARMSTUB_DTB_LOADER=y +CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER=y +# CONFIG_EFI_BOOTLOADER_CONTROL is not set +# CONFIG_EFI_CAPSULE_LOADER is not set +# CONFIG_EFI_TEST is not set +# CONFIG_RESET_ATTACK_MITIGATION is not set +# CONFIG_EFI_DISABLE_PCI_DMA is not set +# end of EFI (Extensible Firmware Interface) Support + +CONFIG_EFI_EARLYCON=y +CONFIG_ARM_PSCI_FW=y +# CONFIG_ARM_PSCI_CHECKER is not set +CONFIG_HAVE_ARM_SMCCC=y +CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y +CONFIG_ARM_SMCCC_SOC_ID=y + +# +# Tegra firmware driver +# +# end of Tegra firmware driver + +# +# Zynq MPSoC Firmware Drivers +# +CONFIG_ZYNQMP_FIRMWARE=y +# CONFIG_ZYNQMP_FIRMWARE_DEBUG is not set +# CONFIG_ZYNQMP_FIRMWARE_SECURE is not set +# end of Zynq MPSoC Firmware Drivers +# end of Firmware Drivers + +CONFIG_ARCH_SUPPORTS_ACPI=y +# CONFIG_ACPI is not set +# CONFIG_VIRTUALIZATION is not set +# CONFIG_ARM64_CRYPTO is not set + +# +# General architecture-dependent options +# +CONFIG_SET_FS=y +# CONFIG_KPROBES is not set +# CONFIG_JUMP_LABEL is not set +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y +CONFIG_HAVE_NMI=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_ARCH_HAS_FORTIFY_SOURCE=y +CONFIG_ARCH_HAS_KEEPINITRD=y +CONFIG_ARCH_HAS_SET_MEMORY=y +CONFIG_ARCH_HAS_SET_DIRECT_MAP=y +CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y +CONFIG_HAVE_ASM_MODVERSIONS=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_RSEQ=y +CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y +CONFIG_HAVE_HW_BREAKPOINT=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y +CONFIG_MMU_GATHER_TABLE_FREE=y +CONFIG_MMU_GATHER_RCU_TABLE_FREE=y +CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y +CONFIG_HAVE_CMPXCHG_LOCAL=y +CONFIG_HAVE_CMPXCHG_DOUBLE=y +CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y +CONFIG_HAVE_ARCH_SECCOMP=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_SECCOMP=y +CONFIG_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_STACKLEAK=y +CONFIG_HAVE_STACKPROTECTOR=y +CONFIG_STACKPROTECTOR=y +CONFIG_STACKPROTECTOR_STRONG=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_MOVE_PMD=y +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y +CONFIG_HAVE_ARCH_HUGE_VMAP=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_MODULES_USE_ELF_RELA=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_HAVE_ARCH_MMAP_RND_BITS=y +CONFIG_ARCH_MMAP_RND_BITS=18 +CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y +CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11 +CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_COMPAT_OLD_SIGACTION=y +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_HAVE_ARCH_VMAP_STACK=y +CONFIG_VMAP_STACK=y +CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y +CONFIG_STRICT_KERNEL_RWX=y +CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y +CONFIG_STRICT_MODULE_RWX=y +CONFIG_HAVE_ARCH_COMPILER_H=y +CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y +CONFIG_ARCH_USE_MEMREMAP_PROT=y +# CONFIG_LOCK_EVENT_COUNTS is not set +CONFIG_ARCH_HAS_RELR=y +CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +# end of GCOV-based kernel profiling + +CONFIG_HAVE_GCC_PLUGINS=y +# end of General architecture-dependent options + +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_MODULE_SIG is not set +# CONFIG_MODULE_COMPRESS is not set +# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_TRIM_UNUSED_KSYMS is not set +CONFIG_MODULES_TREE_LOOKUP=y +CONFIG_BLOCK=y +CONFIG_BLK_SCSI_REQUEST=y +CONFIG_BLK_DEV_BSG=y +# CONFIG_BLK_DEV_BSGLIB is not set +# CONFIG_BLK_DEV_INTEGRITY is not set +# CONFIG_BLK_DEV_ZONED is not set +# CONFIG_BLK_CMDLINE_PARSER is not set +# CONFIG_BLK_WBT is not set +CONFIG_BLK_DEBUG_FS=y +# CONFIG_BLK_SED_OPAL is not set +# CONFIG_BLK_INLINE_ENCRYPTION is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_EFI_PARTITION=y +# end of Partition Types + +CONFIG_BLOCK_COMPAT=y +CONFIG_BLK_MQ_PCI=y +CONFIG_BLK_MQ_VIRTIO=y +CONFIG_BLK_PM=y + +# +# IO Schedulers +# +CONFIG_MQ_IOSCHED_DEADLINE=y +CONFIG_MQ_IOSCHED_KYBER=y +# CONFIG_IOSCHED_BFQ is not set +# end of IO Schedulers + +CONFIG_ASN1=y +CONFIG_ARCH_INLINE_SPIN_TRYLOCK=y +CONFIG_ARCH_INLINE_SPIN_TRYLOCK_BH=y +CONFIG_ARCH_INLINE_SPIN_LOCK=y +CONFIG_ARCH_INLINE_SPIN_LOCK_BH=y +CONFIG_ARCH_INLINE_SPIN_LOCK_IRQ=y +CONFIG_ARCH_INLINE_SPIN_LOCK_IRQSAVE=y +CONFIG_ARCH_INLINE_SPIN_UNLOCK=y +CONFIG_ARCH_INLINE_SPIN_UNLOCK_BH=y +CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQ=y +CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE=y +CONFIG_ARCH_INLINE_READ_LOCK=y +CONFIG_ARCH_INLINE_READ_LOCK_BH=y +CONFIG_ARCH_INLINE_READ_LOCK_IRQ=y +CONFIG_ARCH_INLINE_READ_LOCK_IRQSAVE=y +CONFIG_ARCH_INLINE_READ_UNLOCK=y +CONFIG_ARCH_INLINE_READ_UNLOCK_BH=y +CONFIG_ARCH_INLINE_READ_UNLOCK_IRQ=y +CONFIG_ARCH_INLINE_READ_UNLOCK_IRQRESTORE=y +CONFIG_ARCH_INLINE_WRITE_LOCK=y +CONFIG_ARCH_INLINE_WRITE_LOCK_BH=y +CONFIG_ARCH_INLINE_WRITE_LOCK_IRQ=y +CONFIG_ARCH_INLINE_WRITE_LOCK_IRQSAVE=y +CONFIG_ARCH_INLINE_WRITE_UNLOCK=y +CONFIG_ARCH_INLINE_WRITE_UNLOCK_BH=y +CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQ=y +CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE=y +CONFIG_INLINE_SPIN_TRYLOCK=y +CONFIG_INLINE_SPIN_TRYLOCK_BH=y +CONFIG_INLINE_SPIN_LOCK=y +CONFIG_INLINE_SPIN_LOCK_BH=y +CONFIG_INLINE_SPIN_LOCK_IRQ=y +CONFIG_INLINE_SPIN_LOCK_IRQSAVE=y +CONFIG_INLINE_SPIN_UNLOCK_BH=y +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE=y +CONFIG_INLINE_READ_LOCK=y +CONFIG_INLINE_READ_LOCK_BH=y +CONFIG_INLINE_READ_LOCK_IRQ=y +CONFIG_INLINE_READ_LOCK_IRQSAVE=y +CONFIG_INLINE_READ_UNLOCK=y +CONFIG_INLINE_READ_UNLOCK_BH=y +CONFIG_INLINE_READ_UNLOCK_IRQ=y +CONFIG_INLINE_READ_UNLOCK_IRQRESTORE=y +CONFIG_INLINE_WRITE_LOCK=y +CONFIG_INLINE_WRITE_LOCK_BH=y +CONFIG_INLINE_WRITE_LOCK_IRQ=y +CONFIG_INLINE_WRITE_LOCK_IRQSAVE=y +CONFIG_INLINE_WRITE_UNLOCK=y +CONFIG_INLINE_WRITE_UNLOCK_BH=y +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE=y +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y +CONFIG_QUEUED_SPINLOCKS=y +CONFIG_ARCH_USE_QUEUED_RWLOCKS=y +CONFIG_QUEUED_RWLOCKS=y +CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y +CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y +CONFIG_FREEZER=y + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +CONFIG_COMPAT_BINFMT_ELF=y +CONFIG_ARCH_BINFMT_ELF_STATE=y +CONFIG_ARCH_HAVE_ELF_PROT=y +CONFIG_ARCH_USE_GNU_PROPERTY=y +CONFIG_ELFCORE=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +CONFIG_BINFMT_SCRIPT=y +# CONFIG_BINFMT_MISC is not set +CONFIG_COREDUMP=y +# end of Executable file formats + +# +# Memory Management options +# +CONFIG_SELECT_MEMORY_MODEL=y +# CONFIG_FLATMEM_MANUAL is not set +CONFIG_SPARSEMEM_MANUAL=y +CONFIG_SPARSEMEM=y +CONFIG_SPARSEMEM_EXTREME=y +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_SPARSEMEM_VMEMMAP=y +CONFIG_HAVE_FAST_GUP=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_MEMORY_ISOLATION=y +# CONFIG_MEMORY_HOTPLUG is not set +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_COMPACTION=y +# CONFIG_PAGE_REPORTING is not set +CONFIG_MIGRATION=y +CONFIG_CONTIG_ALLOC=y +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_BOUNCE=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=32768 +CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y +# CONFIG_MEMORY_FAILURE is not set +CONFIG_TRANSPARENT_HUGEPAGE=y +# CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS is not set +CONFIG_TRANSPARENT_HUGEPAGE_MADVISE=y +# CONFIG_CLEANCACHE is not set +# CONFIG_FRONTSWAP is not set +CONFIG_CMA=y +# CONFIG_CMA_DEBUG is not set +# CONFIG_CMA_DEBUGFS is not set +CONFIG_CMA_AREAS=7 +# CONFIG_ZPOOL is not set +# CONFIG_ZBUD is not set +# CONFIG_ZSMALLOC is not set +CONFIG_GENERIC_EARLY_IOREMAP=y +# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set +# CONFIG_IDLE_PAGE_TRACKING is not set +CONFIG_ARCH_HAS_PTE_DEVMAP=y +CONFIG_FRAME_VECTOR=y +CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y +# CONFIG_PERCPU_STATS is not set +# CONFIG_GUP_BENCHMARK is not set +# CONFIG_READ_ONLY_THP_FOR_FS is not set +CONFIG_ARCH_HAS_PTE_SPECIAL=y +# end of Memory Management options + CONFIG_NET=y CONFIG_COMPAT_NETLINK_MESSAGES=y CONFIG_NET_INGRESS=y +CONFIG_SKB_EXTENSIONS=y # # Networking options @@ -629,11 +859,13 @@ CONFIG_NET_INGRESS=y CONFIG_PACKET=y # CONFIG_PACKET_DIAG is not set CONFIG_UNIX=y +CONFIG_UNIX_SCM=y # CONFIG_UNIX_DIAG is not set # CONFIG_TLS is not set CONFIG_XFRM=y CONFIG_XFRM_ALGO=y CONFIG_XFRM_USER=y +# CONFIG_XFRM_INTERFACE is not set # CONFIG_XFRM_SUB_POLICY is not set CONFIG_XFRM_MIGRATE=y # CONFIG_XFRM_STATISTICS is not set @@ -646,35 +878,49 @@ CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y CONFIG_IP_PNP_RARP=y -CONFIG_NET_IPIP=y +CONFIG_NET_IPIP=m # CONFIG_NET_IPGRE_DEMUX is not set -CONFIG_NET_IP_TUNNEL=y +CONFIG_NET_IP_TUNNEL=m +CONFIG_IP_MROUTE_COMMON=y CONFIG_IP_MROUTE=y CONFIG_IP_PIMSM_V1=y CONFIG_IP_PIMSM_V2=y CONFIG_SYN_COOKIES=y -# CONFIG_NET_IPVTI is not set -# CONFIG_NET_UDP_TUNNEL is not set -# CONFIG_NET_FOU is not set +CONFIG_NET_IPVTI=m +CONFIG_NET_UDP_TUNNEL=m +CONFIG_NET_FOU=m # CONFIG_NET_FOU_IP_TUNNELS is not set # CONFIG_INET_AH is not set # CONFIG_INET_ESP is not set # CONFIG_INET_IPCOMP is not set -# CONFIG_INET_XFRM_TUNNEL is not set -CONFIG_INET_TUNNEL=y -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y +CONFIG_INET_TUNNEL=m CONFIG_INET_DIAG=y CONFIG_INET_TCP_DIAG=y -# CONFIG_INET_UDP_DIAG is not set -# CONFIG_INET_RAW_DIAG is not set +CONFIG_INET_UDP_DIAG=m +CONFIG_INET_RAW_DIAG=m # CONFIG_INET_DIAG_DESTROY is not set -# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_ADVANCED=y +CONFIG_TCP_CONG_BIC=m CONFIG_TCP_CONG_CUBIC=y +CONFIG_TCP_CONG_WESTWOOD=m +CONFIG_TCP_CONG_HTCP=m +# CONFIG_TCP_CONG_HSTCP is not set +# CONFIG_TCP_CONG_HYBLA is not set +# CONFIG_TCP_CONG_VEGAS is not set +# CONFIG_TCP_CONG_NV is not set +# CONFIG_TCP_CONG_SCALABLE is not set +# CONFIG_TCP_CONG_LP is not set +# CONFIG_TCP_CONG_VENO is not set +# CONFIG_TCP_CONG_YEAH is not set +# CONFIG_TCP_CONG_ILLINOIS is not set +# CONFIG_TCP_CONG_DCTCP is not set +# CONFIG_TCP_CONG_CDG is not set +# CONFIG_TCP_CONG_BBR is not set +CONFIG_DEFAULT_CUBIC=y +# CONFIG_DEFAULT_RENO is not set CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TCP_MD5SIG is not set -CONFIG_IPV6=m +CONFIG_IPV6=y # CONFIG_IPV6_ROUTER_PREF is not set # CONFIG_IPV6_OPTIMISTIC_DAD is not set # CONFIG_INET6_AH is not set @@ -682,49 +928,52 @@ CONFIG_IPV6=m # CONFIG_INET6_IPCOMP is not set # CONFIG_IPV6_MIP6 is not set # CONFIG_IPV6_ILA is not set -# CONFIG_INET6_XFRM_TUNNEL is not set -# CONFIG_INET6_TUNNEL is not set -CONFIG_INET6_XFRM_MODE_TRANSPORT=m -CONFIG_INET6_XFRM_MODE_TUNNEL=m -CONFIG_INET6_XFRM_MODE_BEET=m -# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set -# CONFIG_IPV6_VTI is not set +CONFIG_INET6_TUNNEL=m +CONFIG_IPV6_VTI=m CONFIG_IPV6_SIT=m # CONFIG_IPV6_SIT_6RD is not set CONFIG_IPV6_NDISC_NODETYPE=y -# CONFIG_IPV6_TUNNEL is not set -# CONFIG_IPV6_FOU is not set -# CONFIG_IPV6_FOU_TUNNEL is not set -# CONFIG_IPV6_MULTIPLE_TABLES is not set +CONFIG_IPV6_TUNNEL=m +CONFIG_IPV6_FOU=m +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_SUBTREES=y CONFIG_IPV6_MROUTE=y CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y CONFIG_IPV6_PIMSM_V2=y # CONFIG_IPV6_SEG6_LWTUNNEL is not set # CONFIG_IPV6_SEG6_HMAC is not set +# CONFIG_IPV6_RPL_LWTUNNEL is not set +CONFIG_MPTCP=y +CONFIG_INET_MPTCP_DIAG=y +CONFIG_MPTCP_IPV6=y CONFIG_NETWORK_SECMARK=y CONFIG_NET_PTP_CLASSIFY=y -# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +CONFIG_NETWORK_PHY_TIMESTAMPING=y CONFIG_NETFILTER=y CONFIG_NETFILTER_ADVANCED=y -CONFIG_BRIDGE_NETFILTER=m +# CONFIG_BRIDGE_NETFILTER is not set # # Core Netfilter Configuration # CONFIG_NETFILTER_INGRESS=y CONFIG_NETFILTER_NETLINK=y +CONFIG_NETFILTER_FAMILY_BRIDGE=y # CONFIG_NETFILTER_NETLINK_ACCT is not set # CONFIG_NETFILTER_NETLINK_QUEUE is not set CONFIG_NETFILTER_NETLINK_LOG=y +# CONFIG_NETFILTER_NETLINK_OSF is not set CONFIG_NF_CONNTRACK=m CONFIG_NF_LOG_COMMON=y # CONFIG_NF_LOG_NETDEV is not set CONFIG_NF_CONNTRACK_MARK=y # CONFIG_NF_CONNTRACK_SECMARK is not set +# CONFIG_NF_CONNTRACK_ZONES is not set CONFIG_NF_CONNTRACK_PROCFS=y # CONFIG_NF_CONNTRACK_EVENTS is not set # CONFIG_NF_CONNTRACK_TIMEOUT is not set # CONFIG_NF_CONNTRACK_TIMESTAMP is not set +# CONFIG_NF_CONNTRACK_LABELS is not set CONFIG_NF_CT_PROTO_DCCP=y CONFIG_NF_CT_PROTO_SCTP=y CONFIG_NF_CT_PROTO_UDPLITE=y @@ -739,19 +988,8 @@ CONFIG_NF_CT_PROTO_UDPLITE=y # CONFIG_NF_CONNTRACK_SIP is not set # CONFIG_NF_CONNTRACK_TFTP is not set CONFIG_NF_CT_NETLINK=m -# CONFIG_NF_CT_NETLINK_TIMEOUT is not set # CONFIG_NETFILTER_NETLINK_GLUE_CT is not set -CONFIG_NF_NAT=m -CONFIG_NF_NAT_NEEDED=y -CONFIG_NF_NAT_PROTO_DCCP=y -CONFIG_NF_NAT_PROTO_UDPLITE=y -CONFIG_NF_NAT_PROTO_SCTP=y -# CONFIG_NF_NAT_AMANDA is not set -# CONFIG_NF_NAT_FTP is not set -# CONFIG_NF_NAT_IRC is not set -# CONFIG_NF_NAT_SIP is not set -# CONFIG_NF_NAT_TFTP is not set -CONFIG_NF_NAT_REDIRECT=m +# CONFIG_NF_NAT is not set # CONFIG_NF_TABLES is not set CONFIG_NETFILTER_XTABLES=y @@ -775,12 +1013,9 @@ CONFIG_NETFILTER_XT_TARGET_CHECKSUM=y # CONFIG_NETFILTER_XT_TARGET_LED is not set CONFIG_NETFILTER_XT_TARGET_LOG=y # CONFIG_NETFILTER_XT_TARGET_MARK is not set -# CONFIG_NETFILTER_XT_NAT is not set -# CONFIG_NETFILTER_XT_TARGET_NETMAP is not set # CONFIG_NETFILTER_XT_TARGET_NFLOG is not set # CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set # CONFIG_NETFILTER_XT_TARGET_RATEEST is not set -CONFIG_NETFILTER_XT_TARGET_REDIRECT=m # CONFIG_NETFILTER_XT_TARGET_TEE is not set # CONFIG_NETFILTER_XT_TARGET_TPROXY is not set # CONFIG_NETFILTER_XT_TARGET_SECMARK is not set @@ -821,19 +1056,21 @@ CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y # CONFIG_NETFILTER_XT_MATCH_OSF is not set # CONFIG_NETFILTER_XT_MATCH_OWNER is not set # CONFIG_NETFILTER_XT_MATCH_POLICY is not set -# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set # CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set # CONFIG_NETFILTER_XT_MATCH_QUOTA is not set # CONFIG_NETFILTER_XT_MATCH_RATEEST is not set # CONFIG_NETFILTER_XT_MATCH_REALM is not set # CONFIG_NETFILTER_XT_MATCH_RECENT is not set # CONFIG_NETFILTER_XT_MATCH_SCTP is not set +# CONFIG_NETFILTER_XT_MATCH_SOCKET is not set CONFIG_NETFILTER_XT_MATCH_STATE=m # CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set # CONFIG_NETFILTER_XT_MATCH_STRING is not set # CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set # CONFIG_NETFILTER_XT_MATCH_TIME is not set # CONFIG_NETFILTER_XT_MATCH_U32 is not set +# end of Core Netfilter Configuration + # CONFIG_IP_SET is not set # CONFIG_IP_VS is not set @@ -841,16 +1078,12 @@ CONFIG_NETFILTER_XT_MATCH_STATE=m # IP: Netfilter Configuration # CONFIG_NF_DEFRAG_IPV4=m -CONFIG_NF_CONNTRACK_IPV4=m # CONFIG_NF_SOCKET_IPV4 is not set +# CONFIG_NF_TPROXY_IPV4 is not set # CONFIG_NF_DUP_IPV4 is not set # CONFIG_NF_LOG_ARP is not set CONFIG_NF_LOG_IPV4=y CONFIG_NF_REJECT_IPV4=y -CONFIG_NF_NAT_IPV4=m -# CONFIG_NF_NAT_MASQUERADE_IPV4 is not set -# CONFIG_NF_NAT_PPTP is not set -# CONFIG_NF_NAT_H323 is not set CONFIG_IP_NF_IPTABLES=y # CONFIG_IP_NF_MATCH_AH is not set # CONFIG_IP_NF_MATCH_ECN is not set @@ -866,19 +1099,17 @@ CONFIG_IP_NF_MANGLE=y # CONFIG_IP_NF_TARGET_TTL is not set # CONFIG_IP_NF_RAW is not set # CONFIG_IP_NF_ARPTABLES is not set +# end of IP: Netfilter Configuration # # IPv6: Netfilter Configuration # -CONFIG_NF_DEFRAG_IPV6=m -CONFIG_NF_CONNTRACK_IPV6=m # CONFIG_NF_SOCKET_IPV6 is not set +# CONFIG_NF_TPROXY_IPV6 is not set # CONFIG_NF_DUP_IPV6 is not set -CONFIG_NF_REJECT_IPV6=m -CONFIG_NF_LOG_IPV6=m -CONFIG_NF_NAT_IPV6=m -# CONFIG_NF_NAT_MASQUERADE_IPV6 is not set -CONFIG_IP6_NF_IPTABLES=m +CONFIG_NF_REJECT_IPV6=y +CONFIG_NF_LOG_IPV6=y +CONFIG_IP6_NF_IPTABLES=y # CONFIG_IP6_NF_MATCH_AH is not set # CONFIG_IP6_NF_MATCH_EUI64 is not set # CONFIG_IP6_NF_MATCH_FRAG is not set @@ -888,17 +1119,22 @@ CONFIG_IP6_NF_IPTABLES=m # CONFIG_IP6_NF_MATCH_MH is not set # CONFIG_IP6_NF_MATCH_RPFILTER is not set # CONFIG_IP6_NF_MATCH_RT is not set +# CONFIG_IP6_NF_MATCH_SRH is not set # CONFIG_IP6_NF_TARGET_HL is not set -CONFIG_IP6_NF_FILTER=m -CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_FILTER=y +CONFIG_IP6_NF_TARGET_REJECT=y # CONFIG_IP6_NF_TARGET_SYNPROXY is not set -CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_MANGLE=y # CONFIG_IP6_NF_RAW is not set # CONFIG_IP6_NF_NAT is not set -CONFIG_BRIDGE_NF_EBTABLES=m +# end of IPv6: Netfilter Configuration + +CONFIG_NF_DEFRAG_IPV6=m +# CONFIG_NF_CONNTRACK_BRIDGE is not set +CONFIG_BRIDGE_NF_EBTABLES=y # CONFIG_BRIDGE_EBT_BROUTE is not set -CONFIG_BRIDGE_EBT_T_FILTER=m -CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_T_FILTER=y +CONFIG_BRIDGE_EBT_T_NAT=y # CONFIG_BRIDGE_EBT_802_3 is not set # CONFIG_BRIDGE_EBT_AMONG is not set # CONFIG_BRIDGE_EBT_ARP is not set @@ -911,48 +1147,123 @@ CONFIG_BRIDGE_EBT_T_NAT=m # CONFIG_BRIDGE_EBT_VLAN is not set # CONFIG_BRIDGE_EBT_ARPREPLY is not set # CONFIG_BRIDGE_EBT_DNAT is not set -CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_MARK_T=y # CONFIG_BRIDGE_EBT_REDIRECT is not set # CONFIG_BRIDGE_EBT_SNAT is not set # CONFIG_BRIDGE_EBT_LOG is not set # CONFIG_BRIDGE_EBT_NFLOG is not set +CONFIG_BPFILTER=y +CONFIG_BPFILTER_UMH=m # CONFIG_IP_DCCP is not set # CONFIG_IP_SCTP is not set # CONFIG_RDS is not set # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_L2TP is not set -CONFIG_STP=m -CONFIG_BRIDGE=m +CONFIG_STP=y +CONFIG_BRIDGE=y CONFIG_BRIDGE_IGMP_SNOOPING=y -CONFIG_BRIDGE_VLAN_FILTERING=y +# CONFIG_BRIDGE_VLAN_FILTERING is not set +# CONFIG_BRIDGE_MRP is not set CONFIG_HAVE_NET_DSA=y -# CONFIG_NET_DSA is not set -CONFIG_VLAN_8021Q=y +CONFIG_NET_DSA=y +# CONFIG_NET_DSA_TAG_AR9331 is not set +# CONFIG_NET_DSA_TAG_BRCM is not set +# CONFIG_NET_DSA_TAG_BRCM_PREPEND is not set +# CONFIG_NET_DSA_TAG_GSWIP is not set +# CONFIG_NET_DSA_TAG_DSA is not set +# CONFIG_NET_DSA_TAG_EDSA is not set +# CONFIG_NET_DSA_TAG_MTK is not set +# CONFIG_NET_DSA_TAG_KSZ is not set +# CONFIG_NET_DSA_TAG_RTL4_A is not set +# CONFIG_NET_DSA_TAG_OCELOT is not set +# CONFIG_NET_DSA_TAG_QCA is not set +# CONFIG_NET_DSA_TAG_LAN9303 is not set +# CONFIG_NET_DSA_TAG_SJA1105 is not set +# CONFIG_NET_DSA_TAG_TRAILER is not set +CONFIG_VLAN_8021Q=m # CONFIG_VLAN_8021Q_GVRP is not set # CONFIG_VLAN_8021Q_MVRP is not set # CONFIG_DECNET is not set -CONFIG_LLC=m +CONFIG_LLC=y # CONFIG_LLC2 is not set -# CONFIG_IPX is not set # CONFIG_ATALK is not set # CONFIG_X25 is not set # CONFIG_LAPB is not set # CONFIG_PHONET is not set # CONFIG_6LOWPAN is not set -# CONFIG_IEEE802154 is not set -# CONFIG_NET_SCHED is not set +CONFIG_IEEE802154=y +# CONFIG_IEEE802154_NL802154_EXPERIMENTAL is not set +CONFIG_IEEE802154_SOCKET=y +CONFIG_MAC802154=y +CONFIG_NET_SCHED=y + +# +# Queueing/Scheduling +# +# CONFIG_NET_SCH_CBQ is not set +# CONFIG_NET_SCH_HTB is not set +# CONFIG_NET_SCH_HFSC is not set +# CONFIG_NET_SCH_PRIO is not set +# CONFIG_NET_SCH_MULTIQ is not set +# CONFIG_NET_SCH_RED is not set +# CONFIG_NET_SCH_SFB is not set +# CONFIG_NET_SCH_SFQ is not set +# CONFIG_NET_SCH_TEQL is not set +# CONFIG_NET_SCH_TBF is not set +# CONFIG_NET_SCH_CBS is not set +# CONFIG_NET_SCH_ETF is not set +# CONFIG_NET_SCH_TAPRIO is not set +# CONFIG_NET_SCH_GRED is not set +# CONFIG_NET_SCH_DSMARK is not set +# CONFIG_NET_SCH_NETEM is not set +# CONFIG_NET_SCH_DRR is not set +# CONFIG_NET_SCH_MQPRIO is not set +# CONFIG_NET_SCH_SKBPRIO is not set +# CONFIG_NET_SCH_CHOKE is not set +# CONFIG_NET_SCH_QFQ is not set +# CONFIG_NET_SCH_CODEL is not set +# CONFIG_NET_SCH_FQ_CODEL is not set +# CONFIG_NET_SCH_CAKE is not set +# CONFIG_NET_SCH_FQ is not set +# CONFIG_NET_SCH_HHF is not set +# CONFIG_NET_SCH_PIE is not set +# CONFIG_NET_SCH_PLUG is not set +# CONFIG_NET_SCH_ETS is not set +# CONFIG_NET_SCH_DEFAULT is not set + +# +# Classification +# +# CONFIG_NET_CLS_BASIC is not set +# CONFIG_NET_CLS_TCINDEX is not set +# CONFIG_NET_CLS_ROUTE4 is not set +# CONFIG_NET_CLS_FW is not set +# CONFIG_NET_CLS_U32 is not set +# CONFIG_NET_CLS_RSVP is not set +# CONFIG_NET_CLS_RSVP6 is not set +# CONFIG_NET_CLS_FLOW is not set +# CONFIG_NET_CLS_CGROUP is not set +# CONFIG_NET_CLS_BPF is not set +# CONFIG_NET_CLS_FLOWER is not set +# CONFIG_NET_CLS_MATCHALL is not set +# CONFIG_NET_EMATCH is not set +# CONFIG_NET_CLS_ACT is not set +CONFIG_NET_SCH_FIFO=y # CONFIG_DCB is not set CONFIG_DNS_RESOLVER=y # CONFIG_BATMAN_ADV is not set -# CONFIG_OPENVSWITCH is not set +CONFIG_OPENVSWITCH=m # CONFIG_VSOCKETS is not set -# CONFIG_NETLINK_DIAG is not set -# CONFIG_MPLS is not set -# CONFIG_NET_NSH is not set +CONFIG_NETLINK_DIAG=m +CONFIG_MPLS=y +CONFIG_NET_MPLS_GSO=m +# CONFIG_MPLS_ROUTING is not set +CONFIG_NET_NSH=m # CONFIG_HSR is not set -# CONFIG_NET_SWITCHDEV is not set +CONFIG_NET_SWITCHDEV=y # CONFIG_NET_L3_MASTER_DEV is not set +# CONFIG_QRTR is not set # CONFIG_NET_NCSI is not set CONFIG_RPS=y CONFIG_RFS_ACCEL=y @@ -968,11 +1279,16 @@ CONFIG_NET_FLOW_LIMIT=y # Network testing # CONFIG_NET_PKTGEN=y +# end of Network testing +# end of Networking options + # CONFIG_HAMRADIO is not set CONFIG_CAN=y CONFIG_CAN_RAW=y CONFIG_CAN_BCM=y CONFIG_CAN_GW=y +# CONFIG_CAN_J1939 is not set +# CONFIG_CAN_ISOTP is not set # # CAN Device Drivers @@ -982,8 +1298,9 @@ CONFIG_CAN_GW=y # CONFIG_CAN_SLCAN is not set CONFIG_CAN_DEV=y CONFIG_CAN_CALC_BITTIMING=y -# CONFIG_CAN_LEDS is not set +# CONFIG_CAN_FLEXCAN is not set # CONFIG_CAN_GRCAN is not set +# CONFIG_CAN_KVASER_PCIEFD is not set CONFIG_CAN_XILINXCAN=y # CONFIG_CAN_C_CAN is not set # CONFIG_CAN_CC770 is not set @@ -998,18 +1315,25 @@ CONFIG_CAN_XILINXCAN=y # # CONFIG_CAN_HI311X is not set # CONFIG_CAN_MCP251X is not set +# CONFIG_CAN_MCP251XFD is not set +# end of CAN SPI interfaces # # CAN USB interfaces # +# CONFIG_CAN_8DEV_USB is not set # CONFIG_CAN_EMS_USB is not set # CONFIG_CAN_ESD_USB2 is not set # CONFIG_CAN_GS_USB is not set # CONFIG_CAN_KVASER_USB is not set -# CONFIG_CAN_PEAK_USB is not set -# CONFIG_CAN_8DEV_USB is not set # CONFIG_CAN_MCBA_USB is not set +# CONFIG_CAN_PEAK_USB is not set +# CONFIG_CAN_UCAN is not set +# end of CAN USB interfaces + # CONFIG_CAN_DEBUG_DEVICES is not set +# end of CAN Device Drivers + CONFIG_BT=y CONFIG_BT_BREDR=y CONFIG_BT_RFCOMM=y @@ -1018,11 +1342,13 @@ CONFIG_BT_BNEP=y CONFIG_BT_BNEP_MC_FILTER=y CONFIG_BT_BNEP_PROTO_FILTER=y CONFIG_BT_HIDP=y -CONFIG_BT_HS=y +# CONFIG_BT_HS is not set CONFIG_BT_LE=y CONFIG_BT_LEDS=y -# CONFIG_BT_SELFTEST is not set +# CONFIG_BT_MSFTEXT is not set CONFIG_BT_DEBUGFS=y +# CONFIG_BT_SELFTEST is not set +# CONFIG_BT_FEATURE_DEBUG is not set # # Bluetooth device drivers @@ -1032,15 +1358,22 @@ CONFIG_BT_BCM=y CONFIG_BT_RTL=y CONFIG_BT_QCA=y CONFIG_BT_HCIBTUSB=y +# CONFIG_BT_HCIBTUSB_AUTOSUSPEND is not set CONFIG_BT_HCIBTUSB_BCM=y +# CONFIG_BT_HCIBTUSB_MTK is not set CONFIG_BT_HCIBTUSB_RTL=y CONFIG_BT_HCIBTSDIO=y CONFIG_BT_HCIUART=y +CONFIG_BT_HCIUART_SERDEV=y CONFIG_BT_HCIUART_H4=y +# CONFIG_BT_HCIUART_NOKIA is not set CONFIG_BT_HCIUART_BCSP=y CONFIG_BT_HCIUART_ATH3K=y +CONFIG_BT_HCIUART_LL=y CONFIG_BT_HCIUART_3WIRE=y CONFIG_BT_HCIUART_INTEL=y +# CONFIG_BT_HCIUART_BCM is not set +# CONFIG_BT_HCIUART_RTL is not set CONFIG_BT_HCIUART_QCA=y # CONFIG_BT_HCIUART_AG6XX is not set # CONFIG_BT_HCIUART_MRVL is not set @@ -1051,31 +1384,32 @@ CONFIG_BT_HCIVHCI=y CONFIG_BT_MRVL=y CONFIG_BT_MRVL_SDIO=y CONFIG_BT_ATH3K=y -CONFIG_BT_WILINK=y +# CONFIG_BT_MTKSDIO is not set +# CONFIG_BT_MTKUART is not set +# end of Bluetooth device drivers + # CONFIG_AF_RXRPC is not set # CONFIG_AF_KCM is not set -# CONFIG_STREAM_PARSER is not set CONFIG_FIB_RULES=y CONFIG_WIRELESS=y CONFIG_WEXT_CORE=y CONFIG_WEXT_PROC=y -CONFIG_CFG80211=m +CONFIG_CFG80211=y CONFIG_NL80211_TESTMODE=y CONFIG_CFG80211_DEVELOPER_WARNINGS=y CONFIG_CFG80211_CERTIFICATION_ONUS=y +CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y +CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y +CONFIG_CFG80211_EXTRA_REGDB_KEYDIR="" CONFIG_CFG80211_REG_CELLULAR_HINTS=y CONFIG_CFG80211_REG_RELAX_NO_IR=y -CONFIG_CFG80211_DEFAULT_PS=y +# CONFIG_CFG80211_DEFAULT_PS is not set CONFIG_CFG80211_DEBUGFS=y -# CONFIG_CFG80211_INTERNAL_REGDB is not set CONFIG_CFG80211_CRDA_SUPPORT=y CONFIG_CFG80211_WEXT=y -# CONFIG_LIB80211 is not set -CONFIG_MAC80211=m +CONFIG_MAC80211=y CONFIG_MAC80211_HAS_RC=y CONFIG_MAC80211_RC_MINSTREL=y -CONFIG_MAC80211_RC_MINSTREL_HT=y -CONFIG_MAC80211_RC_MINSTREL_VHT=y CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y CONFIG_MAC80211_RC_DEFAULT="minstrel_ht" CONFIG_MAC80211_MESH=y @@ -1106,6 +1440,7 @@ CONFIG_RFKILL_LEDS=y CONFIG_RFKILL_INPUT=y CONFIG_RFKILL_GPIO=y CONFIG_NET_9P=y +# CONFIG_NET_9P_VIRTIO is not set # CONFIG_NET_9P_DEBUG is not set # CONFIG_CAIF is not set # CONFIG_CEPH_LIB is not set @@ -1115,29 +1450,116 @@ CONFIG_NET_9P=y # CONFIG_LWTUNNEL is not set CONFIG_DST_CACHE=y CONFIG_GRO_CELLS=y -# CONFIG_NET_DEVLINK is not set -CONFIG_MAY_USE_DEVLINK=y +CONFIG_NET_DEVLINK=y +# CONFIG_FAILOVER is not set +CONFIG_ETHTOOL_NETLINK=y CONFIG_HAVE_EBPF_JIT=y # # Device Drivers # CONFIG_ARM_AMBA=y +CONFIG_HAVE_PCI=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +CONFIG_PCI_SYSCALL=y +# CONFIG_PCIEPORTBUS is not set +CONFIG_PCIEASPM=y +CONFIG_PCIEASPM_DEFAULT=y +# CONFIG_PCIEASPM_POWERSAVE is not set +# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set +# CONFIG_PCIEASPM_PERFORMANCE is not set +# CONFIG_PCIE_PTM is not set +CONFIG_PCI_MSI=y +CONFIG_PCI_MSI_IRQ_DOMAIN=y +CONFIG_PCI_QUIRKS=y +# CONFIG_PCI_DEBUG is not set +# CONFIG_PCI_STUB is not set +# CONFIG_PCI_IOV is not set +# CONFIG_PCI_PRI is not set +# CONFIG_PCI_PASID is not set +# CONFIG_PCIE_BUS_TUNE_OFF is not set +CONFIG_PCIE_BUS_DEFAULT=y +# CONFIG_PCIE_BUS_SAFE is not set +# CONFIG_PCIE_BUS_PERFORMANCE is not set +# CONFIG_PCIE_BUS_PEER2PEER is not set +# CONFIG_HOTPLUG_PCI is not set + +# +# PCI controller drivers +# +CONFIG_PCIE_XILINX_NWL=y +# CONFIG_PCI_FTPCI100 is not set +# CONFIG_PCI_HOST_GENERIC is not set +# CONFIG_PCIE_XILINX is not set +# CONFIG_PCIE_XILINX_CPM is not set +# CONFIG_PCIE_XDMA_PL is not set +# CONFIG_PCI_XGENE is not set +# CONFIG_PCIE_ALTERA is not set +# CONFIG_PCI_HOST_THUNDER_PEM is not set +# CONFIG_PCI_HOST_THUNDER_ECAM is not set + +# +# DesignWare PCI Core Support +# +# CONFIG_PCIE_DW_PLAT_HOST is not set +# CONFIG_PCI_HISI is not set +# CONFIG_PCIE_KIRIN is not set +# CONFIG_PCI_MESON is not set +# CONFIG_PCIE_AL is not set +# end of DesignWare PCI Core Support + +# +# Mobiveil PCIe Core Support +# +# CONFIG_PCIE_MOBIVEIL_PLAT is not set +# CONFIG_PCIE_LAYERSCAPE_GEN4 is not set +# end of Mobiveil PCIe Core Support + +# +# Cadence PCIe controllers support +# +# CONFIG_PCIE_CADENCE_PLAT_HOST is not set +# CONFIG_PCI_J721E_HOST is not set +# end of Cadence PCIe controllers support +# end of PCI controller drivers + +# +# PCI Endpoint +# +# CONFIG_PCI_ENDPOINT is not set +# end of PCI Endpoint + +# +# PCI switch controller drivers +# +# CONFIG_PCI_SW_SWITCHTEC is not set +# end of PCI switch controller drivers + +# CONFIG_PCCARD is not set +# CONFIG_RAPIDIO is not set # # Generic Driver Options # -CONFIG_UEVENT_HELPER=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_UEVENT_HELPER is not set CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y + +# +# Firmware loader +# CONFIG_FW_LOADER=y -CONFIG_FIRMWARE_IN_KERNEL=y -CONFIG_EXTRA_FIRMWARE="Mykonos_M3.bin TaliseStream.bin TaliseTDDArmFirmware.bin TaliseTxArmFirmware.bin TaliseRxArmFirmware.bin" +CONFIG_EXTRA_FIRMWARE="ad9144_fmc_ebz_ad9516.stp Mykonos_M3.bin TaliseStream.bin TaliseTDDArmFirmware.bin TaliseTxArmFirmware.bin TaliseRxArmFirmware.bin adau1761.bin Navassa_EvaluationFw.bin RxGainTable.csv RxGainTable_GainCompensated.csv ORxGainTable.csv TxAttenTable.csv Navassa_Stream.bin Navassa_CMOS_profile.json Navassa_LVDS_profile.json" CONFIG_EXTRA_FIRMWARE_DIR="./firmware" -# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set +# CONFIG_FW_LOADER_USER_HELPER is not set +# CONFIG_FW_LOADER_COMPRESS is not set +CONFIG_FW_CACHE=y +# end of Firmware loader + CONFIG_WANT_DEV_COREDUMP=y CONFIG_ALLOW_DEV_COREDUMP=y CONFIG_DEV_COREDUMP=y @@ -1145,9 +1567,9 @@ CONFIG_DEV_COREDUMP=y # CONFIG_DEBUG_DEVRES is not set # CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set # CONFIG_TEST_ASYNC_DRIVER_PROBE is not set -# CONFIG_SYS_HYPERVISOR is not set -# CONFIG_GENERIC_CPU_DEVICES is not set CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_CPU_VULNERABILITIES=y +CONFIG_SOC_BUS=y CONFIG_REGMAP=y CONFIG_REGMAP_I2C=y CONFIG_REGMAP_SPI=y @@ -1155,44 +1577,34 @@ CONFIG_REGMAP_MMIO=y CONFIG_REGMAP_IRQ=y CONFIG_DMA_SHARED_BUFFER=y # CONFIG_DMA_FENCE_TRACE is not set -CONFIG_DMA_CMA=y - -# -# Default contiguous memory area size: -# -CONFIG_CMA_SIZE_MBYTES=256 -CONFIG_CMA_SIZE_SEL_MBYTES=y -# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set -# CONFIG_CMA_SIZE_SEL_MIN is not set -# CONFIG_CMA_SIZE_SEL_MAX is not set -CONFIG_CMA_ALIGNMENT=8 CONFIG_GENERIC_ARCH_TOPOLOGY=y +# end of Generic Driver Options # # Bus devices # -CONFIG_ARM_CCI=y -CONFIG_ARM_CCI_PMU=y -CONFIG_ARM_CCI400_COMMON=y -CONFIG_ARM_CCI400_PMU=y -# CONFIG_ARM_CCI5xx_PMU is not set -# CONFIG_ARM_CCN is not set # CONFIG_BRCMSTB_GISB_ARB is not set +# CONFIG_MOXTET is not set # CONFIG_SIMPLE_PM_BUS is not set # CONFIG_VEXPRESS_CONFIG is not set +# CONFIG_MHI_BUS is not set +# end of Bus devices + CONFIG_CONNECTOR=y CONFIG_PROC_EVENTS=y +# CONFIG_GNSS is not set CONFIG_MTD=y CONFIG_MTD_TESTS=m -# CONFIG_MTD_REDBOOT_PARTS is not set -CONFIG_MTD_CMDLINE_PARTS=y -# CONFIG_MTD_AFS_PARTS is not set -CONFIG_MTD_OF_PARTS=y -# CONFIG_MTD_AR7_PARTS is not set # # Partition parsers # +# CONFIG_MTD_AR7_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_OF_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +# end of Partition parsers # # User Modules And Translation Layers @@ -1205,7 +1617,7 @@ CONFIG_MTD_BLOCK=y # CONFIG_RFD_FTL is not set # CONFIG_SSFDC is not set # CONFIG_SM_FTL is not set -CONFIG_MTD_OOPS=y +# CONFIG_MTD_OOPS is not set # CONFIG_MTD_SWAP is not set # CONFIG_MTD_PARTITIONED_MASTER is not set @@ -1219,13 +1631,8 @@ CONFIG_MTD_GEN_PROBE=y CONFIG_MTD_MAP_BANK_WIDTH_1=y CONFIG_MTD_MAP_BANK_WIDTH_2=y CONFIG_MTD_MAP_BANK_WIDTH_4=y -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set CONFIG_MTD_CFI_I1=y CONFIG_MTD_CFI_I2=y -# CONFIG_MTD_CFI_I4 is not set -# CONFIG_MTD_CFI_I8 is not set CONFIG_MTD_CFI_INTELEXT=y # CONFIG_MTD_CFI_AMDSTD is not set # CONFIG_MTD_CFI_STAA is not set @@ -1233,15 +1640,16 @@ CONFIG_MTD_CFI_UTIL=y # CONFIG_MTD_RAM is not set # CONFIG_MTD_ROM is not set # CONFIG_MTD_ABSENT is not set +# end of RAM/ROM/Flash chip drivers # # Mapping drivers for chip access # # CONFIG_MTD_COMPLEX_MAPPINGS is not set # CONFIG_MTD_PHYSMAP is not set -# CONFIG_MTD_PHYSMAP_OF is not set # CONFIG_MTD_INTEL_VR_NOR is not set # CONFIG_MTD_PLATRAM is not set +# end of Mapping drivers for chip access # # Self-contained MTD device drivers @@ -1250,7 +1658,6 @@ CONFIG_MTD_CFI_UTIL=y CONFIG_MTD_DATAFLASH=y # CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set # CONFIG_MTD_DATAFLASH_OTP is not set -CONFIG_MTD_M25P80=y # CONFIG_MTD_MCHP23K256 is not set # CONFIG_MTD_SST25L is not set # CONFIG_MTD_SLRAM is not set @@ -1262,54 +1669,50 @@ CONFIG_MTD_M25P80=y # Disk-On-Chip Device Drivers # # CONFIG_MTD_DOCG3 is not set -CONFIG_MTD_NAND_ECC=y -# CONFIG_MTD_NAND_ECC_SMC is not set -CONFIG_MTD_NAND=y -# CONFIG_MTD_NAND_ECC_BCH is not set -# CONFIG_MTD_SM_COMMON is not set -# CONFIG_MTD_NAND_DENALI_PCI is not set -# CONFIG_MTD_NAND_DENALI_DT is not set -# CONFIG_MTD_NAND_GPIO is not set -# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set -# CONFIG_MTD_NAND_RICOH is not set -# CONFIG_MTD_NAND_DISKONCHIP is not set -# CONFIG_MTD_NAND_DOCG4 is not set -# CONFIG_MTD_NAND_CAFE is not set -# CONFIG_MTD_NAND_NANDSIM is not set -# CONFIG_MTD_NAND_BRCMNAND is not set -# CONFIG_MTD_NAND_PLATFORM is not set -CONFIG_MTD_NAND_ARASAN=y +# end of Self-contained MTD device drivers + +# +# NAND +# # CONFIG_MTD_ONENAND is not set +# CONFIG_MTD_RAW_NAND is not set +# CONFIG_MTD_SPI_NAND is not set + +# +# ECC engine support +# +# end of ECC engine support +# end of NAND # # LPDDR & LPDDR2 PCM memory drivers # # CONFIG_MTD_LPDDR is not set +# end of LPDDR & LPDDR2 PCM memory drivers + CONFIG_MTD_SPI_NOR=y -# CONFIG_MTD_MT81xx_NOR is not set CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y # CONFIG_MTD_UBI is not set +# CONFIG_MTD_HYPERBUS is not set CONFIG_DTC=y CONFIG_OF=y # CONFIG_OF_UNITTEST is not set CONFIG_OF_FLATTREE=y CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_KOBJ=y +CONFIG_OF_DYNAMIC=y CONFIG_OF_ADDRESS=y -CONFIG_OF_ADDRESS_PCI=y CONFIG_OF_IRQ=y CONFIG_OF_NET=y -CONFIG_OF_MDIO=y -CONFIG_OF_PCI=y -CONFIG_OF_PCI_IRQ=y CONFIG_OF_RESERVED_MEM=y -# CONFIG_OF_OVERLAY is not set +CONFIG_OF_RESOLVE=y +CONFIG_OF_OVERLAY=y +CONFIG_OF_CONFIGFS=y # CONFIG_PARPORT is not set CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_NULL_BLK is not set # CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set -# CONFIG_BLK_DEV_DAC960 is not set # CONFIG_BLK_DEV_UMEM is not set -# CONFIG_BLK_DEV_COW_COMMON is not set CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 # CONFIG_BLK_DEV_CRYPTOLOOP is not set @@ -1322,20 +1725,27 @@ CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=65536 # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set +# CONFIG_VIRTIO_BLK is not set # CONFIG_BLK_DEV_RBD is not set # CONFIG_BLK_DEV_RSXX is not set + +# +# NVME Support +# # CONFIG_BLK_DEV_NVME is not set # CONFIG_NVME_FC is not set # CONFIG_NVME_TARGET is not set +# end of NVME Support # # Misc devices # -# CONFIG_SENSORS_LIS3LV02D is not set -# CONFIG_AD525X_DPOT is not set +CONFIG_AD525X_DPOT=y +CONFIG_AD525X_DPOT_I2C=y +CONFIG_AD525X_DPOT_SPI=y +CONFIG_ADI_AXI_DATA_OFFLOAD=y # CONFIG_DUMMY_IRQ is not set # CONFIG_PHANTOM is not set -# CONFIG_SGI_IOC4 is not set # CONFIG_TIFM_CORE is not set # CONFIG_ICS932S401 is not set # CONFIG_ENCLOSURE_SERVICES is not set @@ -1348,13 +1758,15 @@ CONFIG_BLK_DEV_RAM_SIZE=65536 # CONFIG_SENSORS_APDS990X is not set # CONFIG_HMC6352 is not set # CONFIG_DS1682 is not set -# CONFIG_TI_DAC7512 is not set -# CONFIG_USB_SWITCH_FSA9480 is not set # CONFIG_LATTICE_ECP3_CONFIG is not set # CONFIG_SRAM is not set # CONFIG_PCI_ENDPOINT_TEST is not set -# CONFIG_XILINX_SDFEC is not set +CONFIG_XILINX_SDFEC=y +# CONFIG_XILINX_FLEX_PM is not set # CONFIG_XILINX_TRAFGEN is not set +# CONFIG_XILINX_AIE is not set +# CONFIG_PVPANIC is not set +# CONFIG_HISI_HIKEY_USB is not set CONFIG_XILINX_JESD204B=y CONFIG_XILINX_JESD204B_PHY=y # CONFIG_C2PORT is not set @@ -1369,66 +1781,40 @@ CONFIG_EEPROM_AT25=y # CONFIG_EEPROM_93CX6 is not set # CONFIG_EEPROM_93XX46 is not set # CONFIG_EEPROM_IDT_89HPESX is not set +# CONFIG_EEPROM_EE1004 is not set +# end of EEPROM support + # CONFIG_CB710_CORE is not set # # Texas Instruments shared transport line discipline # CONFIG_TI_ST=y +# end of Texas Instruments shared transport line discipline + # CONFIG_SENSORS_LIS3_SPI is not set # CONFIG_SENSORS_LIS3_I2C is not set - -# -# Altera FPGA firmware download module -# # CONFIG_ALTERA_STAPL is not set # # MathWorks IP Drivers # -CONFIG_MATHWORKS_IP_CORE=m -CONFIG_MWIPCORE=m -CONFIG_MWIPCORE_DMA_STREAMING=m -CONFIG_MWIPCORE_IIO_STREAMING=m -CONFIG_MATHWORKS_GENERIC_OF=m -CONFIG_MATHWORKS_GENERIC_PCI=m +CONFIG_MATHWORKS_IP_CORE=y +CONFIG_MWIPCORE=y +CONFIG_MWIPCORE_DMA_STREAMING=y +CONFIG_MWIPCORE_IIO_STREAMING=y +CONFIG_MATHWORKS_GENERIC_OF=y +# CONFIG_MATHWORKS_GENERIC_PCI is not set +# end of MathWorks IP Drivers -# -# Intel MIC Bus Driver -# - -# -# SCIF Bus Driver -# - -# -# VOP Bus Driver -# - -# -# Intel MIC Host Driver -# - -# -# Intel MIC Card Driver -# - -# -# SCIF Driver -# - -# -# Intel MIC Coprocessor State Management (COSM) Drivers -# - -# -# VOP Driver -# # CONFIG_GENWQE is not set # CONFIG_ECHO is not set -# CONFIG_CXL_BASE is not set -# CONFIG_CXL_AFU_DRIVER_OPS is not set -# CONFIG_CXL_LIB is not set +# CONFIG_MISC_ALCOR_PCI is not set +# CONFIG_MISC_RTSX_PCI is not set +# CONFIG_MISC_RTSX_USB is not set +# CONFIG_HABANA_AI is not set +# CONFIG_UACCE is not set +# end of Misc devices # # SCSI device support @@ -1437,8 +1823,6 @@ CONFIG_SCSI_MOD=y # CONFIG_RAID_ATTRS is not set CONFIG_SCSI=y CONFIG_SCSI_DMA=y -# CONFIG_SCSI_NETLINK is not set -# CONFIG_SCSI_MQ_DEFAULT is not set CONFIG_SCSI_PROC_FS=y # @@ -1446,7 +1830,6 @@ CONFIG_SCSI_PROC_FS=y # CONFIG_BLK_DEV_SD=y # CONFIG_CHR_DEV_ST is not set -# CONFIG_CHR_DEV_OSST is not set # CONFIG_BLK_DEV_SR is not set # CONFIG_CHR_DEV_SG is not set # CONFIG_CHR_DEV_SCH is not set @@ -1463,6 +1846,8 @@ CONFIG_BLK_DEV_SD=y # CONFIG_SCSI_SAS_ATTRS is not set # CONFIG_SCSI_SAS_LIBSAS is not set # CONFIG_SCSI_SRP_ATTRS is not set +# end of SCSI Transports + CONFIG_SCSI_LOWLEVEL=y # CONFIG_ISCSI_TCP is not set # CONFIG_ISCSI_BOOT_SYSFS is not set @@ -1493,9 +1878,12 @@ CONFIG_SCSI_LOWLEVEL=y # CONFIG_SCSI_SMARTPQI is not set # CONFIG_SCSI_UFSHCD is not set # CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_MYRB is not set +# CONFIG_SCSI_MYRS is not set # CONFIG_SCSI_SNIC is not set # CONFIG_SCSI_DMX3191D is not set -# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_FDOMAIN_PCI is not set +# CONFIG_SCSI_GDTH is not set # CONFIG_SCSI_IPS is not set # CONFIG_SCSI_INITIO is not set # CONFIG_SCSI_INIA100 is not set @@ -1510,13 +1898,15 @@ CONFIG_SCSI_LOWLEVEL=y # CONFIG_SCSI_DEBUG is not set # CONFIG_SCSI_PMCRAID is not set # CONFIG_SCSI_PM8001 is not set -# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set +# CONFIG_SCSI_VIRTIO is not set # CONFIG_SCSI_DH is not set -# CONFIG_SCSI_OSD_INITIATOR is not set +# end of SCSI device support + CONFIG_HAVE_PATA_PLATFORM=y CONFIG_ATA=y -# CONFIG_ATA_NONSTANDARD is not set +CONFIG_SATA_HOST=y CONFIG_ATA_VERBOSE_ERROR=y +CONFIG_ATA_FORCE=y CONFIG_SATA_PMP=y # @@ -1539,33 +1929,55 @@ CONFIG_AHCI_CEVA=y # # CONFIG_FIREWIRE is not set # CONFIG_FIREWIRE_NOSY is not set +# end of IEEE 1394 (FireWire) support + CONFIG_NETDEVICES=y CONFIG_MII=y CONFIG_NET_CORE=y # CONFIG_BONDING is not set # CONFIG_DUMMY is not set +# CONFIG_WIREGUARD is not set # CONFIG_EQUALIZER is not set # CONFIG_NET_FC is not set # CONFIG_NET_TEAM is not set # CONFIG_MACVLAN is not set +# CONFIG_IPVLAN is not set # CONFIG_VXLAN is not set +# CONFIG_GENEVE is not set +# CONFIG_BAREUDP is not set +# CONFIG_GTP is not set # CONFIG_MACSEC is not set # CONFIG_NETCONSOLE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set CONFIG_TUN=y # CONFIG_TUN_VNET_CROSS_LE is not set # CONFIG_VETH is not set +# CONFIG_VIRTIO_NET is not set # CONFIG_NLMON is not set # CONFIG_ARCNET is not set -# -# CAIF transport drivers -# - # # Distributed Switch Architecture drivers # +# CONFIG_B53 is not set +# CONFIG_NET_DSA_BCM_SF2 is not set +# CONFIG_NET_DSA_LOOP is not set +# CONFIG_NET_DSA_LANTIQ_GSWIP is not set +# CONFIG_NET_DSA_MT7530 is not set +# CONFIG_NET_DSA_MV88E6060 is not set +# CONFIG_NET_DSA_MICROCHIP_KSZ9477 is not set +# CONFIG_NET_DSA_MICROCHIP_KSZ8795 is not set +# CONFIG_NET_DSA_MV88E6XXX is not set +# CONFIG_NET_DSA_MSCC_SEVILLE is not set +# CONFIG_NET_DSA_AR9331 is not set +# CONFIG_NET_DSA_SJA1105 is not set +# CONFIG_NET_DSA_QCA8K is not set +# CONFIG_NET_DSA_REALTEK_SMI is not set +# CONFIG_NET_DSA_SMSC_LAN9303_I2C is not set +# CONFIG_NET_DSA_SMSC_LAN9303_MDIO is not set +# CONFIG_NET_DSA_VITESSE_VSC73XX_SPI is not set +# CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM is not set +# end of Distributed Switch Architecture drivers + CONFIG_ETHERNET=y CONFIG_NET_VENDOR_3COM=y # CONFIG_VORTEX is not set @@ -1580,12 +1992,13 @@ CONFIG_NET_VENDOR_ALTEON=y # CONFIG_ACENIC is not set # CONFIG_ALTERA_TSE is not set CONFIG_NET_VENDOR_AMAZON=y +# CONFIG_ENA_ETHERNET is not set CONFIG_NET_VENDOR_AMD=y # CONFIG_AMD8111_ETH is not set # CONFIG_PCNET32 is not set # CONFIG_AMD_XGBE is not set -# CONFIG_AMD_XGBE_HAVE_ECC is not set CONFIG_NET_VENDOR_AQUANTIA=y +# CONFIG_AQTION is not set CONFIG_NET_VENDOR_ARC=y CONFIG_NET_VENDOR_ATHEROS=y # CONFIG_ATL2 is not set @@ -1593,11 +2006,8 @@ CONFIG_NET_VENDOR_ATHEROS=y # CONFIG_ATL1E is not set # CONFIG_ATL1C is not set # CONFIG_ALX is not set -# CONFIG_NET_VENDOR_AURORA is not set -CONFIG_NET_CADENCE=y -CONFIG_MACB=y -CONFIG_MACB_USE_HWSTAMP=y -# CONFIG_MACB_PCI is not set +CONFIG_NET_VENDOR_AURORA=y +# CONFIG_AURORA_NB8800 is not set CONFIG_NET_VENDOR_BROADCOM=y # CONFIG_B44 is not set # CONFIG_BCMGENET is not set @@ -1609,11 +2019,16 @@ CONFIG_NET_VENDOR_BROADCOM=y # CONFIG_BNXT is not set CONFIG_NET_VENDOR_BROCADE=y # CONFIG_BNA is not set +CONFIG_NET_VENDOR_CADENCE=y +CONFIG_MACB=y +CONFIG_MACB_USE_HWSTAMP=y +# CONFIG_MACB_PCI is not set CONFIG_NET_VENDOR_CAVIUM=y # CONFIG_THUNDER_NIC_PF is not set # CONFIG_THUNDER_NIC_VF is not set # CONFIG_THUNDER_NIC_BGX is not set # CONFIG_THUNDER_NIC_RGX is not set +# CONFIG_CAVIUM_PTP is not set # CONFIG_LIQUIDIO is not set # CONFIG_LIQUIDIO_VF is not set CONFIG_NET_VENDOR_CHELSIO=y @@ -1623,6 +2038,8 @@ CONFIG_NET_VENDOR_CHELSIO=y # CONFIG_CHELSIO_T4VF is not set CONFIG_NET_VENDOR_CISCO=y # CONFIG_ENIC is not set +CONFIG_NET_VENDOR_CORTINA=y +# CONFIG_GEMINI_ETHERNET is not set # CONFIG_DNET is not set CONFIG_NET_VENDOR_DEC=y # CONFIG_NET_TULIP is not set @@ -1633,20 +2050,18 @@ CONFIG_NET_VENDOR_EMULEX=y # CONFIG_BE2NET is not set CONFIG_NET_VENDOR_EZCHIP=y # CONFIG_EZCHIP_NPS_MANAGEMENT_ENET is not set -CONFIG_NET_VENDOR_EXAR=y -# CONFIG_S2IO is not set -# CONFIG_VXGE is not set +CONFIG_NET_VENDOR_GOOGLE=y +# CONFIG_GVE is not set CONFIG_NET_VENDOR_HISILICON=y # CONFIG_HIX5HD2_GMAC is not set # CONFIG_HISI_FEMAC is not set # CONFIG_HIP04_ETH is not set -# CONFIG_HNS is not set # CONFIG_HNS_DSAF is not set # CONFIG_HNS_ENET is not set # CONFIG_HNS3 is not set -CONFIG_NET_VENDOR_HP=y -# CONFIG_HP100 is not set CONFIG_NET_VENDOR_HUAWEI=y +# CONFIG_HINIC is not set +CONFIG_NET_VENDOR_I825XX=y CONFIG_NET_VENDOR_INTEL=y # CONFIG_E100 is not set # CONFIG_E1000 is not set @@ -1658,16 +2073,21 @@ CONFIG_NET_VENDOR_INTEL=y # CONFIG_IXGBEVF is not set # CONFIG_I40E is not set # CONFIG_I40EVF is not set +# CONFIG_ICE is not set # CONFIG_FM10K is not set -CONFIG_NET_VENDOR_I825XX=y +# CONFIG_IGC is not set # CONFIG_JME is not set +CONFIG_NET_VENDOR_ADI=y +CONFIG_ADIN1110=y CONFIG_NET_VENDOR_MARVELL=y # CONFIG_MVMDIO is not set # CONFIG_SKGE is not set # CONFIG_SKY2 is not set +# CONFIG_OCTEONTX2_AF is not set +# CONFIG_OCTEONTX2_PF is not set +# CONFIG_PRESTERA is not set CONFIG_NET_VENDOR_MELLANOX=y # CONFIG_MLX4_EN is not set -# CONFIG_MLX4_CORE is not set # CONFIG_MLX5_CORE is not set # CONFIG_MLXSW_CORE is not set # CONFIG_MLXFW is not set @@ -1679,57 +2099,69 @@ CONFIG_NET_VENDOR_MICREL=y CONFIG_NET_VENDOR_MICROCHIP=y # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set +# CONFIG_LAN743X is not set +CONFIG_NET_VENDOR_MICROSEMI=y +# CONFIG_MSCC_OCELOT_SWITCH is not set CONFIG_NET_VENDOR_MYRI=y # CONFIG_MYRI10GE is not set # CONFIG_FEALNX is not set CONFIG_NET_VENDOR_NATSEMI=y # CONFIG_NATSEMI is not set # CONFIG_NS83820 is not set +CONFIG_NET_VENDOR_NETERION=y +# CONFIG_S2IO is not set +# CONFIG_VXGE is not set CONFIG_NET_VENDOR_NETRONOME=y # CONFIG_NFP is not set +CONFIG_NET_VENDOR_NI=y +# CONFIG_NI_XGE_MANAGEMENT_ENET is not set CONFIG_NET_VENDOR_8390=y # CONFIG_NE2K_PCI is not set CONFIG_NET_VENDOR_NVIDIA=y # CONFIG_FORCEDETH is not set CONFIG_NET_VENDOR_OKI=y # CONFIG_ETHOC is not set -CONFIG_NET_PACKET_ENGINE=y +CONFIG_NET_VENDOR_PACKET_ENGINES=y # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set +CONFIG_NET_VENDOR_PENSANDO=y +# CONFIG_IONIC is not set CONFIG_NET_VENDOR_QLOGIC=y # CONFIG_QLA3XXX is not set # CONFIG_QLCNIC is not set -# CONFIG_QLGE is not set # CONFIG_NETXEN_NIC is not set # CONFIG_QED is not set CONFIG_NET_VENDOR_QUALCOMM=y # CONFIG_QCA7000_SPI is not set +# CONFIG_QCA7000_UART is not set # CONFIG_QCOM_EMAC is not set # CONFIG_RMNET is not set +CONFIG_NET_VENDOR_RDC=y +# CONFIG_R6040 is not set CONFIG_NET_VENDOR_REALTEK=y # CONFIG_8139CP is not set # CONFIG_8139TOO is not set # CONFIG_R8169 is not set CONFIG_NET_VENDOR_RENESAS=y -CONFIG_NET_VENDOR_RDC=y -# CONFIG_R6040 is not set CONFIG_NET_VENDOR_ROCKER=y +# CONFIG_ROCKER is not set CONFIG_NET_VENDOR_SAMSUNG=y # CONFIG_SXGBE_ETH is not set CONFIG_NET_VENDOR_SEEQ=y +CONFIG_NET_VENDOR_SOLARFLARE=y +# CONFIG_SFC is not set +# CONFIG_SFC_FALCON is not set CONFIG_NET_VENDOR_SILAN=y # CONFIG_SC92031 is not set CONFIG_NET_VENDOR_SIS=y # CONFIG_SIS900 is not set # CONFIG_SIS190 is not set -CONFIG_NET_VENDOR_SOLARFLARE=y -# CONFIG_SFC is not set -# CONFIG_SFC_FALCON is not set CONFIG_NET_VENDOR_SMSC=y # CONFIG_SMC91X is not set # CONFIG_EPIC100 is not set # CONFIG_SMSC911X is not set # CONFIG_SMSC9420 is not set +CONFIG_NET_VENDOR_SOCIONEXT=y CONFIG_NET_VENDOR_STMICRO=y # CONFIG_STMMAC_ETH is not set CONFIG_NET_VENDOR_SUN=y @@ -1737,10 +2169,12 @@ CONFIG_NET_VENDOR_SUN=y # CONFIG_SUNGEM is not set # CONFIG_CASSINI is not set # CONFIG_NIU is not set +CONFIG_NET_VENDOR_SYNOPSYS=y +# CONFIG_DWC_XLGMAC is not set CONFIG_NET_VENDOR_TEHUTI=y # CONFIG_TEHUTI is not set CONFIG_NET_VENDOR_TI=y -# CONFIG_TI_CPSW_ALE is not set +# CONFIG_TI_CPSW_PHY_SEL is not set # CONFIG_TLAN is not set CONFIG_NET_VENDOR_VIA=y # CONFIG_VIA_RHINE is not set @@ -1753,61 +2187,89 @@ CONFIG_XILINX_EMACLITE=y CONFIG_XILINX_AXI_EMAC=y # CONFIG_XILINX_AXI_EMAC_HWTSTAMP is not set # CONFIG_AXIENET_HAS_MCDMA is not set +# CONFIG_XILINX_LL_TEMAC is not set # CONFIG_XILINX_TSN is not set -CONFIG_NET_VENDOR_SYNOPSYS=y -# CONFIG_DWC_XLGMAC is not set # CONFIG_FDDI is not set # CONFIG_HIPPI is not set -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_BUS=y -# CONFIG_MDIO_BCM_UNIMAC is not set -# CONFIG_MDIO_BITBANG is not set -# CONFIG_MDIO_BUS_MUX_GPIO is not set -# CONFIG_MDIO_BUS_MUX_MMIOREG is not set -# CONFIG_MDIO_HISI_FEMAC is not set -# CONFIG_MDIO_OCTEON is not set -# CONFIG_MDIO_THUNDER is not set +CONFIG_PHYLINK=y CONFIG_PHYLIB=y CONFIG_SWPHY=y # CONFIG_LED_TRIGGER_PHY is not set +CONFIG_FIXED_PHY=y +# CONFIG_SFP is not set # # MII PHY device drivers # -CONFIG_ADIN_PHY=y CONFIG_AMD_PHY=y +CONFIG_ADIN_PHY=y +CONFIG_ADIN1100_PHY=y # CONFIG_AQUANTIA_PHY is not set -CONFIG_AT803X_PHY=y +# CONFIG_AX88796B_PHY is not set +CONFIG_BROADCOM_PHY=y +# CONFIG_BCM54140_PHY is not set CONFIG_BCM7XXX_PHY=y +# CONFIG_BCM84881_PHY is not set CONFIG_BCM87XX_PHY=y CONFIG_BCM_NET_PHYLIB=y -CONFIG_BROADCOM_PHY=y CONFIG_CICADA_PHY=y # CONFIG_CORTINA_PHY is not set CONFIG_DAVICOM_PHY=y -# CONFIG_DP83848_PHY is not set -CONFIG_DP83867_PHY=y -CONFIG_FIXED_PHY=y CONFIG_ICPLUS_PHY=y +CONFIG_LXT_PHY=y # CONFIG_INTEL_XWAY_PHY is not set CONFIG_LSI_ET1011C_PHY=y -CONFIG_LXT_PHY=y CONFIG_MARVELL_PHY=y # CONFIG_MARVELL_10G_PHY is not set CONFIG_MICREL_PHY=y # CONFIG_MICROCHIP_PHY is not set +# CONFIG_MICROCHIP_T1_PHY is not set # CONFIG_MICROSEMI_PHY is not set CONFIG_NATIONAL_PHY=y +# CONFIG_NXP_TJA11XX_PHY is not set +CONFIG_AT803X_PHY=y CONFIG_QSEMI_PHY=y CONFIG_REALTEK_PHY=y +# CONFIG_RENESAS_PHY is not set # CONFIG_ROCKCHIP_PHY is not set CONFIG_SMSC_PHY=y CONFIG_STE10XP=y # CONFIG_TERANETICS_PHY is not set +# CONFIG_DP83822_PHY is not set +# CONFIG_DP83TC811_PHY is not set +# CONFIG_DP83848_PHY is not set +CONFIG_DP83867_PHY=y +# CONFIG_DP83869_PHY is not set CONFIG_VITESSE_PHY=y # CONFIG_XILINX_PHY is not set CONFIG_XILINX_GMII2RGMII=y # CONFIG_MICREL_KS8995MA is not set +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_BUS=y +CONFIG_OF_MDIO=y +CONFIG_MDIO_DEVRES=y +# CONFIG_MDIO_BITBANG is not set +# CONFIG_MDIO_BCM_UNIMAC is not set +# CONFIG_MDIO_HISI_FEMAC is not set +# CONFIG_MDIO_MVUSB is not set +# CONFIG_MDIO_MSCC_MIIM is not set +# CONFIG_MDIO_OCTEON is not set +# CONFIG_MDIO_IPQ4019 is not set +# CONFIG_MDIO_THUNDER is not set + +# +# MDIO Multiplexers +# +# CONFIG_MDIO_BUS_MUX_GPIO is not set +# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set +# CONFIG_MDIO_BUS_MUX_MMIOREG is not set + +# +# PCS device drivers +# +# CONFIG_PCS_XPCS is not set +# end of PCS device drivers + # CONFIG_PPP is not set # CONFIG_SLIP is not set CONFIG_USB_NET_DRIVERS=y @@ -1853,6 +2315,7 @@ CONFIG_USB_NET_ZAURUS=y # CONFIG_USB_SIERRA_NET is not set # CONFIG_USB_VL600 is not set # CONFIG_USB_NET_CH9200 is not set +# CONFIG_USB_NET_AQC111 is not set CONFIG_WLAN=y # CONFIG_WIRELESS_WDS is not set CONFIG_WLAN_VENDOR_ADMTEK=y @@ -1897,12 +2360,24 @@ CONFIG_WLAN_VENDOR_MARVELL=y # CONFIG_MWL8K is not set CONFIG_WLAN_VENDOR_MEDIATEK=y # CONFIG_MT7601U is not set +# CONFIG_MT76x0U is not set +# CONFIG_MT76x0E is not set +# CONFIG_MT76x2E is not set +# CONFIG_MT76x2U is not set +# CONFIG_MT7603E is not set +# CONFIG_MT7615E is not set +# CONFIG_MT7663U is not set +# CONFIG_MT7663S is not set +# CONFIG_MT7915E is not set +CONFIG_WLAN_VENDOR_MICROCHIP=y +# CONFIG_WILC1000_SDIO is not set +# CONFIG_WILC1000_SPI is not set CONFIG_WLAN_VENDOR_RALINK=y # CONFIG_RT2X00 is not set CONFIG_WLAN_VENDOR_REALTEK=y # CONFIG_RTL8180 is not set # CONFIG_RTL8187 is not set -CONFIG_RTL_CARDS=m +CONFIG_RTL_CARDS=y # CONFIG_RTL8192CE is not set # CONFIG_RTL8192SE is not set # CONFIG_RTL8192DE is not set @@ -1913,6 +2388,7 @@ CONFIG_RTL_CARDS=m # CONFIG_RTL8821AE is not set # CONFIG_RTL8192CU is not set # CONFIG_RTL8XXXU is not set +# CONFIG_RTW88 is not set CONFIG_WLAN_VENDOR_RSI=y # CONFIG_RSI_91X is not set CONFIG_WLAN_VENDOR_ST=y @@ -1920,24 +2396,37 @@ CONFIG_WLAN_VENDOR_ST=y CONFIG_WLAN_VENDOR_TI=y # CONFIG_WL1251 is not set # CONFIG_WL12XX is not set -CONFIG_WL18XX=m -CONFIG_WLCORE=m -CONFIG_WLCORE_SPI=m -CONFIG_WLCORE_SDIO=m +CONFIG_WL18XX=y +CONFIG_WLCORE=y +CONFIG_WLCORE_SPI=y +CONFIG_WLCORE_SDIO=y CONFIG_WILINK_PLATFORM_DATA=y CONFIG_WLAN_VENDOR_ZYDAS=y # CONFIG_USB_ZD1201 is not set # CONFIG_ZD1211RW is not set CONFIG_WLAN_VENDOR_QUANTENNA=y -# CONFIG_QTNFMAC_PEARL_PCIE is not set +# CONFIG_QTNFMAC_PCIE is not set # CONFIG_MAC80211_HWSIM is not set # CONFIG_USB_NET_RNDIS_WLAN is not set +# CONFIG_VIRT_WIFI is not set # # Enable WiMAX (Networking options) to see the WiMAX drivers # # CONFIG_WAN is not set +CONFIG_IEEE802154_DRIVERS=y +# CONFIG_IEEE802154_FAKELB is not set +# CONFIG_IEEE802154_AT86RF230 is not set +# CONFIG_IEEE802154_MRF24J40 is not set +# CONFIG_IEEE802154_CC2520 is not set +# CONFIG_IEEE802154_ATUSB is not set +CONFIG_IEEE802154_ADF7242=y +# CONFIG_IEEE802154_CA8210 is not set +# CONFIG_IEEE802154_MCR20A is not set +# CONFIG_IEEE802154_HWSIM is not set # CONFIG_VMXNET3 is not set +# CONFIG_NETDEVSIM is not set +# CONFIG_NET_FAILOVER is not set # CONFIG_ISDN is not set # CONFIG_NVM is not set @@ -1947,7 +2436,7 @@ CONFIG_WLAN_VENDOR_QUANTENNA=y CONFIG_INPUT=y CONFIG_INPUT_LEDS=y # CONFIG_INPUT_FF_MEMLESS is not set -CONFIG_INPUT_POLLDEV=y +# CONFIG_INPUT_POLLDEV is not set # CONFIG_INPUT_SPARSEKMAP is not set # CONFIG_INPUT_MATRIXKMAP is not set @@ -1964,9 +2453,11 @@ CONFIG_INPUT_EVDEV=y # CONFIG_INPUT_KEYBOARD=y # CONFIG_KEYBOARD_ADC is not set -# CONFIG_KEYBOARD_ADP5588 is not set -# CONFIG_KEYBOARD_ADP5589 is not set +CONFIG_KEYBOARD_ADP5520=y +CONFIG_KEYBOARD_ADP5588=y +CONFIG_KEYBOARD_ADP5589=y CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_QT1050 is not set # CONFIG_KEYBOARD_QT1070 is not set # CONFIG_KEYBOARD_QT2160 is not set # CONFIG_KEYBOARD_DLINK_DIR685 is not set @@ -2016,8 +2507,105 @@ CONFIG_MOUSE_PS2_SMBUS=y # CONFIG_MOUSE_SYNAPTICS_USB is not set # CONFIG_INPUT_JOYSTICK is not set # CONFIG_INPUT_TABLET is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_PROPERTIES=y +CONFIG_TOUCHSCREEN_ADS7846=y +CONFIG_TOUCHSCREEN_AD7877=y +CONFIG_TOUCHSCREEN_AD7879=y +CONFIG_TOUCHSCREEN_AD7879_I2C=y +CONFIG_TOUCHSCREEN_AD7879_SPI=y +# CONFIG_TOUCHSCREEN_ADC is not set +# CONFIG_TOUCHSCREEN_AR1021_I2C is not set +# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set +# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set +# CONFIG_TOUCHSCREEN_BU21013 is not set +# CONFIG_TOUCHSCREEN_BU21029 is not set +# CONFIG_TOUCHSCREEN_CHIPONE_ICN8318 is not set +# CONFIG_TOUCHSCREEN_CY8CTMA140 is not set +# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set +# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set +# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set +# CONFIG_TOUCHSCREEN_DYNAPRO is not set +# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set +# CONFIG_TOUCHSCREEN_EETI is not set +# CONFIG_TOUCHSCREEN_EGALAX is not set +# CONFIG_TOUCHSCREEN_EGALAX_SERIAL is not set +# CONFIG_TOUCHSCREEN_EXC3000 is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GOODIX is not set +# CONFIG_TOUCHSCREEN_HIDEEP is not set +# CONFIG_TOUCHSCREEN_ILI210X is not set +# CONFIG_TOUCHSCREEN_S6SY761 is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_EKTF2127 is not set +# CONFIG_TOUCHSCREEN_ELAN is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_WACOM_I2C is not set +# CONFIG_TOUCHSCREEN_MAX11801 is not set +# CONFIG_TOUCHSCREEN_MCS5000 is not set +# CONFIG_TOUCHSCREEN_MMS114 is not set +# CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_PIXCIR is not set +# CONFIG_TOUCHSCREEN_WDT87XX_I2C is not set +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_TSC_SERIO is not set +# CONFIG_TOUCHSCREEN_TSC2004 is not set +# CONFIG_TOUCHSCREEN_TSC2005 is not set +# CONFIG_TOUCHSCREEN_TSC2007 is not set +# CONFIG_TOUCHSCREEN_RM_TS is not set +# CONFIG_TOUCHSCREEN_SILEAD is not set +# CONFIG_TOUCHSCREEN_SIS_I2C is not set +# CONFIG_TOUCHSCREEN_ST1232 is not set +# CONFIG_TOUCHSCREEN_STMFTS is not set +# CONFIG_TOUCHSCREEN_SUR40 is not set +# CONFIG_TOUCHSCREEN_SURFACE3_SPI is not set +# CONFIG_TOUCHSCREEN_SX8654 is not set +# CONFIG_TOUCHSCREEN_TPS6507X is not set +# CONFIG_TOUCHSCREEN_ZET6223 is not set +# CONFIG_TOUCHSCREEN_ZFORCE is not set +# CONFIG_TOUCHSCREEN_ROHM_BU21023 is not set +# CONFIG_TOUCHSCREEN_IQS5XX is not set +# CONFIG_TOUCHSCREEN_ZINITIX is not set +CONFIG_INPUT_MISC=y +CONFIG_INPUT_AD714X=y +CONFIG_INPUT_AD714X_I2C=y +CONFIG_INPUT_AD714X_SPI=y +# CONFIG_INPUT_ATMEL_CAPTOUCH is not set +# CONFIG_INPUT_BMA150 is not set +# CONFIG_INPUT_E3X0_BUTTON is not set +# CONFIG_INPUT_MMA8450 is not set +# CONFIG_INPUT_GPIO_BEEPER is not set +# CONFIG_INPUT_GPIO_DECODER is not set +# CONFIG_INPUT_GPIO_VIBRA is not set +# CONFIG_INPUT_ATI_REMOTE2 is not set +# CONFIG_INPUT_KEYSPAN_REMOTE is not set +# CONFIG_INPUT_KXTJ9 is not set +# CONFIG_INPUT_POWERMATE is not set +# CONFIG_INPUT_YEALINK is not set +# CONFIG_INPUT_CM109 is not set +# CONFIG_INPUT_REGULATOR_HAPTIC is not set +# CONFIG_INPUT_UINPUT is not set +CONFIG_INPUT_PCF8574=y +# CONFIG_INPUT_PWM_BEEPER is not set +# CONFIG_INPUT_PWM_VIBRA is not set +# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set +# CONFIG_INPUT_ADXL34X is not set +# CONFIG_INPUT_IMS_PCU is not set +# CONFIG_INPUT_IQS269A is not set +# CONFIG_INPUT_CMA3000 is not set +# CONFIG_INPUT_DRV260X_HAPTICS is not set +# CONFIG_INPUT_DRV2665_HAPTICS is not set +# CONFIG_INPUT_DRV2667_HAPTICS is not set # CONFIG_RMI4_CORE is not set # @@ -2036,6 +2624,8 @@ CONFIG_SERIO_LIBPS2=y # CONFIG_SERIO_GPIO_PS2 is not set # CONFIG_USERIO is not set # CONFIG_GAMEPORT is not set +# end of Hardware I/O ports +# end of Input device support # # Character devices @@ -2050,11 +2640,7 @@ CONFIG_VT_HW_CONSOLE_BINDING=y CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 -# CONFIG_SERIAL_NONSTANDARD is not set -# CONFIG_NOZOMI is not set -# CONFIG_N_GSM is not set -# CONFIG_TRACE_SINK is not set -CONFIG_DEVMEM=y +CONFIG_LDISC_AUTOLOAD=y # # Serial drivers @@ -2062,6 +2648,7 @@ CONFIG_DEVMEM=y CONFIG_SERIAL_EARLYCON=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y +CONFIG_SERIAL_8250_16550A_VARIANTS=y # CONFIG_SERIAL_8250_FINTEK is not set CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_DMA=y @@ -2070,11 +2657,9 @@ CONFIG_SERIAL_8250_EXAR=y CONFIG_SERIAL_8250_NR_UARTS=4 CONFIG_SERIAL_8250_RUNTIME_UARTS=4 # CONFIG_SERIAL_8250_EXTENDED is not set -# CONFIG_SERIAL_8250_ASPEED_VUART is not set CONFIG_SERIAL_8250_FSL=y # CONFIG_SERIAL_8250_DW is not set # CONFIG_SERIAL_8250_RT288X is not set -# CONFIG_SERIAL_8250_MOXA is not set CONFIG_SERIAL_OF_PLATFORM=y # @@ -2087,9 +2672,11 @@ CONFIG_SERIAL_OF_PLATFORM=y CONFIG_SERIAL_MAX310X=y CONFIG_SERIAL_UARTLITE=y CONFIG_SERIAL_UARTLITE_CONSOLE=y +CONFIG_SERIAL_UARTLITE_NR_UARTS=1 CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_SERIAL_JSM is not set +# CONFIG_SERIAL_SIFIVE is not set # CONFIG_SERIAL_SCCNXP is not set # CONFIG_SERIAL_SC16IS7XX is not set # CONFIG_SERIAL_ALTERA_JTAGUART is not set @@ -2100,23 +2687,35 @@ CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y # CONFIG_SERIAL_ARC is not set # CONFIG_SERIAL_RP2 is not set # CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_FSL_LINFLEXUART is not set # CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set -# CONFIG_SERIAL_DEV_BUS is not set -# CONFIG_TTY_PRINTK is not set +# CONFIG_SERIAL_SPRD is not set +# end of Serial drivers + +CONFIG_SERIAL_MCTRL_GPIO=y +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_N_GSM is not set +# CONFIG_NOZOMI is not set +# CONFIG_NULL_TTY is not set +# CONFIG_TRACE_SINK is not set # CONFIG_HVC_DCC is not set +CONFIG_SERIAL_DEV_BUS=y +CONFIG_SERIAL_DEV_CTRL_TTYPORT=y +# CONFIG_TTY_PRINTK is not set +# CONFIG_VIRTIO_CONSOLE is not set # CONFIG_IPMI_HANDLER is not set # CONFIG_HW_RANDOM is not set -# CONFIG_R3964 is not set # CONFIG_APPLICOM is not set - -# -# PCMCIA character devices -# +CONFIG_DEVMEM=y # CONFIG_RAW_DRIVER is not set -# CONFIG_TCG_TPM is not set CONFIG_DEVPORT=y +# CONFIG_TCG_TPM is not set # CONFIG_XILLYBUS is not set -# CONFIG_AXI_INTR_MONITOR is not set +CONFIG_AXI_INTR_MONITOR=y +# end of Character devices + +# CONFIG_RANDOM_TRUST_CPU is not set +# CONFIG_RANDOM_TRUST_BOOTLOADER is not set # # I2C support @@ -2132,14 +2731,16 @@ CONFIG_I2C_MUX=y # # CONFIG_I2C_ARB_GPIO_CHALLENGE is not set # CONFIG_I2C_MUX_GPIO is not set -# CONFIG_I2C_MUX_GPMUX is not set -# CONFIG_I2C_MUX_LTC4306 is not set +CONFIG_I2C_MUX_GPMUX=y +CONFIG_I2C_MUX_LTC4306=y CONFIG_I2C_MUX_PCA9541=y CONFIG_I2C_MUX_PCA954x=y # CONFIG_I2C_MUX_PINCTRL is not set # CONFIG_I2C_MUX_REG is not set # CONFIG_I2C_DEMUX_PINCTRL is not set # CONFIG_I2C_MUX_MLXCPLD is not set +# end of Multiplexer I2C Chip support + CONFIG_I2C_HELPER_AUTO=y CONFIG_I2C_ALGOBIT=y @@ -2159,6 +2760,7 @@ CONFIG_I2C_ALGOBIT=y # CONFIG_I2C_ISCH is not set # CONFIG_I2C_PIIX4 is not set # CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_NVIDIA_GPU is not set # CONFIG_I2C_SIS5595 is not set # CONFIG_I2C_SIS630 is not set # CONFIG_I2C_SIS96X is not set @@ -2177,7 +2779,6 @@ CONFIG_I2C_CADENCE=y # CONFIG_I2C_NOMADIK is not set # CONFIG_I2C_OCORES is not set # CONFIG_I2C_PCA_PLATFORM is not set -# CONFIG_I2C_PXA_PCI is not set # CONFIG_I2C_RK3X is not set # CONFIG_I2C_SIMTEC is not set # CONFIG_I2C_THUNDERX is not set @@ -2187,7 +2788,6 @@ CONFIG_I2C_XILINX=y # External I2C/SMBus adapter drivers # # CONFIG_I2C_DIOLAN_U2C is not set -# CONFIG_I2C_PARPORT_LIGHT is not set # CONFIG_I2C_ROBOTFUZZ_OSIF is not set # CONFIG_I2C_TAOS_EVM is not set # CONFIG_I2C_TINY_USB is not set @@ -2195,36 +2795,51 @@ CONFIG_I2C_XILINX=y # # Other I2C/SMBus bus drivers # +# end of I2C Hardware Bus support + # CONFIG_I2C_STUB is not set # CONFIG_I2C_SLAVE is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set # CONFIG_I2C_DEBUG_BUS is not set +# end of I2C support + +# CONFIG_I3C is not set CONFIG_SPI=y # CONFIG_SPI_DEBUG is not set CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y # # SPI Master Controller Drivers # # CONFIG_SPI_ALTERA is not set -# CONFIG_SPI_AXI_SPI_ENGINE is not set +CONFIG_SPI_AXI_SPI_ENGINE=y CONFIG_SPI_BITBANG=y CONFIG_SPI_CADENCE=y +# CONFIG_SPI_CADENCE_QUADSPI is not set # CONFIG_SPI_DESIGNWARE is not set +# CONFIG_SPI_NXP_FLEXSPI is not set # CONFIG_SPI_GPIO is not set # CONFIG_SPI_FSL_SPI is not set # CONFIG_SPI_OC_TINY is not set # CONFIG_SPI_PL022 is not set # CONFIG_SPI_PXA2XX is not set -# CONFIG_SPI_PXA2XX_PCI is not set # CONFIG_SPI_ROCKCHIP is not set # CONFIG_SPI_SC18IS602 is not set +# CONFIG_SPI_SIFIVE is not set +# CONFIG_SPI_MXIC is not set # CONFIG_SPI_THUNDERX is not set # CONFIG_SPI_XCOMM is not set -# CONFIG_SPI_AD9250FMC is not set +CONFIG_SPI_AD9250FMC=y CONFIG_SPI_XILINX=y CONFIG_SPI_ZYNQMP_GQSPI=y +# CONFIG_SPI_AMD is not set + +# +# SPI Multiplexer support +# +# CONFIG_SPI_MUX is not set # # SPI Protocol Masters @@ -2233,6 +2848,7 @@ CONFIG_SPI_ZYNQMP_GQSPI=y # CONFIG_SPI_LOOPBACK_TEST is not set # CONFIG_SPI_TLE62X0 is not set # CONFIG_SPI_SLAVE is not set +CONFIG_SPI_DYNAMIC=y # CONFIG_SPMI is not set # CONFIG_HSI is not set CONFIG_PPS=y @@ -2253,86 +2869,113 @@ CONFIG_PPS=y # PTP clock support # CONFIG_PTP_1588_CLOCK=y +# CONFIG_DP83640_PHY is not set +# CONFIG_PTP_1588_CLOCK_INES is not set +# CONFIG_PTP_1588_CLOCK_IDT82P33 is not set +# CONFIG_PTP_1588_CLOCK_IDTCM is not set +CONFIG_PTP_1588_CLOCK_XILINX=y +# end of PTP clock support -# -# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. -# CONFIG_PINCTRL=y - -# -# Pin controllers -# CONFIG_PINMUX=y CONFIG_PINCONF=y CONFIG_GENERIC_PINCONF=y # CONFIG_DEBUG_PINCTRL is not set -# CONFIG_PINCTRL_AMD is not set # CONFIG_PINCTRL_MCP23S08 is not set # CONFIG_PINCTRL_SINGLE is not set # CONFIG_PINCTRL_SX150X is not set +# CONFIG_PINCTRL_STMFX is not set CONFIG_PINCTRL_ZYNQMP=y +# CONFIG_PINCTRL_OCELOT is not set + +# +# Renesas pinctrl drivers +# +# end of Renesas pinctrl drivers + CONFIG_GPIOLIB=y +CONFIG_GPIOLIB_FASTPATH_LIMIT=512 CONFIG_OF_GPIO=y CONFIG_GPIOLIB_IRQCHIP=y # CONFIG_DEBUG_GPIO is not set CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_CDEV=y +CONFIG_GPIO_CDEV_V1=y # # Memory mapped GPIO drivers # # CONFIG_GPIO_74XX_MMIO is not set # CONFIG_GPIO_ALTERA is not set +# CONFIG_GPIO_CADENCE is not set # CONFIG_GPIO_DWAPB is not set # CONFIG_GPIO_EXAR is not set # CONFIG_GPIO_FTGPIO010 is not set # CONFIG_GPIO_GENERIC_PLATFORM is not set # CONFIG_GPIO_GRGPIO is not set -# CONFIG_GPIO_MOCKUP is not set +# CONFIG_GPIO_HLWD is not set +# CONFIG_GPIO_MB86S7X is not set # CONFIG_GPIO_PL061 is not set +# CONFIG_GPIO_SIFIVE is not set # CONFIG_GPIO_XGENE is not set CONFIG_GPIO_XILINX=y CONFIG_GPIO_ZYNQ=y +# CONFIG_GPIO_ZYNQMP_MODEPIN is not set +# CONFIG_GPIO_AMD_FCH is not set +# end of Memory mapped GPIO drivers # # I2C GPIO expanders # -# CONFIG_GPIO_ADP5588 is not set +CONFIG_GPIO_ADP5588=y +CONFIG_GPIO_ADP5588_IRQ=y # CONFIG_GPIO_ADNP is not set +# CONFIG_GPIO_GW_PLD is not set # CONFIG_GPIO_MAX7300 is not set # CONFIG_GPIO_MAX732X is not set CONFIG_GPIO_PCA953X=y # CONFIG_GPIO_PCA953X_IRQ is not set +# CONFIG_GPIO_PCA9570 is not set # CONFIG_GPIO_PCF857X is not set -# CONFIG_GPIO_SX150X is not set # CONFIG_GPIO_TPIC2810 is not set +# end of I2C GPIO expanders # # MFD GPIO expanders # +CONFIG_GPIO_ADP5520=y CONFIG_GPIO_TPS65086=y +# end of MFD GPIO expanders # # PCI GPIO expanders # # CONFIG_GPIO_BT8XX is not set # CONFIG_GPIO_PCI_IDIO_16 is not set +# CONFIG_GPIO_PCIE_IDIO_24 is not set # CONFIG_GPIO_RDC321X is not set +# end of PCI GPIO expanders # # SPI GPIO expanders # # CONFIG_GPIO_74X164 is not set -# CONFIG_GPIO_ADI_DAQ1 is not set +CONFIG_GPIO_ADI_DAQ1=y +# CONFIG_GPIO_MAX3191X is not set # CONFIG_GPIO_MAX7301 is not set # CONFIG_GPIO_MC33880 is not set # CONFIG_GPIO_PISOSR is not set # CONFIG_GPIO_XRA1403 is not set +# end of SPI GPIO expanders # # USB GPIO expanders # +# end of USB GPIO expanders + +# CONFIG_GPIO_AGGREGATOR is not set +# CONFIG_GPIO_MOCKUP is not set # CONFIG_W1 is not set -# CONFIG_POWER_AVS is not set CONFIG_POWER_RESET=y # CONFIG_POWER_RESET_GPIO is not set # CONFIG_POWER_RESET_GPIO_RESTART is not set @@ -2341,18 +2984,21 @@ CONFIG_POWER_RESET_LTC2952=y # CONFIG_POWER_RESET_XGENE is not set # CONFIG_POWER_RESET_SYSCON is not set # CONFIG_POWER_RESET_SYSCON_POWEROFF is not set +# CONFIG_NVMEM_REBOOT_MODE is not set CONFIG_POWER_SUPPLY=y # CONFIG_POWER_SUPPLY_DEBUG is not set +CONFIG_POWER_SUPPLY_HWMON=y # CONFIG_PDA_POWER is not set # CONFIG_GENERIC_ADC_BATTERY is not set # CONFIG_TEST_POWER is not set -# CONFIG_CHARGER_ADP5061 is not set +CONFIG_CHARGER_ADP5061=y +# CONFIG_BATTERY_CW2015 is not set # CONFIG_BATTERY_DS2780 is not set # CONFIG_BATTERY_DS2781 is not set # CONFIG_BATTERY_DS2782 is not set -# CONFIG_BATTERY_LEGO_EV3 is not set # CONFIG_BATTERY_SBS is not set # CONFIG_CHARGER_SBS is not set +# CONFIG_MANAGER_SBS is not set # CONFIG_BATTERY_BQ27XXX is not set # CONFIG_BATTERY_MAX17040 is not set # CONFIG_BATTERY_MAX17042 is not set @@ -2361,42 +3007,51 @@ CONFIG_POWER_SUPPLY=y # CONFIG_CHARGER_LP8727 is not set # CONFIG_CHARGER_GPIO is not set # CONFIG_CHARGER_MANAGER is not set -# CONFIG_CHARGER_LTC3651 is not set +CONFIG_CHARGER_LT3651=y # CONFIG_CHARGER_DETECTOR_MAX14656 is not set # CONFIG_CHARGER_BQ2415X is not set # CONFIG_CHARGER_BQ24190 is not set # CONFIG_CHARGER_BQ24257 is not set # CONFIG_CHARGER_BQ24735 is not set +# CONFIG_CHARGER_BQ2515X is not set # CONFIG_CHARGER_BQ25890 is not set +# CONFIG_CHARGER_BQ25980 is not set # CONFIG_CHARGER_SMB347 is not set -# CONFIG_BATTERY_GAUGE_LTC2941 is not set +CONFIG_BATTERY_GAUGE_LTC2941=y # CONFIG_CHARGER_RT9455 is not set +# CONFIG_CHARGER_UCS1002 is not set +# CONFIG_CHARGER_BD99954 is not set CONFIG_HWMON=y -# CONFIG_HWMON_VID is not set +CONFIG_HWMON_VID=y # CONFIG_HWMON_DEBUG_CHIP is not set # # Native drivers # -# CONFIG_SENSORS_AD7314 is not set -# CONFIG_SENSORS_AD7414 is not set -CONFIG_SENSORS_AXI_FAN_CONTROL=y -# CONFIG_SENSORS_AD7418 is not set -# CONFIG_SENSORS_ADM1021 is not set -# CONFIG_SENSORS_ADM1025 is not set -# CONFIG_SENSORS_ADM1026 is not set -# CONFIG_SENSORS_ADM1029 is not set -# CONFIG_SENSORS_ADM1031 is not set -# CONFIG_SENSORS_ADM9240 is not set -# CONFIG_SENSORS_ADT7310 is not set -# CONFIG_SENSORS_ADT7410 is not set -# CONFIG_SENSORS_ADT7411 is not set -# CONFIG_SENSORS_ADT7462 is not set -# CONFIG_SENSORS_ADT7470 is not set -# CONFIG_SENSORS_ADT7475 is not set +CONFIG_SENSORS_AD7314=y +CONFIG_SENSORS_AD7414=y +CONFIG_SENSORS_AD7418=y +CONFIG_SENSORS_ADM1021=y +CONFIG_SENSORS_ADM1025=y +CONFIG_SENSORS_ADM1026=y +CONFIG_SENSORS_ADM1029=y +CONFIG_SENSORS_ADM1031=y +CONFIG_SENSORS_ADM1177=y +CONFIG_SENSORS_ADM9240=y +CONFIG_SENSORS_ADT7X10=y +CONFIG_SENSORS_ADT7310=y +CONFIG_SENSORS_ADT7410=y +CONFIG_SENSORS_ADT7411=y +CONFIG_SENSORS_ADT7462=y +CONFIG_SENSORS_ADT7470=y +CONFIG_SENSORS_ADT7475=y +# CONFIG_SENSORS_AS370 is not set # CONFIG_SENSORS_ASC7621 is not set +CONFIG_SENSORS_AXI_FAN_CONTROL=y # CONFIG_SENSORS_ASPEED is not set # CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_CORSAIR_CPRO is not set +# CONFIG_SENSORS_DRIVETEMP is not set # CONFIG_SENSORS_DS620 is not set # CONFIG_SENSORS_DS1621 is not set # CONFIG_SENSORS_I5K_AMB is not set @@ -2412,25 +3067,29 @@ CONFIG_SENSORS_AXI_FAN_CONTROL=y # CONFIG_SENSORS_HIH6130 is not set CONFIG_SENSORS_IIO_HWMON=y # CONFIG_SENSORS_IT87 is not set -# CONFIG_SENSORS_JC42 is not set +CONFIG_SENSORS_JC42=y # CONFIG_SENSORS_POWR1220 is not set # CONFIG_SENSORS_LINEAGE is not set -# CONFIG_SENSORS_LTC2945 is not set -# CONFIG_SENSORS_LTC2947_I2C is not set -# CONFIG_SENSORS_LTC2947_SPI is not set -# CONFIG_SENSORS_LTC2990 is not set -# CONFIG_SENSORS_LTC4151 is not set -# CONFIG_SENSORS_LTC4215 is not set -# CONFIG_SENSORS_LTC4222 is not set -# CONFIG_SENSORS_LTC4245 is not set -# CONFIG_SENSORS_LTC4260 is not set -# CONFIG_SENSORS_LTC4261 is not set +CONFIG_SENSORS_LTC2945=y +CONFIG_SENSORS_LTC2947=y +CONFIG_SENSORS_LTC2947_I2C=y +CONFIG_SENSORS_LTC2947_SPI=y +CONFIG_SENSORS_LTC2990=y +CONFIG_SENSORS_LTC2992=y +CONFIG_SENSORS_LTC4151=y +CONFIG_SENSORS_LTC4215=y +CONFIG_SENSORS_LTC4222=y +CONFIG_SENSORS_LTC4245=y +CONFIG_SENSORS_LTC4260=y +CONFIG_SENSORS_LTC4261=y # CONFIG_SENSORS_MAX1111 is not set # CONFIG_SENSORS_MAX16065 is not set # CONFIG_SENSORS_MAX1619 is not set # CONFIG_SENSORS_MAX1668 is not set # CONFIG_SENSORS_MAX197 is not set # CONFIG_SENSORS_MAX31722 is not set +# CONFIG_SENSORS_MAX31730 is not set +# CONFIG_SENSORS_MAX6621 is not set # CONFIG_SENSORS_MAX6639 is not set # CONFIG_SENSORS_MAX6642 is not set # CONFIG_SENSORS_MAX6650 is not set @@ -2438,6 +3097,7 @@ CONFIG_SENSORS_IIO_HWMON=y # CONFIG_SENSORS_MAX31790 is not set # CONFIG_SENSORS_MCP3021 is not set # CONFIG_SENSORS_TC654 is not set +# CONFIG_SENSORS_MR75203 is not set # CONFIG_SENSORS_ADCXX is not set # CONFIG_SENSORS_LM63 is not set # CONFIG_SENSORS_LM70 is not set @@ -2448,8 +3108,8 @@ CONFIG_SENSORS_IIO_HWMON=y # CONFIG_SENSORS_LM80 is not set # CONFIG_SENSORS_LM83 is not set # CONFIG_SENSORS_LM85 is not set -# CONFIG_SENSORS_LM87 is not set -# CONFIG_SENSORS_LM90 is not set +CONFIG_SENSORS_LM87=y +CONFIG_SENSORS_LM90=y # CONFIG_SENSORS_LM92 is not set # CONFIG_SENSORS_LM93 is not set # CONFIG_SENSORS_LM95234 is not set @@ -2462,24 +3122,41 @@ CONFIG_SENSORS_IIO_HWMON=y # CONFIG_SENSORS_NCT6775 is not set # CONFIG_SENSORS_NCT7802 is not set # CONFIG_SENSORS_NCT7904 is not set +# CONFIG_SENSORS_NPCM7XX is not set +# CONFIG_SENSORS_OCC_P8_I2C is not set # CONFIG_SENSORS_PCF8591 is not set CONFIG_PMBUS=y CONFIG_SENSORS_PMBUS=y -# CONFIG_SENSORS_ADM1275 is not set +CONFIG_SENSORS_ADM1266=y +CONFIG_SENSORS_ADM1275=y +# CONFIG_SENSORS_BEL_PFE is not set # CONFIG_SENSORS_IBM_CFFPS is not set +# CONFIG_SENSORS_INSPUR_IPSPS is not set # CONFIG_SENSORS_IR35221 is not set +# CONFIG_SENSORS_IR38064 is not set +# CONFIG_SENSORS_IRPS5401 is not set +# CONFIG_SENSORS_ISL68137 is not set # CONFIG_SENSORS_LM25066 is not set -# CONFIG_SENSORS_LTC2978 is not set -# CONFIG_SENSORS_LTC3815 is not set +CONFIG_SENSORS_LTC2978=y +CONFIG_SENSORS_LTC2978_REGULATOR=y +CONFIG_SENSORS_LTC3815=y # CONFIG_SENSORS_MAX16064 is not set +# CONFIG_SENSORS_MAX16601 is not set +# CONFIG_SENSORS_MAX20730 is not set CONFIG_SENSORS_MAX20751=y +# CONFIG_SENSORS_MAX31785 is not set # CONFIG_SENSORS_MAX34440 is not set # CONFIG_SENSORS_MAX8688 is not set +# CONFIG_SENSORS_MP2975 is not set +# CONFIG_SENSORS_PXE1610 is not set # CONFIG_SENSORS_TPS40422 is not set # CONFIG_SENSORS_TPS53679 is not set +# CONFIG_SENSORS_TPS544 is not set # CONFIG_SENSORS_UCD9000 is not set # CONFIG_SENSORS_UCD9200 is not set +# CONFIG_SENSORS_XDPE122 is not set # CONFIG_SENSORS_ZL6100 is not set +# CONFIG_SENSORS_PWM_FAN is not set # CONFIG_SENSORS_SHT15 is not set # CONFIG_SENSORS_SHT21 is not set # CONFIG_SENSORS_SHT3x is not set @@ -2492,13 +3169,11 @@ CONFIG_SENSORS_MAX20751=y # CONFIG_SENSORS_SMSC47M1 is not set # CONFIG_SENSORS_SMSC47M192 is not set # CONFIG_SENSORS_SMSC47B397 is not set -# CONFIG_SENSORS_SCH56XX_COMMON is not set # CONFIG_SENSORS_SCH5627 is not set # CONFIG_SENSORS_SCH5636 is not set # CONFIG_SENSORS_STTS751 is not set # CONFIG_SENSORS_SMM665 is not set # CONFIG_SENSORS_ADC128D818 is not set -# CONFIG_SENSORS_ADS1015 is not set # CONFIG_SENSORS_ADS7828 is not set # CONFIG_SENSORS_ADS7871 is not set # CONFIG_SENSORS_AMC6821 is not set @@ -2512,9 +3187,11 @@ CONFIG_SENSORS_INA2XX=y # CONFIG_SENSORS_TMP108 is not set # CONFIG_SENSORS_TMP401 is not set # CONFIG_SENSORS_TMP421 is not set +# CONFIG_SENSORS_TMP513 is not set # CONFIG_SENSORS_VIA686A is not set # CONFIG_SENSORS_VT1211 is not set # CONFIG_SENSORS_VT8231 is not set +# CONFIG_SENSORS_W83773G is not set # CONFIG_SENSORS_W83781D is not set # CONFIG_SENSORS_W83791D is not set # CONFIG_SENSORS_W83792D is not set @@ -2529,8 +3206,14 @@ CONFIG_WATCHDOG=y CONFIG_WATCHDOG_CORE=y # CONFIG_WATCHDOG_NOWAYOUT is not set CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y +CONFIG_WATCHDOG_OPEN_TIMEOUT=0 # CONFIG_WATCHDOG_SYSFS is not set +# +# Watchdog Pretimeout Governors +# +# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set + # # Watchdog Device Drivers # @@ -2543,6 +3226,7 @@ CONFIG_XILINX_WATCHDOG=y CONFIG_CADENCE_WATCHDOG=y # CONFIG_DW_WATCHDOG is not set # CONFIG_MAX63XX_WATCHDOG is not set +# CONFIG_ARM_SMC_WATCHDOG is not set # CONFIG_ALIM7101_WDT is not set # CONFIG_I6300ESB_WDT is not set # CONFIG_MEN_A21_WDT is not set @@ -2557,16 +3241,7 @@ CONFIG_CADENCE_WATCHDOG=y # USB-based Watchdog Cards # # CONFIG_USBPCWATCHDOG is not set - -# -# Watchdog Pretimeout Governors -# -# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set CONFIG_SSB_POSSIBLE=y - -# -# Sonics Silicon Backplane -# # CONFIG_SSB is not set CONFIG_BCMA_POSSIBLE=y # CONFIG_BCMA is not set @@ -2578,14 +3253,14 @@ CONFIG_MFD_CORE=y # CONFIG_MFD_ACT8945A is not set # CONFIG_MFD_AS3711 is not set # CONFIG_MFD_AS3722 is not set -# CONFIG_PMIC_ADP5520 is not set +CONFIG_PMIC_ADP5520=y # CONFIG_MFD_AAT2870_CORE is not set # CONFIG_MFD_ATMEL_FLEXCOM is not set # CONFIG_MFD_ATMEL_HLCDC is not set # CONFIG_MFD_BCM590XX is not set # CONFIG_MFD_BD9571MWV is not set # CONFIG_MFD_AXP20X_I2C is not set -# CONFIG_MFD_CROS_EC is not set +# CONFIG_MFD_MADERA is not set # CONFIG_PMIC_DA903X is not set # CONFIG_MFD_DA9052_SPI is not set # CONFIG_MFD_DA9052_I2C is not set @@ -2594,13 +3269,16 @@ CONFIG_MFD_CORE=y # CONFIG_MFD_DA9063 is not set # CONFIG_MFD_DA9150 is not set # CONFIG_MFD_DLN2 is not set +# CONFIG_MFD_GATEWORKS_GSC is not set # CONFIG_MFD_MC13XXX_SPI is not set # CONFIG_MFD_MC13XXX_I2C is not set +# CONFIG_MFD_MP2629 is not set # CONFIG_MFD_HI6421_PMIC is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_HTC_I2CPLD is not set # CONFIG_LPC_ICH is not set # CONFIG_LPC_SCH is not set +# CONFIG_MFD_IQS62X is not set # CONFIG_MFD_JANZ_CMODIO is not set # CONFIG_MFD_KEMPLD is not set # CONFIG_MFD_88PM800 is not set @@ -2608,6 +3286,7 @@ CONFIG_MFD_CORE=y # CONFIG_MFD_88PM860X is not set # CONFIG_MFD_MAX14577 is not set # CONFIG_MFD_MAX77620 is not set +# CONFIG_MFD_MAX77650 is not set # CONFIG_MFD_MAX77686 is not set # CONFIG_MFD_MAX77693 is not set # CONFIG_MFD_MAX77843 is not set @@ -2615,6 +3294,7 @@ CONFIG_MFD_CORE=y # CONFIG_MFD_MAX8925 is not set # CONFIG_MFD_MAX8997 is not set # CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_MT6360 is not set # CONFIG_MFD_MT6397 is not set # CONFIG_MFD_MENF21BMC is not set # CONFIG_EZX_PCAP is not set @@ -2623,17 +3303,15 @@ CONFIG_MFD_CORE=y # CONFIG_MFD_RETU is not set # CONFIG_MFD_PCF50633 is not set # CONFIG_MFD_RDC321X is not set -# CONFIG_MFD_RTSX_PCI is not set # CONFIG_MFD_RT5033 is not set -# CONFIG_MFD_RTSX_USB is not set # CONFIG_MFD_RC5T583 is not set # CONFIG_MFD_RK808 is not set # CONFIG_MFD_RN5T618 is not set # CONFIG_MFD_SEC_CORE is not set # CONFIG_MFD_SI476X_CORE is not set +# CONFIG_MFD_SL28CPLD is not set # CONFIG_MFD_SM501 is not set # CONFIG_MFD_SKY81452 is not set -# CONFIG_MFD_SMSC is not set # CONFIG_ABX500_CORE is not set # CONFIG_MFD_STMPE is not set # CONFIG_MFD_SYSCON is not set @@ -2661,8 +3339,9 @@ CONFIG_MFD_TPS65086=y # CONFIG_MFD_WL1273_CORE is not set # CONFIG_MFD_LM3533 is not set # CONFIG_MFD_TC3589X is not set -# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_TQMX86 is not set # CONFIG_MFD_VX855 is not set +# CONFIG_MFD_LOCHNAGAR is not set # CONFIG_MFD_ARIZONA_I2C is not set # CONFIG_MFD_ARIZONA_SPI is not set # CONFIG_MFD_WM8400 is not set @@ -2670,16 +3349,28 @@ CONFIG_MFD_TPS65086=y # CONFIG_MFD_WM831X_SPI is not set # CONFIG_MFD_WM8350_I2C is not set # CONFIG_MFD_WM8994 is not set +# CONFIG_MFD_ROHM_BD718XX is not set +# CONFIG_MFD_ROHM_BD70528 is not set +# CONFIG_MFD_ROHM_BD71828 is not set +# CONFIG_MFD_STPMIC1 is not set +# CONFIG_MFD_STMFX is not set +# CONFIG_RAVE_SP_CORE is not set +# CONFIG_MFD_INTEL_M10_BMC is not set +# end of Multifunction device drivers + CONFIG_REGULATOR=y # CONFIG_REGULATOR_DEBUG is not set CONFIG_REGULATOR_FIXED_VOLTAGE=y # CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set # CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +# CONFIG_REGULATOR_88PG86X is not set # CONFIG_REGULATOR_ACT8865 is not set -# CONFIG_REGULATOR_AD5398 is not set +CONFIG_REGULATOR_AD5398=y +# CONFIG_REGULATOR_DA9121 is not set # CONFIG_REGULATOR_DA9210 is not set # CONFIG_REGULATOR_DA9211 is not set # CONFIG_REGULATOR_FAN53555 is not set +# CONFIG_REGULATOR_FAN53880 is not set CONFIG_REGULATOR_GPIO=y # CONFIG_REGULATOR_ISL9305 is not set # CONFIG_REGULATOR_ISL6271A is not set @@ -2687,17 +3378,32 @@ CONFIG_REGULATOR_GPIO=y # CONFIG_REGULATOR_LP3972 is not set # CONFIG_REGULATOR_LP872X is not set # CONFIG_REGULATOR_LP8755 is not set -# CONFIG_REGULATOR_LTC3589 is not set -# CONFIG_REGULATOR_LTC3676 is not set +CONFIG_REGULATOR_LTC3589=y +CONFIG_REGULATOR_LTC3676=y # CONFIG_REGULATOR_MAX1586 is not set # CONFIG_REGULATOR_MAX8649 is not set # CONFIG_REGULATOR_MAX8660 is not set # CONFIG_REGULATOR_MAX8952 is not set +# CONFIG_REGULATOR_MAX77826 is not set +# CONFIG_REGULATOR_MCP16502 is not set +# CONFIG_REGULATOR_MP5416 is not set +# CONFIG_REGULATOR_MP8859 is not set +# CONFIG_REGULATOR_MP886X is not set +# CONFIG_REGULATOR_MPQ7920 is not set # CONFIG_REGULATOR_MT6311 is not set +# CONFIG_REGULATOR_PCA9450 is not set # CONFIG_REGULATOR_PFUZE100 is not set # CONFIG_REGULATOR_PV88060 is not set # CONFIG_REGULATOR_PV88080 is not set # CONFIG_REGULATOR_PV88090 is not set +# CONFIG_REGULATOR_PWM is not set +# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set +# CONFIG_REGULATOR_RT4801 is not set +# CONFIG_REGULATOR_RTMV20 is not set +# CONFIG_REGULATOR_SLG51000 is not set +# CONFIG_REGULATOR_SY8106A is not set +# CONFIG_REGULATOR_SY8824X is not set +# CONFIG_REGULATOR_SY8827N is not set # CONFIG_REGULATOR_TPS51632 is not set # CONFIG_REGULATOR_TPS62360 is not set # CONFIG_REGULATOR_TPS65023 is not set @@ -2706,44 +3412,65 @@ CONFIG_REGULATOR_TPS65086=y # CONFIG_REGULATOR_TPS65132 is not set # CONFIG_REGULATOR_TPS6524X is not set # CONFIG_REGULATOR_VCTRL is not set -CONFIG_RC_CORE=y -CONFIG_RC_MAP=y -CONFIG_RC_DECODERS=y -# CONFIG_LIRC is not set -CONFIG_IR_NEC_DECODER=y -CONFIG_IR_RC5_DECODER=y -CONFIG_IR_RC6_DECODER=y -CONFIG_IR_JVC_DECODER=y -CONFIG_IR_SONY_DECODER=y -CONFIG_IR_SANYO_DECODER=y -CONFIG_IR_SHARP_DECODER=y -CONFIG_IR_MCE_KBD_DECODER=y -CONFIG_IR_XMP_DECODER=y -# CONFIG_RC_DEVICES is not set +# CONFIG_RC_CORE is not set +CONFIG_CEC_CORE=y +CONFIG_MEDIA_CEC_SUPPORT=y +# CONFIG_CEC_CH7322 is not set +# CONFIG_USB_PULSE8_CEC is not set +# CONFIG_USB_RAINSHADOW_CEC is not set CONFIG_MEDIA_SUPPORT=y +# CONFIG_MEDIA_SUPPORT_FILTER is not set +# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set # -# Multimedia core support +# Media device types # CONFIG_MEDIA_CAMERA_SUPPORT=y -# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set -# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set -# CONFIG_MEDIA_RADIO_SUPPORT is not set -# CONFIG_MEDIA_SDR_SUPPORT is not set -# CONFIG_MEDIA_CEC_SUPPORT is not set -CONFIG_MEDIA_CONTROLLER=y +CONFIG_MEDIA_ANALOG_TV_SUPPORT=y +CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y +CONFIG_MEDIA_RADIO_SUPPORT=y +CONFIG_MEDIA_SDR_SUPPORT=y +CONFIG_MEDIA_PLATFORM_SUPPORT=y +CONFIG_MEDIA_TEST_SUPPORT=y +# end of Media device types + +# +# Media core support +# CONFIG_VIDEO_DEV=y -CONFIG_VIDEO_V4L2_SUBDEV_API=y +CONFIG_MEDIA_CONTROLLER=y +CONFIG_DVB_CORE=y +# end of Media core support + +# +# Video4Linux options +# CONFIG_VIDEO_V4L2=y -# CONFIG_VIDEO_ADV_DEBUG is not set +CONFIG_VIDEO_V4L2_I2C=y +CONFIG_VIDEO_V4L2_SUBDEV_API=y +CONFIG_VIDEO_ADV_DEBUG=y # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set -# CONFIG_VIDEO_PCI_SKELETON is not set +CONFIG_V4L2_MEM2MEM_DEV=y +# CONFIG_V4L2_FLASH_LED_CLASS is not set CONFIG_V4L2_FWNODE=y -CONFIG_VIDEOBUF2_CORE=y -CONFIG_VIDEOBUF2_MEMOPS=y -CONFIG_VIDEOBUF2_DMA_CONTIG=y -CONFIG_VIDEOBUF2_VMALLOC=y -# CONFIG_TTPCI_EEPROM is not set +# end of Video4Linux options + +# +# Media controller options +# +# CONFIG_MEDIA_CONTROLLER_DVB is not set +# end of Media controller options + +# +# Digital TV options +# +# CONFIG_DVB_MMAP is not set +CONFIG_DVB_NET=y +CONFIG_DVB_MAX_ADAPTERS=16 +CONFIG_DVB_DYNAMIC_MINORS=y +# CONFIG_DVB_DEMUX_SECTION_LOSS_LOG is not set +# CONFIG_DVB_ULE_DEBUG is not set +# end of Digital TV options # # Media drivers @@ -2812,103 +3539,515 @@ CONFIG_USB_GSPCA=m # CONFIG_USB_S2255 is not set # CONFIG_VIDEO_USBTV is not set +# +# Analog TV USB devices +# +# CONFIG_VIDEO_PVRUSB2 is not set +# CONFIG_VIDEO_HDPVR is not set +# CONFIG_VIDEO_STK1160_COMMON is not set +# CONFIG_VIDEO_GO7007 is not set + +# +# Analog/digital TV USB devices +# +# CONFIG_VIDEO_AU0828 is not set +# CONFIG_VIDEO_CX231XX is not set + +# +# Digital TV USB devices +# +# CONFIG_DVB_USB_V2 is not set +# CONFIG_DVB_TTUSB_BUDGET is not set +# CONFIG_DVB_TTUSB_DEC is not set +# CONFIG_SMS_USB_DRV is not set +# CONFIG_DVB_B2C2_FLEXCOP_USB is not set +# CONFIG_DVB_AS102 is not set + # # Webcam, TV (analog/digital) USB devices # # CONFIG_VIDEO_EM28XX is not set + +# +# Software defined radio USB devices +# +# CONFIG_USB_AIRSPY is not set +# CONFIG_USB_HACKRF is not set +# CONFIG_USB_MSI2500 is not set # CONFIG_MEDIA_PCI_SUPPORT is not set +CONFIG_RADIO_ADAPTERS=y +# CONFIG_RADIO_SI470X is not set +# CONFIG_RADIO_SI4713 is not set +# CONFIG_USB_MR800 is not set +# CONFIG_USB_DSBR is not set +# CONFIG_RADIO_MAXIRADIO is not set +# CONFIG_RADIO_SHARK is not set +# CONFIG_RADIO_SHARK2 is not set +# CONFIG_USB_KEENE is not set +# CONFIG_USB_RAREMONO is not set +# CONFIG_USB_MA901 is not set +# CONFIG_RADIO_TEA5764 is not set +# CONFIG_RADIO_SAA7706H is not set +# CONFIG_RADIO_TEF6862 is not set +# CONFIG_RADIO_WL1273 is not set +# CONFIG_RADIO_WL128X is not set +CONFIG_VIDEOBUF2_CORE=y +CONFIG_VIDEOBUF2_V4L2=y +CONFIG_VIDEOBUF2_MEMOPS=y +CONFIG_VIDEOBUF2_DMA_CONTIG=y +CONFIG_VIDEOBUF2_VMALLOC=y CONFIG_V4L_PLATFORM_DRIVERS=y # CONFIG_VIDEO_CAFE_CCIC is not set +# CONFIG_VIDEO_CADENCE is not set +# CONFIG_VIDEO_ASPEED is not set # CONFIG_VIDEO_MUX is not set -# CONFIG_VIDEO_AXI_HDMI_RX is not set +CONFIG_VIDEO_AXI_HDMI_RX=y # CONFIG_VIDEO_IMAGEON_BRIDGE is not set -# CONFIG_SOC_CAMERA is not set CONFIG_VIDEO_XILINX=y -# CONFIG_VIDEO_XILINX_AXI4S_SWITCH is not set +CONFIG_VIDEO_XILINX_CSI2RXSS=y +CONFIG_VIDEO_XILINX_AXI4S_SWITCH=y CONFIG_VIDEO_XILINX_CFA=y CONFIG_VIDEO_XILINX_CRESAMPLE=y -# CONFIG_VIDEO_XILINX_DEMOSAIC is not set -# CONFIG_VIDEO_XILINX_GAMMA is not set +CONFIG_VIDEO_XILINX_DEMOSAIC=y +CONFIG_VIDEO_XILINX_GAMMA=y +# CONFIG_VIDEO_XILINX_HDMI21RXSS is not set CONFIG_VIDEO_XILINX_HLS=y CONFIG_VIDEO_XILINX_REMAPPER=y CONFIG_VIDEO_XILINX_RGB2YUV=y CONFIG_VIDEO_XILINX_SCALER=y -# CONFIG_VIDEO_XILINX_MULTISCALER is not set +CONFIG_VIDEO_XILINX_MULTISCALER=y CONFIG_VIDEO_XILINX_SDIRXSS=y CONFIG_VIDEO_XILINX_SWITCH=y CONFIG_VIDEO_XILINX_TPG=y -# CONFIG_VIDEO_XILINX_VPSS_CSC is not set -# CONFIG_VIDEO_XILINX_VPSS_SCALER is not set +CONFIG_VIDEO_XILINX_VPSS_CSC=y +CONFIG_VIDEO_XILINX_VPSS_SCALER=y CONFIG_VIDEO_XILINX_VTC=y -# CONFIG_VIDEO_XILINX_CSI2RXSS is not set -# CONFIG_VIDEO_XILINX_SCD is not set -# CONFIG_VIDEO_XILINX_M2M is not set +# CONFIG_VIDEO_XILINX_DPRXSS is not set +CONFIG_VIDEO_XILINX_SCD=y +CONFIG_VIDEO_XILINX_M2M=y +# CONFIG_VIDEO_XILINX_AXI4S_BROADCASTER is not set # CONFIG_V4L_MEM2MEM_DRIVERS is not set -# CONFIG_ADI_AXI_VIDEO_FRAME_BUFFER is not set +CONFIG_ADI_AXI_VIDEO_FRAME_BUFFER=y +# CONFIG_DVB_PLATFORM_DRIVERS is not set +# CONFIG_SDR_PLATFORM_DRIVERS is not set + +# +# MMC/SDIO DVB adapters +# +# CONFIG_SMS_SDIO_DRV is not set # CONFIG_V4L_TEST_DRIVERS is not set +# CONFIG_DVB_TEST_DRIVERS is not set +# end of Media drivers # -# Supported MMC/SDIO adapters +# Media ancillary drivers # -# CONFIG_CYPRESS_FIRMWARE is not set - -# -# Media ancillary drivers (tuners, sensors, i2c, spi, frontends) -# -CONFIG_MEDIA_SUBDRV_AUTOSELECT=y -CONFIG_VIDEO_IR_I2C=y +CONFIG_MEDIA_ATTACH=y # # Audio decoders, processors and mixers # +# CONFIG_VIDEO_TVAUDIO is not set +# CONFIG_VIDEO_TDA7432 is not set +# CONFIG_VIDEO_TDA9840 is not set +# CONFIG_VIDEO_TDA1997X is not set +# CONFIG_VIDEO_TEA6415C is not set +# CONFIG_VIDEO_TEA6420 is not set +# CONFIG_VIDEO_MSP3400 is not set +# CONFIG_VIDEO_CS3308 is not set +# CONFIG_VIDEO_CS5345 is not set +# CONFIG_VIDEO_CS53L32A is not set +# CONFIG_VIDEO_TLV320AIC23B is not set +# CONFIG_VIDEO_UDA1342 is not set +# CONFIG_VIDEO_WM8775 is not set +# CONFIG_VIDEO_WM8739 is not set +# CONFIG_VIDEO_VP27SMPX is not set +# CONFIG_VIDEO_SONY_BTF_MPX is not set +# end of Audio decoders, processors and mixers # # RDS decoders # +# CONFIG_VIDEO_SAA6588 is not set +# end of RDS decoders # # Video decoders # +CONFIG_VIDEO_ADV7180=y +CONFIG_VIDEO_ADV7183=y +CONFIG_VIDEO_ADV748X=y +CONFIG_VIDEO_ADV7604=y +CONFIG_VIDEO_ADV7604_CEC=y +CONFIG_VIDEO_ADV7842=y +CONFIG_VIDEO_ADV7842_CEC=y +# CONFIG_VIDEO_BT819 is not set +# CONFIG_VIDEO_BT856 is not set +# CONFIG_VIDEO_BT866 is not set +# CONFIG_VIDEO_KS0127 is not set +# CONFIG_VIDEO_ML86V7667 is not set +# CONFIG_VIDEO_SAA7110 is not set +# CONFIG_VIDEO_SAA711X is not set +# CONFIG_VIDEO_TC358743 is not set +# CONFIG_VIDEO_TVP514X is not set +# CONFIG_VIDEO_TVP5150 is not set +# CONFIG_VIDEO_TVP7002 is not set +# CONFIG_VIDEO_TW2804 is not set +# CONFIG_VIDEO_TW9903 is not set +# CONFIG_VIDEO_TW9906 is not set +# CONFIG_VIDEO_TW9910 is not set +# CONFIG_VIDEO_VPX3220 is not set +# CONFIG_VIDEO_MAX9286 is not set # # Video and audio decoders # +# CONFIG_VIDEO_SAA717X is not set +# CONFIG_VIDEO_CX25840 is not set +# end of Video decoders # # Video encoders # - -# -# Camera sensor devices -# - -# -# Flash devices -# +# CONFIG_VIDEO_SAA7127 is not set +# CONFIG_VIDEO_SAA7185 is not set +CONFIG_VIDEO_ADV7170=y +CONFIG_VIDEO_ADV7175=y +CONFIG_VIDEO_ADV7343=y +CONFIG_VIDEO_ADV7393=y +CONFIG_VIDEO_AD9389B=y +# CONFIG_VIDEO_AK881X is not set +# CONFIG_VIDEO_THS8200 is not set +# end of Video encoders # # Video improvement chips # +# CONFIG_VIDEO_UPD64031A is not set +# CONFIG_VIDEO_UPD64083 is not set +# end of Video improvement chips + +# CONFIG_VIDEO_AP1302 is not set # # Audio/Video compression chips # +# CONFIG_VIDEO_SAA6752HS is not set +# end of Audio/Video compression chips # # SDR tuner chips # +# CONFIG_SDR_MAX2175 is not set +# end of SDR tuner chips # # Miscellaneous helper chips # +# CONFIG_VIDEO_THS7303 is not set +# CONFIG_VIDEO_M52790 is not set +# CONFIG_VIDEO_I2C is not set +# CONFIG_VIDEO_ST_MIPID02 is not set +# end of Miscellaneous helper chips # -# Sensors used on soc_camera driver +# Camera sensor devices # +CONFIG_VIDEO_ADDI9036=y +# CONFIG_VIDEO_HI556 is not set +# CONFIG_VIDEO_IMX214 is not set +# CONFIG_VIDEO_IMX219 is not set +# CONFIG_VIDEO_IMX258 is not set +# CONFIG_VIDEO_IMX274 is not set +# CONFIG_VIDEO_IMX290 is not set +# CONFIG_VIDEO_IMX319 is not set +# CONFIG_VIDEO_IMX355 is not set +# CONFIG_VIDEO_OV2640 is not set +# CONFIG_VIDEO_OV2659 is not set +# CONFIG_VIDEO_OV2680 is not set +# CONFIG_VIDEO_OV2685 is not set +# CONFIG_VIDEO_OV5640 is not set +# CONFIG_VIDEO_OV5645 is not set +# CONFIG_VIDEO_OV5647 is not set +# CONFIG_VIDEO_OV6650 is not set +# CONFIG_VIDEO_OV5670 is not set +# CONFIG_VIDEO_OV5675 is not set +# CONFIG_VIDEO_OV5695 is not set +# CONFIG_VIDEO_OV7251 is not set +# CONFIG_VIDEO_OV772X is not set +# CONFIG_VIDEO_OV7640 is not set +# CONFIG_VIDEO_OV7670 is not set +# CONFIG_VIDEO_OV7740 is not set +# CONFIG_VIDEO_OV8856 is not set +# CONFIG_VIDEO_OV9640 is not set +# CONFIG_VIDEO_OV9650 is not set +# CONFIG_VIDEO_OV13858 is not set +# CONFIG_VIDEO_VS6624 is not set +# CONFIG_VIDEO_MT9M001 is not set +# CONFIG_VIDEO_MT9M032 is not set +# CONFIG_VIDEO_MT9M111 is not set +# CONFIG_VIDEO_MT9P031 is not set +# CONFIG_VIDEO_MT9T001 is not set +# CONFIG_VIDEO_MT9T112 is not set +# CONFIG_VIDEO_MT9V011 is not set +# CONFIG_VIDEO_MT9V032 is not set +# CONFIG_VIDEO_MT9V111 is not set +# CONFIG_VIDEO_SR030PC30 is not set +# CONFIG_VIDEO_NOON010PC30 is not set +# CONFIG_VIDEO_M5MOLS is not set +# CONFIG_VIDEO_RDACM20 is not set +# CONFIG_VIDEO_RJ54N1 is not set +# CONFIG_VIDEO_S5K6AA is not set +# CONFIG_VIDEO_S5K6A3 is not set +# CONFIG_VIDEO_S5K4ECGX is not set +# CONFIG_VIDEO_S5K5BAF is not set +# CONFIG_VIDEO_SMIAPP is not set +# CONFIG_VIDEO_ET8EK8 is not set +# CONFIG_VIDEO_S5C73M3 is not set +# end of Camera sensor devices + +# +# Lens drivers +# +# CONFIG_VIDEO_AD5820 is not set +# CONFIG_VIDEO_AK7375 is not set +# CONFIG_VIDEO_DW9714 is not set +# CONFIG_VIDEO_DW9768 is not set +# CONFIG_VIDEO_DW9807_VCM is not set +# end of Lens drivers + +# +# Flash devices +# +CONFIG_VIDEO_ADP1653=y +# CONFIG_VIDEO_LM3560 is not set +# CONFIG_VIDEO_LM3646 is not set +# end of Flash devices + +# +# SPI helper chips +# +# CONFIG_VIDEO_GS1662 is not set +# end of SPI helper chips + +# +# Media SPI Adapters +# +CONFIG_CXD2880_SPI_DRV=m +# end of Media SPI Adapters + +CONFIG_MEDIA_TUNER=y + +# +# Customize TV tuners +# +CONFIG_MEDIA_TUNER_SIMPLE=m +CONFIG_MEDIA_TUNER_TDA18250=m +CONFIG_MEDIA_TUNER_TDA8290=m +CONFIG_MEDIA_TUNER_TDA827X=m +CONFIG_MEDIA_TUNER_TDA18271=m +CONFIG_MEDIA_TUNER_TDA9887=m +CONFIG_MEDIA_TUNER_TEA5761=m +CONFIG_MEDIA_TUNER_TEA5767=m +CONFIG_MEDIA_TUNER_MSI001=m +CONFIG_MEDIA_TUNER_MT20XX=m +CONFIG_MEDIA_TUNER_MT2060=m +CONFIG_MEDIA_TUNER_MT2063=m +CONFIG_MEDIA_TUNER_MT2266=m +CONFIG_MEDIA_TUNER_MT2131=m +CONFIG_MEDIA_TUNER_QT1010=m +CONFIG_MEDIA_TUNER_XC2028=m +CONFIG_MEDIA_TUNER_XC5000=m +CONFIG_MEDIA_TUNER_XC4000=m +CONFIG_MEDIA_TUNER_MXL5005S=m +CONFIG_MEDIA_TUNER_MXL5007T=m +CONFIG_MEDIA_TUNER_MC44S803=m +CONFIG_MEDIA_TUNER_MAX2165=m +CONFIG_MEDIA_TUNER_TDA18218=m +CONFIG_MEDIA_TUNER_FC0011=m +CONFIG_MEDIA_TUNER_FC0012=m +CONFIG_MEDIA_TUNER_FC0013=m +CONFIG_MEDIA_TUNER_TDA18212=m +CONFIG_MEDIA_TUNER_E4000=m +CONFIG_MEDIA_TUNER_FC2580=m +CONFIG_MEDIA_TUNER_M88RS6000T=m +CONFIG_MEDIA_TUNER_TUA9001=m +CONFIG_MEDIA_TUNER_SI2157=m +CONFIG_MEDIA_TUNER_IT913X=m +CONFIG_MEDIA_TUNER_R820T=m +CONFIG_MEDIA_TUNER_MXL301RF=m +CONFIG_MEDIA_TUNER_QM1D1C0042=m +CONFIG_MEDIA_TUNER_QM1D1B0004=m +# end of Customize TV tuners + +# +# Customise DVB Frontends +# + +# +# Multistandard (satellite) frontends +# +CONFIG_DVB_STB0899=m +CONFIG_DVB_STB6100=m +CONFIG_DVB_STV090x=m +CONFIG_DVB_STV0910=m +CONFIG_DVB_STV6110x=m +CONFIG_DVB_STV6111=m +CONFIG_DVB_MXL5XX=m +CONFIG_DVB_M88DS3103=m + +# +# Multistandard (cable + terrestrial) frontends +# +CONFIG_DVB_DRXK=m +CONFIG_DVB_TDA18271C2DD=m +CONFIG_DVB_SI2165=m +CONFIG_DVB_MN88472=m +CONFIG_DVB_MN88473=m + +# +# DVB-S (satellite) frontends +# +CONFIG_DVB_CX24110=m +CONFIG_DVB_CX24123=m +CONFIG_DVB_MT312=m +CONFIG_DVB_ZL10036=m +CONFIG_DVB_ZL10039=m +CONFIG_DVB_S5H1420=m +CONFIG_DVB_STV0288=m +CONFIG_DVB_STB6000=m +CONFIG_DVB_STV0299=m +CONFIG_DVB_STV6110=m +CONFIG_DVB_STV0900=m +CONFIG_DVB_TDA8083=m +CONFIG_DVB_TDA10086=m +CONFIG_DVB_TDA8261=m +CONFIG_DVB_VES1X93=m +CONFIG_DVB_TUNER_ITD1000=m +CONFIG_DVB_TUNER_CX24113=m +CONFIG_DVB_TDA826X=m +CONFIG_DVB_TUA6100=m +CONFIG_DVB_CX24116=m +CONFIG_DVB_CX24117=m +CONFIG_DVB_CX24120=m +CONFIG_DVB_SI21XX=m +CONFIG_DVB_TS2020=m +CONFIG_DVB_DS3000=m +CONFIG_DVB_MB86A16=m +CONFIG_DVB_TDA10071=m + +# +# DVB-T (terrestrial) frontends +# +CONFIG_DVB_SP8870=m +CONFIG_DVB_SP887X=m +CONFIG_DVB_CX22700=m +CONFIG_DVB_CX22702=m +CONFIG_DVB_S5H1432=m +CONFIG_DVB_DRXD=m +CONFIG_DVB_L64781=m +CONFIG_DVB_TDA1004X=m +CONFIG_DVB_NXT6000=m +CONFIG_DVB_MT352=m +CONFIG_DVB_ZL10353=m +CONFIG_DVB_DIB3000MB=m +CONFIG_DVB_DIB3000MC=m +CONFIG_DVB_DIB7000M=m +CONFIG_DVB_DIB7000P=m +CONFIG_DVB_DIB9000=m +CONFIG_DVB_TDA10048=m +CONFIG_DVB_AF9013=m +CONFIG_DVB_EC100=m +CONFIG_DVB_STV0367=m +CONFIG_DVB_CXD2820R=m +CONFIG_DVB_CXD2841ER=m +CONFIG_DVB_RTL2830=m +CONFIG_DVB_RTL2832=m +CONFIG_DVB_RTL2832_SDR=m +CONFIG_DVB_SI2168=m +CONFIG_DVB_ZD1301_DEMOD=m +CONFIG_DVB_CXD2880=m + +# +# DVB-C (cable) frontends +# +CONFIG_DVB_VES1820=m +CONFIG_DVB_TDA10021=m +CONFIG_DVB_TDA10023=m +CONFIG_DVB_STV0297=m + +# +# ATSC (North American/Korean Terrestrial/Cable DTV) frontends +# +CONFIG_DVB_NXT200X=m +CONFIG_DVB_OR51211=m +CONFIG_DVB_OR51132=m +CONFIG_DVB_BCM3510=m +CONFIG_DVB_LGDT330X=m +CONFIG_DVB_LGDT3305=m +CONFIG_DVB_LGDT3306A=m +CONFIG_DVB_LG2160=m +CONFIG_DVB_S5H1409=m +CONFIG_DVB_AU8522=m +CONFIG_DVB_AU8522_DTV=m +CONFIG_DVB_AU8522_V4L=m +CONFIG_DVB_S5H1411=m + +# +# ISDB-T (terrestrial) frontends +# +CONFIG_DVB_S921=m +CONFIG_DVB_DIB8000=m +CONFIG_DVB_MB86A20S=m + +# +# ISDB-S (satellite) & ISDB-T (terrestrial) frontends +# +CONFIG_DVB_TC90522=m +CONFIG_DVB_MN88443X=m + +# +# Digital terrestrial only tuners/PLL +# +CONFIG_DVB_PLL=m +CONFIG_DVB_TUNER_DIB0070=m +CONFIG_DVB_TUNER_DIB0090=m + +# +# SEC control devices for DVB-S +# +CONFIG_DVB_DRX39XYJ=m +CONFIG_DVB_LNBH25=m +CONFIG_DVB_LNBH29=m +CONFIG_DVB_LNBP21=m +CONFIG_DVB_LNBP22=m +CONFIG_DVB_ISL6405=m +CONFIG_DVB_ISL6421=m +CONFIG_DVB_ISL6423=m +CONFIG_DVB_A8293=m +CONFIG_DVB_LGS8GL5=m +CONFIG_DVB_LGS8GXX=m +CONFIG_DVB_ATBM8830=m +CONFIG_DVB_TDA665x=m +CONFIG_DVB_IX2505V=m +CONFIG_DVB_M88RS2000=m +CONFIG_DVB_AF9033=m +CONFIG_DVB_HORUS3A=m +CONFIG_DVB_ASCOT2E=m +CONFIG_DVB_HELENE=m + +# +# Common Interface (EN50221) controller drivers +# +CONFIG_DVB_CXD2099=m +CONFIG_DVB_SP2=m +# end of Customise DVB Frontends # # Tools to develop new frontends # +# CONFIG_DVB_DUMMY_FE is not set +# end of Media ancillary drivers # # Graphics support @@ -2918,86 +4057,168 @@ CONFIG_DRM=y CONFIG_DRM_MIPI_DSI=y # CONFIG_DRM_DP_AUX_CHARDEV is not set # CONFIG_DRM_DEBUG_MM is not set -# CONFIG_DRM_DEBUG_MM_SELFTEST is not set +# CONFIG_DRM_DEBUG_SELFTEST is not set CONFIG_DRM_KMS_HELPER=y CONFIG_DRM_KMS_FB_HELPER=y +# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set CONFIG_DRM_FBDEV_EMULATION=y CONFIG_DRM_FBDEV_OVERALLOC=100 +# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set # CONFIG_DRM_LOAD_EDID_FIRMWARE is not set +# CONFIG_DRM_DP_CEC is not set CONFIG_DRM_GEM_CMA_HELPER=y CONFIG_DRM_KMS_CMA_HELPER=y # # I2C encoder or helper chips # -# CONFIG_DRM_I2C_ADV7511_LEGACY is not set # CONFIG_DRM_I2C_CH7006 is not set # CONFIG_DRM_I2C_SIL164 is not set # CONFIG_DRM_I2C_NXP_TDA998X is not set -# CONFIG_DRM_HDLCD is not set -# CONFIG_DRM_MALI_DISPLAY is not set -# CONFIG_DRM_RADEON is not set -# CONFIG_DRM_AMDGPU is not set +# CONFIG_DRM_I2C_NXP_TDA9950 is not set +# end of I2C encoder or helper chips # -# ACP (Audio CoProcessor) Configuration +# ARM devices # +# CONFIG_DRM_HDLCD is not set +# CONFIG_DRM_MALI_DISPLAY is not set +# CONFIG_DRM_KOMEDA is not set +# end of ARM devices + +# CONFIG_DRM_RADEON is not set +# CONFIG_DRM_AMDGPU is not set # CONFIG_DRM_NOUVEAU is not set +CONFIG_DRM_ADI_AXI_HDMI=y # CONFIG_DRM_VGEM is not set -# CONFIG_DRM_ADI_AXI_HDMI is not set +# CONFIG_DRM_VKMS is not set # CONFIG_DRM_UDL is not set # CONFIG_DRM_AST is not set # CONFIG_DRM_MGAG200 is not set -# CONFIG_DRM_CIRRUS_QEMU is not set # CONFIG_DRM_RCAR_DW_HDMI is not set +# CONFIG_DRM_RCAR_LVDS is not set # CONFIG_DRM_QXL is not set # CONFIG_DRM_BOCHS is not set +# CONFIG_DRM_VIRTIO_GPU is not set CONFIG_DRM_PANEL=y # # Display Panels # +# CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596 is not set +# CONFIG_DRM_PANEL_BOE_HIMAX8279D is not set +# CONFIG_DRM_PANEL_BOE_TV101WUM_NL6 is not set # CONFIG_DRM_PANEL_LVDS is not set CONFIG_DRM_PANEL_SIMPLE=y +# CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set +# CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set +# CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set +# CONFIG_DRM_PANEL_ILITEK_IL9322 is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set # CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set # CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set +# CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04 is not set +# CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W is not set +# CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 is not set # CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set +# CONFIG_DRM_PANEL_LG_LB035Q02 is not set # CONFIG_DRM_PANEL_LG_LG4573 is not set +# CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set +# CONFIG_DRM_PANEL_NOVATEK_NT35510 is not set +# CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set +# CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set +# CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set +# CONFIG_DRM_PANEL_ORISETECH_OTM8009A is not set +# CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS is not set # CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00 is not set +# CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN is not set +# CONFIG_DRM_PANEL_RAYDIUM_RM67191 is not set +# CONFIG_DRM_PANEL_RAYDIUM_RM68200 is not set +# CONFIG_DRM_PANEL_RONBO_RB070D30 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set +# CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set # CONFIG_DRM_PANEL_SHARP_LQ101R1SX01 is not set +# CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set # CONFIG_DRM_PANEL_SHARP_LS043T1LE01 is not set +# CONFIG_DRM_PANEL_SITRONIX_ST7701 is not set +# CONFIG_DRM_PANEL_SITRONIX_ST7703 is not set # CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set +# CONFIG_DRM_PANEL_SONY_ACX424AKP is not set +# CONFIG_DRM_PANEL_SONY_ACX565AKM is not set +# CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set +# CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set +# CONFIG_DRM_PANEL_TPO_TPG110 is not set +# CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA is not set +# CONFIG_DRM_PANEL_VISIONOX_RM69299 is not set +# CONFIG_DRM_PANEL_XINPENG_XPP055C272 is not set +# end of Display Panels + CONFIG_DRM_BRIDGE=y CONFIG_DRM_PANEL_BRIDGE=y # # Display Interface Bridges # -# CONFIG_DRM_ANALOGIX_ANX78XX is not set -# CONFIG_DRM_DUMB_VGA_DAC is not set -# CONFIG_DRM_LVDS_ENCODER is not set +# CONFIG_DRM_CDNS_DSI is not set +# CONFIG_DRM_CHRONTEL_CH7033 is not set +# CONFIG_DRM_DISPLAY_CONNECTOR is not set +# CONFIG_DRM_LONTIUM_LT9611 is not set +# CONFIG_DRM_LVDS_CODEC is not set # CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set +# CONFIG_DRM_NWL_MIPI_DSI is not set # CONFIG_DRM_NXP_PTN3460 is not set # CONFIG_DRM_PARADE_PS8622 is not set +# CONFIG_DRM_PARADE_PS8640 is not set # CONFIG_DRM_SIL_SII8620 is not set # CONFIG_DRM_SII902X is not set +# CONFIG_DRM_SII9234 is not set +# CONFIG_DRM_SIMPLE_BRIDGE is not set +# CONFIG_DRM_THINE_THC63LVD1024 is not set +# CONFIG_DRM_TOSHIBA_TC358762 is not set +# CONFIG_DRM_TOSHIBA_TC358764 is not set # CONFIG_DRM_TOSHIBA_TC358767 is not set +# CONFIG_DRM_TOSHIBA_TC358768 is not set +# CONFIG_DRM_TOSHIBA_TC358775 is not set # CONFIG_DRM_TI_TFP410 is not set -# CONFIG_DRM_I2C_ADV7511 is not set -# CONFIG_DRM_XILINX is not set -# CONFIG_DRM_ZOCL is not set +# CONFIG_DRM_TI_SN65DSI86 is not set +# CONFIG_DRM_TI_TPD12S015 is not set +# CONFIG_DRM_ANALOGIX_ANX6345 is not set +# CONFIG_DRM_ANALOGIX_ANX78XX is not set +CONFIG_DRM_I2C_ADV7511=y +CONFIG_DRM_I2C_ADV7511_AUDIO=y +CONFIG_DRM_I2C_ADV7511_CEC=y +# CONFIG_DRM_CDNS_MHDP8546 is not set +# end of Display Interface Bridges + +# CONFIG_DRM_ETNAVIV is not set # CONFIG_DRM_ARCPGU is not set # CONFIG_DRM_HISI_HIBMC is not set # CONFIG_DRM_HISI_KIRIN is not set # CONFIG_DRM_MXSFB is not set -# CONFIG_DRM_TINYDRM is not set +# CONFIG_DRM_CIRRUS_QEMU is not set +# CONFIG_DRM_GM12U320 is not set +# CONFIG_TINYDRM_HX8357D is not set +# CONFIG_TINYDRM_ILI9225 is not set +# CONFIG_TINYDRM_ILI9341 is not set +# CONFIG_TINYDRM_ILI9486 is not set +# CONFIG_TINYDRM_MI0283QT is not set +# CONFIG_TINYDRM_REPAPER is not set +# CONFIG_TINYDRM_ST7586 is not set +# CONFIG_TINYDRM_ST7735R is not set # CONFIG_DRM_PL111 is not set +# CONFIG_DRM_LIMA is not set +# CONFIG_DRM_PANFROST is not set +# CONFIG_DRM_TIDSS is not set +CONFIG_DRM_ZYNQMP_DPSUB=y CONFIG_DRM_XLNX=y CONFIG_DRM_XLNX_BRIDGE=y -# CONFIG_DRM_XLNX_BRIDGE_DEBUG_FS is not set -CONFIG_DRM_ZYNQMP_DPSUB=y +CONFIG_DRM_XLNX_BRIDGE_DEBUG_FS=y +# CONFIG_DRM_XLNX_DPTX is not set CONFIG_DRM_XLNX_DSI=y CONFIG_DRM_XLNX_MIXER=y CONFIG_DRM_XLNX_PL_DISP=y @@ -3006,37 +4227,32 @@ CONFIG_DRM_XLNX_BRIDGE_CSC=y CONFIG_DRM_XLNX_BRIDGE_SCALER=y CONFIG_DRM_XLNX_BRIDGE_VTC=y # CONFIG_DRM_LEGACY is not set -# CONFIG_DRM_LIB_RANDOM is not set +CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y # # Frame buffer Devices # -CONFIG_FB=y -# CONFIG_FIRMWARE_EDID is not set CONFIG_FB_CMDLINE=y CONFIG_FB_NOTIFY=y -# CONFIG_FB_DDC is not set -# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set CONFIG_FB_CFB_FILLRECT=y CONFIG_FB_CFB_COPYAREA=y CONFIG_FB_CFB_IMAGEBLIT=y -# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set CONFIG_FB_SYS_FILLRECT=y CONFIG_FB_SYS_COPYAREA=y CONFIG_FB_SYS_IMAGEBLIT=y -# CONFIG_FB_PROVIDE_GET_FB_UNMAPPED_AREA is not set # CONFIG_FB_FOREIGN_ENDIAN is not set CONFIG_FB_SYS_FOPS=y CONFIG_FB_DEFERRED_IO=y -# CONFIG_FB_SVGALIB is not set -# CONFIG_FB_MACMODES is not set -# CONFIG_FB_BACKLIGHT is not set +CONFIG_FB_BACKLIGHT=y # CONFIG_FB_MODE_HELPERS is not set # CONFIG_FB_TILEBLITTING is not set # # Frame buffer hardware drivers # +# CONFIG_FB_ALTERA_VIP is not set # CONFIG_FB_CIRRUS is not set # CONFIG_FB_PM2 is not set # CONFIG_FB_ARMCLCD is not set @@ -3073,37 +4289,32 @@ CONFIG_FB_XILINX=y # CONFIG_FB_VIRTUAL is not set # CONFIG_FB_METRONOME is not set # CONFIG_FB_MB862XX is not set -# CONFIG_FB_BROADSHEET is not set -# CONFIG_FB_AUO_K190X is not set # CONFIG_FB_SIMPLE is not set # CONFIG_FB_SSD1307 is not set # CONFIG_FB_SM712 is not set -CONFIG_BACKLIGHT_LCD_SUPPORT=y -CONFIG_LCD_CLASS_DEVICE=m -# CONFIG_LCD_L4F00242T03 is not set -# CONFIG_LCD_LMS283GF05 is not set -# CONFIG_LCD_LTV350QV is not set -# CONFIG_LCD_ILI922X is not set -# CONFIG_LCD_ILI9320 is not set -# CONFIG_LCD_TDO24M is not set -# CONFIG_LCD_VGG2432A4 is not set -# CONFIG_LCD_PLATFORM is not set -# CONFIG_LCD_S6E63M0 is not set -# CONFIG_LCD_LD9040 is not set -# CONFIG_LCD_AMS369FG06 is not set -# CONFIG_LCD_LMS501KF03 is not set -# CONFIG_LCD_HX8357 is not set +# end of Frame buffer Devices + +# +# Backlight & LCD device support +# +# CONFIG_LCD_CLASS_DEVICE is not set CONFIG_BACKLIGHT_CLASS_DEVICE=y -CONFIG_BACKLIGHT_GENERIC=y -# CONFIG_BACKLIGHT_PM8941_WLED is not set -# CONFIG_BACKLIGHT_ADP8860 is not set -# CONFIG_BACKLIGHT_ADP8870 is not set +# CONFIG_BACKLIGHT_KTD253 is not set +# CONFIG_BACKLIGHT_PWM is not set +# CONFIG_BACKLIGHT_QCOM_WLED is not set +CONFIG_BACKLIGHT_ADP5520=y +CONFIG_BACKLIGHT_ADP8860=y +CONFIG_BACKLIGHT_ADP8870=y +# CONFIG_BACKLIGHT_LM3630A is not set # CONFIG_BACKLIGHT_LM3639 is not set +# CONFIG_BACKLIGHT_LP855X is not set # CONFIG_BACKLIGHT_GPIO is not set # CONFIG_BACKLIGHT_LV5207LP is not set # CONFIG_BACKLIGHT_BD6107 is not set # CONFIG_BACKLIGHT_ARCXCNN is not set -# CONFIG_VGASTATE is not set +# CONFIG_BACKLIGHT_LED is not set +# end of Backlight & LCD device support + CONFIG_VIDEOMODE_HELPERS=y CONFIG_HDMI=y @@ -3116,13 +4327,21 @@ CONFIG_DUMMY_CONSOLE_ROWS=25 CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y # CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +# CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set +# end of Console display driver support + # CONFIG_LOGO is not set +# end of Graphics support + CONFIG_SOUND=y -# CONFIG_SOUND_OSS_CORE is not set CONFIG_SND=y CONFIG_SND_TIMER=y CONFIG_SND_PCM=y +CONFIG_SND_PCM_ELD=y +CONFIG_SND_PCM_IEC958=y CONFIG_SND_DMAENGINE_PCM=y +CONFIG_SND_HWDEP=y +CONFIG_SND_RAWMIDI=y CONFIG_SND_JACK=y CONFIG_SND_JACK_INPUT_DEV=y # CONFIG_SND_OSSEMUL is not set @@ -3135,18 +4354,19 @@ CONFIG_SND_VERBOSE_PROCFS=y # CONFIG_SND_VERBOSE_PRINTK is not set # CONFIG_SND_DEBUG is not set # CONFIG_SND_SEQUENCER is not set -# CONFIG_SND_OPL3_LIB_SEQ is not set -# CONFIG_SND_OPL4_LIB_SEQ is not set # CONFIG_SND_DRIVERS is not set # CONFIG_SND_PCI is not set # # HD-Audio # +# end of HD-Audio + CONFIG_SND_HDA_PREALLOC_SIZE=64 CONFIG_SND_SPI=y CONFIG_SND_USB=y -# CONFIG_SND_USB_AUDIO is not set +CONFIG_SND_USB_AUDIO=y +CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y # CONFIG_SND_USB_UA101 is not set # CONFIG_SND_USB_CAIAQ is not set # CONFIG_SND_USB_6FIRE is not set @@ -3158,8 +4378,13 @@ CONFIG_SND_USB=y # CONFIG_SND_USB_VARIAX is not set CONFIG_SND_SOC=y CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y +CONFIG_SND_SOC_ADI=y +CONFIG_SND_SOC_ADI_AXI_I2S=y +CONFIG_SND_SOC_ADI_AXI_SPDIF=y +CONFIG_SND_SOC_ADRV936X_BOX=y # CONFIG_SND_SOC_AMD_ACP is not set # CONFIG_SND_ATMEL_SOC is not set +# CONFIG_SND_BCM63XX_I2S_WHISTLER is not set # CONFIG_SND_DESIGNWARE_I2S is not set # @@ -3171,20 +4396,31 @@ CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y # # CONFIG_SND_SOC_FSL_ASRC is not set # CONFIG_SND_SOC_FSL_SAI is not set +# CONFIG_SND_SOC_FSL_AUDMIX is not set # CONFIG_SND_SOC_FSL_SSI is not set # CONFIG_SND_SOC_FSL_SPDIF is not set # CONFIG_SND_SOC_FSL_ESAI is not set +# CONFIG_SND_SOC_FSL_MICFIL is not set # CONFIG_SND_SOC_IMX_AUDMUX is not set +# end of SoC Audio for Freescale CPUs + # CONFIG_SND_I2S_HI6210_I2S is not set # CONFIG_SND_SOC_IMG is not set +# CONFIG_SND_SOC_INTEL_KEEMBAY is not set +# CONFIG_SND_SOC_MTK_BTCVSD is not set +# CONFIG_SND_SOC_SOF_TOPLEVEL is not set # # STMicroelectronics STM32 SOC audio support # +# end of STMicroelectronics STM32 SOC audio support + CONFIG_SND_SOC_XILINX_DP=y -# CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set -# CONFIG_SND_SOC_XILINX_SDI is not set -# CONFIG_SND_SOC_XILINX_I2S is not set +CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER=y +CONFIG_SND_SOC_XILINX_SDI=y +CONFIG_SND_SOC_XILINX_I2S=y +CONFIG_SND_SOC_XILINX_SPDIF=y +CONFIG_SND_SOC_XILINX_PL_SND_CARD=y # CONFIG_SND_SOC_XTFPGA_I2S is not set # CONFIG_ZX_TDM is not set CONFIG_SND_SOC_I2C_AND_SPI=y @@ -3193,75 +4429,134 @@ CONFIG_SND_SOC_I2C_AND_SPI=y # CODEC drivers # # CONFIG_SND_SOC_AC97_CODEC is not set -# CONFIG_SND_SOC_ADAU1373 is not set -# CONFIG_SND_SOC_ADAU1701 is not set -# CONFIG_SND_SOC_ADAU1761_I2C is not set -# CONFIG_SND_SOC_ADAU1761_SPI is not set -# CONFIG_SND_SOC_ADAU7002 is not set +CONFIG_SND_SOC_AD1836=y +CONFIG_SND_SOC_AD193X=y +CONFIG_SND_SOC_AD193X_SPI=y +CONFIG_SND_SOC_AD193X_I2C=y +CONFIG_SND_SOC_AD73311=y +CONFIG_SND_SOC_ADAU_UTILS=y +CONFIG_SND_SOC_ADAU1373=y +CONFIG_SND_SOC_ADAU1701=y +CONFIG_SND_SOC_ADAU17X1=y +CONFIG_SND_SOC_ADAU1761=y +CONFIG_SND_SOC_ADAU1761_I2C=y +CONFIG_SND_SOC_ADAU1761_SPI=y +CONFIG_SND_SOC_ADAU1781=y +CONFIG_SND_SOC_ADAU1781_I2C=y +CONFIG_SND_SOC_ADAU1781_SPI=y +CONFIG_SND_SOC_ADAU1977=y +CONFIG_SND_SOC_ADAU1977_SPI=y +CONFIG_SND_SOC_ADAU1977_I2C=y +CONFIG_SND_SOC_ADAU7002=y +CONFIG_SND_SOC_ADAU7118=y +CONFIG_SND_SOC_ADAU7118_HW=y +CONFIG_SND_SOC_ADAU7118_I2C=y +CONFIG_SND_SOC_ADAV80X=y +CONFIG_SND_SOC_ADAV801=y +CONFIG_SND_SOC_ADAV803=y # CONFIG_SND_SOC_AK4104 is not set +# CONFIG_SND_SOC_AK4118 is not set +# CONFIG_SND_SOC_AK4458 is not set # CONFIG_SND_SOC_AK4554 is not set # CONFIG_SND_SOC_AK4613 is not set # CONFIG_SND_SOC_AK4642 is not set # CONFIG_SND_SOC_AK5386 is not set +# CONFIG_SND_SOC_AK5558 is not set # CONFIG_SND_SOC_ALC5623 is not set +# CONFIG_SND_SOC_BD28623 is not set # CONFIG_SND_SOC_BT_SCO is not set # CONFIG_SND_SOC_CS35L32 is not set # CONFIG_SND_SOC_CS35L33 is not set # CONFIG_SND_SOC_CS35L34 is not set # CONFIG_SND_SOC_CS35L35 is not set +# CONFIG_SND_SOC_CS35L36 is not set # CONFIG_SND_SOC_CS42L42 is not set # CONFIG_SND_SOC_CS42L51_I2C is not set # CONFIG_SND_SOC_CS42L52 is not set # CONFIG_SND_SOC_CS42L56 is not set # CONFIG_SND_SOC_CS42L73 is not set +# CONFIG_SND_SOC_CS4234 is not set # CONFIG_SND_SOC_CS4265 is not set # CONFIG_SND_SOC_CS4270 is not set # CONFIG_SND_SOC_CS4271_I2C is not set # CONFIG_SND_SOC_CS4271_SPI is not set # CONFIG_SND_SOC_CS42XX8_I2C is not set # CONFIG_SND_SOC_CS43130 is not set +# CONFIG_SND_SOC_CS4341 is not set # CONFIG_SND_SOC_CS4349 is not set # CONFIG_SND_SOC_CS53L30 is not set -# CONFIG_SND_SOC_DIO2125 is not set +# CONFIG_SND_SOC_CX2072X is not set +# CONFIG_SND_SOC_DA7213 is not set +# CONFIG_SND_SOC_DMIC is not set +CONFIG_SND_SOC_HDMI_CODEC=y # CONFIG_SND_SOC_ES7134 is not set +# CONFIG_SND_SOC_ES7241 is not set # CONFIG_SND_SOC_ES8316 is not set # CONFIG_SND_SOC_ES8328_I2C is not set # CONFIG_SND_SOC_ES8328_SPI is not set # CONFIG_SND_SOC_GTM601 is not set # CONFIG_SND_SOC_INNO_RK3036 is not set +# CONFIG_SND_SOC_MAX98088 is not set +# CONFIG_SND_SOC_MAX98357A is not set # CONFIG_SND_SOC_MAX98504 is not set +# CONFIG_SND_SOC_MAX9867 is not set # CONFIG_SND_SOC_MAX98927 is not set +# CONFIG_SND_SOC_MAX98373_I2C is not set +# CONFIG_SND_SOC_MAX98390 is not set # CONFIG_SND_SOC_MAX9860 is not set # CONFIG_SND_SOC_MSM8916_WCD_DIGITAL is not set # CONFIG_SND_SOC_PCM1681 is not set +# CONFIG_SND_SOC_PCM1789_I2C is not set # CONFIG_SND_SOC_PCM179X_I2C is not set # CONFIG_SND_SOC_PCM179X_SPI is not set +# CONFIG_SND_SOC_PCM186X_I2C is not set +# CONFIG_SND_SOC_PCM186X_SPI is not set +# CONFIG_SND_SOC_PCM3060_I2C is not set +# CONFIG_SND_SOC_PCM3060_SPI is not set # CONFIG_SND_SOC_PCM3168A_I2C is not set # CONFIG_SND_SOC_PCM3168A_SPI is not set # CONFIG_SND_SOC_PCM512x_I2C is not set # CONFIG_SND_SOC_PCM512x_SPI is not set +# CONFIG_SND_SOC_RK3328 is not set # CONFIG_SND_SOC_RT5616 is not set # CONFIG_SND_SOC_RT5631 is not set -# CONFIG_SND_SOC_RT5677_SPI is not set # CONFIG_SND_SOC_SGTL5000 is not set +CONFIG_SND_SOC_SIGMADSP=y +CONFIG_SND_SOC_SIGMADSP_I2C=y +CONFIG_SND_SOC_SIGMADSP_REGMAP=y +# CONFIG_SND_SOC_SIMPLE_AMPLIFIER is not set # CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set # CONFIG_SND_SOC_SPDIF is not set -# CONFIG_SND_SOC_SSM2602_SPI is not set -# CONFIG_SND_SOC_SSM2602_I2C is not set -# CONFIG_SND_SOC_SSM4567 is not set +CONFIG_SND_SOC_SSM2305=y +CONFIG_SND_SOC_SSM2518=y +CONFIG_SND_SOC_SSM2602=y +CONFIG_SND_SOC_SSM2602_SPI=y +CONFIG_SND_SOC_SSM2602_I2C=y +CONFIG_SND_SOC_SSM4567=y # CONFIG_SND_SOC_STA32X is not set # CONFIG_SND_SOC_STA350 is not set # CONFIG_SND_SOC_STI_SAS is not set # CONFIG_SND_SOC_TAS2552 is not set +# CONFIG_SND_SOC_TAS2562 is not set +# CONFIG_SND_SOC_TAS2764 is not set +# CONFIG_SND_SOC_TAS2770 is not set # CONFIG_SND_SOC_TAS5086 is not set # CONFIG_SND_SOC_TAS571X is not set # CONFIG_SND_SOC_TAS5720 is not set +# CONFIG_SND_SOC_TAS6424 is not set +# CONFIG_SND_SOC_TDA7419 is not set # CONFIG_SND_SOC_TFA9879 is not set # CONFIG_SND_SOC_TLV320AIC23_I2C is not set # CONFIG_SND_SOC_TLV320AIC23_SPI is not set # CONFIG_SND_SOC_TLV320AIC31XX is not set +# CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set +# CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set # CONFIG_SND_SOC_TLV320AIC3X is not set -# CONFIG_SND_SOC_TS3A227E is not set +# CONFIG_SND_SOC_TLV320ADCX140 is not set +CONFIG_SND_SOC_TS3A227E=y +# CONFIG_SND_SOC_TSCS42XX is not set +# CONFIG_SND_SOC_TSCS454 is not set +# CONFIG_SND_SOC_UDA1334 is not set # CONFIG_SND_SOC_WM8510 is not set # CONFIG_SND_SOC_WM8523 is not set # CONFIG_SND_SOC_WM8524 is not set @@ -3275,23 +4570,32 @@ CONFIG_SND_SOC_I2C_AND_SPI=y # CONFIG_SND_SOC_WM8753 is not set # CONFIG_SND_SOC_WM8770 is not set # CONFIG_SND_SOC_WM8776 is not set +# CONFIG_SND_SOC_WM8782 is not set # CONFIG_SND_SOC_WM8804_I2C is not set # CONFIG_SND_SOC_WM8804_SPI is not set # CONFIG_SND_SOC_WM8903 is not set +# CONFIG_SND_SOC_WM8904 is not set # CONFIG_SND_SOC_WM8960 is not set # CONFIG_SND_SOC_WM8962 is not set # CONFIG_SND_SOC_WM8974 is not set # CONFIG_SND_SOC_WM8978 is not set # CONFIG_SND_SOC_WM8985 is not set +# CONFIG_SND_SOC_ZL38060 is not set # CONFIG_SND_SOC_ZX_AUD96P22 is not set +# CONFIG_SND_SOC_MAX9759 is not set +# CONFIG_SND_SOC_MT6351 is not set +# CONFIG_SND_SOC_MT6358 is not set +# CONFIG_SND_SOC_MT6660 is not set # CONFIG_SND_SOC_NAU8540 is not set # CONFIG_SND_SOC_NAU8810 is not set +# CONFIG_SND_SOC_NAU8822 is not set # CONFIG_SND_SOC_NAU8824 is not set # CONFIG_SND_SOC_TPA6130A2 is not set -# CONFIG_SND_SIMPLE_CARD is not set -# CONFIG_SND_SIMPLE_SCU_CARD is not set +# end of CODEC drivers + +CONFIG_SND_SIMPLE_CARD_UTILS=y +CONFIG_SND_SIMPLE_CARD=y # CONFIG_SND_AUDIO_GRAPH_CARD is not set -# CONFIG_SND_AUDIO_GRAPH_SCU_CARD is not set # # HID support @@ -3314,29 +4618,37 @@ CONFIG_HID_GENERIC=y # CONFIG_HID_AUREAL is not set # CONFIG_HID_BELKIN is not set # CONFIG_HID_BETOP_FF is not set +# CONFIG_HID_BIGBEN_FF is not set # CONFIG_HID_CHERRY is not set # CONFIG_HID_CHICONY is not set # CONFIG_HID_CORSAIR is not set +# CONFIG_HID_COUGAR is not set +# CONFIG_HID_MACALLY is not set # CONFIG_HID_PRODIKEYS is not set # CONFIG_HID_CMEDIA is not set -# CONFIG_HID_CP2112 is not set +# CONFIG_HID_CREATIVE_SB0540 is not set # CONFIG_HID_CYPRESS is not set # CONFIG_HID_DRAGONRISE is not set # CONFIG_HID_EMS_FF is not set +# CONFIG_HID_ELAN is not set # CONFIG_HID_ELECOM is not set # CONFIG_HID_ELO is not set # CONFIG_HID_EZKEY is not set # CONFIG_HID_GEMBIRD is not set # CONFIG_HID_GFRM is not set +# CONFIG_HID_GLORIOUS is not set # CONFIG_HID_HOLTEK is not set +# CONFIG_HID_VIVALDI is not set # CONFIG_HID_GT683R is not set # CONFIG_HID_KEYTOUCH is not set # CONFIG_HID_KYE is not set # CONFIG_HID_UCLOGIC is not set # CONFIG_HID_WALTOP is not set +# CONFIG_HID_VIEWSONIC is not set # CONFIG_HID_GYRATION is not set # CONFIG_HID_ICADE is not set # CONFIG_HID_ITE is not set +# CONFIG_HID_JABRA is not set # CONFIG_HID_TWINHAN is not set # CONFIG_HID_KENSINGTON is not set # CONFIG_HID_LCPOWER is not set @@ -3344,7 +4656,9 @@ CONFIG_HID_GENERIC=y # CONFIG_HID_LENOVO is not set # CONFIG_HID_LOGITECH is not set # CONFIG_HID_MAGICMOUSE is not set +# CONFIG_HID_MALTRON is not set # CONFIG_HID_MAYFLASH is not set +# CONFIG_HID_REDRAGON is not set # CONFIG_HID_MICROSOFT is not set # CONFIG_HID_MONTEREY is not set # CONFIG_HID_MULTITOUCH is not set @@ -3363,6 +4677,7 @@ CONFIG_HID_GENERIC=y # CONFIG_HID_SAMSUNG is not set # CONFIG_HID_SONY is not set # CONFIG_HID_SPEEDLINK is not set +# CONFIG_HID_STEAM is not set # CONFIG_HID_STEELSERIES is not set # CONFIG_HID_SUNPLUS is not set # CONFIG_HID_RMI is not set @@ -3380,21 +4695,30 @@ CONFIG_HID_GENERIC=y # CONFIG_HID_ZYDACRON is not set # CONFIG_HID_SENSOR_HUB is not set # CONFIG_HID_ALPS is not set +# CONFIG_HID_MCP2221 is not set +# end of Special HID drivers # # USB HID support # CONFIG_USB_HID=y # CONFIG_HID_PID is not set -# CONFIG_USB_HIDDEV is not set +CONFIG_USB_HIDDEV=y +# end of USB HID support # # I2C HID support # # CONFIG_I2C_HID is not set +# end of I2C HID support +# end of HID support + CONFIG_USB_OHCI_LITTLE_ENDIAN=y CONFIG_USB_SUPPORT=y CONFIG_USB_COMMON=y +# CONFIG_USB_LED_TRIG is not set +CONFIG_USB_ULPI_BUS=y +# CONFIG_USB_CONN_GPIO is not set CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB=y CONFIG_USB_PCI=y @@ -3403,27 +4727,34 @@ CONFIG_USB_ANNOUNCE_NEW_DEVICES=y # # Miscellaneous USB options # -# CONFIG_USB_DEFAULT_PERSIST is not set +CONFIG_USB_DEFAULT_PERSIST=y +# CONFIG_USB_FEW_INIT_RETRIES is not set # CONFIG_USB_DYNAMIC_MINORS is not set CONFIG_USB_OTG=y -# CONFIG_USB_OTG_WHITELIST is not set -# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_OTG_PRODUCTLIST is not set +# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set CONFIG_USB_OTG_FSM=y # CONFIG_USB_LEDS_TRIGGER_USBPORT is not set +CONFIG_USB_AUTOSUSPEND_DELAY=2 # CONFIG_USB_MON is not set -# CONFIG_USB_WUSB_CBAF is not set # # USB Host Controller Drivers # # CONFIG_USB_C67X00_HCD is not set CONFIG_USB_XHCI_HCD=y +# CONFIG_USB_XHCI_DBGCAP is not set CONFIG_USB_XHCI_PCI=y +# CONFIG_USB_XHCI_PCI_RENESAS is not set CONFIG_USB_XHCI_PLATFORM=y -# CONFIG_USB_EHCI_HCD is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +CONFIG_USB_EHCI_PCI=y +# CONFIG_USB_EHCI_FSL is not set +# CONFIG_USB_EHCI_HCD_PLATFORM is not set # CONFIG_USB_OXU210HP_HCD is not set # CONFIG_USB_ISP116X_HCD is not set -# CONFIG_USB_ISP1362_HCD is not set # CONFIG_USB_FOTG210_HCD is not set # CONFIG_USB_MAX3421_HCD is not set # CONFIG_USB_OHCI_HCD is not set @@ -3470,25 +4801,99 @@ CONFIG_USB_UAS=y # CONFIG_USB_MDC800 is not set # CONFIG_USB_MICROTEK is not set # CONFIG_USBIP_CORE is not set +# CONFIG_USB_CDNS3 is not set # CONFIG_USB_MUSB_HDRC is not set CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_ULPI=y # CONFIG_USB_DWC3_HOST is not set # CONFIG_USB_DWC3_GADGET is not set -# CONFIG_USB_DWC3_DUAL_ROLE is not set -CONFIG_USB_DWC3_OTG=y +CONFIG_USB_DWC3_DUAL_ROLE=y +# CONFIG_USB_DWC3_OTG is not set # # Platform Glue Driver Support # +CONFIG_USB_DWC3_HAPS=y CONFIG_USB_DWC3_OF_SIMPLE=y -# CONFIG_USB_DWC2 is not set -# CONFIG_USB_CHIPIDEA is not set +CONFIG_USB_DWC3_XILINX=y +CONFIG_USB_DWC2=y +# CONFIG_USB_DWC2_HOST is not set + +# +# Gadget/Dual-role mode requires USB Gadget support to be enabled +# +# CONFIG_USB_DWC2_PERIPHERAL is not set +CONFIG_USB_DWC2_DUAL_ROLE=y +# CONFIG_USB_DWC2_PCI is not set +# CONFIG_USB_DWC2_DEBUG is not set +# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set +CONFIG_USB_CHIPIDEA=y +CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_CHIPIDEA_PCI=y +CONFIG_USB_CHIPIDEA_MSM=y +CONFIG_USB_CHIPIDEA_IMX=y +CONFIG_USB_CHIPIDEA_GENERIC=y +CONFIG_USB_CHIPIDEA_TEGRA=y # CONFIG_USB_ISP1760 is not set # # USB port drivers # -# CONFIG_USB_SERIAL is not set +CONFIG_USB_SERIAL=y +# CONFIG_USB_SERIAL_CONSOLE is not set +CONFIG_USB_SERIAL_GENERIC=y +# CONFIG_USB_SERIAL_SIMPLE is not set +# CONFIG_USB_SERIAL_AIRCABLE is not set +# CONFIG_USB_SERIAL_ARK3116 is not set +# CONFIG_USB_SERIAL_BELKIN is not set +# CONFIG_USB_SERIAL_CH341 is not set +# CONFIG_USB_SERIAL_WHITEHEAT is not set +# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set +# CONFIG_USB_SERIAL_CP210X is not set +# CONFIG_USB_SERIAL_CYPRESS_M8 is not set +# CONFIG_USB_SERIAL_EMPEG is not set +CONFIG_USB_SERIAL_FTDI_SIO=y +# CONFIG_USB_SERIAL_VISOR is not set +# CONFIG_USB_SERIAL_IPAQ is not set +# CONFIG_USB_SERIAL_IR is not set +# CONFIG_USB_SERIAL_EDGEPORT is not set +# CONFIG_USB_SERIAL_EDGEPORT_TI is not set +# CONFIG_USB_SERIAL_F81232 is not set +# CONFIG_USB_SERIAL_F8153X is not set +# CONFIG_USB_SERIAL_GARMIN is not set +# CONFIG_USB_SERIAL_IPW is not set +# CONFIG_USB_SERIAL_IUU is not set +# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set +# CONFIG_USB_SERIAL_KEYSPAN is not set +# CONFIG_USB_SERIAL_KLSI is not set +# CONFIG_USB_SERIAL_KOBIL_SCT is not set +# CONFIG_USB_SERIAL_MCT_U232 is not set +# CONFIG_USB_SERIAL_METRO is not set +# CONFIG_USB_SERIAL_MOS7720 is not set +# CONFIG_USB_SERIAL_MOS7840 is not set +# CONFIG_USB_SERIAL_MXUPORT is not set +# CONFIG_USB_SERIAL_NAVMAN is not set +# CONFIG_USB_SERIAL_PL2303 is not set +# CONFIG_USB_SERIAL_OTI6858 is not set +# CONFIG_USB_SERIAL_QCAUX is not set +# CONFIG_USB_SERIAL_QUALCOMM is not set +# CONFIG_USB_SERIAL_SPCP8X5 is not set +# CONFIG_USB_SERIAL_SAFE is not set +# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set +# CONFIG_USB_SERIAL_SYMBOL is not set +# CONFIG_USB_SERIAL_TI is not set +# CONFIG_USB_SERIAL_CYBERJACK is not set +# CONFIG_USB_SERIAL_XIRCOM is not set +# CONFIG_USB_SERIAL_OPTION is not set +# CONFIG_USB_SERIAL_OMNINET is not set +# CONFIG_USB_SERIAL_OPTICON is not set +# CONFIG_USB_SERIAL_XSENS_MT is not set +# CONFIG_USB_SERIAL_WISHBONE is not set +# CONFIG_USB_SERIAL_SSU100 is not set +# CONFIG_USB_SERIAL_QT2 is not set +CONFIG_USB_SERIAL_UPD78F0730=y +# CONFIG_USB_SERIAL_DEBUG is not set # # USB Miscellaneous drivers @@ -3497,7 +4902,6 @@ CONFIG_USB_DWC3_OF_SIMPLE=y # CONFIG_USB_EMI26 is not set # CONFIG_USB_ADUTUX is not set # CONFIG_USB_SEVSEG is not set -# CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set # CONFIG_USB_CYPRESS_CY7C63 is not set @@ -3505,6 +4909,8 @@ CONFIG_USB_DWC3_OF_SIMPLE=y # CONFIG_USB_IDMOUSE is not set # CONFIG_USB_FTDI_ELAN is not set # CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_APPLE_MFI_FASTCHARGE is not set +# CONFIG_USB_SISUSBVGA is not set # CONFIG_USB_LD is not set # CONFIG_USB_TRANCEVIBRATOR is not set # CONFIG_USB_IOWARRIOR is not set @@ -3514,6 +4920,7 @@ CONFIG_USB_DWC3_OF_SIMPLE=y # CONFIG_USB_YUREX is not set # CONFIG_USB_EZUSB_FX2 is not set # CONFIG_USB_HUB_USB251XB is not set +# CONFIG_USB_USB5744 is not set # CONFIG_USB_HSIC_USB3503 is not set # CONFIG_USB_HSIC_USB4604 is not set # CONFIG_USB_LINK_LAYER_TEST is not set @@ -3522,10 +4929,13 @@ CONFIG_USB_DWC3_OF_SIMPLE=y # USB Physical Layer drivers # CONFIG_USB_PHY=y -# CONFIG_NOP_USB_XCEIV is not set +CONFIG_NOP_USB_XCEIV=y # CONFIG_USB_GPIO_VBUS is not set # CONFIG_USB_ISP1301 is not set -# CONFIG_USB_ULPI is not set +CONFIG_USB_ULPI=y +CONFIG_USB_ULPI_VIEWPORT=y +# end of USB Physical Layer drivers + CONFIG_USB_GADGET=y # CONFIG_USB_GADGET_DEBUG is not set # CONFIG_USB_GADGET_DEBUG_FILES is not set @@ -3552,25 +4962,30 @@ CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 # CONFIG_USB_GOKU is not set # CONFIG_USB_EG20T is not set CONFIG_USB_GADGET_XILINX=y +# CONFIG_USB_MAX3420_UDC is not set # CONFIG_USB_DUMMY_HCD is not set +# end of USB Peripheral Controller + CONFIG_USB_LIBCOMPOSITE=y CONFIG_USB_F_ACM=y CONFIG_USB_U_SERIAL=y CONFIG_USB_U_ETHER=y -CONFIG_USB_F_ECM=m +CONFIG_USB_F_SERIAL=y +CONFIG_USB_F_NCM=y +CONFIG_USB_F_ECM=y CONFIG_USB_F_EEM=y -CONFIG_USB_F_SUBSET=m -CONFIG_USB_F_RNDIS=m +CONFIG_USB_F_SUBSET=y +CONFIG_USB_F_RNDIS=y CONFIG_USB_F_MASS_STORAGE=y CONFIG_USB_F_FS=y CONFIG_USB_CONFIGFS=y -# CONFIG_USB_CONFIGFS_SERIAL is not set +CONFIG_USB_CONFIGFS_SERIAL=y CONFIG_USB_CONFIGFS_ACM=y # CONFIG_USB_CONFIGFS_OBEX is not set -# CONFIG_USB_CONFIGFS_NCM is not set -# CONFIG_USB_CONFIGFS_ECM is not set -# CONFIG_USB_CONFIGFS_ECM_SUBSET is not set -# CONFIG_USB_CONFIGFS_RNDIS is not set +CONFIG_USB_CONFIGFS_NCM=y +CONFIG_USB_CONFIGFS_ECM=y +CONFIG_USB_CONFIGFS_ECM_SUBSET=y +CONFIG_USB_CONFIGFS_RNDIS=y CONFIG_USB_CONFIGFS_EEM=y CONFIG_USB_CONFIGFS_MASS_STORAGE=y # CONFIG_USB_CONFIGFS_F_LB_SS is not set @@ -3582,15 +4997,17 @@ CONFIG_USB_CONFIGFS_F_FS=y # CONFIG_USB_CONFIGFS_F_HID is not set # CONFIG_USB_CONFIGFS_F_UVC is not set # CONFIG_USB_CONFIGFS_F_PRINTER is not set + +# +# USB Gadget precomposed configurations +# # CONFIG_USB_ZERO is not set # CONFIG_USB_AUDIO is not set -CONFIG_USB_ETH=m -CONFIG_USB_ETH_RNDIS=y -CONFIG_USB_ETH_EEM=y +# CONFIG_USB_ETH is not set # CONFIG_USB_G_NCM is not set # CONFIG_USB_GADGETFS is not set # CONFIG_USB_FUNCTIONFS is not set -CONFIG_USB_MASS_STORAGE=m +# CONFIG_USB_MASS_STORAGE is not set # CONFIG_USB_G_SERIAL is not set # CONFIG_USB_MIDI_GADGET is not set # CONFIG_USB_G_PRINTER is not set @@ -3600,14 +5017,29 @@ CONFIG_USB_MASS_STORAGE=m # CONFIG_USB_G_HID is not set # CONFIG_USB_G_DBGP is not set # CONFIG_USB_G_WEBCAM is not set +# CONFIG_USB_RAW_GADGET is not set +# end of USB Gadget precomposed configurations + +CONFIG_TYPEC=y +# CONFIG_TYPEC_TCPM is not set +# CONFIG_TYPEC_UCSI is not set +# CONFIG_TYPEC_HD3SS3220 is not set +CONFIG_TYPEC_TPS6598X=y +# CONFIG_TYPEC_STUSB160X is not set # -# USB Power Delivery and Type-C drivers +# USB Type-C Multiplexer/DeMultiplexer Switch support # -# CONFIG_TYPEC_UCSI is not set -# CONFIG_USB_LED_TRIG is not set -# CONFIG_USB_ULPI_BUS is not set -# CONFIG_UWB is not set +# CONFIG_TYPEC_MUX_PI3USB30532 is not set +# end of USB Type-C Multiplexer/DeMultiplexer Switch support + +# +# USB Type-C Alternate Mode drivers +# +# CONFIG_TYPEC_DP_ALTMODE is not set +# end of USB Type-C Alternate Mode drivers + +CONFIG_USB_ROLE_SWITCH=y CONFIG_MMC=y CONFIG_PWRSEQ_EMMC=y # CONFIG_PWRSEQ_SD8787 is not set @@ -3626,52 +5058,69 @@ CONFIG_MMC_SDHCI=y # CONFIG_MMC_SDHCI_PCI is not set CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SDHCI_OF_ARASAN=y +# CONFIG_MMC_SDHCI_OF_ASPEED is not set # CONFIG_MMC_SDHCI_OF_AT91 is not set +# CONFIG_MMC_SDHCI_OF_DWCMSHC is not set # CONFIG_MMC_SDHCI_CADENCE is not set # CONFIG_MMC_SDHCI_F_SDH30 is not set +# CONFIG_MMC_SDHCI_MILBEAUT is not set # CONFIG_MMC_TIFM_SD is not set # CONFIG_MMC_SPI is not set # CONFIG_MMC_CB710 is not set # CONFIG_MMC_VIA_SDMMC is not set -# CONFIG_MMC_CAVIUM_THUNDERX is not set # CONFIG_MMC_DW is not set # CONFIG_MMC_VUB300 is not set # CONFIG_MMC_USHC is not set # CONFIG_MMC_USDHI6ROL0 is not set +CONFIG_MMC_CQHCI=y +# CONFIG_MMC_HSQ is not set # CONFIG_MMC_TOSHIBA_PCI is not set # CONFIG_MMC_MTK is not set # CONFIG_MMC_SDHCI_XENON is not set +# CONFIG_MMC_SDHCI_OMAP is not set +# CONFIG_MMC_SDHCI_AM654 is not set # CONFIG_MEMSTICK is not set CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y -# CONFIG_LEDS_CLASS_FLASH is not set -# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set +CONFIG_LEDS_CLASS_FLASH=y +# CONFIG_LEDS_CLASS_MULTICOLOR is not set +CONFIG_LEDS_BRIGHTNESS_HW_CHANGED=y # # LED drivers # +# CONFIG_LEDS_AAT1290 is not set +# CONFIG_LEDS_AN30259A is not set +CONFIG_LEDS_AS3645A=y +# CONFIG_LEDS_AW2013 is not set # CONFIG_LEDS_BCM6328 is not set # CONFIG_LEDS_BCM6358 is not set +# CONFIG_LEDS_CR0014114 is not set +# CONFIG_LEDS_EL15203000 is not set # CONFIG_LEDS_LM3530 is not set +# CONFIG_LEDS_LM3532 is not set # CONFIG_LEDS_LM3642 is not set +# CONFIG_LEDS_LM3692X is not set +# CONFIG_LEDS_LM3601X is not set # CONFIG_LEDS_PCA9532 is not set CONFIG_LEDS_GPIO=y # CONFIG_LEDS_LP3944 is not set # CONFIG_LEDS_LP3952 is not set -# CONFIG_LEDS_LP5521 is not set -# CONFIG_LEDS_LP5523 is not set -# CONFIG_LEDS_LP5562 is not set -# CONFIG_LEDS_LP8501 is not set +# CONFIG_LEDS_LP50XX is not set +# CONFIG_LEDS_LP55XX_COMMON is not set # CONFIG_LEDS_LP8860 is not set # CONFIG_LEDS_PCA955X is not set # CONFIG_LEDS_PCA963X is not set # CONFIG_LEDS_DAC124S085 is not set +# CONFIG_LEDS_PWM is not set # CONFIG_LEDS_REGULATOR is not set # CONFIG_LEDS_BD2802 is not set # CONFIG_LEDS_LT3593 is not set +CONFIG_LEDS_ADP5520=y # CONFIG_LEDS_TCA6507 is not set # CONFIG_LEDS_TLC591XX is not set # CONFIG_LEDS_LM355x is not set +# CONFIG_LEDS_KTD2692 is not set # CONFIG_LEDS_IS31FL319X is not set # CONFIG_LEDS_IS31FL32XX is not set @@ -3679,7 +5128,11 @@ CONFIG_LEDS_GPIO=y # LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM) # # CONFIG_LEDS_BLINKM is not set +# CONFIG_LEDS_MLXREG is not set # CONFIG_LEDS_USER is not set +# CONFIG_LEDS_SPI_BYTE is not set +# CONFIG_LEDS_TI_LMU_COMMON is not set +# CONFIG_LEDS_SGM3140 is not set # # LED Triggers @@ -3692,6 +5145,7 @@ CONFIG_LEDS_TRIGGER_ONESHOT=y CONFIG_LEDS_TRIGGER_HEARTBEAT=y CONFIG_LEDS_TRIGGER_BACKLIGHT=y CONFIG_LEDS_TRIGGER_CPU=y +# CONFIG_LEDS_TRIGGER_ACTIVITY is not set CONFIG_LEDS_TRIGGER_GPIO=y CONFIG_LEDS_TRIGGER_DEFAULT_ON=y @@ -3701,9 +5155,21 @@ CONFIG_LEDS_TRIGGER_DEFAULT_ON=y CONFIG_LEDS_TRIGGER_TRANSIENT=y CONFIG_LEDS_TRIGGER_CAMERA=y # CONFIG_LEDS_TRIGGER_PANIC is not set +# CONFIG_LEDS_TRIGGER_NETDEV is not set +# CONFIG_LEDS_TRIGGER_PATTERN is not set +# CONFIG_LEDS_TRIGGER_AUDIO is not set # CONFIG_ACCESSIBILITY is not set # CONFIG_INFINIBAND is not set CONFIG_EDAC_SUPPORT=y +CONFIG_EDAC=y +CONFIG_EDAC_LEGACY_SYSFS=y +# CONFIG_EDAC_DEBUG is not set +# CONFIG_EDAC_THUNDERX is not set +CONFIG_EDAC_SYNOPSYS=y +CONFIG_EDAC_ZYNQMP_OCM=y +# CONFIG_EDAC_XGENE is not set +# CONFIG_EDAC_DMC520 is not set +# CONFIG_EDAC_XILINX_DDR is not set CONFIG_RTC_LIB=y CONFIG_RTC_CLASS=y CONFIG_RTC_HCTOSYS=y @@ -3726,6 +5192,7 @@ CONFIG_RTC_INTF_DEV=y # I2C RTC drivers # # CONFIG_RTC_DRV_ABB5ZES3 is not set +# CONFIG_RTC_DRV_ABEOZ9 is not set # CONFIG_RTC_DRV_ABX80X is not set # CONFIG_RTC_DRV_DS1307 is not set # CONFIG_RTC_DRV_DS1374 is not set @@ -3735,9 +5202,11 @@ CONFIG_RTC_INTF_DEV=y # CONFIG_RTC_DRV_RS5C372 is not set # CONFIG_RTC_DRV_ISL1208 is not set # CONFIG_RTC_DRV_ISL12022 is not set +# CONFIG_RTC_DRV_ISL12026 is not set # CONFIG_RTC_DRV_X1205 is not set # CONFIG_RTC_DRV_PCF8523 is not set # CONFIG_RTC_DRV_PCF85063 is not set +# CONFIG_RTC_DRV_PCF85363 is not set # CONFIG_RTC_DRV_PCF8563 is not set # CONFIG_RTC_DRV_PCF8583 is not set # CONFIG_RTC_DRV_M41T80 is not set @@ -3748,7 +5217,10 @@ CONFIG_RTC_INTF_DEV=y # CONFIG_RTC_DRV_RX8581 is not set # CONFIG_RTC_DRV_RX8025 is not set # CONFIG_RTC_DRV_EM3027 is not set +# CONFIG_RTC_DRV_RV3028 is not set +# CONFIG_RTC_DRV_RV3032 is not set # CONFIG_RTC_DRV_RV8803 is not set +# CONFIG_RTC_DRV_SD3078 is not set # # SPI RTC drivers @@ -3802,14 +5274,13 @@ CONFIG_RTC_DRV_ZYNQMP=y # # CONFIG_RTC_DRV_PL030 is not set # CONFIG_RTC_DRV_PL031 is not set +# CONFIG_RTC_DRV_CADENCE is not set # CONFIG_RTC_DRV_FTRTC010 is not set -# CONFIG_RTC_DRV_SNVS is not set # CONFIG_RTC_DRV_R7301 is not set # # HID Sensor RTC drivers # -# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set CONFIG_DMADEVICES=y # CONFIG_DMADEVICES_DEBUG is not set @@ -3821,39 +5292,49 @@ CONFIG_DMA_VIRTUAL_CHANNELS=y CONFIG_DMA_OF=y # CONFIG_ALTERA_MSGDMA is not set # CONFIG_AMBA_PL08X is not set -CONFIG_AXI_DMAC=y +CONFIG_AXI_DMAC=m # CONFIG_BCM_SBA_RAID is not set +# CONFIG_DW_AXI_DMAC is not set # CONFIG_FSL_EDMA is not set +# CONFIG_FSL_QDMA is not set +# CONFIG_HISI_DMA is not set # CONFIG_INTEL_IDMA64 is not set # CONFIG_MV_XOR_V2 is not set # CONFIG_PL330_DMA is not set -CONFIG_XILINX_DMA_ENGINES=y -CONFIG_XILINX_DMATEST=m -# CONFIG_XILINX_VDMATEST is not set -# CONFIG_XILINX_CDMATEST is not set -CONFIG_XILINX_DPDMA=y -# CONFIG_XILINX_DPDMA_DEBUG_FS is not set -CONFIG_XILINX_FRMBUF=y +# CONFIG_PLX_DMA is not set CONFIG_XILINX_DMA=m CONFIG_XILINX_ZYNQMP_DMA=y +CONFIG_XILINX_ZYNQMP_DPDMA=y +CONFIG_XILINX_FRMBUF=y # CONFIG_XILINX_PS_PCIE_DMA is not set # CONFIG_QCOM_HIDMA_MGMT is not set # CONFIG_QCOM_HIDMA is not set # CONFIG_DW_DMAC is not set # CONFIG_DW_DMAC_PCI is not set +# CONFIG_DW_EDMA is not set +# CONFIG_DW_EDMA_PCIE is not set +# CONFIG_SF_PDMA is not set # # DMA Clients # # CONFIG_ASYNC_TX_DMA is not set -CONFIG_DMATEST=y +CONFIG_DMATEST=m CONFIG_DMA_ENGINE_RAID=y +CONFIG_XILINX_DMATEST=m +# CONFIG_XILINX_VDMATEST is not set # # DMABUF options # CONFIG_SYNC_FILE=y # CONFIG_SW_SYNC is not set +# CONFIG_UDMABUF is not set +# CONFIG_DMABUF_MOVE_NOTIFY is not set +# CONFIG_DMABUF_SELFTESTS is not set +# CONFIG_DMABUF_HEAPS is not set +# end of DMABUF options + # CONFIG_AUXDISPLAY is not set CONFIG_UIO=y # CONFIG_UIO_CIF is not set @@ -3866,21 +5347,27 @@ CONFIG_UIO_DMEM_GENIRQ=m # CONFIG_UIO_PRUSS is not set # CONFIG_UIO_MF624 is not set CONFIG_UIO_XILINX_APM=y +# CONFIG_UIO_XILINX_AI_ENGINE is not set # CONFIG_VFIO is not set # CONFIG_VIRT_DRIVERS is not set - -# -# Virtio drivers -# +CONFIG_VIRTIO=y +CONFIG_VIRTIO_MENU=y # CONFIG_VIRTIO_PCI is not set +# CONFIG_VIRTIO_BALLOON is not set +# CONFIG_VIRTIO_INPUT is not set # CONFIG_VIRTIO_MMIO is not set +# CONFIG_VDPA is not set +CONFIG_VHOST_MENU=y +# CONFIG_VHOST_NET is not set +# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set # # Microsoft Hyper-V guest support # -# CONFIG_HYPERV_TSCPAGE is not set +# end of Microsoft Hyper-V guest support + +# CONFIG_GREYBUS is not set CONFIG_STAGING=y -# CONFIG_IRDA is not set # CONFIG_PRISM2_USB is not set # CONFIG_COMEDI is not set # CONFIG_RTL8192U is not set @@ -3888,7 +5375,6 @@ CONFIG_STAGING=y # CONFIG_RTL8723BS is not set # CONFIG_R8712U is not set # CONFIG_R8188EU is not set -# CONFIG_R8822BE is not set # CONFIG_RTS5208 is not set # CONFIG_VT6655 is not set # CONFIG_VT6656 is not set @@ -3900,131 +5386,165 @@ CONFIG_STAGING=y # # Accelerometers # -# CONFIG_ADIS16201 is not set -# CONFIG_ADIS16203 is not set -# CONFIG_ADIS16209 is not set -# CONFIG_ADIS16240 is not set +CONFIG_ADIS16203=y +CONFIG_ADIS16240=y +# end of Accelerometers # # Analog to digital converters # -# CONFIG_AD7780 is not set -# CONFIG_AD7816 is not set -# CONFIG_AD7192 is not set -# CONFIG_AD7280 is not set +CONFIG_AD7816=y +CONFIG_AD7280=y +# end of Analog to digital converters # # Analog digital bi-direction converters # -# CONFIG_ADT7316 is not set +CONFIG_ADT7316=y +CONFIG_ADT7316_SPI=y +CONFIG_ADT7316_I2C=y +# end of Analog digital bi-direction converters # # Capacitance to digital converters # -# CONFIG_AD7150 is not set -# CONFIG_AD7152 is not set -# CONFIG_AD7746 is not set +CONFIG_AD7150=y +CONFIG_AD7746=y +# end of Capacitance to digital converters # # Direct Digital Synthesis # -# CONFIG_AD9832 is not set -# CONFIG_AD9834 is not set - -# -# Digital gyroscope sensors -# -# CONFIG_ADIS16060 is not set +CONFIG_AD9832=y +CONFIG_AD9834=y +# end of Direct Digital Synthesis # # Network Analyzer, Impedance Converters # -# CONFIG_AD5933 is not set - -# -# Light sensors -# -# CONFIG_TSL2x7x is not set +CONFIG_AD5933=y +# end of Network Analyzer, Impedance Converters # # Active energy metering IC # -# CONFIG_ADE7753 is not set -# CONFIG_ADE7754 is not set -# CONFIG_ADE7758 is not set -# CONFIG_ADE7759 is not set -# CONFIG_ADE7854 is not set +CONFIG_ADE7854=y +CONFIG_ADE7854_I2C=y +CONFIG_ADE7854_SPI=y +# end of Active energy metering IC # # Resolver to digital converters # -# CONFIG_AD2S90 is not set -# CONFIG_AD2S1200 is not set -# CONFIG_AD2S1210 is not set +CONFIG_AD2S1210=y +# end of Resolver to digital converters +# end of IIO staging drivers -# -# Triggers - standalone -# # CONFIG_FB_SM750 is not set -# CONFIG_FB_XGI is not set - -# -# Speakup console speech -# -# CONFIG_SPEAKUP is not set # CONFIG_STAGING_MEDIA is not set # # Android # +# CONFIG_ASHMEM is not set +CONFIG_ION=y +CONFIG_ION_SYSTEM_HEAP=y +CONFIG_ION_CMA_HEAP=y +# end of Android + # CONFIG_STAGING_BOARD is not set # CONFIG_LTE_GDM724X is not set -# CONFIG_MTD_SPINAND_MT29F is not set -# CONFIG_LNET is not set -# CONFIG_DGNC is not set # CONFIG_GS_FPGABOOT is not set +# CONFIG_UNISYSSPAR is not set # CONFIG_XILINX_APF is not set -CONFIG_COMMON_CLK_XLNX_CLKWZRD=y -# CONFIG_FB_TFT is not set -# CONFIG_WILC1000_SDIO is not set -# CONFIG_WILC1000_SPI is not set -# CONFIG_MOST is not set +CONFIG_FB_TFT=y +# CONFIG_FB_TFT_AGM1264K_FL is not set +# CONFIG_FB_TFT_BD663474 is not set +# CONFIG_FB_TFT_HX8340BN is not set +# CONFIG_FB_TFT_HX8347D is not set +# CONFIG_FB_TFT_HX8353D is not set +# CONFIG_FB_TFT_HX8357D is not set +# CONFIG_FB_TFT_ILI9163 is not set +# CONFIG_FB_TFT_ILI9320 is not set +# CONFIG_FB_TFT_ILI9325 is not set +# CONFIG_FB_TFT_ILI9340 is not set +# CONFIG_FB_TFT_ILI9341 is not set +# CONFIG_FB_TFT_ILI9481 is not set +# CONFIG_FB_TFT_ILI9486 is not set +# CONFIG_FB_TFT_PCD8544 is not set +# CONFIG_FB_TFT_RA8875 is not set +# CONFIG_FB_TFT_S6D02A1 is not set +# CONFIG_FB_TFT_S6D1121 is not set +CONFIG_FB_TFT_SEPS525=y +# CONFIG_FB_TFT_SH1106 is not set +# CONFIG_FB_TFT_SSD1289 is not set +# CONFIG_FB_TFT_SSD1305 is not set +# CONFIG_FB_TFT_SSD1306 is not set +# CONFIG_FB_TFT_SSD1331 is not set +# CONFIG_FB_TFT_SSD1351 is not set +# CONFIG_FB_TFT_ST7735R is not set +# CONFIG_FB_TFT_ST7789V is not set +# CONFIG_FB_TFT_TINYLCD is not set +# CONFIG_FB_TFT_TLS8204 is not set +# CONFIG_FB_TFT_UC1611 is not set +# CONFIG_FB_TFT_UC1701 is not set +# CONFIG_FB_TFT_UPD161704 is not set +# CONFIG_FB_TFT_WATTEROTT is not set # CONFIG_KS7010 is not set -# CONFIG_GREYBUS is not set +# CONFIG_PI433 is not set # -# USB Power Delivery and Type-C drivers +# Gasket devices # -# CONFIG_TYPEC_TCPM is not set -# CONFIG_PI433 is not set +# CONFIG_STAGING_GASKET_FRAMEWORK is not set +# end of Gasket devices + +# CONFIG_XIL_AXIS_FIFO is not set +# CONFIG_FIELDBUS_DEV is not set +# CONFIG_KPC2000 is not set +# CONFIG_QLGE is not set +# CONFIG_WFX is not set CONFIG_XILINX_FCLK=y +# CONFIG_XLNX_SYNC is not set +# CONFIG_XLNX_TSMUX is not set # CONFIG_XROE_FRAMER is not set +# CONFIG_XROE_TRAFFIC_GEN is not set # CONFIG_GOLDFISH is not set # CONFIG_CHROME_PLATFORMS is not set +# CONFIG_MELLANOX_PLATFORM is not set +CONFIG_HAVE_CLK=y CONFIG_CLKDEV_LOOKUP=y CONFIG_HAVE_CLK_PREPARE=y CONFIG_COMMON_CLK=y - -# -# Common Clock Framework -# -# CONFIG_COMMON_CLK_VERSATILE is not set -# CONFIG_CLK_HSDK is not set +# CONFIG_COMMON_CLK_MAX9485 is not set +CONFIG_COMMON_CLK_SI5341=y # CONFIG_COMMON_CLK_SI5351 is not set -# CONFIG_COMMON_CLK_SI514 is not set +CONFIG_COMMON_CLK_SI514=y +# CONFIG_COMMON_CLK_SI544 is not set CONFIG_COMMON_CLK_SI570=y -# CONFIG_COMMON_CLK_SI5324 is not set +CONFIG_COMMON_CLK_SI5324=y # CONFIG_COMMON_CLK_IDT8T49N24X is not set # CONFIG_COMMON_CLK_CDCE706 is not set # CONFIG_COMMON_CLK_CDCE925 is not set # CONFIG_COMMON_CLK_CS2000_CP is not set CONFIG_COMMON_CLK_AXI_CLKGEN=y # CONFIG_CLK_QORIQ is not set +CONFIG_COMMON_CLK_ADI=y # CONFIG_COMMON_CLK_XGENE is not set -# CONFIG_COMMON_CLK_NXP is not set -# CONFIG_COMMON_CLK_PXA is not set -# CONFIG_COMMON_CLK_PIC32 is not set +# CONFIG_COMMON_CLK_PWM is not set # CONFIG_COMMON_CLK_VC5 is not set +# CONFIG_COMMON_CLK_FIXED_MMIO is not set +CONFIG_COMMON_CLK_XLNX_CLKWZRD=y +# CONFIG_COMMON_CLK_XLNX_CLKWZRD_V is not set + +# +# Analog Devices Clock Drivers +# +CONFIG_COMMON_CLK_AD9545=y +CONFIG_COMMON_CLK_AD9545_I2C=y +CONFIG_COMMON_CLK_AD9545_SPI=y +# end of Analog Devices Clock Drivers + CONFIG_COMMON_CLK_ZYNQMP=y # CONFIG_HWSPINLOCK is not set @@ -4039,20 +5559,17 @@ CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y CONFIG_FSL_ERRATUM_A008585=y CONFIG_HISILICON_ERRATUM_161010101=y CONFIG_ARM64_ERRATUM_858921=y -# CONFIG_ARM_TIMER_SP804 is not set -# CONFIG_ATMEL_PIT is not set -# CONFIG_SH_TIMER_CMT is not set -# CONFIG_SH_TIMER_MTU2 is not set -# CONFIG_SH_TIMER_TMU is not set -# CONFIG_EM_TIMER_STI is not set +# CONFIG_MICROCHIP_PIT64B is not set +# end of Clock Source drivers + CONFIG_MAILBOX=y # CONFIG_ARM_MHU is not set # CONFIG_PLATFORM_MHU is not set # CONFIG_PL320_MBOX is not set # CONFIG_ALTERA_MBOX is not set # CONFIG_MAILBOX_TEST is not set -# CONFIG_BCM_FLEXRM_MBOX is not set CONFIG_ZYNQMP_IPI_MBOX=y +CONFIG_IOMMU_IOVA=y CONFIG_IOMMU_API=y CONFIG_IOMMU_SUPPORT=y @@ -4063,21 +5580,36 @@ CONFIG_IOMMU_IO_PGTABLE=y CONFIG_IOMMU_IO_PGTABLE_LPAE=y # CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set # CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set -CONFIG_IOMMU_IOVA=y +# end of Generic IOMMU Pagetable Support + +# CONFIG_IOMMU_DEBUGFS is not set +# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set CONFIG_OF_IOMMU=y CONFIG_IOMMU_DMA=y CONFIG_ARM_SMMU=y +# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set +CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y # CONFIG_ARM_SMMU_V3 is not set +# CONFIG_VIRTIO_IOMMU is not set # # Remoteproc drivers # -# CONFIG_REMOTEPROC is not set +CONFIG_REMOTEPROC=y +# CONFIG_REMOTEPROC_CDEV is not set +CONFIG_ZYNQMP_R5_REMOTEPROC=m +# end of Remoteproc drivers # # Rpmsg drivers # +CONFIG_RPMSG=m +# CONFIG_RPMSG_CHAR is not set # CONFIG_RPMSG_QCOM_GLINK_RPM is not set +CONFIG_RPMSG_VIRTIO=m +# end of Rpmsg drivers + +# CONFIG_SOUNDWIRE is not set # # SOC (System On Chip) specific Drivers @@ -4086,32 +5618,48 @@ CONFIG_ARM_SMMU=y # # Amlogic SoC drivers # +# end of Amlogic SoC drivers + +# +# Aspeed SoC drivers +# +# end of Aspeed SoC drivers # # Broadcom SoC drivers # # CONFIG_SOC_BRCMSTB is not set +# end of Broadcom SoC drivers + +# +# NXP/Freescale QorIQ SoC drivers +# +# CONFIG_QUICC_ENGINE is not set +# CONFIG_FSL_RCPM is not set +# end of NXP/Freescale QorIQ SoC drivers # # i.MX SoC drivers # +# end of i.MX SoC drivers # # Qualcomm SoC drivers # -# CONFIG_SUNXI_SRAM is not set +# end of Qualcomm SoC drivers + # CONFIG_SOC_TI is not set # # Xilinx SoC drivers # CONFIG_XILINX_VCU=m - -# -# Zynq MPSoC SoC Drivers -# CONFIG_ZYNQMP_POWER=y CONFIG_ZYNQMP_PM_DOMAINS=y +CONFIG_XLNX_EVENT_MANAGER=y +# end of Xilinx SoC drivers +# end of SOC (System On Chip) specific Drivers + # CONFIG_PM_DEVFREQ is not set CONFIG_EXTCON=y @@ -4119,36 +5667,51 @@ CONFIG_EXTCON=y # Extcon Device Drivers # # CONFIG_EXTCON_ADC_JACK is not set +# CONFIG_EXTCON_FSA9480 is not set # CONFIG_EXTCON_GPIO is not set # CONFIG_EXTCON_MAX3355 is not set +# CONFIG_EXTCON_PTN5150 is not set # CONFIG_EXTCON_RT8973A is not set # CONFIG_EXTCON_SM5502 is not set # CONFIG_EXTCON_USB_GPIO is not set # CONFIG_MEMORY is not set CONFIG_IIO=y CONFIG_IIO_BUFFER=y -# CONFIG_IIO_BUFFER_CB is not set +CONFIG_IIO_BUFFER_CB=y CONFIG_IIO_BUFFER_DMA=y CONFIG_IIO_BUFFER_DMAENGINE=y +CONFIG_IIO_BUFFER_HW_CONSUMER=y CONFIG_IIO_KFIFO_BUF=y CONFIG_IIO_TRIGGERED_BUFFER=y -CONFIG_IIO_HW_CONSUMER=y -# CONFIG_IIO_CONFIGFS is not set +CONFIG_IIO_CONFIGFS=y CONFIG_IIO_TRIGGER=y CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 -# CONFIG_IIO_SW_DEVICE is not set -# CONFIG_IIO_SW_TRIGGER is not set +CONFIG_IIO_SW_DEVICE=y +CONFIG_IIO_SW_TRIGGER=y +CONFIG_IIO_TRIGGERED_EVENT=y # # Accelerometers # -# CONFIG_ADXL345_I2C is not set -# CONFIG_ADXL345_SPI is not set +CONFIG_ADIS16201=y +CONFIG_ADIS16209=y +# CONFIG_ADXL313_I2C is not set +# CONFIG_ADXL313_SPI is not set +CONFIG_ADXL345=y +CONFIG_ADXL345_I2C=y +CONFIG_ADXL345_SPI=y +CONFIG_ADXL355=y +CONFIG_ADXL355_I2C=y +CONFIG_ADXL355_SPI=y +CONFIG_ADXL367=y +CONFIG_ADXL367_SPI=y +CONFIG_ADXL367_I2C=y CONFIG_ADXL372=y CONFIG_ADXL372_SPI=y CONFIG_ADXL372_I2C=y # CONFIG_BMA180 is not set # CONFIG_BMA220 is not set +# CONFIG_BMA400 is not set # CONFIG_BMC150_ACCEL is not set # CONFIG_DA280 is not set # CONFIG_DA311 is not set @@ -4170,37 +5733,51 @@ CONFIG_ADXL372_I2C=y # CONFIG_SCA3000 is not set # CONFIG_STK8312 is not set # CONFIG_STK8BA50 is not set +# end of Accelerometers # # Analog to digital converters # CONFIG_AD_SIGMA_DELTA=y -# CONFIG_AD400X is not set +CONFIG_AD400X=y +CONFIG_AD4630=y CONFIG_AD7091R5=y -# CONFIG_AD7124 is not set +CONFIG_AD7124=y CONFIG_AD7173=y +CONFIG_AD7192=y CONFIG_AD7266=y CONFIG_AD7291=y +CONFIG_AD7292=y CONFIG_AD7298=y CONFIG_AD738X=y CONFIG_AD7476=y -# CONFIG_AD7606_IFACE_PARALLEL is not set -# CONFIG_AD7606_IFACE_SPI is not set -# CONFIG_AD7766 is not set -# CONFIG_AD7768 is not set -# CONFIG_AD7768_1 is not set +CONFIG_AD7606=y +CONFIG_AD7606_IFACE_PARALLEL=y +CONFIG_AD7606_IFACE_SPI=y +CONFIG_AD7766=y +CONFIG_AD7768=y +CONFIG_AD7768_1=y +CONFIG_AD7780=y CONFIG_AD7791=y CONFIG_AD7793=y CONFIG_AD7887=y CONFIG_AD7923=y +CONFIG_AD7949=y CONFIG_AD799X=y -# CONFIG_AD9963 is not set -CONFIG_ADM1177=y +CONFIG_AD9963=y +# CONFIG_ADM1177 is not set +# CONFIG_ADI_AXI_ADC is not set CONFIG_CF_AXI_ADC=y +CONFIG_AD9081=y +CONFIG_AD9083=y CONFIG_AD9208=y -CONFIG_AD9361=m -# CONFIG_AD9361_EXT_BAND_CONTROL is not set -CONFIG_AD9371=m +CONFIG_AD9361=y +CONFIG_AD9361_EXT_BAND_CONTROL=y +CONFIG_AD9371=y +CONFIG_ADRV9001=y +CONFIG_ADRV9001_COMMON_VERBOSE=y +CONFIG_ADRV9001_ARM_VERBOSE=y +CONFIG_ADRV9001_VALIDATE_PARAMS=y CONFIG_ADRV9009=y CONFIG_AD6676=y CONFIG_AD9467=y @@ -4213,17 +5790,22 @@ CONFIG_AXI_FMCADC5_SYNC=y # CONFIG_ENVELOPE_DETECTOR is not set # CONFIG_HI8435 is not set # CONFIG_HX711 is not set +CONFIG_LTC2308=y CONFIG_LTC2471=y CONFIG_LTC2485=y -# CONFIG_LTC2497 is not set +CONFIG_LTC2496=y +CONFIG_LTC2497=y # CONFIG_MAX1027 is not set # CONFIG_MAX11100 is not set # CONFIG_MAX1118 is not set +# CONFIG_MAX1241 is not set # CONFIG_MAX1363 is not set # CONFIG_MAX9611 is not set # CONFIG_MCP320X is not set # CONFIG_MCP3422 is not set +# CONFIG_MCP3911 is not set # CONFIG_NAU7802 is not set +# CONFIG_SD_ADC_MODULATOR is not set # CONFIG_TI_ADC081C is not set # CONFIG_TI_ADC0832 is not set # CONFIG_TI_ADC084S021 is not set @@ -4233,41 +5815,75 @@ CONFIG_LTC2485=y # CONFIG_TI_ADC161S626 is not set # CONFIG_TI_ADS1015 is not set # CONFIG_TI_ADS7950 is not set +# CONFIG_TI_ADS8344 is not set # CONFIG_TI_ADS8688 is not set +# CONFIG_TI_ADS124S08 is not set # CONFIG_TI_TLC4541 is not set # CONFIG_VF610_ADC is not set CONFIG_XILINX_XADC=y CONFIG_XILINX_AMS=y +# CONFIG_VERSAL_SYSMON is not set +# end of Analog to digital converters + +# +# Analog to digital and digital to analog converters +# +CONFIG_AD74413R=y +CONFIG_ONE_BIT_ADC_DAC=y +# end of Analog to digital and digital to analog converters + +# +# Analog Front Ends +# +# CONFIG_IIO_RESCALE is not set +# end of Analog Front Ends # # Amplifiers # CONFIG_AD8366=y +CONFIG_AD916X_AMP=y +CONFIG_ADA4250=y +CONFIG_HMC425=y +# end of Amplifiers + +# +# Beamformers +# +CONFIG_ADAR1000=y +CONFIG_ADAR3000=y +# end of Beamformers # # Chemical Sensors # # CONFIG_ATLAS_PH_SENSOR is not set +# CONFIG_ATLAS_EZO_SENSOR is not set +# CONFIG_BME680 is not set # CONFIG_CCS811 is not set # CONFIG_IAQCORE is not set +# CONFIG_PMS7003 is not set +# CONFIG_SCD30_CORE is not set +# CONFIG_SENSIRION_SGP30 is not set +# CONFIG_SPS30 is not set # CONFIG_VZ89X is not set +# end of Chemical Sensors # # Hid Sensor IIO Common # +# end of Hid Sensor IIO Common # # SSP Sensor Common # # CONFIG_IIO_SSP_SENSORHUB is not set - -# -# Counters -# +# end of SSP Sensor Common # # Digital to analog converters # +CONFIG_AD3552R=y CONFIG_AD5064=y CONFIG_AD5270=y CONFIG_AD5360=y @@ -4280,29 +5896,47 @@ CONFIG_AD5592R=y CONFIG_AD5593R=y CONFIG_AD5504=y CONFIG_AD5624R_SPI=y -# CONFIG_LTC2632 is not set +CONFIG_LTC2688=y CONFIG_AD5686=y CONFIG_AD5686_SPI=y -# CONFIG_AD5696_I2C is not set +CONFIG_AD5696_I2C=y CONFIG_AD5755=y -# CONFIG_AD5758 is not set +CONFIG_AD5758=y CONFIG_AD5761=y CONFIG_AD5764=y -# CONFIG_AD5770R is not set +CONFIG_AD5766=y +CONFIG_AD5770R=y CONFIG_AD5791=y +CONFIG_AD7293=y CONFIG_AD7303=y CONFIG_AD8801=y # CONFIG_DPOT_DAC is not set +# CONFIG_DS4424 is not set +CONFIG_LTC1660=y +CONFIG_LTC2632=y # CONFIG_M62332 is not set # CONFIG_MAX517 is not set # CONFIG_MAX5821 is not set # CONFIG_MCP4725 is not set # CONFIG_MCP4922 is not set +# CONFIG_TI_DAC082S085 is not set +# CONFIG_TI_DAC5571 is not set +# CONFIG_TI_DAC7311 is not set +# CONFIG_TI_DAC7612 is not set # CONFIG_VF610_DAC is not set +# end of Digital to analog converters # # IIO dummy driver # +# CONFIG_IIO_SIMPLE_DUMMY is not set +# end of IIO dummy driver + +# +# Filters +# +CONFIG_ADMV8818=y +# end of Filters # # Frequency Synthesizers DDS/PLL @@ -4316,7 +5950,13 @@ CONFIG_AD9523=y CONFIG_AD9528=y CONFIG_AD9548=y CONFIG_AD9517=y +CONFIG_ADMV1013=y +CONFIG_ADMV1014=y +CONFIG_ADMV4420=y +CONFIG_ADRF6780=y CONFIG_HMC7044=y +CONFIG_LTC6952=y +# end of Clock Generator/Distribution # # Direct Digital Synthesis @@ -4327,15 +5967,27 @@ CONFIG_CF_AXI_DDS_AD9144=y CONFIG_CF_AXI_DDS_AD9162=y CONFIG_CF_AXI_DDS_AD9172=y CONFIG_CF_AXI_DDS_AD9739A=y -# CONFIG_M2K_DAC is not set +CONFIG_CF_AXI_DDS_AD9783=y +CONFIG_M2K_DAC=y +# end of Direct Digital Synthesis # # Phase-Locked Loop (PLL) frequency synthesizers # +CONFIG_ADF4159=y CONFIG_ADF4350=y -CONFIG_ADF5355=y -# CONFIG_ADF4371 is not set CONFIG_ADF4360=y +CONFIG_ADF4371=y +CONFIG_ADF4377=y +CONFIG_ADF5355=y +# end of Phase-Locked Loop (PLL) frequency synthesizers + +# +# RF Font-Ends +# +CONFIG_ADL5960=y +# end of RF Font-Ends +# end of Frequency Synthesizers DDS/PLL # # Digital gyroscope sensors @@ -4344,11 +5996,14 @@ CONFIG_ADIS16080=y CONFIG_ADIS16130=y CONFIG_ADIS16136=y CONFIG_ADIS16260=y +CONFIG_ADXRS290=y CONFIG_ADXRS450=y # CONFIG_BMG160 is not set +# CONFIG_FXAS21002C is not set # CONFIG_MPU3050_I2C is not set # CONFIG_IIO_ST_GYRO_3AXIS is not set # CONFIG_ITG3200 is not set +# end of Digital gyroscope sensors # # Health Sensors @@ -4361,6 +6016,8 @@ CONFIG_ADXRS450=y # CONFIG_AFE4404 is not set # CONFIG_MAX30100 is not set # CONFIG_MAX30102 is not set +# end of Heart Rate Monitors +# end of Health Sensors # # Humidity sensors @@ -4368,40 +6025,52 @@ CONFIG_ADXRS450=y # CONFIG_AM2315 is not set # CONFIG_DHT11 is not set # CONFIG_HDC100X is not set +# CONFIG_HDC2010 is not set # CONFIG_HTS221 is not set # CONFIG_HTU21 is not set # CONFIG_SI7005 is not set # CONFIG_SI7020 is not set +# end of Humidity sensors # # Inertial measurement units # CONFIG_ADIS16400=y CONFIG_ADIS16460=y +CONFIG_ADIS16475=y CONFIG_ADIS16480=y # CONFIG_BMI160_I2C is not set # CONFIG_BMI160_SPI is not set +# CONFIG_FXOS8700_I2C is not set +# CONFIG_FXOS8700_SPI is not set # CONFIG_KMX61 is not set +# CONFIG_INV_ICM42600_I2C is not set +# CONFIG_INV_ICM42600_SPI is not set # CONFIG_INV_MPU6050_I2C is not set # CONFIG_INV_MPU6050_SPI is not set # CONFIG_IIO_ST_LSM6DSX is not set +# end of Inertial measurement units + CONFIG_IIO_ADIS_LIB=y CONFIG_IIO_ADIS_LIB_BUFFER=y -CONFIG_JESD204=y # CONFIG_ALTERA_ARRIA10_JESD204_PHY is not set CONFIG_AXI_ADXCVR=y # CONFIG_AXI_JESD204B is not set CONFIG_AXI_JESD204_TX=y CONFIG_AXI_JESD204_RX=y CONFIG_XILINX_TRANSCEIVER=y +CONFIG_ADI_IIO_FAKEDEV=y # # Light sensors # # CONFIG_ADJD_S311 is not set +CONFIG_ADUX1020=y +# CONFIG_AL3010 is not set # CONFIG_AL3320A is not set # CONFIG_APDS9300 is not set # CONFIG_APDS9960 is not set +# CONFIG_AS73211 is not set # CONFIG_BH1750 is not set # CONFIG_BH1780 is not set # CONFIG_CM32181 is not set @@ -4409,6 +6078,7 @@ CONFIG_XILINX_TRANSCEIVER=y # CONFIG_CM3323 is not set # CONFIG_CM3605 is not set # CONFIG_CM36651 is not set +# CONFIG_GP2AP002 is not set # CONFIG_GP2AP020A00F is not set # CONFIG_SENSORS_ISL29018 is not set # CONFIG_SENSORS_ISL29028 is not set @@ -4416,25 +6086,36 @@ CONFIG_XILINX_TRANSCEIVER=y # CONFIG_JSA1212 is not set # CONFIG_RPR0521 is not set # CONFIG_LTR501 is not set +# CONFIG_LV0104CS is not set # CONFIG_MAX44000 is not set +# CONFIG_MAX44009 is not set +# CONFIG_NOA1305 is not set # CONFIG_OPT3001 is not set # CONFIG_PA12203001 is not set +# CONFIG_SI1133 is not set # CONFIG_SI1145 is not set # CONFIG_STK3310 is not set +# CONFIG_ST_UVIS25 is not set # CONFIG_TCS3414 is not set # CONFIG_TCS3472 is not set # CONFIG_SENSORS_TSL2563 is not set # CONFIG_TSL2583 is not set +# CONFIG_TSL2772 is not set # CONFIG_TSL4531 is not set # CONFIG_US5182D is not set # CONFIG_VCNL4000 is not set +# CONFIG_VCNL4035 is not set +# CONFIG_VEML6030 is not set # CONFIG_VEML6070 is not set # CONFIG_VL6180 is not set +# CONFIG_ZOPT2201 is not set +# end of Light sensors # # Logic Analyzers # -# CONFIG_M2K_LOGIC_ANALYZER is not set +CONFIG_M2K_LOGIC_ANALYZER=y +# end of Logic Analyzers # # Magnetometer sensors @@ -4449,43 +6130,74 @@ CONFIG_XILINX_TRANSCEIVER=y # CONFIG_IIO_ST_MAGN_3AXIS is not set # CONFIG_SENSORS_HMC5843_I2C is not set # CONFIG_SENSORS_HMC5843_SPI is not set +# CONFIG_SENSORS_RM3100_I2C is not set +# CONFIG_SENSORS_RM3100_SPI is not set +# end of Magnetometer sensors # # Multiplexers # # CONFIG_IIO_MUX is not set +CONFIG_IIO_GEN_MUX=y +# end of Multiplexers + +# +# IIO Regmap Access Drivers +# +CONFIG_IIO_REGMAP=y +CONFIG_IIO_REGMAP_I2C=y +CONFIG_IIO_REGMAP_SPI=y +# end of IIO Regmap Access Drivers # # Inclinometer sensors # +# end of Inclinometer sensors # # Triggers - standalone # +CONFIG_IIO_HRTIMER_TRIGGER=y CONFIG_IIO_INTERRUPT_TRIGGER=y +CONFIG_IIO_TIGHTLOOP_TRIGGER=y CONFIG_IIO_SYSFS_TRIGGER=y +# end of Triggers - standalone + +# +# Linear and angular position sensors +# +# end of Linear and angular position sensors # # Digital potentiometers # +CONFIG_AD5272=y # CONFIG_DS1803 is not set +# CONFIG_MAX5432 is not set # CONFIG_MAX5481 is not set # CONFIG_MAX5487 is not set +# CONFIG_MCP4018 is not set # CONFIG_MCP4131 is not set # CONFIG_MCP4531 is not set +# CONFIG_MCP41010 is not set # CONFIG_TPL0102 is not set +# end of Digital potentiometers # # Digital potentiostats # # CONFIG_LMP91000 is not set +# end of Digital potentiostats # # Pressure sensors # # CONFIG_ABP060MG is not set # CONFIG_BMP280 is not set +# CONFIG_DLHL60D is not set +# CONFIG_DPS310 is not set # CONFIG_HP03 is not set +# CONFIG_ICP10100 is not set # CONFIG_MPL115_I2C is not set # CONFIG_MPL115_SPI is not set # CONFIG_MPL3115 is not set @@ -4495,147 +6207,190 @@ CONFIG_IIO_SYSFS_TRIGGER=y # CONFIG_T5403 is not set # CONFIG_HP206C is not set # CONFIG_ZPA2326 is not set +# end of Pressure sensors # # Lightning sensors # # CONFIG_AS3935 is not set +# end of Lightning sensors # # Proximity and distance sensors # +# CONFIG_ISL29501 is not set # CONFIG_LIDAR_LITE_V2 is not set +# CONFIG_MB1232 is not set +# CONFIG_PING is not set +# CONFIG_RFD77402 is not set # CONFIG_SRF04 is not set +# CONFIG_SX9310 is not set # CONFIG_SX9500 is not set # CONFIG_SRF08 is not set +# CONFIG_VCNL3020 is not set +# CONFIG_VL53L0X_I2C is not set +# end of Proximity and distance sensors + +# +# Resolver to digital converters +# +CONFIG_AD2S90=y +CONFIG_AD2S1200=y +# end of Resolver to digital converters # # Temperature sensors # +CONFIG_LTC2983=y # CONFIG_MAXIM_THERMOCOUPLE is not set -# CONFIG_LTC2983 is not set # CONFIG_MLX90614 is not set +# CONFIG_MLX90632 is not set # CONFIG_TMP006 is not set # CONFIG_TMP007 is not set # CONFIG_TSYS01 is not set # CONFIG_TSYS02D is not set +# CONFIG_MAX31856 is not set +# end of Temperature sensors + +CONFIG_JESD204=y +CONFIG_JESD204_TOP_DEVICE=y # CONFIG_NTB is not set # CONFIG_VME_BUS is not set -# CONFIG_PWM is not set +CONFIG_PWM=y +CONFIG_PWM_SYSFS=y +# CONFIG_PWM_DEBUG is not set +CONFIG_PWM_AXI_PWMGEN=y +# CONFIG_PWM_FSL_FTM is not set +# CONFIG_PWM_PCA9685 is not set + +# +# IRQ chip support +# CONFIG_IRQCHIP=y CONFIG_ARM_GIC=y CONFIG_ARM_GIC_MAX_NR=1 CONFIG_ARM_GIC_V2M=y CONFIG_ARM_GIC_V3=y CONFIG_ARM_GIC_V3_ITS=y +CONFIG_ARM_GIC_V3_ITS_PCI=y +# CONFIG_AL_FIC is not set CONFIG_XILINX_INTC=y +# CONFIG_IRQCHIP_XILINX_INTC_MODULE_SUPPORT_EXPERIMENTAL is not set CONFIG_PARTITION_PERCPU=y +# end of IRQ chip support + # CONFIG_IPACK_BUS is not set CONFIG_RESET_CONTROLLER=y -# CONFIG_RESET_ATH79 is not set -# CONFIG_RESET_BERLIN is not set -# CONFIG_RESET_IMX7 is not set -# CONFIG_RESET_LANTIQ is not set -# CONFIG_RESET_LPC18XX is not set -# CONFIG_RESET_MESON is not set -# CONFIG_RESET_PISTACHIO is not set -# CONFIG_RESET_SOCFPGA is not set -# CONFIG_RESET_STM32 is not set -# CONFIG_RESET_SUNXI is not set +# CONFIG_RESET_BRCMSTB_RESCAL is not set +# CONFIG_RESET_INTEL_GW is not set # CONFIG_RESET_TI_SYSCON is not set -# CONFIG_RESET_ZYNQ is not set -CONFIG_ZYNQMP_RESET_CONTROLLER=y -# CONFIG_RESET_TEGRA_BPMP is not set -# CONFIG_FMC is not set # # PHY Subsystem # CONFIG_GENERIC_PHY=y # CONFIG_PHY_XGENE is not set +# CONFIG_USB_LGM_PHY is not set # CONFIG_BCM_KONA_USB2_PHY is not set +# CONFIG_PHY_CADENCE_TORRENT is not set +# CONFIG_PHY_CADENCE_DPHY is not set +# CONFIG_PHY_CADENCE_SIERRA is not set +# CONFIG_PHY_CADENCE_SALVO is not set +# CONFIG_PHY_FSL_IMX8MQ_USB is not set +# CONFIG_PHY_MIXEL_MIPI_DPHY is not set # CONFIG_PHY_PXA_28NM_HSIC is not set # CONFIG_PHY_PXA_28NM_USB2 is not set # CONFIG_PHY_CPCAP_USB is not set +# CONFIG_PHY_MAPPHONE_MDM6600 is not set +# CONFIG_PHY_QCOM_USB_HS is not set +# CONFIG_PHY_QCOM_USB_HSIC is not set +# CONFIG_PHY_SAMSUNG_USB2 is not set +# CONFIG_PHY_TUSB1210 is not set CONFIG_PHY_XILINX_ZYNQMP=y +# end of PHY Subsystem + # CONFIG_POWERCAP is not set # CONFIG_MCB is not set # # Performance monitor support # +# CONFIG_ARM_CCI_PMU is not set +# CONFIG_ARM_CCN is not set +# CONFIG_ARM_CMN is not set CONFIG_ARM_PMU=y -# CONFIG_RAS is not set +# CONFIG_ARM_DSU_PMU is not set +# CONFIG_ARM_SPE_PMU is not set +# end of Performance monitor support + +CONFIG_RAS=y +# CONFIG_USB4 is not set # # Android # -# CONFIG_ANDROID is not set +CONFIG_ANDROID=y +# CONFIG_ANDROID_BINDER_IPC is not set +# end of Android + # CONFIG_LIBNVDIMM is not set # CONFIG_DAX is not set CONFIG_NVMEM=y +CONFIG_NVMEM_SYSFS=y CONFIG_NVMEM_AXI_SYSID=y CONFIG_NVMEM_ZYNQMP=y + +# +# HW tracing support +# # CONFIG_STM is not set # CONFIG_INTEL_TH is not set +# end of HW tracing support + CONFIG_FPGA=y -CONFIG_FPGA_REGION=y # CONFIG_FPGA_MGR_DEBUG_FS is not set -# CONFIG_FPGA_MGR_ICE40_SPI is not set -# CONFIG_FPGA_MGR_ALTERA_CVP is not set +# CONFIG_ALTERA_PR_IP_CORE is not set # CONFIG_FPGA_MGR_ALTERA_PS_SPI is not set +# CONFIG_FPGA_MGR_ALTERA_CVP is not set # CONFIG_FPGA_MGR_XILINX_SPI is not set -CONFIG_FPGA_MGR_ZYNQMP_FPGA=y +# CONFIG_FPGA_MGR_ICE40_SPI is not set +# CONFIG_FPGA_MGR_MACHXO2_SPI is not set CONFIG_XILINX_AFI_FPGA=y CONFIG_FPGA_BRIDGE=y -# CONFIG_ALTERA_PR_IP_CORE is not set +# CONFIG_ALTERA_FREEZE_BRIDGE is not set CONFIG_XILINX_PR_DECOUPLER=y - -# -# FSI support -# +CONFIG_FPGA_REGION=y +CONFIG_OF_FPGA_REGION=y +# CONFIG_FPGA_DFL is not set +CONFIG_FPGA_MGR_ZYNQMP_FPGA=y +# CONFIG_FPGA_MGR_VERSAL_FPGA is not set # CONFIG_FSI is not set # CONFIG_TEE is not set +CONFIG_MULTIPLEXER=y # -# Firmware Drivers +# Multiplexer drivers # -CONFIG_ARM_PSCI_FW=y -# CONFIG_ARM_PSCI_CHECKER is not set -# CONFIG_ARM_SCPI_PROTOCOL is not set -# CONFIG_FIRMWARE_MEMMAP is not set -# CONFIG_FW_CFG_SYSFS is not set -CONFIG_HAVE_ARM_SMCCC=y -# CONFIG_GOOGLE_FIRMWARE is not set +CONFIG_MUX_ADG792A=y +CONFIG_MUX_ADGS1408=y +CONFIG_MUX_GPIO=y +# CONFIG_MUX_MMIO is not set +# end of Multiplexer drivers -# -# EFI (Extensible Firmware Interface) Support -# -# CONFIG_EFI_VARS is not set -CONFIG_EFI_ESRT=y -CONFIG_EFI_PARAMS_FROM_FDT=y -CONFIG_EFI_RUNTIME_WRAPPERS=y -CONFIG_EFI_ARMSTUB=y -# CONFIG_EFI_CAPSULE_LOADER is not set -# CONFIG_EFI_TEST is not set -# CONFIG_RESET_ATTACK_MITIGATION is not set -# CONFIG_MESON_SM is not set - -# -# Tegra firmware driver -# - -# -# Zynq MPSoC Firmware Drivers -# -CONFIG_ZYNQMP_FIRMWARE=y -# CONFIG_ZYNQMP_FIRMWARE_DEBUG is not set -# CONFIG_ACPI is not set +CONFIG_PM_OPP=y +# CONFIG_SIOX is not set +# CONFIG_SLIMBUS is not set +# CONFIG_INTERCONNECT is not set +# CONFIG_COUNTER is not set +# CONFIG_MOST is not set +# end of Device Drivers # # File systems # CONFIG_DCACHE_WORD_ACCESS=y +# CONFIG_VALIDATE_FS_PARSER is not set +CONFIG_FS_IOMAP=y CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XATTR is not set CONFIG_EXT3_FS=y @@ -4644,7 +6399,6 @@ CONFIG_EXT3_FS=y CONFIG_EXT4_FS=y CONFIG_EXT4_FS_POSIX_ACL=y CONFIG_EXT4_FS_SECURITY=y -# CONFIG_EXT4_ENCRYPTION is not set # CONFIG_EXT4_DEBUG is not set CONFIG_JBD2=y # CONFIG_JBD2_DEBUG is not set @@ -4660,6 +6414,7 @@ CONFIG_BTRFS_FS=y # CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set # CONFIG_BTRFS_DEBUG is not set # CONFIG_BTRFS_ASSERT is not set +# CONFIG_BTRFS_FS_REF_VERIFY is not set # CONFIG_NILFS2_FS is not set # CONFIG_F2FS_FS is not set # CONFIG_FS_DAX is not set @@ -4669,6 +6424,7 @@ CONFIG_EXPORTFS=y CONFIG_FILE_LOCKING=y CONFIG_MANDATORY_FILE_LOCKING=y # CONFIG_FS_ENCRYPTION is not set +# CONFIG_FS_VERITY is not set CONFIG_FSNOTIFY=y CONFIG_DNOTIFY=y CONFIG_INOTIFY_USER=y @@ -4682,22 +6438,27 @@ CONFIG_QUOTA_TREE=y CONFIG_QFMT_V2=y CONFIG_QUOTACTL=y CONFIG_AUTOFS4_FS=y -# CONFIG_FUSE_FS is not set +CONFIG_AUTOFS_FS=y +CONFIG_FUSE_FS=y +# CONFIG_CUSE is not set +# CONFIG_VIRTIO_FS is not set # CONFIG_OVERLAY_FS is not set # # Caches # # CONFIG_FSCACHE is not set +# end of Caches # # CD-ROM/DVD Filesystems # # CONFIG_ISO9660_FS is not set # CONFIG_UDF_FS is not set +# end of CD-ROM/DVD Filesystems # -# DOS/FAT/NT Filesystems +# DOS/FAT/EXFAT/NT Filesystems # CONFIG_FAT_FS=y CONFIG_MSDOS_FS=y @@ -4705,7 +6466,9 @@ CONFIG_VFAT_FS=y CONFIG_FAT_DEFAULT_CODEPAGE=437 CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" # CONFIG_FAT_DEFAULT_UTF8 is not set +# CONFIG_EXFAT_FS is not set # CONFIG_NTFS_FS is not set +# end of DOS/FAT/EXFAT/NT Filesystems # # Pseudo filesystems @@ -4720,11 +6483,15 @@ CONFIG_SYSFS=y CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y CONFIG_TMPFS_XATTR=y +# CONFIG_TMPFS_INODE64 is not set CONFIG_HUGETLBFS=y CONFIG_HUGETLB_PAGE=y +CONFIG_MEMFD_CREATE=y CONFIG_ARCH_HAS_GIGANTIC_PAGE=y CONFIG_CONFIGFS_FS=y CONFIG_EFIVAR_FS=m +# end of Pseudo filesystems + CONFIG_MISC_FILESYSTEMS=y # CONFIG_ORANGEFS_FS is not set # CONFIG_ADFS_FS is not set @@ -4754,6 +6521,8 @@ CONFIG_JFFS2_CMODE_PRIORITY=y # CONFIG_JFFS2_CMODE_SIZE is not set # CONFIG_JFFS2_CMODE_FAVOURLZO is not set CONFIG_CRAMFS=y +CONFIG_CRAMFS_BLOCKDEV=y +# CONFIG_CRAMFS_MTD is not set # CONFIG_SQUASHFS is not set # CONFIG_VXFS_FS is not set # CONFIG_MINIX_FS is not set @@ -4765,6 +6534,7 @@ CONFIG_CRAMFS=y # CONFIG_PSTORE is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set +# CONFIG_EROFS_FS is not set CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y CONFIG_NFS_V2=y @@ -4781,6 +6551,8 @@ CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org" CONFIG_ROOT_NFS=y # CONFIG_NFS_USE_LEGACY_DNS is not set CONFIG_NFS_USE_KERNEL_DNS=y +CONFIG_NFS_DISABLE_UDP_SUPPORT=y +# CONFIG_NFS_V4_2_READ_PLUS is not set # CONFIG_NFSD is not set CONFIG_GRACE_PERIOD=y CONFIG_LOCKD=y @@ -4793,7 +6565,6 @@ CONFIG_SUNRPC_BACKCHANNEL=y # CONFIG_SUNRPC_DEBUG is not set # CONFIG_CEPH_FS is not set # CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set # CONFIG_9P_FS is not set @@ -4849,192 +6620,16 @@ CONFIG_NLS_ISO8859_1=y # CONFIG_NLS_MAC_TURKISH is not set # CONFIG_NLS_UTF8 is not set # CONFIG_DLM is not set -# CONFIG_VIRTUALIZATION is not set - -# -# Kernel hacking -# - -# -# printk and dmesg options -# -CONFIG_PRINTK_TIME=y -CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 -CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 -# CONFIG_BOOT_PRINTK_DELAY is not set -# CONFIG_DYNAMIC_DEBUG is not set - -# -# Compile-time checks and compiler options -# -CONFIG_DEBUG_INFO=y -# CONFIG_DEBUG_INFO_REDUCED is not set -# CONFIG_DEBUG_INFO_SPLIT is not set -# CONFIG_DEBUG_INFO_DWARF4 is not set -# CONFIG_GDB_SCRIPTS is not set -CONFIG_ENABLE_WARN_DEPRECATED=y -CONFIG_ENABLE_MUST_CHECK=y -CONFIG_FRAME_WARN=2048 -# CONFIG_STRIP_ASM_SYMS is not set -# CONFIG_READABLE_ASM is not set -# CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_PAGE_OWNER is not set -CONFIG_DEBUG_FS=y -# CONFIG_HEADERS_CHECK is not set -# CONFIG_DEBUG_SECTION_MISMATCH is not set -CONFIG_SECTION_MISMATCH_WARN_ONLY=y -CONFIG_ARCH_WANT_FRAME_POINTERS=y -CONFIG_FRAME_POINTER=y -# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set -CONFIG_MAGIC_SYSRQ=y -CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 -CONFIG_MAGIC_SYSRQ_SERIAL=y -CONFIG_DEBUG_KERNEL=y - -# -# Memory Debugging -# -# CONFIG_PAGE_EXTENSION is not set -# CONFIG_DEBUG_PAGEALLOC is not set -# CONFIG_PAGE_POISONING is not set -# CONFIG_DEBUG_RODATA_TEST is not set -# CONFIG_DEBUG_OBJECTS is not set -# CONFIG_DEBUG_SLAB is not set -CONFIG_HAVE_DEBUG_KMEMLEAK=y -# CONFIG_DEBUG_KMEMLEAK is not set -# CONFIG_DEBUG_STACK_USAGE is not set -# CONFIG_DEBUG_VM is not set -CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y -# CONFIG_DEBUG_VIRTUAL is not set -# CONFIG_DEBUG_MEMORY_INIT is not set -# CONFIG_DEBUG_PER_CPU_MAPS is not set -CONFIG_HAVE_ARCH_KASAN=y -# CONFIG_KASAN is not set -CONFIG_ARCH_HAS_KCOV=y -# CONFIG_KCOV is not set -# CONFIG_DEBUG_SHIRQ is not set - -# -# Debug Lockups and Hangs -# -# CONFIG_SOFTLOCKUP_DETECTOR is not set -# CONFIG_DETECT_HUNG_TASK is not set -# CONFIG_WQ_WATCHDOG is not set -# CONFIG_PANIC_ON_OOPS is not set -CONFIG_PANIC_ON_OOPS_VALUE=0 -CONFIG_PANIC_TIMEOUT=0 -# CONFIG_SCHED_DEBUG is not set -CONFIG_SCHED_INFO=y -# CONFIG_SCHEDSTATS is not set -# CONFIG_SCHED_STACK_END_CHECK is not set -# CONFIG_DEBUG_TIMEKEEPING is not set - -# -# Lock Debugging (spinlocks, mutexes, etc...) -# -# CONFIG_DEBUG_RT_MUTEXES is not set -# CONFIG_DEBUG_SPINLOCK is not set -# CONFIG_DEBUG_MUTEXES is not set -# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set -# CONFIG_DEBUG_LOCK_ALLOC is not set -# CONFIG_PROVE_LOCKING is not set -# CONFIG_LOCK_STAT is not set -# CONFIG_DEBUG_ATOMIC_SLEEP is not set -# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set -# CONFIG_LOCK_TORTURE_TEST is not set -# CONFIG_WW_MUTEX_SELFTEST is not set -# CONFIG_STACKTRACE is not set -# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set -# CONFIG_DEBUG_KOBJECT is not set -CONFIG_HAVE_DEBUG_BUGVERBOSE=y -CONFIG_DEBUG_BUGVERBOSE=y -# CONFIG_DEBUG_LIST is not set -# CONFIG_DEBUG_PI_LIST is not set -# CONFIG_DEBUG_SG is not set -# CONFIG_DEBUG_NOTIFIERS is not set -# CONFIG_DEBUG_CREDENTIALS is not set - -# -# RCU Debugging -# -# CONFIG_PROVE_RCU is not set -# CONFIG_TORTURE_TEST is not set -# CONFIG_RCU_PERF_TEST is not set -# CONFIG_RCU_TORTURE_TEST is not set -CONFIG_RCU_CPU_STALL_TIMEOUT=21 -CONFIG_RCU_TRACE=y -# CONFIG_RCU_EQS_DEBUG is not set -# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set -# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set -# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set -# CONFIG_NOTIFIER_ERROR_INJECTION is not set -# CONFIG_FAULT_INJECTION is not set -# CONFIG_LATENCYTOP is not set -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y -CONFIG_HAVE_SYSCALL_TRACEPOINTS=y -CONFIG_HAVE_C_RECORDMCOUNT=y -CONFIG_TRACE_CLOCK=y -CONFIG_TRACING_SUPPORT=y -# CONFIG_FTRACE is not set -# CONFIG_DMA_API_DEBUG is not set - -# -# Runtime Testing -# -# CONFIG_LKDTM is not set -# CONFIG_TEST_LIST_SORT is not set -# CONFIG_TEST_SORT is not set -# CONFIG_BACKTRACE_SELF_TEST is not set -# CONFIG_RBTREE_TEST is not set -# CONFIG_INTERVAL_TREE_TEST is not set -# CONFIG_PERCPU_TEST is not set -# CONFIG_ATOMIC64_SELFTEST is not set -# CONFIG_TEST_HEXDUMP is not set -# CONFIG_TEST_STRING_HELPERS is not set -# CONFIG_TEST_KSTRTOX is not set -# CONFIG_TEST_PRINTF is not set -# CONFIG_TEST_BITMAP is not set -# CONFIG_TEST_UUID is not set -# CONFIG_TEST_RHASHTABLE is not set -# CONFIG_TEST_HASH is not set -# CONFIG_TEST_LKM is not set -# CONFIG_TEST_USER_COPY is not set -# CONFIG_TEST_BPF is not set -# CONFIG_TEST_FIRMWARE is not set -# CONFIG_TEST_SYSCTL is not set -# CONFIG_TEST_UDELAY is not set -# CONFIG_TEST_STATIC_KEYS is not set -# CONFIG_TEST_KMOD is not set -# CONFIG_MEMTEST is not set -# CONFIG_BUG_ON_DATA_CORRUPTION is not set -# CONFIG_SAMPLES is not set -CONFIG_HAVE_ARCH_KGDB=y -# CONFIG_KGDB is not set -CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y -# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set -# CONFIG_UBSAN is not set -CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y -# CONFIG_STRICT_DEVMEM is not set -# CONFIG_ARM64_PTDUMP_CORE is not set -# CONFIG_ARM64_PTDUMP_DEBUGFS is not set -# CONFIG_PID_IN_CONTEXTIDR is not set -# CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set -# CONFIG_DEBUG_WX is not set -# CONFIG_DEBUG_ALIGN_RODATA is not set -# CONFIG_DEBUG_EFI is not set -# CONFIG_ARM64_RELOC_TEST is not set -# CONFIG_CORESIGHT is not set +# CONFIG_UNICODE is not set +CONFIG_IO_WQ=y +# end of File systems # # Security options # CONFIG_KEYS=y -CONFIG_KEYS_COMPAT=y +# CONFIG_KEYS_REQUEST_CACHE is not set # CONFIG_PERSISTENT_KEYRINGS is not set -# CONFIG_BIG_KEYS is not set # CONFIG_ENCRYPTED_KEYS is not set # CONFIG_KEY_DH_OPERATIONS is not set # CONFIG_SECURITY_DMESG_RESTRICT is not set @@ -5045,7 +6640,22 @@ CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y # CONFIG_FORTIFY_SOURCE is not set # CONFIG_STATIC_USERMODEHELPER is not set CONFIG_DEFAULT_SECURITY_DAC=y -CONFIG_DEFAULT_SECURITY="" +CONFIG_LSM="lockdown,yama,loadpin,safesetid,integrity,bpf" + +# +# Kernel hardening options +# + +# +# Memory initialization +# +CONFIG_INIT_STACK_NONE=y +# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set +# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set +# end of Memory initialization +# end of Kernel hardening options +# end of Security options + CONFIG_XOR_BLOCKS=y CONFIG_CRYPTO=y @@ -5056,32 +6666,42 @@ CONFIG_CRYPTO_ALGAPI=y CONFIG_CRYPTO_ALGAPI2=y CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_BLKCIPHER=y -CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_SKCIPHER=y +CONFIG_CRYPTO_SKCIPHER2=y CONFIG_CRYPTO_HASH=y CONFIG_CRYPTO_HASH2=y CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_RNG2=y CONFIG_CRYPTO_RNG_DEFAULT=y CONFIG_CRYPTO_AKCIPHER2=y +CONFIG_CRYPTO_AKCIPHER=y CONFIG_CRYPTO_KPP2=y +CONFIG_CRYPTO_KPP=y CONFIG_CRYPTO_ACOMP2=y -# CONFIG_CRYPTO_RSA is not set -# CONFIG_CRYPTO_DH is not set -CONFIG_CRYPTO_ECDH=y CONFIG_CRYPTO_MANAGER=y CONFIG_CRYPTO_MANAGER2=y # CONFIG_CRYPTO_USER is not set # CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set +# CONFIG_CRYPTO_MANAGER_EXTRA_TESTS is not set CONFIG_CRYPTO_GF128MUL=y CONFIG_CRYPTO_NULL=y CONFIG_CRYPTO_NULL2=y # CONFIG_CRYPTO_PCRYPT is not set -CONFIG_CRYPTO_WORKQUEUE=y # CONFIG_CRYPTO_CRYPTD is not set -# CONFIG_CRYPTO_MCRYPTD is not set -# CONFIG_CRYPTO_AUTHENC is not set +CONFIG_CRYPTO_AUTHENC=y # CONFIG_CRYPTO_TEST is not set +CONFIG_CRYPTO_ENGINE=y + +# +# Public-key cryptography +# +CONFIG_CRYPTO_RSA=y +# CONFIG_CRYPTO_DH is not set +CONFIG_CRYPTO_ECC=y +CONFIG_CRYPTO_ECDH=y +# CONFIG_CRYPTO_ECRDSA is not set +# CONFIG_CRYPTO_SM2 is not set +# CONFIG_CRYPTO_CURVE25519 is not set # # Authenticated Encryption with Associated Data @@ -5089,20 +6709,25 @@ CONFIG_CRYPTO_WORKQUEUE=y CONFIG_CRYPTO_CCM=y CONFIG_CRYPTO_GCM=y # CONFIG_CRYPTO_CHACHA20POLY1305 is not set -CONFIG_CRYPTO_SEQIV=y -CONFIG_CRYPTO_ECHAINIV=m +# CONFIG_CRYPTO_AEGIS128 is not set +# CONFIG_CRYPTO_SEQIV is not set +# CONFIG_CRYPTO_ECHAINIV is not set # # Block modes # CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CFB is not set CONFIG_CRYPTO_CTR=y # CONFIG_CRYPTO_CTS is not set CONFIG_CRYPTO_ECB=y # CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_OFB is not set # CONFIG_CRYPTO_PCBC is not set # CONFIG_CRYPTO_XTS is not set # CONFIG_CRYPTO_KEYWRAP is not set +# CONFIG_CRYPTO_ADIANTUM is not set +# CONFIG_CRYPTO_ESSIV is not set # # Hash modes @@ -5117,6 +6742,9 @@ CONFIG_CRYPTO_HMAC=y # CONFIG_CRYPTO_CRC32C=y # CONFIG_CRYPTO_CRC32 is not set +CONFIG_CRYPTO_XXHASH=y +CONFIG_CRYPTO_BLAKE2B=y +# CONFIG_CRYPTO_BLAKE2S is not set CONFIG_CRYPTO_CRCT10DIF=y CONFIG_CRYPTO_GHASH=y # CONFIG_CRYPTO_POLY1305 is not set @@ -5131,6 +6759,8 @@ CONFIG_CRYPTO_MD5=y CONFIG_CRYPTO_SHA256=y # CONFIG_CRYPTO_SHA512 is not set # CONFIG_CRYPTO_SHA3 is not set +# CONFIG_CRYPTO_SM3 is not set +# CONFIG_CRYPTO_STREEBOG is not set # CONFIG_CRYPTO_TGR192 is not set # CONFIG_CRYPTO_WP512 is not set @@ -5140,7 +6770,7 @@ CONFIG_CRYPTO_SHA256=y CONFIG_CRYPTO_AES=y # CONFIG_CRYPTO_AES_TI is not set # CONFIG_CRYPTO_ANUBIS is not set -CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_ARC4 is not set # CONFIG_CRYPTO_BLOWFISH is not set # CONFIG_CRYPTO_CAMELLIA is not set # CONFIG_CRYPTO_CAST5 is not set @@ -5152,6 +6782,7 @@ CONFIG_CRYPTO_ARC4=y # CONFIG_CRYPTO_CHACHA20 is not set # CONFIG_CRYPTO_SEED is not set # CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_SM4 is not set # CONFIG_CRYPTO_TEA is not set # CONFIG_CRYPTO_TWOFISH is not set @@ -5163,6 +6794,7 @@ CONFIG_CRYPTO_ARC4=y # CONFIG_CRYPTO_842 is not set # CONFIG_CRYPTO_LZ4 is not set # CONFIG_CRYPTO_LZ4HC is not set +# CONFIG_CRYPTO_ZSTD is not set # # Random Number Generation @@ -5174,34 +6806,79 @@ CONFIG_CRYPTO_DRBG_HMAC=y # CONFIG_CRYPTO_DRBG_CTR is not set CONFIG_CRYPTO_DRBG=y CONFIG_CRYPTO_JITTERENTROPY=y +CONFIG_CRYPTO_USER_API=y # CONFIG_CRYPTO_USER_API_HASH is not set -# CONFIG_CRYPTO_USER_API_SKCIPHER is not set +CONFIG_CRYPTO_USER_API_SKCIPHER=y # CONFIG_CRYPTO_USER_API_RNG is not set # CONFIG_CRYPTO_USER_API_AEAD is not set -# CONFIG_CRYPTO_HW is not set -# CONFIG_ASYMMETRIC_KEY_TYPE is not set +CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y +CONFIG_CRYPTO_HASH_INFO=y + +# +# Crypto library routines +# +CONFIG_CRYPTO_LIB_AES=y +CONFIG_CRYPTO_LIB_ARC4=y +# CONFIG_CRYPTO_LIB_BLAKE2S is not set +# CONFIG_CRYPTO_LIB_CHACHA is not set +# CONFIG_CRYPTO_LIB_CURVE25519 is not set +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9 +# CONFIG_CRYPTO_LIB_POLY1305 is not set +# CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set +CONFIG_CRYPTO_LIB_SHA256=y +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set +# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set +# CONFIG_CRYPTO_DEV_CCP is not set +# CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set +# CONFIG_CRYPTO_DEV_CAVIUM_ZIP is not set +CONFIG_CRYPTO_DEV_ZYNQMP_SHA3=y +CONFIG_CRYPTO_DEV_XILINX_RSA=y +CONFIG_CRYPTO_DEV_ZYNQMP_AES=y +# CONFIG_CRYPTO_DEV_VIRTIO is not set +# CONFIG_CRYPTO_DEV_SAFEXCEL is not set +# CONFIG_CRYPTO_DEV_CCREE is not set +# CONFIG_CRYPTO_DEV_HISI_SEC is not set +# CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set +CONFIG_ASYMMETRIC_KEY_TYPE=y +CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y +CONFIG_X509_CERTIFICATE_PARSER=y +# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set +CONFIG_PKCS7_MESSAGE_PARSER=y +# CONFIG_PKCS7_TEST_KEY is not set +# CONFIG_SIGNED_PE_FILE_VERIFICATION is not set # # Certificates for signature checking # +CONFIG_SYSTEM_TRUSTED_KEYRING=y +CONFIG_SYSTEM_TRUSTED_KEYS="" +# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set +# CONFIG_SECONDARY_TRUSTED_KEYRING is not set # CONFIG_SYSTEM_BLACKLIST_KEYRING is not set -# CONFIG_ARM64_CRYPTO is not set -# CONFIG_BINARY_PRINTF is not set +# end of Certificates for signature checking # # Library routines # CONFIG_RAID6_PQ=y +CONFIG_RAID6_PQ_BENCHMARK=y +CONFIG_LINEAR_RANGES=y +# CONFIG_PACKING is not set CONFIG_BITREVERSE=y CONFIG_HAVE_ARCH_BITREVERSE=y -CONFIG_RATIONAL=y CONFIG_GENERIC_STRNCPY_FROM_USER=y CONFIG_GENERIC_STRNLEN_USER=y CONFIG_GENERIC_NET_UTILS=y +# CONFIG_CORDIC is not set +# CONFIG_PRIME_NUMBERS is not set +CONFIG_RATIONAL=y CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_IO=y CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y -# CONFIG_CRC_CCITT is not set +CONFIG_ARCH_HAS_FAST_MULTIPLIER=y +CONFIG_ARCH_USE_SYM_ANNOTATIONS=y +# CONFIG_INDIRECT_PIO is not set +CONFIG_CRC_CCITT=y CONFIG_CRC16=y # CONFIG_CRC_T10DIF is not set # CONFIG_CRC_ITU_T is not set @@ -5211,10 +6888,11 @@ CONFIG_CRC32_SLICEBY8=y # CONFIG_CRC32_SLICEBY4 is not set # CONFIG_CRC32_SARWATE is not set # CONFIG_CRC32_BIT is not set +# CONFIG_CRC64 is not set # CONFIG_CRC4 is not set CONFIG_CRC7=y -CONFIG_LIBCRC32C=m -# CONFIG_CRC8 is not set +CONFIG_LIBCRC32C=y +CONFIG_CRC8=y CONFIG_XXHASH=y CONFIG_AUDIT_GENERIC=y CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y @@ -5242,31 +6920,308 @@ CONFIG_DECOMPRESS_LZMA=y CONFIG_DECOMPRESS_XZ=y CONFIG_DECOMPRESS_LZO=y CONFIG_DECOMPRESS_LZ4=y +CONFIG_DECOMPRESS_ZSTD=y CONFIG_GENERIC_ALLOCATOR=y -CONFIG_RADIX_TREE_MULTIORDER=y +CONFIG_XARRAY_MULTI=y CONFIG_ASSOCIATIVE_ARRAY=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT_MAP=y CONFIG_HAS_DMA=y -# CONFIG_DMA_NOOP_OPS is not set -# CONFIG_DMA_VIRT_OPS is not set +CONFIG_DMA_OPS=y +CONFIG_NEED_SG_DMA_LENGTH=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_DMA_DECLARE_COHERENT=y +CONFIG_ARCH_HAS_SETUP_DMA_OPS=y +CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y +CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y +CONFIG_SWIOTLB=y +CONFIG_DMA_NONCOHERENT_MMAP=y +CONFIG_DMA_COHERENT_POOL=y +CONFIG_DMA_REMAP=y +CONFIG_DMA_DIRECT_REMAP=y +CONFIG_DMA_CMA=y +# CONFIG_DMA_PERNUMA_CMA is not set + +# +# Default contiguous memory area size: +# +CONFIG_CMA_SIZE_MBYTES=256 +CONFIG_CMA_SIZE_SEL_MBYTES=y +# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set +# CONFIG_CMA_SIZE_SEL_MIN is not set +# CONFIG_CMA_SIZE_SEL_MAX is not set +CONFIG_CMA_ALIGNMENT=8 +# CONFIG_DMA_API_DEBUG is not set +CONFIG_SGL_ALLOC=y CONFIG_CPU_RMAP=y CONFIG_DQL=y CONFIG_GLOB=y # CONFIG_GLOB_SELFTEST is not set CONFIG_NLATTR=y -# CONFIG_CORDIC is not set -# CONFIG_DDR is not set +CONFIG_CLZ_TAB=y # CONFIG_IRQ_POLL is not set +CONFIG_MPILIB=y CONFIG_LIBFDT=y CONFIG_OID_REGISTRY=y CONFIG_UCS2_STRING=y +CONFIG_HAVE_GENERIC_VDSO=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_VDSO_TIME_NS=y CONFIG_FONT_SUPPORT=y # CONFIG_FONTS is not set CONFIG_FONT_8x8=y CONFIG_FONT_8x16=y -# CONFIG_SG_SPLIT is not set CONFIG_SG_POOL=y -CONFIG_ARCH_HAS_SG_CHAIN=y +CONFIG_ARCH_STACKWALK=y CONFIG_SBITMAP=y # CONFIG_STRING_SELFTEST is not set +# end of Library routines + +# +# Kernel hacking +# + +# +# printk and dmesg options +# +CONFIG_PRINTK_TIME=y +# CONFIG_PRINTK_CALLER is not set +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 +CONFIG_CONSOLE_LOGLEVEL_QUIET=4 +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_DYNAMIC_DEBUG_CORE is not set +CONFIG_SYMBOLIC_ERRNAME=y +CONFIG_DEBUG_BUGVERBOSE=y +# end of printk and dmesg options + +# +# Compile-time checks and compiler options +# +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_INFO_REDUCED is not set +# CONFIG_DEBUG_INFO_COMPRESSED is not set +# CONFIG_DEBUG_INFO_SPLIT is not set +# CONFIG_DEBUG_INFO_DWARF4 is not set +# CONFIG_DEBUG_INFO_BTF is not set +# CONFIG_GDB_SCRIPTS is not set +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=2048 +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_READABLE_ASM is not set +# CONFIG_HEADERS_INSTALL is not set +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_SECTION_MISMATCH_WARN_ONLY=y +# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_32B is not set +CONFIG_ARCH_WANT_FRAME_POINTERS=y +CONFIG_FRAME_POINTER=y +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# end of Compile-time checks and compiler options + +# +# Generic Kernel Debugging Instruments +# +CONFIG_MAGIC_SYSRQ=y +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 +CONFIG_MAGIC_SYSRQ_SERIAL=y +CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE="" +CONFIG_DEBUG_FS=y +CONFIG_DEBUG_FS_ALLOW_ALL=y +# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set +# CONFIG_DEBUG_FS_ALLOW_NONE is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y +# CONFIG_UBSAN is not set +# end of Generic Kernel Debugging Instruments + +CONFIG_DEBUG_KERNEL=y +CONFIG_DEBUG_MISC=y + +# +# Memory Debugging +# +# CONFIG_PAGE_EXTENSION is not set +# CONFIG_DEBUG_PAGEALLOC is not set +# CONFIG_PAGE_OWNER is not set +# CONFIG_PAGE_POISONING is not set +# CONFIG_DEBUG_RODATA_TEST is not set +CONFIG_ARCH_HAS_DEBUG_WX=y +# CONFIG_DEBUG_WX is not set +CONFIG_GENERIC_PTDUMP=y +# CONFIG_PTDUMP_DEBUGFS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_SLAB is not set +CONFIG_HAVE_DEBUG_KMEMLEAK=y +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_SCHED_STACK_END_CHECK is not set +CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_VM_PGTABLE is not set +CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y +# CONFIG_DEBUG_VIRTUAL is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_PER_CPU_MAPS is not set +CONFIG_HAVE_ARCH_KASAN=y +CONFIG_HAVE_ARCH_KASAN_SW_TAGS=y +CONFIG_CC_HAS_KASAN_GENERIC=y +CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y +# CONFIG_KASAN is not set +# end of Memory Debugging + +# CONFIG_DEBUG_SHIRQ is not set + +# +# Debug Oops, Lockups and Hangs +# +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=0 +# CONFIG_SOFTLOCKUP_DETECTOR is not set +# CONFIG_DETECT_HUNG_TASK is not set +# CONFIG_WQ_WATCHDOG is not set +# CONFIG_TEST_LOCKUP is not set +# end of Debug Oops, Lockups and Hangs + +# +# Scheduler Debugging +# +# CONFIG_SCHED_DEBUG is not set +CONFIG_SCHED_INFO=y +# CONFIG_SCHEDSTATS is not set +# end of Scheduler Debugging + +# CONFIG_DEBUG_TIMEKEEPING is not set + +# +# Lock Debugging (spinlocks, mutexes, etc...) +# +CONFIG_LOCK_DEBUGGING_SUPPORT=y +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set +# CONFIG_DEBUG_RWSEMS is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_DEBUG_ATOMIC_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_LOCK_TORTURE_TEST is not set +# CONFIG_WW_MUTEX_SELFTEST is not set +# CONFIG_SCF_TORTURE_TEST is not set +# CONFIG_CSD_LOCK_WAIT_DEBUG is not set +# end of Lock Debugging (spinlocks, mutexes, etc...) + +# CONFIG_STACKTRACE is not set +# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_HAVE_DEBUG_BUGVERBOSE=y + +# +# Debug kernel data structures +# +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_PLIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_BUG_ON_DATA_CORRUPTION is not set +# end of Debug kernel data structures + +# CONFIG_DEBUG_CREDENTIALS is not set + +# +# RCU Debugging +# +# CONFIG_RCU_SCALE_TEST is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_REF_SCALE_TEST is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=21 +CONFIG_RCU_TRACE=y +# CONFIG_RCU_EQS_DEBUG is not set +# end of RCU Debugging + +# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set +# CONFIG_LATENCYTOP is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACE_CLOCK=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_SAMPLES is not set +CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y +CONFIG_STRICT_DEVMEM=y +# CONFIG_IO_STRICT_DEVMEM is not set + +# +# arm64 Debugging +# +# CONFIG_PID_IN_CONTEXTIDR is not set +# CONFIG_DEBUG_EFI is not set +# CONFIG_ARM64_RELOC_TEST is not set +# CONFIG_CORESIGHT is not set +# end of arm64 Debugging + +# +# Kernel Testing and Coverage +# +# CONFIG_KUNIT is not set +# CONFIG_NOTIFIER_ERROR_INJECTION is not set +# CONFIG_FAULT_INJECTION is not set +CONFIG_ARCH_HAS_KCOV=y +CONFIG_CC_HAS_SANCOV_TRACE_PC=y +# CONFIG_KCOV is not set +CONFIG_RUNTIME_TESTING_MENU=y +# CONFIG_LKDTM is not set +# CONFIG_TEST_LIST_SORT is not set +# CONFIG_TEST_MIN_HEAP is not set +# CONFIG_TEST_SORT is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_RBTREE_TEST is not set +# CONFIG_REED_SOLOMON_TEST is not set +# CONFIG_INTERVAL_TREE_TEST is not set +# CONFIG_PERCPU_TEST is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_TEST_HEXDUMP is not set +# CONFIG_TEST_STRING_HELPERS is not set +# CONFIG_TEST_STRSCPY is not set +# CONFIG_TEST_KSTRTOX is not set +# CONFIG_TEST_PRINTF is not set +# CONFIG_TEST_BITMAP is not set +# CONFIG_TEST_UUID is not set +# CONFIG_TEST_XARRAY is not set +# CONFIG_TEST_OVERFLOW is not set +# CONFIG_TEST_RHASHTABLE is not set +# CONFIG_TEST_HASH is not set +# CONFIG_TEST_IDA is not set +# CONFIG_TEST_LKM is not set +# CONFIG_TEST_BITOPS is not set +# CONFIG_TEST_VMALLOC is not set +# CONFIG_TEST_USER_COPY is not set +# CONFIG_TEST_BPF is not set +# CONFIG_TEST_BLACKHOLE_DEV is not set +# CONFIG_FIND_BIT_BENCHMARK is not set +# CONFIG_TEST_FIRMWARE is not set +# CONFIG_TEST_SYSCTL is not set +# CONFIG_TEST_UDELAY is not set +# CONFIG_TEST_STATIC_KEYS is not set +# CONFIG_TEST_KMOD is not set +# CONFIG_TEST_MEMCAT_P is not set +# CONFIG_TEST_STACKINIT is not set +# CONFIG_TEST_MEMINIT is not set +# CONFIG_TEST_FREE_PAGES is not set +# CONFIG_MEMTEST is not set +# end of Kernel Testing and Coverage +# end of Kernel hacking diff --git a/kernel_boot/kernel_patch_readme.md b/kernel_boot/kernel_patch_readme.md new file mode 100644 index 0000000..b06c54b --- /dev/null +++ b/kernel_boot/kernel_patch_readme.md @@ -0,0 +1,6 @@ +axi_hdmi_crtc.patch to avoid axi hdmi compiling error after enable Xilinx axi dma. + +ad9361.patch to expose some APIs for openwifi driver. + +ad9361_conv.patch to avoid 61.44Msps lvds interface self timing calibration for some low-end/bad hardware (sometimes difficult). + diff --git a/user_space/arbitrary_iq_gen/single_carrier_gen.m b/user_space/arbitrary_iq_gen/single_carrier_gen.m index 67b5cfb..a8e9a5b 100644 --- a/user_space/arbitrary_iq_gen/single_carrier_gen.m +++ b/user_space/arbitrary_iq_gen/single_carrier_gen.m @@ -1,4 +1,6 @@ -% xianjun.jiao@imec.be +% Author: Xianjun Jiao (xianjun.jiao@imec.be; putaoshu@msn.com) +% SPDX-FileCopyrightText: 2023 UGent +% SPDX-License-Identifier: AGPL-3.0-or-later function single_carrier_gen(carrier_freq, num_iq) if exist('carrier_freq', 'var')==0 || isempty(carrier_freq) diff --git a/user_space/boot_bin_gen.sh b/user_space/boot_bin_gen.sh index 22cecfb..928d648 100755 --- a/user_space/boot_bin_gen.sh +++ b/user_space/boot_bin_gen.sh @@ -5,18 +5,18 @@ # SPDX-License-Identifier: AGPL-3.0-or-later if [ "$#" -ne 3 ]; then - echo "You must enter exactly 3 arguments: \$OPENWIFI_HW_DIR \$XILINX_DIR \$BOARD_NAME" + echo "You must enter exactly 3 arguments: \$XILINX_DIR \$BOARD_NAME DIR_TO_system_top.xsa" exit 1 fi -OPENWIFI_HW_DIR=$1 -XILINX_DIR=$2 -BOARD_NAME=$3 +XILINX_DIR=$1 +BOARD_NAME=$2 +XSA_FILE=$3 OPENWIFI_DIR=$(pwd)/../ echo OPENWIFI_DIR $OPENWIFI_DIR -echo OPENWIFI_HW_DIR $OPENWIFI_HW_DIR +echo XSA_FILE $XSA_FILE if [ -f "$OPENWIFI_DIR/LICENSE" ]; then echo "\$OPENWIFI_DIR is found!" @@ -25,24 +25,24 @@ else exit 1 fi -if [ -d "$XILINX_DIR/SDK" ]; then +if [ -d "$XILINX_DIR/Vitis" ]; then echo "\$XILINX_DIR is found!" else echo "\$XILINX_DIR is not correct. Please check!" exit 1 fi -if [ "$BOARD_NAME" != "antsdr" ] && [ "$BOARD_NAME" != "antsdr_e200" ] && [ "$BOARD_NAME" != "sdrpi" ] && [ "$BOARD_NAME" != "zc706_fmcs2" ] && [ "$BOARD_NAME" != "zc702_fmcs2" ] && [ "$BOARD_NAME" != "zed_fmcs2" ] && [ "$BOARD_NAME" != "adrv9361z7035" ] && [ "$BOARD_NAME" != "adrv9364z7020" ]; then - echo "\$BOARD_NAME is not correct. Please check!" - exit 1 -else - echo "\$BOARD_NAME is found!" -fi +# if [ "$BOARD_NAME" != "antsdr" ] && [ "$BOARD_NAME" != "zc706_fmcs2" ] && [ "$BOARD_NAME" != "zc702_fmcs2" ] && [ "$BOARD_NAME" != "zed_fmcs2" ] && [ "$BOARD_NAME" != "adrv9361z7035" ] && [ "$BOARD_NAME" != "adrv9364z7020" ]; then +# echo "\$BOARD_NAME is not correct. Please check!" +# exit 1 +# else +# echo "\$BOARD_NAME is found!" +# fi -if [ -d "$OPENWIFI_HW_DIR/boards/$BOARD_NAME" ]; then - echo "\$OPENWIFI_HW_DIR is found!" +if [ -f "$XSA_FILE" ]; then + echo "\$XSA_FILE is found!" else - echo "\$OPENWIFI_HW_DIR is not correct. Please check!" + echo "\$XSA_FILE is not found. Please check!" exit 1 fi @@ -50,17 +50,32 @@ home_dir=$(pwd) set -ex -# check if user entered the right path to SDK -source $XILINX_DIR/SDK/2018.3/settings64.sh - -# uncompress the system.hdf and system_top.bit for use -mkdir -p hdf_and_bit -tar -zxvf $OPENWIFI_HW_DIR/boards/$BOARD_NAME/sdk/system_top_hw_platform_0/hdf_and_bit.tar.gz -C ./hdf_and_bit -cp ./hdf_and_bit/$BOARD_NAME/sdk/system_top_hw_platform_0/system.hdf $OPENWIFI_HW_DIR/boards/$BOARD_NAME/sdk/system_top_hw_platform_0/ -rf -cp ./hdf_and_bit/$BOARD_NAME/sdk/system_top_hw_platform_0/system_top.bit $OPENWIFI_HW_DIR/boards/$BOARD_NAME/sdk/system_top_hw_platform_0/ -rf +source $XILINX_DIR/Vitis/2021.1/settings64.sh cd $OPENWIFI_DIR/kernel_boot -./build_boot_bin.sh $OPENWIFI_HW_DIR $BOARD_NAME +if [ "$BOARD_NAME" == "zcu102_fmcs2" ] || [ "$BOARD_NAME" == "zcu102_9371" ]; then + ./build_zynqmp_boot_bin.sh $XSA_FILE boards/$BOARD_NAME/u-boot_xilinx_zynqmp_zcu102_revA.elf boards/$BOARD_NAME/bl31.elf + ARCH="zynqmp" + ARCH_BIT=64 +elif [ "$BOARD_NAME" == "antsdr" ] || [ "$BOARD_NAME" == "antsdr_e200" ] || [ "$BOARD_NAME" == "sdrpi" ] || [ "$BOARD_NAME" == "neptunesdr" ] || [ "$BOARD_NAME" == "zc706_fmcs2" ] || [ "$BOARD_NAME" == "zc702_fmcs2" ] || [ "$BOARD_NAME" == "zed_fmcs2" ] || [ "$BOARD_NAME" == "adrv9361z7035" ] || [ "$BOARD_NAME" == "adrv9364z7020" ]; then + ./build_boot_bin.sh $XSA_FILE boards/$BOARD_NAME/u-boot.elf + ARCH="zynq" + ARCH_BIT=32 +else + echo "\$BOARD_NAME is not correct. Please check!" + cd $home_dir + exit 1 +fi + +rm -rf build_boot_bin +rm -rf boards/$BOARD_NAME/output_boot_bin +mv output_boot_bin boards/$BOARD_NAME/ cd $home_dir + +# generate system_top.bit.bin for FPGA dynamic loading +unzip -o $XSA_FILE +rm -rf ./system_top.bit.bin +bootgen -image system_top.bif -arch $ARCH -process_bitstream bin -w +ls ./system_top.bit.bin -al diff --git a/user_space/boot_bin_gen_zynqmp.sh b/user_space/boot_bin_gen_zynqmp.sh deleted file mode 100755 index fc1b6de..0000000 --- a/user_space/boot_bin_gen_zynqmp.sh +++ /dev/null @@ -1,70 +0,0 @@ -#!/bin/bash - -# Author: Xianjun Jiao -# SPDX-FileCopyrightText: 2019 UGent -# SPDX-License-Identifier: AGPL-3.0-or-later - -if [ "$#" -ne 3 ]; then - echo "You must enter exactly 3 arguments: \$OPENWIFI_HW_DIR \$XILINX_DIR \$BOARD_NAME" - exit 1 -fi - -OPENWIFI_HW_DIR=$1 -XILINX_DIR=$2 -BOARD_NAME=$3 - -OPENWIFI_DIR=$(pwd)/../ - -echo OPENWIFI_DIR $OPENWIFI_DIR -echo OPENWIFI_HW_DIR $OPENWIFI_HW_DIR - -if [ -f "$OPENWIFI_DIR/LICENSE" ]; then - echo "\$OPENWIFI_DIR is found!" -else - echo "\$OPENWIFI_DIR is not correct. Please check!" - exit 1 -fi - -if [ -d "$XILINX_DIR/SDK" ]; then - echo "\$XILINX_DIR is found!" -else - echo "\$XILINX_DIR is not correct. Please check!" - exit 1 -fi - -if [ "$BOARD_NAME" != "zcu102_fmcs2" ] && [ "$BOARD_NAME" != "zcu102_9371" ]; then - echo "\$BOARD_NAME is not correct. Please check!" - exit 1 -else - echo "\$BOARD_NAME is found!" -fi - -if [ -d "$OPENWIFI_HW_DIR/boards/$BOARD_NAME" ]; then - echo "\$OPENWIFI_HW_DIR is found!" -else - echo "\$OPENWIFI_HW_DIR is not correct. Please check!" - exit 1 -fi - -home_dir=$(pwd) - -set -ex - -# check if user entered the right path to SDK -source $XILINX_DIR/SDK/2018.3/settings64.sh - -# uncompress the system.hdf and system_top.bit for use -mkdir -p hdf_and_bit -tar -zxvf $OPENWIFI_HW_DIR/boards/$BOARD_NAME/sdk/system_top_hw_platform_0/hdf_and_bit.tar.gz -C ./hdf_and_bit -cp ./hdf_and_bit/$BOARD_NAME/sdk/system_top_hw_platform_0/system.hdf $OPENWIFI_HW_DIR/boards/$BOARD_NAME/sdk/system_top_hw_platform_0/ -rf -cp ./hdf_and_bit/$BOARD_NAME/sdk/system_top_hw_platform_0/system_top.bit $OPENWIFI_HW_DIR/boards/$BOARD_NAME/sdk/system_top_hw_platform_0/ -rf - -cd $OPENWIFI_DIR/kernel_boot - -./build_zynqmp_boot_bin.sh $OPENWIFI_HW_DIR/boards/$BOARD_NAME/sdk/system_top_hw_platform_0/system.hdf boards/$BOARD_NAME/u-boot-zcu.elf boards/$BOARD_NAME/bl31.elf - -rm -rf build_boot_bin -rm -rf boards/$BOARD_NAME/output_boot_bin -mv output_boot_bin boards/$BOARD_NAME/ - -cd $home_dir diff --git a/user_space/dhcpd.conf b/user_space/dhcpd.conf index 9cf974a..09c6220 100644 --- a/user_space/dhcpd.conf +++ b/user_space/dhcpd.conf @@ -13,7 +13,7 @@ ddns-update-style none; # option definitions common to all supported networks... -option domain-name "orca-project.eu"; +# option domain-name "orca-project.eu"; #option domain-name-servers ns1.example.org, ns2.example.org; default-lease-time 600; diff --git a/user_space/drv_and_fpga_package_gen.sh b/user_space/drv_and_fpga_package_gen.sh index 8d6a440..7b5c64b 100755 --- a/user_space/drv_and_fpga_package_gen.sh +++ b/user_space/drv_and_fpga_package_gen.sh @@ -7,42 +7,44 @@ if [ "$#" -ne 3 ]; then echo "You have input $# arguments." - echo "You must enter exactly 3 arguments: \$OPENWIFI_HW_DIR \$XILINX_DIR \$BOARD_NAME" + echo "You must enter exactly 3 arguments: \$OPENWIFI_HW_IMG_DIR \$XILINX_DIR \$BOARD_NAME" exit 1 fi -OPENWIFI_HW_DIR=$1 +OPENWIFI_HW_IMG_DIR=$1 XILINX_DIR=$2 BOARD_NAME=$3 -if [ -d "$XILINX_DIR/SDK" ]; then +if [ -d "$XILINX_DIR/Vitis" ]; then echo "\$XILINX_DIR is found!" else echo "\$XILINX_DIR is not correct. Please check!" exit 1 fi -if [ "$BOARD_NAME" != "antsdr" ] && [ "$BOARD_NAME" != "antsdr_e200" ] && [ "$BOARD_NAME" != "sdrpi" ] && [ "$BOARD_NAME" != "zc706_fmcs2" ] && [ "$BOARD_NAME" != "zc702_fmcs2" ] && [ "$BOARD_NAME" != "zed_fmcs2" ] && [ "$BOARD_NAME" != "adrv9361z7035" ] && [ "$BOARD_NAME" != "adrv9364z7020" ] && [ "$BOARD_NAME" != "zcu102_fmcs2" ] && [ "$BOARD_NAME" != "zcu102_9371" ]; then +if [ "$BOARD_NAME" != "neptunesdr" ] && [ "$BOARD_NAME" != "antsdr" ] && [ "$BOARD_NAME" != "antsdr_e200" ] && [ "$BOARD_NAME" != "sdrpi" ] && [ "$BOARD_NAME" != "zc706_fmcs2" ] && [ "$BOARD_NAME" != "zc702_fmcs2" ] && [ "$BOARD_NAME" != "zed_fmcs2" ] && [ "$BOARD_NAME" != "adrv9361z7035" ] && [ "$BOARD_NAME" != "adrv9364z7020" ] && [ "$BOARD_NAME" != "zcu102_fmcs2" ] && [ "$BOARD_NAME" != "zcu102_9371" ]; then echo "\$BOARD_NAME is not correct. Please check!" exit 1 else echo "\$BOARD_NAME is found!" fi -if [ -d "$OPENWIFI_HW_DIR/boards/$BOARD_NAME" ]; then - echo "\$OPENWIFI_HW_DIR is found!" +if [ -d "$OPENWIFI_HW_IMG_DIR/boards/$BOARD_NAME" ]; then + echo "\$OPENWIFI_HW_IMG_DIR is found!" else - echo "\$OPENWIFI_HW_DIR is not correct. Please check!" + echo "\$OPENWIFI_HW_IMG_DIR is not correct. Please check!" exit 1 fi # uncompress the system.hdf and system_top.bit for use mkdir -p hdf_and_bit -tar -zxvf $OPENWIFI_HW_DIR/boards/$BOARD_NAME/sdk/system_top_hw_platform_0/hdf_and_bit.tar.gz -C ./hdf_and_bit -cp ./hdf_and_bit/$BOARD_NAME/sdk/system_top_hw_platform_0/system.hdf $OPENWIFI_HW_DIR/boards/$BOARD_NAME/sdk/system_top_hw_platform_0/ -rf -cp ./hdf_and_bit/$BOARD_NAME/sdk/system_top_hw_platform_0/system_top.bit $OPENWIFI_HW_DIR/boards/$BOARD_NAME/sdk/system_top_hw_platform_0/ -rf +rm hdf_and_bit/* -rf +unzip $OPENWIFI_HW_IMG_DIR/boards/$BOARD_NAME/sdk/system_top.xsa -d ./hdf_and_bit +# cp ./hdf_and_bit/$BOARD_NAME/sdk/system_top_hw_platform_0/system.hdf $OPENWIFI_HW_IMG_DIR/boards/$BOARD_NAME/sdk/system_top_hw_platform_0/ -rf +# cp ./hdf_and_bit/system_top.bit $OPENWIFI_HW_IMG_DIR/boards/$BOARD_NAME/sdk/system_top_hw_platform_0/ -rf -BIT_FILENAME=$OPENWIFI_HW_DIR/boards/$BOARD_NAME/sdk/system_top_hw_platform_0/system_top.bit +# BIT_FILENAME=$OPENWIFI_HW_IMG_DIR/boards/$BOARD_NAME/sdk/system_top_hw_platform_0/system_top.bit +BIT_FILENAME=./hdf_and_bit/system_top.bit if [ -f "$BIT_FILENAME" ]; then echo "\$BIT_FILENAME is found!" @@ -61,7 +63,7 @@ fi # FINAL_BIT_FILENAME=$BOARD_NAME\_system_top_reload.bit.bin -source $XILINX_DIR/SDK/2018.3/settings64.sh +source $XILINX_DIR/Vitis/2021.1/settings64.sh set -x @@ -76,29 +78,29 @@ make clean cd ../user_space mkdir -p drv_and_fpga rm -rf drv_and_fpga/* -cp system_top.bit.bin ../driver/tx_intf/tx_intf.ko ../driver/rx_intf/rx_intf.ko ../driver/openofdm_tx/openofdm_tx.ko ../driver/openofdm_rx/openofdm_rx.ko ../driver/xpu/xpu.ko ../driver/sdr.ko ./drv_and_fpga -f -cp $OPENWIFI_HW_DIR/boards/$BOARD_NAME/sdk/git_info.txt ./drv_and_fpga -f +cp system_top.bit.bin ../driver/side_ch/side_ch.ko ../driver/tx_intf/tx_intf.ko ../driver/rx_intf/rx_intf.ko ../driver/openofdm_tx/openofdm_tx.ko ../driver/openofdm_rx/openofdm_rx.ko ../driver/xpu/xpu.ko ../driver/sdr.ko ./drv_and_fpga -f +cp $OPENWIFI_HW_IMG_DIR/boards/$BOARD_NAME/sdk/git_info.txt ./drv_and_fpga -f tar -cvf ./drv_and_fpga/driver.tar $(git ls-files ../driver/) -dir_save=$(pwd) +# dir_save=$(pwd) -cd $OPENWIFI_HW_DIR/ip/ -tar -cvf $dir_save/drv_and_fpga/openwifi-hw-ip-root.tar $(git ls-files ./ | grep -v -E "/|openofdm_rx") -tar -cvf $dir_save/drv_and_fpga/openwifi-hw-ip-xpu.tar $(git ls-files ./xpu) -tar -cvf $dir_save/drv_and_fpga/openwifi-hw-ip-tx_intf.tar $(git ls-files ./tx_intf) -tar -cvf $dir_save/drv_and_fpga/openwifi-hw-ip-rx_intf.tar $(git ls-files ./rx_intf) -tar -cvf $dir_save/drv_and_fpga/openwifi-hw-ip-openofdm_tx.tar $(git ls-files ./openofdm_tx) -tar -cvf $dir_save/drv_and_fpga/openwifi-hw-ip-side_ch.tar $(git ls-files ./side_ch) +# cd $OPENWIFI_HW_DIR/ip/ +# tar -cvf $dir_save/drv_and_fpga/openwifi-hw-ip-root.tar $(git ls-files ./ | grep -v -E "/|openofdm_rx") +# tar -cvf $dir_save/drv_and_fpga/openwifi-hw-ip-xpu.tar $(git ls-files ./xpu) +# tar -cvf $dir_save/drv_and_fpga/openwifi-hw-ip-tx_intf.tar $(git ls-files ./tx_intf) +# tar -cvf $dir_save/drv_and_fpga/openwifi-hw-ip-rx_intf.tar $(git ls-files ./rx_intf) +# tar -cvf $dir_save/drv_and_fpga/openwifi-hw-ip-openofdm_tx.tar $(git ls-files ./openofdm_tx) +# tar -cvf $dir_save/drv_and_fpga/openwifi-hw-ip-side_ch.tar $(git ls-files ./side_ch) -cd ../boards -tar -cvf $dir_save/drv_and_fpga/openwifi-hw-boards-root.tar $(git ls-files ./ | grep -v "/") -cd ./$BOARD_NAME -tar -cvf $dir_save/drv_and_fpga/openwifi-hw-boards-$BOARD_NAME-root.tar $(git ls-files ./ | grep -v "/") -tar -cvf $dir_save/drv_and_fpga/openwifi-hw-boards-$BOARD_NAME-src.tar $(git ls-files ./src) -tar -cvf $dir_save/drv_and_fpga/openwifi-hw-boards-$BOARD_NAME-ip_repo.tar ip_repo +# cd ../boards +# tar -cvf $dir_save/drv_and_fpga/openwifi-hw-boards-root.tar $(git ls-files ./ | grep -v "/") +# cd ./$BOARD_NAME +# tar -cvf $dir_save/drv_and_fpga/openwifi-hw-boards-$BOARD_NAME-root.tar $(git ls-files ./ | grep -v "/") +# tar -cvf $dir_save/drv_and_fpga/openwifi-hw-boards-$BOARD_NAME-src.tar $(git ls-files ./src) +# tar -cvf $dir_save/drv_and_fpga/openwifi-hw-boards-$BOARD_NAME-ip_repo.tar ip_repo -cd $dir_save -# tar -cvf drv_and_fpga.tar system_top.bit.bin tx_intf.ko rx_intf.ko openofdm_tx.ko openofdm_rx.ko xpu.ko sdr.ko git_info.txt +# cd $dir_save +# # tar -cvf drv_and_fpga.tar system_top.bit.bin tx_intf.ko rx_intf.ko openofdm_tx.ko openofdm_rx.ko xpu.ko sdr.ko git_info.txt tar -zcvf drv_and_fpga.tar.gz drv_and_fpga diff --git a/user_space/eifs_by_last_rx_fail_disable.sh b/user_space/eifs_by_last_rx_fail_disable.sh new file mode 100755 index 0000000..98187a1 --- /dev/null +++ b/user_space/eifs_by_last_rx_fail_disable.sh @@ -0,0 +1,21 @@ +#!/bin/bash + +home_dir=$(pwd) + +if test -d "/sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr"; then + cd /sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr +else + cd /sys/devices/soc0/fpga-axi\@0/fpga-axi\@0\:sdr +fi + +set -x +#set +if [[ -n $1 ]]; then + echo "4$1" > csma_cfg0 +fi + +# show +cat csma_cfg0 +set +x + +cd $home_dir diff --git a/user_space/eifs_by_last_tx_fail_disable.sh b/user_space/eifs_by_last_tx_fail_disable.sh new file mode 100755 index 0000000..ac92581 --- /dev/null +++ b/user_space/eifs_by_last_tx_fail_disable.sh @@ -0,0 +1,21 @@ +#!/bin/bash + +home_dir=$(pwd) + +if test -d "/sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr"; then + cd /sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr +else + cd /sys/devices/soc0/fpga-axi\@0/fpga-axi\@0\:sdr +fi + +set -x +#set +if [[ -n $1 ]]; then + echo "5$1" > csma_cfg0 +fi + +# show +cat csma_cfg0 +set +x + +cd $home_dir diff --git a/user_space/fast_reg_log/fast_reg_log.c b/user_space/fast_reg_log/fast_reg_log.c new file mode 100644 index 0000000..549bc13 --- /dev/null +++ b/user_space/fast_reg_log/fast_reg_log.c @@ -0,0 +1,60 @@ +// Author: Xianjun Jiao (xianjun.jiao@imec.be; putaoshu@msn.com) +// SPDX-FileCopyrightText: 2023 UGent +// SPDX-License-Identifier: AGPL-3.0-or-later + +// Use this example together with fast_reg_log_analyzer.m (notter release) + +#include +#include +#include +#include +#include +#include +#include + +int main() +{ + unsigned int bram_size = 0x10000; // 64KB, aligned with openwifi hw .bd and devicetree + off_t bram_pbase = 0x83c40000; // physical base address, aligned with openwifi hw .bd and devicetree (this example: xpu @ 32bit boards) + uint32_t *bram32_vptr; + int fd, i, j; + uint32_t tsf_reg[524288*2]; + FILE *fp; + // Map the BRAM physical address into user space getting a virtual address for it + if ((fd = open("/dev/mem", O_RDONLY | O_SYNC)) != -1) { + bram32_vptr = (uint32_t *)mmap(NULL, bram_size, PROT_READ, MAP_SHARED, fd, bram_pbase); + + fp = fopen ("fast_reg_log.bin", "wb"); + if (fp == NULL) { + printf("fopen fast_reg_log.bin failed! %d\n", (int)fp); + close(fd); + return(0); + } + + for (j=0; j<10; j++) { + for (i=0; i<(524288*2); i=i+2) { + tsf_reg[i+0] = (*(bram32_vptr+57)); // read xpu register 57: rssi trx agc cca status + tsf_reg[i+1] = (*(bram32_vptr+58)); // read xpu register 58: low 32bit of tsf + } + + // for (i=0; i<1024; i++) { + // printf("%d %x\n", tsf[i], reg[i]); + // } + // memcpy(buf, bram64_vptr, bram_size); + + fwrite(tsf_reg, sizeof(uint32_t), 524288*2, fp); + } + + fclose(fp); + // printf("%016llx\n", buf[65532]); + // printf("%016llx\n", buf[65533]); + // printf("%016llx\n", buf[65534]); + // printf("%016llx\n", buf[65535]); + // //for(i=0; i<32; i++) { + // // printf("0x%02x\n", buf[i]); + // //} + + close(fd); + } + return(0); +} diff --git a/user_space/fast_reg_log/fast_reg_log_analyzer.m b/user_space/fast_reg_log/fast_reg_log_analyzer.m new file mode 100644 index 0000000..89c7210 --- /dev/null +++ b/user_space/fast_reg_log/fast_reg_log_analyzer.m @@ -0,0 +1,71 @@ +% Author: Xianjun Jiao (xianjun.jiao@imec.be; putaoshu@msn.com) +% SPDX-FileCopyrightText: 2023 UGent +% SPDX-License-Identifier: AGPL-3.0-or-later + +function fast_reg_log_analyzer(filename_bin, start_idx, end_idx) +close all; + +% if exist('start_idx', 'var')==0 || isempty(start_idx) +% start_idx = 1; +% end +% +% if exist('end_idx', 'var')==0 || isempty(end_idx) +% end_idx = 65536; +% end + +filename_csv = [filename_bin(1:(end-3)) 'csv']; +disp(['Human readable fast reg log will be in ' filename_csv]); + +fid = fopen(filename_bin); +if fid == -1 + disp('fopen failed!'); + return; +end + +a = fread(fid, inf, 'uint32'); +fclose(fid); +% a = bitand(uint32(a), uint32(268435455)); +% plot(a(1:2:end)); hold on; +% plot(a(2:2:end)); +% legend('1', '2'); + +a = uint32(a); +tsf = a(2:2:end); +% plot(tsf); +state = a(1:2:end); + +% find out overflow idx +overflow_idx = find(diff([0; double(tsf)])<0, 1, 'first'); +% overflow_idx +if ~isempty(overflow_idx) + tsf(overflow_idx:end) = tsf(overflow_idx:end) + (2^32); + disp(num2str(overflow_idx)); +end + +rssi_correction = 145; +rssi_half_db = double(bitand(bitshift(state, 0), uint32((2^11)-1))); +agc_lock = 1 - double(bitand(bitshift(state, -11), uint32(1))); +demod_is_ongoing = double(bitand(bitshift(state, -12), uint32(1))); +tx_is_ongoing = double(bitand(bitshift(state, -13), uint32(1))); +ch_idle = 1 - double(bitand(bitshift(state, -14), uint32(1))); +iq_rssi_half_db = double(bitand(bitshift(state, -16), uint32((2^9)-1))); +agc_gain = double(bitand(bitshift(state, -25), uint32((2^7)-1))); + +rssi_dbm = (rssi_half_db./2) - rssi_correction; + +figure; +subplot(2,1,1); +plot(tsf, -rssi_dbm, 'r+-'); hold on; +plot(tsf, iq_rssi_half_db, 'bo-'); +plot(tsf, agc_gain, 'ks-'); +legend('rssi dbm', 'iq rssi half db', 'agc gain'); +subplot(2,1,2); +plot(tsf, agc_lock+0); hold on; +plot(tsf, demod_is_ongoing+2); +plot(tsf, tx_is_ongoing+4); +plot(tsf, ch_idle+6); + +legend('agc lock', 'demod is ongoing', 'tx is ongoing', 'ch idle'); + +a=table(tsf, rssi_half_db, rssi_dbm, iq_rssi_half_db, agc_gain, agc_lock, demod_is_ongoing, tx_is_ongoing, ch_idle); +writetable(a, filename_csv); diff --git a/user_space/fosdem-11ag.sh b/user_space/fosdem-11ag.sh index 0c9b1fe..4b26872 100755 --- a/user_space/fosdem-11ag.sh +++ b/user_space/fosdem-11ag.sh @@ -15,12 +15,14 @@ killall hostapd killall webfsd cd ~/openwifi -service network-manager stop +# service network-manager stop # ./wgd.sh $test_mode ifconfig sdr0 192.168.13.1 -route add default gw 192.168.10.1 +rm /var/run/dhcpd.pid +sleep 1 service isc-dhcp-server restart hostapd hostapd-openwifi-11ag.conf & sleep 5 cd webserver webfsd -F -p 80 -f index.html & +route add default gw 192.168.10.1 diff --git a/user_space/fosdem.sh b/user_space/fosdem.sh index 7fe77f0..9d35506 100755 --- a/user_space/fosdem.sh +++ b/user_space/fosdem.sh @@ -15,12 +15,15 @@ killall hostapd killall webfsd cd ~/openwifi -service network-manager stop +# service network-manager stop # ./wgd.sh $test_mode ifconfig sdr0 192.168.13.1 -route add default gw 192.168.10.1 +rm /var/run/dhcpd.pid +sleep 1 service isc-dhcp-server restart hostapd hostapd-openwifi.conf & sleep 5 cd webserver webfsd -F -p 80 -f index.html & +route add default gw 192.168.10.1 + diff --git a/user_space/hostapd-openwifi-11ag.conf b/user_space/hostapd-openwifi-11ag.conf index b14d87d..54a24df 100644 --- a/user_space/hostapd-openwifi-11ag.conf +++ b/user_space/hostapd-openwifi-11ag.conf @@ -3,7 +3,7 @@ driver=nl80211 country_code=BE ssid=openwifi hw_mode=a -channel=44 +channel=36 supported_rates=60 90 120 180 240 360 480 540 basic_rates=60 90 120 180 #ieee80211n=1 @@ -11,6 +11,9 @@ basic_rates=60 90 120 180 #require_ht=1 #ieee80211d=1 #ieee80211h=1 -#wpa=2 -#wpa_passphrase=myrabbit +#wpa=1 +#wpa_passphrase=openwifi #wpa_key_mgmt=WPA-PSK +#wpa_pairwise=TKIP CCMP +#wpa_ptk_rekey=600 + diff --git a/user_space/hostapd-openwifi.conf b/user_space/hostapd-openwifi.conf index 64a3e78..b3a09da 100644 --- a/user_space/hostapd-openwifi.conf +++ b/user_space/hostapd-openwifi.conf @@ -3,7 +3,7 @@ driver=nl80211 country_code=BE ssid=openwifi hw_mode=a -channel=44 +channel=36 supported_rates=60 90 120 180 240 360 480 540 basic_rates=60 90 120 180 ieee80211n=1 @@ -11,6 +11,9 @@ ieee80211n=1 require_ht=1 #ieee80211d=1 #ieee80211h=1 -#wpa=2 -#wpa_passphrase=myrabbit +#wpa=1 +#wpa_passphrase=openwifi #wpa_key_mgmt=WPA-PSK +#wpa_pairwise=TKIP CCMP +#wpa_ptk_rekey=600 + diff --git a/user_space/inject_80211/Makefile b/user_space/inject_80211/Makefile index b769ee1..e6596b1 100644 --- a/user_space/inject_80211/Makefile +++ b/user_space/inject_80211/Makefile @@ -2,11 +2,12 @@ all: inject_80211 analyze_80211 inject_80211: inject_80211.c - gcc -Wall -Werror inject_80211.c -o inject_80211 -lpcap +# gcc -Wall -Werror inject_80211.c -o inject_80211 -lpcap + gcc -Wall inject_80211.c -o inject_80211 -lpcap analyze_80211: analyze_80211.c - gcc -Wall -Werror radiotap.c analyze_80211.c -o analyze_80211 -lpcap - +# gcc -Wall -Werror radiotap.c analyze_80211.c -o analyze_80211 -lpcap + gcc -Wall radiotap.c analyze_80211.c -o analyze_80211 -lpcap clean: rm -f inject_80211 analyze_80211 diff --git a/user_space/inject_80211/analyze_80211.c b/user_space/inject_80211/analyze_80211.c index a6d1dbd..32d8049 100644 --- a/user_space/inject_80211/analyze_80211.c +++ b/user_space/inject_80211/analyze_80211.c @@ -75,7 +75,7 @@ int main(int argc, char **argv) if (packet_size < 0) continue; - if (ieee80211_radiotap_iterator_init(&rti, (struct ieee80211_radiotap_header *)packet, packet_size) < 0) + if (ieee80211_radiotap_iterator_init(&rti, (struct ieee80211_radiotap_header *)packet, packet_size, NULL) < 0) continue; while ((n = ieee80211_radiotap_iterator_next(&rti)) == 0) diff --git a/user_space/inject_80211/ieee80211_radiotap.h b/user_space/inject_80211/ieee80211_radiotap.h index cf5846a..e1f78fc 100644 --- a/user_space/inject_80211/ieee80211_radiotap.h +++ b/user_space/inject_80211/ieee80211_radiotap.h @@ -1,196 +1,55 @@ /* - * Copyright (c) 2003, 2004 David Young. All rights reserved. + * Copyright (c) 2017 Intel Deutschland GmbH + * Copyright (c) 2018-2019 Intel Corporation * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of David Young may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. * - * THIS SOFTWARE IS PROVIDED BY DAVID YOUNG ``AS IS'' AND ANY - * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A - * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL DAVID - * YOUNG BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED - * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ +#ifndef __RADIOTAP_H +#define __RADIOTAP_H -/* - * Modifications to fit into the linux IEEE 802.11 stack, - * Mike Kershaw (dragorn@kismetwireless.net) - */ - -#ifndef IEEE80211RADIOTAP_H -#define IEEE80211RADIOTAP_H - -#include #include +// #include -/* Base version of the radiotap packet header data */ -#define PKTHDR_RADIOTAP_VERSION 0 - -/* A generic radio capture format is desirable. There is one for - * Linux, but it is neither rigidly defined (there were not even - * units given for some fields) nor easily extensible. - * - * I suggest the following extensible radio capture format. It is - * based on a bitmap indicating which fields are present. - * - * I am trying to describe precisely what the application programmer - * should expect in the following, and for that reason I tell the - * units and origin of each measurement (where it applies), or else I - * use sufficiently weaselly language ("is a monotonically nondecreasing - * function of...") that I cannot set false expectations for lawyerly - * readers. - */ - -/* - * The radio capture header precedes the 802.11 header. - * All data in the header is little endian on all platforms. +/** + * struct ieee82011_radiotap_header - base radiotap header */ struct ieee80211_radiotap_header { - u8 it_version; /* Version 0. Only increases - * for drastic changes, - * introduction of compatible - * new fields does not count. - */ - u8 it_pad; - __le16 it_len; /* length of the whole - * header in bytes, including - * it_version, it_pad, - * it_len, and data fields. - */ - __le32 it_present; /* A bitmap telling which - * fields are present. Set bit 31 - * (0x80000000) to extend the - * bitmap by another 32 bits. - * Additional extensions are made - * by setting bit 31. - */ -} __packed; + /** + * @it_version: radiotap version, always 0 + */ + uint8_t it_version; -/* Name Data type Units - * ---- --------- ----- - * - * IEEE80211_RADIOTAP_TSFT __le64 microseconds - * - * Value in microseconds of the MAC's 64-bit 802.11 Time - * Synchronization Function timer when the first bit of the - * MPDU arrived at the MAC. For received frames, only. - * - * IEEE80211_RADIOTAP_CHANNEL 2 x __le16 MHz, bitmap - * - * Tx/Rx frequency in MHz, followed by flags (see below). - * - * IEEE80211_RADIOTAP_FHSS __le16 see below - * - * For frequency-hopping radios, the hop set (first byte) - * and pattern (second byte). - * - * IEEE80211_RADIOTAP_RATE u8 500kb/s - * - * Tx/Rx data rate - * - * IEEE80211_RADIOTAP_DBM_ANTSIGNAL s8 decibels from - * one milliwatt (dBm) - * - * RF signal power at the antenna, decibel difference from - * one milliwatt. - * - * IEEE80211_RADIOTAP_DBM_ANTNOISE s8 decibels from - * one milliwatt (dBm) - * - * RF noise power at the antenna, decibel difference from one - * milliwatt. - * - * IEEE80211_RADIOTAP_DB_ANTSIGNAL u8 decibel (dB) - * - * RF signal power at the antenna, decibel difference from an - * arbitrary, fixed reference. - * - * IEEE80211_RADIOTAP_DB_ANTNOISE u8 decibel (dB) - * - * RF noise power at the antenna, decibel difference from an - * arbitrary, fixed reference point. - * - * IEEE80211_RADIOTAP_LOCK_QUALITY __le16 unitless - * - * Quality of Barker code lock. Unitless. Monotonically - * nondecreasing with "better" lock strength. Called "Signal - * Quality" in datasheets. (Is there a standard way to measure - * this?) - * - * IEEE80211_RADIOTAP_TX_ATTENUATION __le16 unitless - * - * Transmit power expressed as unitless distance from max - * power set at factory calibration. 0 is max power. - * Monotonically nondecreasing with lower power levels. - * - * IEEE80211_RADIOTAP_DB_TX_ATTENUATION __le16 decibels (dB) - * - * Transmit power expressed as decibel distance from max power - * set at factory calibration. 0 is max power. Monotonically - * nondecreasing with lower power levels. - * - * IEEE80211_RADIOTAP_DBM_TX_POWER s8 decibels from - * one milliwatt (dBm) - * - * Transmit power expressed as dBm (decibels from a 1 milliwatt - * reference). This is the absolute power level measured at - * the antenna port. - * - * IEEE80211_RADIOTAP_FLAGS u8 bitmap - * - * Properties of transmitted and received frames. See flags - * defined below. - * - * IEEE80211_RADIOTAP_ANTENNA u8 antenna index - * - * Unitless indication of the Rx/Tx antenna for this packet. - * The first antenna is antenna 0. - * - * IEEE80211_RADIOTAP_RX_FLAGS __le16 bitmap - * - * Properties of received frames. See flags defined below. - * - * IEEE80211_RADIOTAP_TX_FLAGS __le16 bitmap - * - * Properties of transmitted frames. See flags defined below. - * - * IEEE80211_RADIOTAP_RTS_RETRIES u8 data - * - * Number of rts retries a transmitted frame used. - * - * IEEE80211_RADIOTAP_DATA_RETRIES u8 data - * - * Number of unicast retries a transmitted frame used. - * - * IEEE80211_RADIOTAP_MCS u8, u8, u8 unitless - * - * Contains a bitmap of known fields/flags, the flags, and - * the MCS index. - * - * IEEE80211_RADIOTAP_AMPDU_STATUS u32, u16, u8, u8 unitless - * - * Contains the AMPDU information for the subframe. - * - * IEEE80211_RADIOTAP_VHT u16, u8, u8, u8[4], u8, u8, u16 - * - * Contains VHT information about this frame. - */ -enum ieee80211_radiotap_type { + /** + * @it_pad: padding (or alignment) + */ + uint8_t it_pad; + + /** + * @it_len: overall radiotap header length + */ + __le16 it_len; + + /** + * @it_present: (first) present word + */ + __le32 it_present; +} __attribute__((packed)); + +/* version is always 0 */ +#define PKTHDR_RADIOTAP_VERSION 0 + +/* see the radiotap website for the descriptions */ +enum ieee80211_radiotap_presence { IEEE80211_RADIOTAP_TSFT = 0, IEEE80211_RADIOTAP_FLAGS = 1, IEEE80211_RADIOTAP_RATE = 2, @@ -209,10 +68,15 @@ enum ieee80211_radiotap_type { IEEE80211_RADIOTAP_TX_FLAGS = 15, IEEE80211_RADIOTAP_RTS_RETRIES = 16, IEEE80211_RADIOTAP_DATA_RETRIES = 17, - + /* 18 is XChannel, but it's not defined yet */ IEEE80211_RADIOTAP_MCS = 19, IEEE80211_RADIOTAP_AMPDU_STATUS = 20, IEEE80211_RADIOTAP_VHT = 21, + IEEE80211_RADIOTAP_TIMESTAMP = 22, + IEEE80211_RADIOTAP_HE = 23, + IEEE80211_RADIOTAP_HE_MU = 24, + IEEE80211_RADIOTAP_ZERO_LEN_PSDU = 26, + IEEE80211_RADIOTAP_LSIG = 27, /* valid in every it_present bitmap, even vendor namespaces */ IEEE80211_RADIOTAP_RADIOTAP_NAMESPACE = 29, @@ -220,88 +84,284 @@ enum ieee80211_radiotap_type { IEEE80211_RADIOTAP_EXT = 31 }; -/* Channel flags. */ -#define IEEE80211_CHAN_TURBO 0x0010 /* Turbo channel */ -#define IEEE80211_CHAN_CCK 0x0020 /* CCK channel */ -#define IEEE80211_CHAN_OFDM 0x0040 /* OFDM channel */ -#define IEEE80211_CHAN_2GHZ 0x0080 /* 2 GHz spectrum channel. */ -#define IEEE80211_CHAN_5GHZ 0x0100 /* 5 GHz spectrum channel */ -#define IEEE80211_CHAN_PASSIVE 0x0200 /* Only passive scan allowed */ -#define IEEE80211_CHAN_DYN 0x0400 /* Dynamic CCK-OFDM channel */ -#define IEEE80211_CHAN_GFSK 0x0800 /* GFSK channel (FHSS PHY) */ +/* for IEEE80211_RADIOTAP_FLAGS */ +enum ieee80211_radiotap_flags { + IEEE80211_RADIOTAP_F_CFP = 0x01, + IEEE80211_RADIOTAP_F_SHORTPRE = 0x02, + IEEE80211_RADIOTAP_F_WEP = 0x04, + IEEE80211_RADIOTAP_F_FRAG = 0x08, + IEEE80211_RADIOTAP_F_FCS = 0x10, + IEEE80211_RADIOTAP_F_DATAPAD = 0x20, + IEEE80211_RADIOTAP_F_BADFCS = 0x40, +}; -/* For IEEE80211_RADIOTAP_FLAGS */ -#define IEEE80211_RADIOTAP_F_CFP 0x01 /* sent/received - * during CFP - */ -#define IEEE80211_RADIOTAP_F_SHORTPRE 0x02 /* sent/received - * with short - * preamble - */ -#define IEEE80211_RADIOTAP_F_WEP 0x04 /* sent/received - * with WEP encryption - */ -#define IEEE80211_RADIOTAP_F_FRAG 0x08 /* sent/received - * with fragmentation - */ -#define IEEE80211_RADIOTAP_F_FCS 0x10 /* frame includes FCS */ -#define IEEE80211_RADIOTAP_F_DATAPAD 0x20 /* frame has padding between - * 802.11 header and payload - * (to 32-bit boundary) - */ -#define IEEE80211_RADIOTAP_F_BADFCS 0x40 /* bad FCS */ +/* for IEEE80211_RADIOTAP_CHANNEL */ +enum ieee80211_radiotap_channel_flags { + IEEE80211_CHAN_CCK = 0x0020, + IEEE80211_CHAN_OFDM = 0x0040, + IEEE80211_CHAN_2GHZ = 0x0080, + IEEE80211_CHAN_5GHZ = 0x0100, + IEEE80211_CHAN_DYN = 0x0400, + IEEE80211_CHAN_HALF = 0x4000, + IEEE80211_CHAN_QUARTER = 0x8000, +}; -/* For IEEE80211_RADIOTAP_RX_FLAGS */ -#define IEEE80211_RADIOTAP_F_RX_BADPLCP 0x0002 /* frame has bad PLCP */ +/* for IEEE80211_RADIOTAP_RX_FLAGS */ +enum ieee80211_radiotap_rx_flags { + IEEE80211_RADIOTAP_F_RX_BADPLCP = 0x0002, +}; -/* For IEEE80211_RADIOTAP_TX_FLAGS */ -#define IEEE80211_RADIOTAP_F_TX_FAIL 0x0001 /* failed due to excessive - * retries */ -#define IEEE80211_RADIOTAP_F_TX_CTS 0x0002 /* used cts 'protection' */ -#define IEEE80211_RADIOTAP_F_TX_RTS 0x0004 /* used rts/cts handshake */ -#define IEEE80211_RADIOTAP_F_TX_NOACK 0x0008 /* don't expect an ack */ +/* for IEEE80211_RADIOTAP_TX_FLAGS */ +enum ieee80211_radiotap_tx_flags { + IEEE80211_RADIOTAP_F_TX_FAIL = 0x0001, + IEEE80211_RADIOTAP_F_TX_CTS = 0x0002, + IEEE80211_RADIOTAP_F_TX_RTS = 0x0004, + IEEE80211_RADIOTAP_F_TX_NOACK = 0x0008, + IEEE80211_RADIOTAP_F_TX_NOSEQNO = 0x0010, +}; +/* for IEEE80211_RADIOTAP_MCS "have" flags */ +enum ieee80211_radiotap_mcs_have { + IEEE80211_RADIOTAP_MCS_HAVE_BW = 0x01, + IEEE80211_RADIOTAP_MCS_HAVE_MCS = 0x02, + IEEE80211_RADIOTAP_MCS_HAVE_GI = 0x04, + IEEE80211_RADIOTAP_MCS_HAVE_FMT = 0x08, + IEEE80211_RADIOTAP_MCS_HAVE_FEC = 0x10, + IEEE80211_RADIOTAP_MCS_HAVE_STBC = 0x20, +}; -/* For IEEE80211_RADIOTAP_MCS */ -#define IEEE80211_RADIOTAP_MCS_HAVE_BW 0x01 -#define IEEE80211_RADIOTAP_MCS_HAVE_MCS 0x02 -#define IEEE80211_RADIOTAP_MCS_HAVE_GI 0x04 -#define IEEE80211_RADIOTAP_MCS_HAVE_FMT 0x08 -#define IEEE80211_RADIOTAP_MCS_HAVE_FEC 0x10 +enum ieee80211_radiotap_mcs_flags { + IEEE80211_RADIOTAP_MCS_BW_MASK = 0x03, + IEEE80211_RADIOTAP_MCS_BW_20 = 0, + IEEE80211_RADIOTAP_MCS_BW_40 = 1, + IEEE80211_RADIOTAP_MCS_BW_20L = 2, + IEEE80211_RADIOTAP_MCS_BW_20U = 3, -#define IEEE80211_RADIOTAP_MCS_BW_MASK 0x03 -#define IEEE80211_RADIOTAP_MCS_BW_20 0 -#define IEEE80211_RADIOTAP_MCS_BW_40 1 -#define IEEE80211_RADIOTAP_MCS_BW_20L 2 -#define IEEE80211_RADIOTAP_MCS_BW_20U 3 -#define IEEE80211_RADIOTAP_MCS_SGI 0x04 -#define IEEE80211_RADIOTAP_MCS_FMT_GF 0x08 -#define IEEE80211_RADIOTAP_MCS_FEC_LDPC 0x10 + IEEE80211_RADIOTAP_MCS_SGI = 0x04, + IEEE80211_RADIOTAP_MCS_FMT_GF = 0x08, + IEEE80211_RADIOTAP_MCS_FEC_LDPC = 0x10, + IEEE80211_RADIOTAP_MCS_STBC_MASK = 0x60, + IEEE80211_RADIOTAP_MCS_STBC_1 = 1, + IEEE80211_RADIOTAP_MCS_STBC_2 = 2, + IEEE80211_RADIOTAP_MCS_STBC_3 = 3, + IEEE80211_RADIOTAP_MCS_STBC_SHIFT = 5, +}; -/* For IEEE80211_RADIOTAP_AMPDU_STATUS */ -#define IEEE80211_RADIOTAP_AMPDU_REPORT_ZEROLEN 0x0001 -#define IEEE80211_RADIOTAP_AMPDU_IS_ZEROLEN 0x0002 -#define IEEE80211_RADIOTAP_AMPDU_LAST_KNOWN 0x0004 -#define IEEE80211_RADIOTAP_AMPDU_IS_LAST 0x0008 -#define IEEE80211_RADIOTAP_AMPDU_DELIM_CRC_ERR 0x0010 -#define IEEE80211_RADIOTAP_AMPDU_DELIM_CRC_KNOWN 0x0020 +/* for IEEE80211_RADIOTAP_AMPDU_STATUS */ +enum ieee80211_radiotap_ampdu_flags { + IEEE80211_RADIOTAP_AMPDU_REPORT_ZEROLEN = 0x0001, + IEEE80211_RADIOTAP_AMPDU_IS_ZEROLEN = 0x0002, + IEEE80211_RADIOTAP_AMPDU_LAST_KNOWN = 0x0004, + IEEE80211_RADIOTAP_AMPDU_IS_LAST = 0x0008, + IEEE80211_RADIOTAP_AMPDU_DELIM_CRC_ERR = 0x0010, + IEEE80211_RADIOTAP_AMPDU_DELIM_CRC_KNOWN = 0x0020, + IEEE80211_RADIOTAP_AMPDU_EOF = 0x0040, + IEEE80211_RADIOTAP_AMPDU_EOF_KNOWN = 0x0080, +}; -/* For IEEE80211_RADIOTAP_VHT */ -#define IEEE80211_RADIOTAP_VHT_KNOWN_STBC 0x0001 -#define IEEE80211_RADIOTAP_VHT_KNOWN_TXOP_PS_NA 0x0002 -#define IEEE80211_RADIOTAP_VHT_KNOWN_GI 0x0004 -#define IEEE80211_RADIOTAP_VHT_KNOWN_SGI_NSYM_DIS 0x0008 -#define IEEE80211_RADIOTAP_VHT_KNOWN_LDPC_EXTRA_OFDM_SYM 0x0010 -#define IEEE80211_RADIOTAP_VHT_KNOWN_BEAMFORMED 0x0020 -#define IEEE80211_RADIOTAP_VHT_KNOWN_BANDWIDTH 0x0040 -#define IEEE80211_RADIOTAP_VHT_KNOWN_GROUP_ID 0x0080 -#define IEEE80211_RADIOTAP_VHT_KNOWN_PARTIAL_AID 0x0100 +/* for IEEE80211_RADIOTAP_VHT */ +enum ieee80211_radiotap_vht_known { + IEEE80211_RADIOTAP_VHT_KNOWN_STBC = 0x0001, + IEEE80211_RADIOTAP_VHT_KNOWN_TXOP_PS_NA = 0x0002, + IEEE80211_RADIOTAP_VHT_KNOWN_GI = 0x0004, + IEEE80211_RADIOTAP_VHT_KNOWN_SGI_NSYM_DIS = 0x0008, + IEEE80211_RADIOTAP_VHT_KNOWN_LDPC_EXTRA_OFDM_SYM = 0x0010, + IEEE80211_RADIOTAP_VHT_KNOWN_BEAMFORMED = 0x0020, + IEEE80211_RADIOTAP_VHT_KNOWN_BANDWIDTH = 0x0040, + IEEE80211_RADIOTAP_VHT_KNOWN_GROUP_ID = 0x0080, + IEEE80211_RADIOTAP_VHT_KNOWN_PARTIAL_AID = 0x0100, +}; -#define IEEE80211_RADIOTAP_VHT_FLAG_STBC 0x01 -#define IEEE80211_RADIOTAP_VHT_FLAG_TXOP_PS_NA 0x02 -#define IEEE80211_RADIOTAP_VHT_FLAG_SGI 0x04 -#define IEEE80211_RADIOTAP_VHT_FLAG_SGI_NSYM_M10_9 0x08 -#define IEEE80211_RADIOTAP_VHT_FLAG_LDPC_EXTRA_OFDM_SYM 0x10 -#define IEEE80211_RADIOTAP_VHT_FLAG_BEAMFORMED 0x20 +enum ieee80211_radiotap_vht_flags { + IEEE80211_RADIOTAP_VHT_FLAG_STBC = 0x01, + IEEE80211_RADIOTAP_VHT_FLAG_TXOP_PS_NA = 0x02, + IEEE80211_RADIOTAP_VHT_FLAG_SGI = 0x04, + IEEE80211_RADIOTAP_VHT_FLAG_SGI_NSYM_M10_9 = 0x08, + IEEE80211_RADIOTAP_VHT_FLAG_LDPC_EXTRA_OFDM_SYM = 0x10, + IEEE80211_RADIOTAP_VHT_FLAG_BEAMFORMED = 0x20, +}; -#endif /* IEEE80211_RADIOTAP_H */ +enum ieee80211_radiotap_vht_coding { + IEEE80211_RADIOTAP_CODING_LDPC_USER0 = 0x01, + IEEE80211_RADIOTAP_CODING_LDPC_USER1 = 0x02, + IEEE80211_RADIOTAP_CODING_LDPC_USER2 = 0x04, + IEEE80211_RADIOTAP_CODING_LDPC_USER3 = 0x08, +}; + +/* for IEEE80211_RADIOTAP_TIMESTAMP */ +enum ieee80211_radiotap_timestamp_unit_spos { + IEEE80211_RADIOTAP_TIMESTAMP_UNIT_MASK = 0x000F, + IEEE80211_RADIOTAP_TIMESTAMP_UNIT_MS = 0x0000, + IEEE80211_RADIOTAP_TIMESTAMP_UNIT_US = 0x0001, + IEEE80211_RADIOTAP_TIMESTAMP_UNIT_NS = 0x0003, + IEEE80211_RADIOTAP_TIMESTAMP_SPOS_MASK = 0x00F0, + IEEE80211_RADIOTAP_TIMESTAMP_SPOS_BEGIN_MDPU = 0x0000, + IEEE80211_RADIOTAP_TIMESTAMP_SPOS_PLCP_SIG_ACQ = 0x0010, + IEEE80211_RADIOTAP_TIMESTAMP_SPOS_EO_PPDU = 0x0020, + IEEE80211_RADIOTAP_TIMESTAMP_SPOS_EO_MPDU = 0x0030, + IEEE80211_RADIOTAP_TIMESTAMP_SPOS_UNKNOWN = 0x00F0, +}; + +enum ieee80211_radiotap_timestamp_flags { + IEEE80211_RADIOTAP_TIMESTAMP_FLAG_64BIT = 0x00, + IEEE80211_RADIOTAP_TIMESTAMP_FLAG_32BIT = 0x01, + IEEE80211_RADIOTAP_TIMESTAMP_FLAG_ACCURACY = 0x02, +}; + +struct ieee80211_radiotap_he { + __le16 data1, data2, data3, data4, data5, data6; +}; + +enum ieee80211_radiotap_he_bits { + IEEE80211_RADIOTAP_HE_DATA1_FORMAT_MASK = 3, + IEEE80211_RADIOTAP_HE_DATA1_FORMAT_SU = 0, + IEEE80211_RADIOTAP_HE_DATA1_FORMAT_EXT_SU = 1, + IEEE80211_RADIOTAP_HE_DATA1_FORMAT_MU = 2, + IEEE80211_RADIOTAP_HE_DATA1_FORMAT_TRIG = 3, + + IEEE80211_RADIOTAP_HE_DATA1_BSS_COLOR_KNOWN = 0x0004, + IEEE80211_RADIOTAP_HE_DATA1_BEAM_CHANGE_KNOWN = 0x0008, + IEEE80211_RADIOTAP_HE_DATA1_UL_DL_KNOWN = 0x0010, + IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN = 0x0020, + IEEE80211_RADIOTAP_HE_DATA1_DATA_DCM_KNOWN = 0x0040, + IEEE80211_RADIOTAP_HE_DATA1_CODING_KNOWN = 0x0080, + IEEE80211_RADIOTAP_HE_DATA1_LDPC_XSYMSEG_KNOWN = 0x0100, + IEEE80211_RADIOTAP_HE_DATA1_STBC_KNOWN = 0x0200, + IEEE80211_RADIOTAP_HE_DATA1_SPTL_REUSE_KNOWN = 0x0400, + IEEE80211_RADIOTAP_HE_DATA1_SPTL_REUSE2_KNOWN = 0x0800, + IEEE80211_RADIOTAP_HE_DATA1_SPTL_REUSE3_KNOWN = 0x1000, + IEEE80211_RADIOTAP_HE_DATA1_SPTL_REUSE4_KNOWN = 0x2000, + IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN = 0x4000, + IEEE80211_RADIOTAP_HE_DATA1_DOPPLER_KNOWN = 0x8000, + + IEEE80211_RADIOTAP_HE_DATA2_PRISEC_80_KNOWN = 0x0001, + IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN = 0x0002, + IEEE80211_RADIOTAP_HE_DATA2_NUM_LTF_SYMS_KNOWN = 0x0004, + IEEE80211_RADIOTAP_HE_DATA2_PRE_FEC_PAD_KNOWN = 0x0008, + IEEE80211_RADIOTAP_HE_DATA2_TXBF_KNOWN = 0x0010, + IEEE80211_RADIOTAP_HE_DATA2_PE_DISAMBIG_KNOWN = 0x0020, + IEEE80211_RADIOTAP_HE_DATA2_TXOP_KNOWN = 0x0040, + IEEE80211_RADIOTAP_HE_DATA2_MIDAMBLE_KNOWN = 0x0080, + IEEE80211_RADIOTAP_HE_DATA2_RU_OFFSET = 0x3f00, + IEEE80211_RADIOTAP_HE_DATA2_RU_OFFSET_KNOWN = 0x4000, + IEEE80211_RADIOTAP_HE_DATA2_PRISEC_80_SEC = 0x8000, + + IEEE80211_RADIOTAP_HE_DATA3_BSS_COLOR = 0x003f, + IEEE80211_RADIOTAP_HE_DATA3_BEAM_CHANGE = 0x0040, + IEEE80211_RADIOTAP_HE_DATA3_UL_DL = 0x0080, + IEEE80211_RADIOTAP_HE_DATA3_DATA_MCS = 0x0f00, + IEEE80211_RADIOTAP_HE_DATA3_DATA_DCM = 0x1000, + IEEE80211_RADIOTAP_HE_DATA3_CODING = 0x2000, + IEEE80211_RADIOTAP_HE_DATA3_LDPC_XSYMSEG = 0x4000, + IEEE80211_RADIOTAP_HE_DATA3_STBC = 0x8000, + + IEEE80211_RADIOTAP_HE_DATA4_SU_MU_SPTL_REUSE = 0x000f, + IEEE80211_RADIOTAP_HE_DATA4_MU_STA_ID = 0x7ff0, + IEEE80211_RADIOTAP_HE_DATA4_TB_SPTL_REUSE1 = 0x000f, + IEEE80211_RADIOTAP_HE_DATA4_TB_SPTL_REUSE2 = 0x00f0, + IEEE80211_RADIOTAP_HE_DATA4_TB_SPTL_REUSE3 = 0x0f00, + IEEE80211_RADIOTAP_HE_DATA4_TB_SPTL_REUSE4 = 0xf000, + + IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC = 0x000f, + IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_20MHZ = 0, + IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_40MHZ = 1, + IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_80MHZ = 2, + IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_160MHZ = 3, + IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_26T = 4, + IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_52T = 5, + IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_106T = 6, + IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_242T = 7, + IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_484T = 8, + IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_996T = 9, + IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_2x996T = 10, + + IEEE80211_RADIOTAP_HE_DATA5_GI = 0x0030, + IEEE80211_RADIOTAP_HE_DATA5_GI_0_8 = 0, + IEEE80211_RADIOTAP_HE_DATA5_GI_1_6 = 1, + IEEE80211_RADIOTAP_HE_DATA5_GI_3_2 = 2, + + IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE = 0x00c0, + IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE_UNKNOWN = 0, + IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE_1X = 1, + IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE_2X = 2, + IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE_4X = 3, + IEEE80211_RADIOTAP_HE_DATA5_NUM_LTF_SYMS = 0x0700, + IEEE80211_RADIOTAP_HE_DATA5_PRE_FEC_PAD = 0x3000, + IEEE80211_RADIOTAP_HE_DATA5_TXBF = 0x4000, + IEEE80211_RADIOTAP_HE_DATA5_PE_DISAMBIG = 0x8000, + + IEEE80211_RADIOTAP_HE_DATA6_NSTS = 0x000f, + IEEE80211_RADIOTAP_HE_DATA6_DOPPLER = 0x0010, + IEEE80211_RADIOTAP_HE_DATA6_TB_PPDU_BW_KNOWN = 0x0020, + IEEE80211_RADIOTAP_HE_DATA6_TB_PPDU_BW = 0x00c0, + IEEE80211_RADIOTAP_HE_DATA6_TB_PPDU_BW_20MHZ = 0, + IEEE80211_RADIOTAP_HE_DATA6_TB_PPDU_BW_40MHZ = 1, + IEEE80211_RADIOTAP_HE_DATA6_TB_PPDU_BW_80MHZ = 2, + IEEE80211_RADIOTAP_HE_DATA6_TB_PPDU_BW_160MHZ = 3, + IEEE80211_RADIOTAP_HE_DATA6_TXOP = 0x7f00, + IEEE80211_RADIOTAP_HE_DATA6_MIDAMBLE_PDCTY = 0x8000, +}; + +struct ieee80211_radiotap_he_mu { + __le16 flags1, flags2; + u8 ru_ch1[4]; + u8 ru_ch2[4]; +}; + +enum ieee80211_radiotap_he_mu_bits { + IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_MCS = 0x000f, + IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_MCS_KNOWN = 0x0010, + IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_DCM = 0x0020, + IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_DCM_KNOWN = 0x0040, + IEEE80211_RADIOTAP_HE_MU_FLAGS1_CH2_CTR_26T_RU_KNOWN = 0x0080, + IEEE80211_RADIOTAP_HE_MU_FLAGS1_CH1_RU_KNOWN = 0x0100, + IEEE80211_RADIOTAP_HE_MU_FLAGS1_CH2_RU_KNOWN = 0x0200, + IEEE80211_RADIOTAP_HE_MU_FLAGS1_CH1_CTR_26T_RU_KNOWN = 0x1000, + IEEE80211_RADIOTAP_HE_MU_FLAGS1_CH1_CTR_26T_RU = 0x2000, + IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_COMP_KNOWN = 0x4000, + IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_SYMS_USERS_KNOWN = 0x8000, + + IEEE80211_RADIOTAP_HE_MU_FLAGS2_BW_FROM_SIG_A_BW = 0x0003, + IEEE80211_RADIOTAP_HE_MU_FLAGS2_BW_FROM_SIG_A_BW_20MHZ = 0x0000, + IEEE80211_RADIOTAP_HE_MU_FLAGS2_BW_FROM_SIG_A_BW_40MHZ = 0x0001, + IEEE80211_RADIOTAP_HE_MU_FLAGS2_BW_FROM_SIG_A_BW_80MHZ = 0x0002, + IEEE80211_RADIOTAP_HE_MU_FLAGS2_BW_FROM_SIG_A_BW_160MHZ = 0x0003, + IEEE80211_RADIOTAP_HE_MU_FLAGS2_BW_FROM_SIG_A_BW_KNOWN = 0x0004, + IEEE80211_RADIOTAP_HE_MU_FLAGS2_SIG_B_COMP = 0x0008, + IEEE80211_RADIOTAP_HE_MU_FLAGS2_SIG_B_SYMS_USERS = 0x00f0, + IEEE80211_RADIOTAP_HE_MU_FLAGS2_PUNC_FROM_SIG_A_BW = 0x0300, + IEEE80211_RADIOTAP_HE_MU_FLAGS2_PUNC_FROM_SIG_A_BW_KNOWN= 0x0400, + IEEE80211_RADIOTAP_HE_MU_FLAGS2_CH2_CTR_26T_RU = 0x0800, +}; + +enum ieee80211_radiotap_lsig_data1 { + IEEE80211_RADIOTAP_LSIG_DATA1_RATE_KNOWN = 0x0001, + IEEE80211_RADIOTAP_LSIG_DATA1_LENGTH_KNOWN = 0x0002, +}; + +enum ieee80211_radiotap_lsig_data2 { + IEEE80211_RADIOTAP_LSIG_DATA2_RATE = 0x000f, + IEEE80211_RADIOTAP_LSIG_DATA2_LENGTH = 0xfff0, +}; + +struct ieee80211_radiotap_lsig { + __le16 data1, data2; +}; + +enum ieee80211_radiotap_zero_len_psdu_type { + IEEE80211_RADIOTAP_ZERO_LEN_PSDU_SOUNDING = 0, + IEEE80211_RADIOTAP_ZERO_LEN_PSDU_NOT_CAPTURED = 1, + IEEE80211_RADIOTAP_ZERO_LEN_PSDU_VENDOR = 0xff, +}; + +// /** +// * ieee80211_get_radiotap_len - get radiotap header length +// */ +// static inline u16 ieee80211_get_radiotap_len(const char *data) +// { +// struct ieee80211_radiotap_header *hdr = (void *)data; + +// return get_unaligned_le16(&hdr->it_len); +// } + +#endif /* __RADIOTAP_H */ diff --git a/user_space/inject_80211/inject_80211.c b/user_space/inject_80211/inject_80211.c index cc189bc..9941658 100644 --- a/user_space/inject_80211/inject_80211.c +++ b/user_space/inject_80211/inject_80211.c @@ -22,7 +22,7 @@ // 2007-03-15 fixes to getopt_long code by Matteo Croce rootkit85@yahoo.it #include "inject_80211.h" -#include "radiotap.h" +#include "ieee80211_radiotap.h" #define BUF_SIZE_MAX (1536) #define BUF_SIZE_TOTAL (BUF_SIZE_MAX+1) // +1 in case the sprintf insert the last 0 @@ -142,7 +142,7 @@ void usage(void) "-h this menu\n\n" "Example:\n" - " iw dev wlan0 interface add mon0 type monitor && ifconfig mon0 up\n" + " iw dev sdr0 interface add mon0 type monitor && ifconfig mon0 up\n" " inject_80211 mon0\n" "\n"); exit(1); @@ -270,6 +270,7 @@ int main(int argc, char *argv[]) ieee_hdr_data[0] = ( ieee_hdr_data[0]|(sub_type<<4) ); ieee_hdr_data[9] = addr1; ieee_hdr_data[15] = addr2; + ieee_hdr_data[21] = addr1; ieee_hdr_len = sizeof(ieee_hdr_data); ieee_hdr = ieee_hdr_data; } @@ -278,6 +279,7 @@ int main(int argc, char *argv[]) ieee_hdr_mgmt[0] = ( ieee_hdr_mgmt[0]|(sub_type<<4) ); ieee_hdr_mgmt[9] = addr1; ieee_hdr_mgmt[15] = addr2; + ieee_hdr_mgmt[21] = addr1; ieee_hdr_len = sizeof(ieee_hdr_mgmt); ieee_hdr = ieee_hdr_mgmt; } diff --git a/user_space/inject_80211/inject_80211.h b/user_space/inject_80211/inject_80211.h index 8eb711b..916a99d 100644 --- a/user_space/inject_80211/inject_80211.h +++ b/user_space/inject_80211/inject_80211.h @@ -12,6 +12,7 @@ #include #include +typedef unsigned long long int u64; typedef unsigned int u32; typedef unsigned short u16; typedef unsigned char u8; diff --git a/user_space/inject_80211/radiotap.c b/user_space/inject_80211/radiotap.c index 179dc15..8730c3b 100644 --- a/user_space/inject_80211/radiotap.c +++ b/user_space/inject_80211/radiotap.c @@ -2,16 +2,110 @@ * Radiotap parser * * Copyright 2007 Andy Green + * Copyright 2009 Johannes Berg + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Alternatively, this software may be distributed under the terms of BSD + * license. + * + * See COPYING for more details. */ +#include +// #include +// #include +// #include +// #include + #include "inject_80211.h" #include "radiotap.h" +#include "unaligned.h" + +// ----- from kernel, needed by ARRAY_SIZE from kernel.h +/* + * Force a compilation error if condition is true, but also produce a + * result (of value 0 and type int), so the expression can be used + * e.g. in a structure initializer (or where-ever else comma expressions + * aren't permitted). + */ +#define BUILD_BUG_ON_ZERO(e) ((int)(sizeof(struct { int:(-!!(e)); }))) + +/* Are two types/vars the same type (ignoring qualifiers)? */ +#define __same_type(a, b) __builtin_types_compatible_p(typeof(a), typeof(b)) + +/* &a[0] degrades to a pointer: a different type from an array */ +#define __must_be_array(a) BUILD_BUG_ON_ZERO(__same_type((a), &(a)[0])) + +// ----- ARRAY_SIZE from kernel.h +/** + * ARRAY_SIZE - get the number of elements in array @arr + * @arr: array to be sized + */ +#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]) + __must_be_array(arr)) + +// ----- radiotap_align_size +// ----- ieee80211_radiotap_namespace +// ----- ieee80211_radiotap_vendor_namespaces from cfg80211.h ----- // +struct radiotap_align_size { + uint8_t align:4, size:4; +}; + +struct ieee80211_radiotap_namespace { + const struct radiotap_align_size *align_size; + int n_bits; + uint32_t oui; + uint8_t subns; +}; + +struct ieee80211_radiotap_vendor_namespaces { + const struct ieee80211_radiotap_namespace *ns; + int n_ns; +}; +// -------------------------------------------------------------------// + +/* function prototypes and related defs are in include/net/cfg80211.h */ + +static const struct radiotap_align_size rtap_namespace_sizes[] = { + [IEEE80211_RADIOTAP_TSFT] = { .align = 8, .size = 8, }, + [IEEE80211_RADIOTAP_FLAGS] = { .align = 1, .size = 1, }, + [IEEE80211_RADIOTAP_RATE] = { .align = 1, .size = 1, }, + [IEEE80211_RADIOTAP_CHANNEL] = { .align = 2, .size = 4, }, + [IEEE80211_RADIOTAP_FHSS] = { .align = 2, .size = 2, }, + [IEEE80211_RADIOTAP_DBM_ANTSIGNAL] = { .align = 1, .size = 1, }, + [IEEE80211_RADIOTAP_DBM_ANTNOISE] = { .align = 1, .size = 1, }, + [IEEE80211_RADIOTAP_LOCK_QUALITY] = { .align = 2, .size = 2, }, + [IEEE80211_RADIOTAP_TX_ATTENUATION] = { .align = 2, .size = 2, }, + [IEEE80211_RADIOTAP_DB_TX_ATTENUATION] = { .align = 2, .size = 2, }, + [IEEE80211_RADIOTAP_DBM_TX_POWER] = { .align = 1, .size = 1, }, + [IEEE80211_RADIOTAP_ANTENNA] = { .align = 1, .size = 1, }, + [IEEE80211_RADIOTAP_DB_ANTSIGNAL] = { .align = 1, .size = 1, }, + [IEEE80211_RADIOTAP_DB_ANTNOISE] = { .align = 1, .size = 1, }, + [IEEE80211_RADIOTAP_RX_FLAGS] = { .align = 2, .size = 2, }, + [IEEE80211_RADIOTAP_TX_FLAGS] = { .align = 2, .size = 2, }, + [IEEE80211_RADIOTAP_RTS_RETRIES] = { .align = 1, .size = 1, }, + [IEEE80211_RADIOTAP_DATA_RETRIES] = { .align = 1, .size = 1, }, + [IEEE80211_RADIOTAP_MCS] = { .align = 1, .size = 3, }, + [IEEE80211_RADIOTAP_AMPDU_STATUS] = { .align = 4, .size = 8, }, + [IEEE80211_RADIOTAP_VHT] = { .align = 2, .size = 12, }, + /* + * add more here as they are defined in radiotap.h + */ +}; + +static const struct ieee80211_radiotap_namespace radiotap_ns = { + .n_bits = ARRAY_SIZE(rtap_namespace_sizes), + .align_size = rtap_namespace_sizes, +}; /** * ieee80211_radiotap_iterator_init - radiotap parser iterator initialization * @iterator: radiotap_iterator to initialize * @radiotap_header: radiotap header to parse * @max_length: total length we can parse into (eg, whole packet length) + * @vns: vendor namespaces to parse * * Returns: 0 or a negative error code if there is a problem. * @@ -36,36 +130,57 @@ * iterator->max_length after executing ieee80211_radiotap_iterator_init() * successfully. * + * Alignment Gotcha: + * You must take care when dereferencing iterator.this_arg + * for multibyte types... the pointer is not aligned. Use + * get_unaligned((type *)iterator.this_arg) to dereference + * iterator.this_arg for type "type" safely on all arches. + * * Example code: - * See Documentation/networking/radiotap-headers.txt + * See Documentation/networking/radiotap-headers.rst */ int ieee80211_radiotap_iterator_init( - struct ieee80211_radiotap_iterator *iterator, - struct ieee80211_radiotap_header *radiotap_header, - int max_length) + struct ieee80211_radiotap_iterator *iterator, + struct ieee80211_radiotap_header *radiotap_header, + int max_length, const struct ieee80211_radiotap_vendor_namespaces *vns) { + /* check the radiotap header can actually be present */ + if (max_length < sizeof(struct ieee80211_radiotap_header)) + return -EINVAL; + /* Linux only supports version 0 radiotap format */ if (radiotap_header->it_version) return -EINVAL; /* sanity check for allowed length and radiotap length field */ - if (max_length < le16_to_cpu(radiotap_header->it_len)) + if (max_length < get_unaligned_le16(&radiotap_header->it_len)) return -EINVAL; - iterator->rtheader = radiotap_header; - iterator->max_length = le16_to_cpu(radiotap_header->it_len); - iterator->arg_index = 0; - iterator->bitmap_shifter = le32_to_cpu(radiotap_header->it_present); - iterator->arg = (u8 *)radiotap_header + sizeof(*radiotap_header); - iterator->this_arg = 0; + iterator->_rtheader = radiotap_header; + iterator->_max_length = get_unaligned_le16(&radiotap_header->it_len); + iterator->_arg_index = 0; + // iterator->_bitmap_shifter = get_unaligned_le32(&radiotap_header->it_present); + iterator->_bitmap_shifter = (uint32_t)le32_to_cpu(radiotap_header->it_present); + iterator->_arg = (uint8_t *)radiotap_header + sizeof(*radiotap_header); + iterator->_reset_on_ext = 0; + iterator->_next_bitmap = &radiotap_header->it_present; + iterator->_next_bitmap++; + iterator->_vns = vns; + iterator->current_namespace = &radiotap_ns; + iterator->is_radiotap_ns = 1; /* find payload start allowing for extended bitmap(s) */ - if (unlikely(iterator->bitmap_shifter & (1<arg)) & - (1<arg += sizeof(u32); + if (iterator->_bitmap_shifter & (1<_arg - + (unsigned long)iterator->_rtheader + sizeof(uint32_t) > + (unsigned long)iterator->_max_length) + return -EINVAL; + // while (get_unaligned_le32(iterator->_arg) & + while (le32_to_cpu(*((u32 *)iterator->_arg)) & + (1 << IEEE80211_RADIOTAP_EXT)) { + iterator->_arg += sizeof(uint32_t); /* * check for insanity where the present bitmaps @@ -73,12 +188,14 @@ int ieee80211_radiotap_iterator_init( * stated radiotap header length */ - if (((ulong)iterator->arg - - (ulong)iterator->rtheader) > iterator->max_length) + if ((unsigned long)iterator->_arg - + (unsigned long)iterator->_rtheader + + sizeof(uint32_t) > + (unsigned long)iterator->_max_length) return -EINVAL; } - iterator->arg += sizeof(u32); + iterator->_arg += sizeof(uint32_t); /* * no need to check again for blowing past stated radiotap @@ -87,10 +204,35 @@ int ieee80211_radiotap_iterator_init( */ } + iterator->this_arg = iterator->_arg; + /* we are all initialized happily */ return 0; } +// EXPORT_SYMBOL(ieee80211_radiotap_iterator_init); + +static void find_ns(struct ieee80211_radiotap_iterator *iterator, + uint32_t oui, uint8_t subns) +{ + int i; + + iterator->current_namespace = NULL; + + if (!iterator->_vns) + return; + + for (i = 0; i < iterator->_vns->n_ns; i++) { + if (iterator->_vns->ns[i].oui != oui) + continue; + if (iterator->_vns->ns[i].subns != subns) + continue; + + iterator->current_namespace = &iterator->_vns->ns[i]; + break; + } +} + /** @@ -107,102 +249,111 @@ int ieee80211_radiotap_iterator_init( * present fields. @this_arg can be changed by the caller (eg, * incremented to move inside a compound argument like * IEEE80211_RADIOTAP_CHANNEL). The args pointed to are in - * little-endian format whatever the endianness of your CPU. + * little-endian format whatever the endianess of your CPU. + * + * Alignment Gotcha: + * You must take care when dereferencing iterator.this_arg + * for multibyte types... the pointer is not aligned. Use + * get_unaligned((type *)iterator.this_arg) to dereference + * iterator.this_arg for type "type" safely on all arches. */ int ieee80211_radiotap_iterator_next( - struct ieee80211_radiotap_iterator *iterator) + struct ieee80211_radiotap_iterator *iterator) { - - /* - * small length lookup table for all radiotap types we heard of - * starting from b0 in the bitmap, so we can walk the payload - * area of the radiotap header - * - * There is a requirement to pad args, so that args - * of a given length must begin at a boundary of that length - * -- but note that compound args are allowed (eg, 2 x u16 - * for IEEE80211_RADIOTAP_CHANNEL) so total arg length is not - * a reliable indicator of alignment requirement. - * - * upper nybble: content alignment for arg - * lower nybble: content length for arg - */ - - static const u8 rt_sizes[] = { - [IEEE80211_RADIOTAP_TSFT] = 0x88, - [IEEE80211_RADIOTAP_FLAGS] = 0x11, - [IEEE80211_RADIOTAP_RATE] = 0x11, - [IEEE80211_RADIOTAP_CHANNEL] = 0x24, - [IEEE80211_RADIOTAP_FHSS] = 0x22, - [IEEE80211_RADIOTAP_DBM_ANTSIGNAL] = 0x11, - [IEEE80211_RADIOTAP_DBM_ANTNOISE] = 0x11, - [IEEE80211_RADIOTAP_LOCK_QUALITY] = 0x22, - [IEEE80211_RADIOTAP_TX_ATTENUATION] = 0x22, - [IEEE80211_RADIOTAP_DB_TX_ATTENUATION] = 0x22, - [IEEE80211_RADIOTAP_DBM_TX_POWER] = 0x11, - [IEEE80211_RADIOTAP_ANTENNA] = 0x11, - [IEEE80211_RADIOTAP_DB_ANTSIGNAL] = 0x11, - [IEEE80211_RADIOTAP_DB_ANTNOISE] = 0x11, - [IEEE80211_RADIOTAP_RX_FLAGS] = 0x22, - [IEEE80211_RADIOTAP_TX_FLAGS] = 0x22, - [IEEE80211_RADIOTAP_RTS_RETRIES] = 0x11, - [IEEE80211_RADIOTAP_DATA_RETRIES] = 0x11, - [IEEE80211_RADIOTAP_MCS] = 0x13, - [IEEE80211_RADIOTAP_AMPDU_STATUS] = 0x48 - /* - * add more here as they are defined in - * include/net/ieee80211_radiotap.h - */ - }; - - /* - * for every radiotap entry we can at - * least skip (by knowing the length)... - */ - - while (iterator->arg_index < sizeof(rt_sizes)) { + while (1) { int hit = 0; - int pad; + int pad, align, size, subns; + uint32_t oui; - if (!(iterator->bitmap_shifter & 1)) + /* if no more EXT bits, that's it */ + if ((iterator->_arg_index % 32) == IEEE80211_RADIOTAP_EXT && + !(iterator->_bitmap_shifter & 1)) + return -ENOENT; + + if (!(iterator->_bitmap_shifter & 1)) goto next_entry; /* arg not present */ + /* get alignment/size of data */ + switch (iterator->_arg_index % 32) { + case IEEE80211_RADIOTAP_RADIOTAP_NAMESPACE: + case IEEE80211_RADIOTAP_EXT: + align = 1; + size = 0; + break; + case IEEE80211_RADIOTAP_VENDOR_NAMESPACE: + align = 2; + size = 6; + break; + default: + if (!iterator->current_namespace || + iterator->_arg_index >= iterator->current_namespace->n_bits) { + if (iterator->current_namespace == &radiotap_ns) + return -ENOENT; + align = 0; + } else { + align = iterator->current_namespace->align_size[iterator->_arg_index].align; + size = iterator->current_namespace->align_size[iterator->_arg_index].size; + } + if (!align) { + /* skip all subsequent data */ + iterator->_arg = iterator->_next_ns_data; + /* give up on this namespace */ + iterator->current_namespace = NULL; + goto next_entry; + } + break; + } + /* * arg is present, account for alignment padding - * 8-bit args can be at any alignment - * 16-bit args must start on 16-bit boundary - * 32-bit args must start on 32-bit boundary - * 64-bit args must start on 64-bit boundary * - * note that total arg size can differ from alignment of - * elements inside arg, so we use upper nybble of length - * table to base alignment on - * - * also note: these alignments are ** relative to the - * start of the radiotap header **. There is no guarantee + * Note that these alignments are relative to the start + * of the radiotap header. There is no guarantee * that the radiotap header itself is aligned on any * kind of boundary. + * + * The above is why get_unaligned() is used to dereference + * multibyte elements from the radiotap area. */ - pad = (((ulong)iterator->arg) - - ((ulong)iterator->rtheader)) & - ((rt_sizes[iterator->arg_index] >> 4) - 1); + pad = ((unsigned long)iterator->_arg - + (unsigned long)iterator->_rtheader) & (align - 1); if (pad) - iterator->arg += - (rt_sizes[iterator->arg_index] >> 4) - pad; + iterator->_arg += align - pad; + + if (iterator->_arg_index % 32 == IEEE80211_RADIOTAP_VENDOR_NAMESPACE) { + int vnslen; + + if ((unsigned long)iterator->_arg + size - + (unsigned long)iterator->_rtheader > + (unsigned long)iterator->_max_length) + return -EINVAL; + + oui = (*iterator->_arg << 16) | + (*(iterator->_arg + 1) << 8) | + *(iterator->_arg + 2); + subns = *(iterator->_arg + 3); + + find_ns(iterator, oui, subns); + + vnslen = get_unaligned_le16(iterator->_arg + 4); + iterator->_next_ns_data = iterator->_arg + size + vnslen; + if (!iterator->current_namespace) + size += vnslen; + } /* * this is what we will return to user, but we need to * move on first so next call has something fresh to test */ - iterator->this_arg_index = iterator->arg_index; - iterator->this_arg = iterator->arg; - hit = 1; + iterator->this_arg_index = iterator->_arg_index; + iterator->this_arg = iterator->_arg; + iterator->this_arg_size = size; /* internally move on the size of this arg */ - iterator->arg += rt_sizes[iterator->arg_index] & 0x0f; + iterator->_arg += size; /* * check for insanity where we are given a bitmap that @@ -211,34 +362,59 @@ int ieee80211_radiotap_iterator_next( * max_length on the last arg, never exceeding it. */ - if (((ulong)iterator->arg - (ulong)iterator->rtheader) > - iterator->max_length) + if ((unsigned long)iterator->_arg - + (unsigned long)iterator->_rtheader > + (unsigned long)iterator->_max_length) return -EINVAL; - next_entry: - iterator->arg_index++; - if (unlikely((iterator->arg_index & 31) == 0)) { - /* completed current u32 bitmap */ - if (iterator->bitmap_shifter & 1) { - /* b31 was set, there is more */ - /* move to next u32 bitmap */ - iterator->bitmap_shifter = - le32_to_cpu(*iterator->next_bitmap); - iterator->next_bitmap++; - } else { - /* no more bitmaps: end */ - iterator->arg_index = sizeof(rt_sizes); - } - } else { /* just try the next bit */ - iterator->bitmap_shifter >>= 1; + /* these special ones are valid in each bitmap word */ + switch (iterator->_arg_index % 32) { + case IEEE80211_RADIOTAP_VENDOR_NAMESPACE: + iterator->_reset_on_ext = 1; + + iterator->is_radiotap_ns = 0; + /* + * If parser didn't register this vendor + * namespace with us, allow it to show it + * as 'raw. Do do that, set argument index + * to vendor namespace. + */ + iterator->this_arg_index = + IEEE80211_RADIOTAP_VENDOR_NAMESPACE; + if (!iterator->current_namespace) + hit = 1; + goto next_entry; + case IEEE80211_RADIOTAP_RADIOTAP_NAMESPACE: + iterator->_reset_on_ext = 1; + iterator->current_namespace = &radiotap_ns; + iterator->is_radiotap_ns = 1; + goto next_entry; + case IEEE80211_RADIOTAP_EXT: + /* + * bit 31 was set, there is more + * -- move to next u32 bitmap + */ + iterator->_bitmap_shifter = + // get_unaligned_le32(iterator->_next_bitmap); + le32_to_cpu(*iterator->_next_bitmap); + iterator->_next_bitmap++; + if (iterator->_reset_on_ext) + iterator->_arg_index = 0; + else + iterator->_arg_index++; + iterator->_reset_on_ext = 0; + break; + default: + /* we've got a hit! */ + hit = 1; + next_entry: + iterator->_bitmap_shifter >>= 1; + iterator->_arg_index++; } /* if we found a valid arg earlier, return it now */ if (hit) return 0; } - - /* we don't know how to handle any more args, we're done */ - return -ENOENT; } - +// EXPORT_SYMBOL(ieee80211_radiotap_iterator_next); diff --git a/user_space/inject_80211/radiotap.h b/user_space/inject_80211/radiotap.h index 55a36de..ba5d885 100644 --- a/user_space/inject_80211/radiotap.h +++ b/user_space/inject_80211/radiotap.h @@ -1,38 +1,60 @@ #include "ieee80211_radiotap.h" -/* Radiotap header iteration - * implemented in net/wireless/radiotap.c - * docs in Documentation/networking/radiotap-headers.txt - */ +// -----ieee80211_radiotap_iterator from cfg80211.h ----- // /** * struct ieee80211_radiotap_iterator - tracks walk thru present radiotap args - * @rtheader: pointer to the radiotap header we are walking through - * @max_length: length of radiotap header in cpu byte ordering - * @this_arg_index: IEEE80211_RADIOTAP_... index of current arg - * @this_arg: pointer to current radiotap arg - * @arg_index: internal next argument index - * @arg: internal next argument pointer - * @next_bitmap: internal pointer to next present u32 - * @bitmap_shifter: internal shifter for curr u32 bitmap, b0 set == arg present + * @this_arg_index: index of current arg, valid after each successful call + * to ieee80211_radiotap_iterator_next() + * @this_arg: pointer to current radiotap arg; it is valid after each + * call to ieee80211_radiotap_iterator_next() but also after + * ieee80211_radiotap_iterator_init() where it will point to + * the beginning of the actual data portion + * @this_arg_size: length of the current arg, for convenience + * @current_namespace: pointer to the current namespace definition + * (or internally %NULL if the current namespace is unknown) + * @is_radiotap_ns: indicates whether the current namespace is the default + * radiotap namespace or not + * + * @_rtheader: pointer to the radiotap header we are walking through + * @_max_length: length of radiotap header in cpu byte ordering + * @_arg_index: next argument index + * @_arg: next argument pointer + * @_next_bitmap: internal pointer to next present u32 + * @_bitmap_shifter: internal shifter for curr u32 bitmap, b0 set == arg present + * @_vns: vendor namespace definitions + * @_next_ns_data: beginning of the next namespace's data + * @_reset_on_ext: internal; reset the arg index to 0 when going to the + * next bitmap word + * + * Describes the radiotap parser state. Fields prefixed with an underscore + * must not be used by users of the parser, only by the parser internally. */ struct ieee80211_radiotap_iterator { - struct ieee80211_radiotap_header *rtheader; - int max_length; - int this_arg_index; - u8 *this_arg; + struct ieee80211_radiotap_header *_rtheader; + const struct ieee80211_radiotap_vendor_namespaces *_vns; + const struct ieee80211_radiotap_namespace *current_namespace; - int arg_index; - u8 *arg; - __le32 *next_bitmap; - u32 bitmap_shifter; + unsigned char *_arg, *_next_ns_data; + __le32 *_next_bitmap; + + unsigned char *this_arg; + int this_arg_index; + int this_arg_size; + + int is_radiotap_ns; + + int _max_length; + int _arg_index; + uint32_t _bitmap_shifter; + int _reset_on_ext; }; extern int ieee80211_radiotap_iterator_init( - struct ieee80211_radiotap_iterator *iterator, - struct ieee80211_radiotap_header *radiotap_header, - int max_length); + struct ieee80211_radiotap_iterator *iterator, + struct ieee80211_radiotap_header *radiotap_header, + int max_length, const struct ieee80211_radiotap_vendor_namespaces *vns); extern int ieee80211_radiotap_iterator_next( - struct ieee80211_radiotap_iterator *iterator); + struct ieee80211_radiotap_iterator *iterator); diff --git a/user_space/inject_80211/unaligned.h b/user_space/inject_80211/unaligned.h new file mode 100644 index 0000000..a554653 --- /dev/null +++ b/user_space/inject_80211/unaligned.h @@ -0,0 +1,106 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Port on Texas Instruments TMS320C6x architecture + * + * Copyright (C) 2004, 2009, 2010 Texas Instruments Incorporated + * Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com) + * Rewritten for 2.6.3x: Mark Salter + */ +#ifndef _ASM_C6X_UNALIGNED_H +#define _ASM_C6X_UNALIGNED_H + +// #include +// #include + +#include "inject_80211.h" + +/* + * The C64x+ can do unaligned word and dword accesses in hardware + * using special load/store instructions. + */ + +static inline u16 get_unaligned_le16(const void *p) +{ + const u8 *_p = p; + return _p[0] | _p[1] << 8; +} + +static inline u16 get_unaligned_be16(const void *p) +{ + const u8 *_p = p; + return _p[0] << 8 | _p[1]; +} + +static inline void put_unaligned_le16(u16 val, void *p) +{ + u8 *_p = p; + _p[0] = val; + _p[1] = val >> 8; +} + +static inline void put_unaligned_be16(u16 val, void *p) +{ + u8 *_p = p; + _p[0] = val >> 8; + _p[1] = val; +} + +// static inline u32 get_unaligned32(const void *p) +// { +// u32 val = (u32) p; +// asm (" ldnw .d1t1 *%0,%0\n" +// " nop 4\n" +// : "+a"(val)); +// return val; +// } + +// static inline void put_unaligned32(u32 val, void *p) +// { +// asm volatile (" stnw .d2t1 %0,*%1\n" +// : : "a"(val), "b"(p) : "memory"); +// } + +// static inline u64 get_unaligned64(const void *p) +// { +// u64 val; +// asm volatile (" ldndw .d1t1 *%1,%0\n" +// " nop 4\n" +// : "=a"(val) : "a"(p)); +// return val; +// } + +// static inline void put_unaligned64(u64 val, const void *p) +// { +// asm volatile (" stndw .d2t1 %0,*%1\n" +// : : "a"(val), "b"(p) : "memory"); +// } + +#ifdef CONFIG_CPU_BIG_ENDIAN + +#define get_unaligned_le32(p) __swab32(get_unaligned32(p)) +#define get_unaligned_le64(p) __swab64(get_unaligned64(p)) +#define get_unaligned_be32(p) get_unaligned32(p) +#define get_unaligned_be64(p) get_unaligned64(p) +#define put_unaligned_le32(v, p) put_unaligned32(__swab32(v), (p)) +#define put_unaligned_le64(v, p) put_unaligned64(__swab64(v), (p)) +#define put_unaligned_be32(v, p) put_unaligned32((v), (p)) +#define put_unaligned_be64(v, p) put_unaligned64((v), (p)) +#define get_unaligned __get_unaligned_be +#define put_unaligned __put_unaligned_be + +#else + +#define get_unaligned_le32(p) get_unaligned32(p) +#define get_unaligned_le64(p) get_unaligned64(p) +#define get_unaligned_be32(p) __swab32(get_unaligned32(p)) +#define get_unaligned_be64(p) __swab64(get_unaligned64(p)) +#define put_unaligned_le32(v, p) put_unaligned32((v), (p)) +#define put_unaligned_le64(v, p) put_unaligned64((v), (p)) +#define put_unaligned_be32(v, p) put_unaligned32(__swab32(v), (p)) +#define put_unaligned_be64(v, p) put_unaligned64(__swab64(v), (p)) +#define get_unaligned __get_unaligned_le +#define put_unaligned __put_unaligned_le + +#endif + +#endif /* _ASM_C6X_UNALIGNED_H */ diff --git a/user_space/openwifi_ad9361_fir_tx_0MHz_11n.ftr b/user_space/openwifi_ad9361_fir_tx_0MHz_11n.ftr index 783ef0f..9b923de 100644 --- a/user_space/openwifi_ad9361_fir_tx_0MHz_11n.ftr +++ b/user_space/openwifi_ad9361_fir_tx_0MHz_11n.ftr @@ -1,18 +1,17 @@ -# Generated with AD9361 Filter Design Wizard 16.1.3-g924f0cd +# Generated with AD9361 Filter Design Wizard 16.1.3 # MATLAB 9.10.0.1602886 (R2021a), 18-Nov-2021 11:34:55 -# Inputs: -# Data Sample Frequency = 40000000 Hz -# Filter = 2 -# Phase Equalization = 0 -# Use AD936x FIR = 1 -# Fpass = 8.750000e+00 -# Fstop = 1.125000e+01 -# Apass = 5.000000e-01 -# Astop = 80 -# Param = 0.000000 -# PLL rate = 1280 -# Converter = 320 -# Data rate = 40 +# Rx setting: +# Data Rate 40, Clock (MHz) ADC 320 DAC 320 1x +# PLL Div 4x, PLL (MHz) 1280 +# Units: dB. Apass 0.5, Astop 80, Astop (FIR) 0 +# Units: MHz. Fpass 8.75, Fstop 11.25, Fcutoff (Analog) 15.6896, RF Bandwidth 22.4138 +# AD936x Decimation Rates. Use Internal FIR. FIR 1X 40, HB1 2X 80, HB2 2X 160, HB3 2X 320 +# Tx setting: +# Data Rate 40, Clock (MHz) ADC 320 DAC 320 1x +# PLL Div 4x, PLL (MHz) 1280 +# Units: dB. Apass 0.5, Astop 80, Astop (FIR) 0 +# Units: MHz. Fpass 8.75, Fstop 11.25, Fcutoff (Analog) 17.6508, RF Bandwidth 22.0636 +# AD936x Interpolation Rates. Use Internal FIR. FIR 1X 40, HB1 2X 80, HB2 2X 160, HB3 2X 320 TX 3 GAIN -6 INT 1 RX 3 GAIN -6 DEC 1 RTX 1280000000 320000000 160000000 80000000 40000000 40000000 diff --git a/user_space/openwifi_ad9361_fir_tx_0MHz_11n_narrow1.ftr b/user_space/openwifi_ad9361_fir_tx_0MHz_11n_narrow1.ftr new file mode 100644 index 0000000..7de6f33 --- /dev/null +++ b/user_space/openwifi_ad9361_fir_tx_0MHz_11n_narrow1.ftr @@ -0,0 +1,68 @@ +# Generated with AD9361 Filter Design Wizard 16.1.3 +# MATLAB 9.10.0.1602886 (R2021a), 31-Oct-2022 15:56:07 +# Rx setting: +# Data Rate 40, Clock (MHz) ADC 320 DAC 320 1x +# PLL Div 4x, PLL (MHz) 1280 +# Units: dB. Apass 0.5, Astop 120, Astop (FIR) 0 +# Units: MHz. Fpass 8.75, Fstop 12.1, Fcutoff (Analog) 15.6896, RF Bandwidth 22.4138 +# AD936x Decimation Rates. Use Internal FIR. FIR 1X 40, HB1 2X 80, HB2 2X 160, HB3 2X 320 +# Tx setting: +# Data Rate 40, Clock (MHz) ADC 320 DAC 320 1x +# PLL Div 4x, PLL (MHz) 1280 +# Units: dB. Apass 0.5, Astop 80, Astop (FIR) 0 +# Units: MHz. Fpass 8.75, Fstop 11.25, Fcutoff (Analog) 17.6508, RF Bandwidth 22.0636 +# AD936x Interpolation Rates. Use Internal FIR. FIR 1X 40, HB1 2X 80, HB2 2X 160, HB3 2X 320 +TX 3 GAIN -6 INT 1 +RX 3 GAIN -6 DEC 1 +RTX 1280000000 320000000 160000000 80000000 40000000 40000000 +RRX 1280000000 320000000 160000000 80000000 40000000 40000000 +BWTX 25215414 +BWRX 25215513 +41,-12 +31,-90 +-187,-279 +-496,-446 +-395,-280 +183,212 +412,395 +-201,-140 +-619,-571 +148,58 +886,827 +-38,87 +-1232,-1169 +-166,-334 +1680,1622 +513,740 +-2284,-2242 +-1107,-1417 +3197,3181 +2238,2687 +-4904,-4913 +-5068,-5819 +10562,10346 +28812,29882 +28812,29882 +10562,10346 +-5068,-5819 +-4904,-4913 +2238,2687 +3197,3181 +-1107,-1417 +-2284,-2242 +513,740 +1680,1622 +-166,-334 +-1232,-1169 +-38,87 +886,827 +148,58 +-619,-571 +-201,-140 +412,395 +183,212 +-395,-280 +-496,-446 +-187,-279 +31,-90 +41,-12 diff --git a/user_space/populate_kernel_image_module_reboot.sh b/user_space/populate_kernel_image_module_reboot.sh new file mode 100755 index 0000000..cf15a99 --- /dev/null +++ b/user_space/populate_kernel_image_module_reboot.sh @@ -0,0 +1,50 @@ +#!/bin/bash + +# Author: Xianjun Jiao +# SPDX-FileCopyrightText: 2019 UGent +# SPDX-License-Identifier: AGPL-3.0-or-later + +set -ex + +MACHINE_TYPE=`uname -m` + +mkdir -p kernel_modules +rm -rf kernel_modules/* +tar -zxvf kernel_modules.tar.gz + +if [ ${MACHINE_TYPE} == 'aarch64' ]; then + IMAGE_FILENAME=Image + DTB_FILENAME="system.dtb" +else + IMAGE_FILENAME=uImage + DTB_FILENAME="devicetree.dtb" +fi + +mv ./kernel_modules/ad9361_drv.ko ./openwifi/ -f || true +mv ./kernel_modules/adi_axi_hdmi.ko ./openwifi/ -f || true +mv ./kernel_modules/axidmatest.ko ./openwifi/ -f || true +mv ./kernel_modules/lcd.ko ./openwifi/ -f || true +mv ./kernel_modules/xilinx_dma.ko ./openwifi/ -f || true + +rm -rf /lib/modules/$(uname -r) +ln -s /root/kernel_modules /lib/modules/$(uname -r) + +depmod + +umount /mnt || /bin/true +mount /dev/mmcblk0p1 /mnt +if test -f "./kernel_modules/$IMAGE_FILENAME"; then + cp ./kernel_modules/$IMAGE_FILENAME /mnt/ +fi +if test -f "./kernel_modules/BOOT.BIN"; then + cp ./kernel_modules/BOOT.BIN /mnt/ +fi +if test -f "./kernel_modules/$DTB_FILENAME"; then + cp ./kernel_modules/$DTB_FILENAME /mnt/ +fi +cd /mnt/ +sync +cd ~ +umount /mnt + +reboot now diff --git a/user_space/post_config.sh b/user_space/post_config.sh index 149319e..789a818 100755 --- a/user_space/post_config.sh +++ b/user_space/post_config.sh @@ -30,6 +30,8 @@ fi # add gateway (PC) for internet access route add default gw 192.168.10.1 || true +sudo apt update + chmod +x *.sh # build sdrctl @@ -53,6 +55,7 @@ sudo apt-get -y install nano sudo apt-get -y install tcpdump sudo apt-get -y install webfs sudo apt-get -y install iperf +sudo apt-get -y install iperf3 sudo apt-get -y install libpcap-dev sudo apt-get -y install bridge-utils diff --git a/user_space/prepare_kernel.sh b/user_space/prepare_kernel.sh index e6ae593..15d3289 100755 --- a/user_space/prepare_kernel.sh +++ b/user_space/prepare_kernel.sh @@ -5,8 +5,18 @@ # SPDX-FileCopyrightText: 2019 UGent # SPDX-License-Identifier: AGPL-3.0-or-later -if [ "$#" -lt 2 ]; then - echo "You must enter at least 2 arguments: \$XILINX_DIR ARCH_BIT(32 or 64)" +# ATTENTION! You need Vitis, NOT Vitis_HLS, installed + +# if [ "$#" -ne 1 ]; then +# echo "You must enter 1 arguments: ARCH_BIT(32 or 64)" +# exit 1 +# fi + +# OPENWIFI_DIR=$(pwd)/../ +# ARCH_OPTION=$1 + +if [ "$#" -ne 2 ]; then + echo "You must enter 2 arguments: \$XILINX_DIR ARCH_BIT(32 or 64)" exit 1 fi @@ -21,7 +31,7 @@ else exit 1 fi -if [ -d "$XILINX_DIR/SDK" ]; then +if [ -d "$XILINX_DIR/Vitis" ]; then echo "\$XILINX_DIR is found!" else echo "\$XILINX_DIR is not correct. Please check!" @@ -55,29 +65,38 @@ set -x cd $OPENWIFI_DIR/ git submodule init $LINUX_KERNEL_SRC_DIR_NAME +cd $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME +git reset --hard +cd $OPENWIFI_DIR/ git submodule update $LINUX_KERNEL_SRC_DIR_NAME cd $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME -git checkout 2019_R1 -git pull origin 2019_R1 -git reset --hard -# git reset --hard 4e81f0927cfb2fada92fc762dbd65d002848405a -cp $LINUX_KERNEL_CONFIG_FILE ./.config -cp $OPENWIFI_DIR/driver/ad9361/ad9361.c $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME/drivers/iio/adc/ad9361.c -rf -cp $OPENWIFI_DIR/driver/ad9361/ad9361_conv.c $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME/drivers/iio/adc/ad9361_conv.c -rf +git fetch +git checkout 2021_r1 +git pull origin 2021_r1 +git reset --hard 2021_r1 -source $XILINX_DIR/SDK/2018.3/settings64.sh export ARCH=$ARCH_NAME export CROSS_COMPILE=$CROSS_COMPILE_NAME +source $XILINX_DIR/Vitis/2021.1/settings64.sh -make oldconfig && make prepare && make modules_prepare +# if [ "$ARCH_OPTION" == "64" ]; then + cp $LINUX_KERNEL_CONFIG_FILE ./.config + # cp $OPENWIFI_DIR/driver/ad9361/ad9361.c $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME/drivers/iio/adc/ad9361.c -rf + # cp $OPENWIFI_DIR/driver/ad9361/ad9361_conv.c $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME/drivers/iio/adc/ad9361_conv.c -rf + git apply ../kernel_boot/axi_hdmi_crtc.patch + git apply ../kernel_boot/ad9361.patch + git apply ../kernel_boot/ad9361_conv.patch +# else + # make zynq_xcomm_adv7511_defconfig +# fi -if [ "$#" -gt 2 ]; then - # if [ -f "$OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME/arch/$ARCH_NAME/boot/$IMAGE_TYPE" ]; then - # echo "Kernel found! Skip the time costly Linux kernel compiling." - # else - make -j12 $IMAGE_TYPE UIMAGE_LOADADDR=0x8000 - make modules - # fi -fi +make oldconfig +# make adi_zynqmp_defconfig +make prepare && make modules_prepare + +# if [ "$#" -gt 2 ]; then +make -j12 $IMAGE_TYPE UIMAGE_LOADADDR=0x8000 +make modules +# fi cd $home_dir diff --git a/user_space/rssi_ad9361_show.sh b/user_space/rssi_ad9361_show.sh new file mode 100755 index 0000000..55e7749 --- /dev/null +++ b/user_space/rssi_ad9361_show.sh @@ -0,0 +1,45 @@ +#!/bin/bash + +# Reads RSSI in dB from RX1, let's call it "r". +# Linear fit offset "o" depends on frequency (2.4GHz or 5GHz and FMCOMMS2/3). +# RSSI(dBm) = -r + o +# 2.4GHz(ch 6) FMCOMMS2: o = 16.74 +# 2.4GHz(ch 6) FMCOMMS3: o = 17.44 +# 5GHz (ch 44) FMCOMMS2: o = 25.41 +# 5GHz (ch 44) FMCOMMS3: o = 24.58 + +home_dir=$(pwd) + +#set -x +if test -f "/sys/bus/iio/devices/iio:device0/in_voltage0_rssi"; then + cd /sys/bus/iio/devices/iio:device0/ +else if test -f "/sys/bus/iio/devices/iio:device1/in_voltage0_rssi"; then + cd /sys/bus/iio/devices/iio:device1/ + else if test -f "/sys/bus/iio/devices/iio:device2/in_voltage0_rssi"; then + cd /sys/bus/iio/devices/iio:device2/ + else if test -f "/sys/bus/iio/devices/iio:device3/in_voltage0_rssi"; then + cd /sys/bus/iio/devices/iio:device3/ + else if test -f "/sys/bus/iio/devices/iio:device4/in_voltage0_rssi"; then + cd /sys/bus/iio/devices/iio:device4/ + else + echo "Can not find in_voltage_rf_bandwidth!" + echo "Check log to make sure ad9361 driver is loaded!" + exit 1 + fi + fi + fi + fi +fi +#set +x + +if [ $# -lt 1 ]; then + cat in_voltage0_rssi +else + num_read=$1 + for ((i=0;i<$num_read;i++)) + do + rssi_str=$(cat in_voltage0_rssi) + echo "${rssi_str//dB}" + done +fi +cd $home_dir diff --git a/user_space/rssi_openwifi_show.sh b/user_space/rssi_openwifi_show.sh new file mode 100755 index 0000000..5d796af --- /dev/null +++ b/user_space/rssi_openwifi_show.sh @@ -0,0 +1,18 @@ +#!/bin/bash + +rssi_raw=$(./sdrctl dev sdr0 get reg xpu 57) +echo $rssi_raw + +rssi_raw=${rssi_raw: -8} +echo $rssi_raw + +rssi_raw_dec=$(( 16#$rssi_raw )) +echo $rssi_raw_dec + +#rssi_half_db=$(expr (16#$rss_raw) \& 2047) +#rssi_half_db=$(($rssi_raw_dec & 2047)) +#rssi_half_db=$(($rssi_raw_dec & 16#7ff)) +#the low 11 bits are rssi_half_db +rssi_half_db=$((16#$rssi_raw & 16#7ff)) +echo $rssi_half_db + diff --git a/user_space/sdcard_boot_update.sh b/user_space/sdcard_boot_update.sh index 10d0a70..4e38d65 100755 --- a/user_space/sdcard_boot_update.sh +++ b/user_space/sdcard_boot_update.sh @@ -6,12 +6,12 @@ if [ "$#" -ne 1 ]; then echo "You must enter the \$BOARD_NAME as argument" - echo "Like: sdrpi antsdr antsdr_e200 adrv9364z7020 adrv9361z7035 zc706_fmcs2 zed_fmcs2 zc702_fmcs2 zcu102_fmcs2 zcu102_9371" + echo "Like: sdrpi antsdr antsdr_e200 adrv9364z7020 adrv9361z7035 zc706_fmcs2 zed_fmcs2 zc702_fmcs2 zcu102_fmcs2 zcu102_9371 neptunesdr" exit 1 fi BOARD_NAME=$1 -if [ "$BOARD_NAME" != "antsdr" ] && [ "$BOARD_NAME" != "antsdr_e200" ] && [ "$BOARD_NAME" != "sdrpi" ] && [ "$BOARD_NAME" != "zc706_fmcs2" ] && [ "$BOARD_NAME" != "zc702_fmcs2" ] && [ "$BOARD_NAME" != "zed_fmcs2" ] && [ "$BOARD_NAME" != "adrv9361z7035" ] && [ "$BOARD_NAME" != "adrv9364z7020" ] && [ "$BOARD_NAME" != "zcu102_fmcs2" ] && [ "$BOARD_NAME" != "zcu102_9371" ]; then +if [ "$BOARD_NAME" != "neptunesdr" ] && [ "$BOARD_NAME" != "antsdr" ] && [ "$BOARD_NAME" != "antsdr_e200" ] && [ "$BOARD_NAME" != "sdrpi" ] && [ "$BOARD_NAME" != "zc706_fmcs2" ] && [ "$BOARD_NAME" != "zc702_fmcs2" ] && [ "$BOARD_NAME" != "zed_fmcs2" ] && [ "$BOARD_NAME" != "adrv9361z7035" ] && [ "$BOARD_NAME" != "adrv9364z7020" ] && [ "$BOARD_NAME" != "zcu102_fmcs2" ] && [ "$BOARD_NAME" != "zcu102_9371" ]; then echo "\$BOARD_NAME is not correct. Please check!" exit 1 else diff --git a/user_space/set_lbt_th.sh b/user_space/set_lbt_th.sh index cb19ae1..a7e6782 100755 --- a/user_space/set_lbt_th.sh +++ b/user_space/set_lbt_th.sh @@ -13,5 +13,6 @@ if [ $lbt_th -ne 987654321 ]; then fi # show -./sdrctl dev sdr0 get reg xpu 8 +# ./sdrctl dev sdr0 get reg xpu 8 +./sdrctl dev sdr0 get reg drv_xpu 0 set +x diff --git a/user_space/setup_once.sh b/user_space/setup_once.sh new file mode 100755 index 0000000..e2f2615 --- /dev/null +++ b/user_space/setup_once.sh @@ -0,0 +1,82 @@ +#!/bin/bash + +# Author: Xianjun Jiao +# SPDX-FileCopyrightText: 2023 UGent +# SPDX-License-Identifier: AGPL-3.0-or-later + +set -ex + +cd /root/ + +MACHINE_TYPE=`uname -m` + +rm -rf kernel_modules +mkdir -p kernel_modules + +# mkdir -p /lib/modules/$(uname -r) +# rm -rf /lib/modules/$(uname -r) +if [ ${MACHINE_TYPE} == 'aarch64' ]; then + cp /root/kernel_modules64/* /root/kernel_modules/ + cp /root/openwifi64/* /root/openwifi/ + # cp ./kernel_modules64/* /lib/modules/$(uname -r)/ +else + cp /root/kernel_modules32/* /root/kernel_modules/ + cp /root/openwifi32/* /root/openwifi/ + # cp ./kernel_modules32/* /lib/modules/$(uname -r)/ +fi + +# Decide board name +DEVICE_TREE_MODEL_STRING=$(cat /proc/device-tree/model) +if [[ $DEVICE_TREE_MODEL_STRING == *"ADRV9361-Z7035"* ]]; then + BOARD_NAME=adrv9361z7035 +elif [[ $DEVICE_TREE_MODEL_STRING == *"ADRV9364-Z7020"* ]]; then + BOARD_NAME=adrv9364z7020 +elif [[ $DEVICE_TREE_MODEL_STRING == *"ANTSDR-E310"* ]]; then + BOARD_NAME=antsdr +elif [[ $DEVICE_TREE_MODEL_STRING == *"ANTSDR-E200"* ]]; then + BOARD_NAME=antsdr_e200 +elif [[ $DEVICE_TREE_MODEL_STRING == *"neptunesdr"* ]]; then + BOARD_NAME=neptunesdr +elif [[ $DEVICE_TREE_MODEL_STRING == *"sdrpi"* ]]; then + BOARD_NAME=sdrpi +elif [[ $DEVICE_TREE_MODEL_STRING == *"ZC702"* ]]; then + BOARD_NAME=zc702_fmcs2 +elif [[ $DEVICE_TREE_MODEL_STRING == *"ZC706"* ]]; then + BOARD_NAME=zc706_fmcs2 +elif [[ $DEVICE_TREE_MODEL_STRING == *"ZCU102"* ]]; then + BOARD_NAME=zcu102_fmcs2 +elif [[ $DEVICE_TREE_MODEL_STRING == *"ZED"* ]]; then + BOARD_NAME=zed_fmcs2 +else + echo $DEVICE_TREE_MODEL_STRING " NOT recognized!" + exit 1 +fi + +mv /root/kernel_modules/ad9361_drv.ko /root/openwifi/ -f || true +mv /root/kernel_modules/adi_axi_hdmi.ko /root/openwifi/ -f || true +mv /root/kernel_modules/axidmatest.ko /root/openwifi/ -f || true +mv /root/kernel_modules/lcd.ko /root/openwifi/ -f || true +mv /root/kernel_modules/xilinx_dma.ko /root/openwifi/ -f || true + +rm -rf /lib/modules/$(uname -r) +ln -s /root/kernel_modules /lib/modules/$(uname -r) +sync +depmod + +echo $BOARD_NAME +cp /root/openwifi_BOOT/$BOARD_NAME/system_top.bit.bin /root/openwifi/ -f || true + +cd /root/openwifi/sdrctl_src +make clean +make +cp sdrctl /root/openwifi/ +cd /root/openwifi/side_ch_ctl_src/ +gcc -o side_ch_ctl side_ch_ctl.c +cp side_ch_ctl /root/openwifi/ +cd /root/openwifi/inject_80211/ +make clean +make +cd .. +sync + +# reboot now diff --git a/user_space/transfer_driver_userspace_to_board.sh b/user_space/transfer_driver_userspace_to_board.sh new file mode 100755 index 0000000..0ad1288 --- /dev/null +++ b/user_space/transfer_driver_userspace_to_board.sh @@ -0,0 +1,37 @@ + +#!/bin/bash + +# Author: Xianjun Jiao +# SPDX-FileCopyrightText: 2019 UGent +# SPDX-License-Identifier: AGPL-3.0-or-later + +# Setup Eth connection before this script! +# Host: 192.168.10.1 +# Board: 192.168.10.122 +# Commands onboard to setup: +# ifconfig eth0 192.168.10.122 netmask 255.255.255.0 +# ifconfig eth0 up +# route add default gw 192.168.10.1 + +# if [ "$#" -ne 2 ]; then +# echo "You have input $# arguments." +# echo "You must enter \$DIR_TO_ADI_LINUX_KERNEL and ARCH_BIT(32 or 64) as argument" +# exit 1 +# fi + +# DIR_TO_ADI_LINUX_KERNEL=$1 +# ARCH_OPTION=$2 + +# if [ "$ARCH_OPTION" == "64" ]; then +# LINUX_KERNEL_IMAGE=$DIR_TO_ADI_LINUX_KERNEL/arch/arm64/boot/Image +# else +# LINUX_KERNEL_IMAGE=$DIR_TO_ADI_LINUX_KERNEL/arch/arm/boot/uImage +# fi + +mkdir -p openwifi +rm -rf ./openwifi/* +find ../driver/ -name \*.ko -exec cp {} ./openwifi/ \; + +tar -zcvf openwifi.tar.gz openwifi + +scp openwifi.tar.gz root@192.168.10.122: diff --git a/user_space/transfer_kernel_image_module_to_board.sh b/user_space/transfer_kernel_image_module_to_board.sh new file mode 100755 index 0000000..c0c0f18 --- /dev/null +++ b/user_space/transfer_kernel_image_module_to_board.sh @@ -0,0 +1,65 @@ + +#!/bin/bash + +# Author: Xianjun Jiao +# SPDX-FileCopyrightText: 2019 UGent +# SPDX-License-Identifier: AGPL-3.0-or-later + +# Setup Eth connection before this script! +# Host: 192.168.10.1 +# Board: 192.168.10.122 +# Commands onboard to setup: +# ifconfig eth0 192.168.10.122 netmask 255.255.255.0 +# ifconfig eth0 up +# route add default gw 192.168.10.1 + +if [ "$#" -ne 2 ]; then + echo "You have input $# arguments." + echo "You must enter \$DIR_TO_ADI_LINUX_KERNEL and \$BOARD_NAME as argument" + exit 1 +fi + +DIR_TO_ADI_LINUX_KERNEL=$1 +BOARD_NAME=$2 + +if [ "$BOARD_NAME" != "antsdr" ] && [ "$BOARD_NAME" != "antsdr_e200" ] && [ "$BOARD_NAME" != "sdrpi" ] && [ "$BOARD_NAME" != "neptunesdr" ] && [ "$BOARD_NAME" != "zc706_fmcs2" ] && [ "$BOARD_NAME" != "zc702_fmcs2" ] && [ "$BOARD_NAME" != "zed_fmcs2" ] && [ "$BOARD_NAME" != "adrv9361z7035" ] && [ "$BOARD_NAME" != "adrv9364z7020" ] && [ "$BOARD_NAME" != "zcu102_fmcs2" ]; then + echo "\$BOARD_NAME is not correct. Please check!" + exit 1 +else + echo "\$BOARD_NAME is found!" +fi + +if [ "$BOARD_NAME" == "zcu102_fmcs2" ] || [ "$BOARD_NAME" == "zcu102_9371" ]; then + LINUX_KERNEL_IMAGE=$DIR_TO_ADI_LINUX_KERNEL/arch/arm64/boot/Image + DTB_FILENAME="system.dtb" +else + LINUX_KERNEL_IMAGE=$DIR_TO_ADI_LINUX_KERNEL/arch/arm/boot/uImage + DTB_FILENAME="devicetree.dtb" +fi + +mkdir -p kernel_modules +rm -rf ./kernel_modules/* +find $DIR_TO_ADI_LINUX_KERNEL/ -name \*.ko -exec cp {} ./kernel_modules/ \; + +cp $DIR_TO_ADI_LINUX_KERNEL/Module.symvers ./kernel_modules/ +cp $DIR_TO_ADI_LINUX_KERNEL/modules.builtin ./kernel_modules/ +cp $DIR_TO_ADI_LINUX_KERNEL/modules.builtin.modinfo ./kernel_modules/ +cp $DIR_TO_ADI_LINUX_KERNEL/modules.order ./kernel_modules/ + +if test -f "$LINUX_KERNEL_IMAGE"; then + cp $LINUX_KERNEL_IMAGE ./kernel_modules/ +fi + +if test -f "../kernel_boot/boards/$BOARD_NAME/output_boot_bin/BOOT.BIN"; then + cp ../kernel_boot/boards/$BOARD_NAME/output_boot_bin/BOOT.BIN ./kernel_modules/ +fi +if test -f "../kernel_boot/boards/$BOARD_NAME/$DTB_FILENAME"; then + cp ../kernel_boot/boards/$BOARD_NAME/$DTB_FILENAME ./kernel_modules/ +fi +tar -zcvf kernel_modules.tar.gz kernel_modules + +scp kernel_modules.tar.gz root@192.168.10.122: + +# scp $LINUX_KERNEL_IMAGE root@192.168.10.122: + +scp populate_kernel_image_module_reboot.sh root@192.168.10.122: diff --git a/user_space/update_sdcard.sh b/user_space/update_sdcard.sh index f8fd683..78f2aec 100755 --- a/user_space/update_sdcard.sh +++ b/user_space/update_sdcard.sh @@ -5,21 +5,41 @@ # SPDX-FileCopyrightText: 2019 UGent # SPDX-License-Identifier: AGPL-3.0-or-later -if [ "$#" -ne 4 ]; then +# Only put BOOT partition (BOOT.BIN devicetree kernel) and kernel modules drivers on the SD card, but not populate them + +if [ "$#" -lt 3 ]; then echo "You have input $# arguments." - echo "You must enter exactly 4 arguments: \$OPENWIFI_HW_DIR \$XILINX_DIR \$BOARD_NAME \$SDCARD_DIR" + echo "You must enter exactly 3 arguments: \$OPENWIFI_HW_IMG_DIR \$XILINX_DIR \$SDCARD_DIR" exit 1 fi -OPENWIFI_HW_DIR=$1 +SKIP_KERNEL_BUILD=0 +SKIP_BOOT=0 +SKIP_rootfs=0 +if [ "$#" -gt 3 ]; then + SKIP_KERNEL_BUILD=$(( ($4 >> 0) & 1 )) + SKIP_BOOT=$(( ($4 >> 1) & 1 )) + SKIP_rootfs=$(( ($4 >> 2) & 1 )) + echo $4 + echo SKIP_KERNEL_BUILD $SKIP_KERNEL_BUILD + echo SKIP_BOOT $SKIP_BOOT + echo SKIP_rootfs $SKIP_rootfs +fi + +BOARD_NAME_ALL="sdrpi antsdr antsdr_e200 zc706_fmcs2 zed_fmcs2 zc702_fmcs2 adrv9361z7035 adrv9364z7020 zcu102_fmcs2 neptunesdr" +if [ "$#" -gt 4 ]; then + BOARD_NAME_ALL=$5 + echo BOARD_NAME_ALL $BOARD_NAME_ALL +fi + +OPENWIFI_HW_IMG_DIR=$1 XILINX_DIR=$2 -BOARD_NAME=$3 -SDCARD_DIR=$4 +SDCARD_DIR=$3 OPENWIFI_DIR=$(pwd)/../ echo OPENWIFI_DIR $OPENWIFI_DIR -echo OPENWIFI_HW_DIR $OPENWIFI_HW_DIR +echo OPENWIFI_HW_IMG_DIR $OPENWIFI_HW_IMG_DIR if [ -f "$OPENWIFI_DIR/LICENSE" ]; then echo "\$OPENWIFI_DIR is found!" @@ -28,32 +48,27 @@ else exit 1 fi -if [ -d "$XILINX_DIR/SDK" ]; then +if [ -d "$XILINX_DIR/Vitis" ]; then echo "\$XILINX_DIR is found!" else echo "\$XILINX_DIR is not correct. Please check!" exit 1 fi -if [ "$BOARD_NAME" != "antsdr" ] && [ "$BOARD_NAME" != "antsdr_e200" ] && [ "$BOARD_NAME" != "sdrpi" ] && [ "$BOARD_NAME" != "zc706_fmcs2" ] && [ "$BOARD_NAME" != "zc702_fmcs2" ] && [ "$BOARD_NAME" != "zed_fmcs2" ] && [ "$BOARD_NAME" != "adrv9361z7035" ] && [ "$BOARD_NAME" != "adrv9364z7020" ] && [ "$BOARD_NAME" != "zcu102_fmcs2" ] && [ "$BOARD_NAME" != "zcu102_9371" ]; then - echo "\$BOARD_NAME is not correct. Please check!" - exit 1 +if [ -d "$OPENWIFI_HW_IMG_DIR/boards/" ]; then + echo "\$OPENWIFI_HW_IMG_DIR is found!" else - echo "\$BOARD_NAME is found!" -fi - -if [ -d "$OPENWIFI_HW_DIR/boards/$BOARD_NAME" ]; then - echo "\$OPENWIFI_HW_DIR is found!" -else - echo "\$OPENWIFI_HW_DIR is not correct. Please check!" + echo "\$OPENWIFI_HW_IMG_DIR is not correct. Please check!" exit 1 fi # detect SD card mounting status if [ -d "$SDCARD_DIR/BOOT/" ]; then echo "$SDCARD_DIR/BOOT/" - sudo mkdir $SDCARD_DIR/BOOT/openwifi - sudo rm -rf $SDCARD_DIR/BOOT/README.txt + sudo rm -f $SDCARD_DIR/BOOT/README.txt + # to save some space + sudo rm -rf $SDCARD_DIR/BOOT/socfpga_* + sudo rm -rf $SDCARD_DIR/BOOT/versal-* else echo "$SDCARD_DIR/BOOT/ does not exist!" exit 1 @@ -66,16 +81,6 @@ else exit 1 fi -if [ "$BOARD_NAME" == "zcu102_fmcs2" ] || [ "$BOARD_NAME" == "zcu102_9371" ]; then - dtb_filename="system.dtb" - dts_filename="system.dts" -else - dtb_filename="devicetree.dtb" - dts_filename="devicetree.dts" -fi -echo $dtb_filename -echo $dts_filename - sudo true home_dir=$(pwd) @@ -85,109 +90,102 @@ set -x LINUX_KERNEL_SRC_DIR_NAME32=adi-linux LINUX_KERNEL_SRC_DIR_NAME64=adi-linux-64 -cd $OPENWIFI_DIR/user_space/ -./prepare_kernel.sh $XILINX_DIR 32 build -sudo true -./prepare_kernel.sh $XILINX_DIR 64 build -sudo true - -BOARD_NAME_ALL="sdrpi antsdr antsdr_e200 zc706_fmcs2 zed_fmcs2 zc702_fmcs2 adrv9361z7035 adrv9364z7020 zcu102_fmcs2 zcu102_9371" -# BOARD_NAME_ALL="zcu102_fmcs2" -# BOARD_NAME_ALL="adrv9361z7035" -for BOARD_NAME_TMP in $BOARD_NAME_ALL -do - if [ "$BOARD_NAME_TMP" == "zcu102_fmcs2" ] || [ "$BOARD_NAME_TMP" == "zcu102_9371" ]; then - dtb_filename_tmp="system.dtb" - dts_filename_tmp="system.dts" - ./boot_bin_gen_zynqmp.sh $OPENWIFI_HW_DIR $XILINX_DIR $BOARD_NAME_TMP - else - dtb_filename_tmp="devicetree.dtb" - dts_filename_tmp="devicetree.dts" - ./boot_bin_gen.sh $OPENWIFI_HW_DIR $XILINX_DIR $BOARD_NAME_TMP - fi - echo $dtb_filename_tmp - echo $dts_filename_tmp - - dtc -I dts -O dtb -o $OPENWIFI_DIR/kernel_boot/boards/$BOARD_NAME_TMP/$dtb_filename_tmp $OPENWIFI_DIR/kernel_boot/boards/$BOARD_NAME_TMP/$dts_filename_tmp - mkdir $SDCARD_DIR/BOOT/openwifi/$BOARD_NAME_TMP - sudo cp $OPENWIFI_DIR/kernel_boot/boards/$BOARD_NAME_TMP/$dtb_filename_tmp $SDCARD_DIR/BOOT/openwifi/$BOARD_NAME_TMP - sudo cp $OPENWIFI_DIR/kernel_boot/boards/$BOARD_NAME_TMP/output_boot_bin/BOOT.BIN $SDCARD_DIR/BOOT/openwifi/$BOARD_NAME_TMP - sudo true -done - -sudo mkdir $SDCARD_DIR/BOOT/openwifi/zynq-common -sudo cp $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME32/arch/arm/boot/uImage $SDCARD_DIR/BOOT/openwifi/zynq-common/ -sudo mkdir $SDCARD_DIR/BOOT/openwifi/zynqmp-common -sudo cp $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME64/arch/arm64/boot/Image $SDCARD_DIR/BOOT/openwifi/zynqmp-common/ - -sudo mkdir $SDCARD_DIR/rootfs/root/openwifi - -# Copy uImage BOOT.BIN and devicetree to SD card BOOT partition and backup at rootfs/root/openwifi -sudo cp $OPENWIFI_DIR/kernel_boot/boards/$BOARD_NAME/$dtb_filename $SDCARD_DIR/BOOT/ -sudo cp $OPENWIFI_DIR/kernel_boot/boards/$BOARD_NAME/$dtb_filename $SDCARD_DIR/rootfs/root/openwifi/ -rf -sudo cp $OPENWIFI_DIR/kernel_boot/boards/$BOARD_NAME/output_boot_bin/BOOT.BIN $SDCARD_DIR/BOOT/ -sudo cp $OPENWIFI_DIR/kernel_boot/boards/$BOARD_NAME/output_boot_bin/BOOT.BIN $SDCARD_DIR/rootfs/root/openwifi/ -rf -if [ "$BOARD_NAME" == "zcu102_fmcs2" ] || [ "$BOARD_NAME" == "zcu102_9371" ]; then - sudo cp $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME64/arch/arm64/boot/Image $SDCARD_DIR/BOOT/ - sudo cp $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME64/arch/arm64/boot/Image $SDCARD_DIR/rootfs/root/openwifi/ -rf -else - sudo cp $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME32/arch/arm/boot/uImage $SDCARD_DIR/BOOT/ - sudo cp $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME32/arch/arm/boot/uImage $SDCARD_DIR/rootfs/root/openwifi/ -rf +if [ "$SKIP_KERNEL_BUILD" == "0" ]; then + cd $OPENWIFI_DIR/user_space/ + ./prepare_kernel.sh $XILINX_DIR 32 + sudo true + ./prepare_kernel.sh $XILINX_DIR 64 + sudo true fi -sudo cp $OPENWIFI_DIR/user_space/* $SDCARD_DIR/rootfs/root/openwifi/ -rf -sudo mv $SDCARD_DIR/rootfs/root/openwifi/system_top.bit.bin $SDCARD_DIR/rootfs/root/openwifi/system_top.bit.bin.bak -sudo wget -P $SDCARD_DIR/rootfs/root/openwifi/webserver/ https://users.ugent.be/~xjiao/openwifi-low-aac.mp4 +if [ "$SKIP_BOOT" == "0" ]; then + sudo rm -rf $SDCARD_DIR/BOOT/openwifi/ + sudo mkdir -p $SDCARD_DIR/BOOT/openwifi + for BOARD_NAME_TMP in $BOARD_NAME_ALL + do + if [ "$BOARD_NAME_TMP" == "zcu102_fmcs2" ] || [ "$BOARD_NAME_TMP" == "zcu102_9371" ]; then + dtb_filename_tmp="system.dtb" + dts_filename_tmp="system.dts" + else + dtb_filename_tmp="devicetree.dtb" + dts_filename_tmp="devicetree.dts" + kernel_img_filename_tmp=$OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME32/arch/arm/boot/uImage + fi + ./boot_bin_gen.sh $XILINX_DIR $BOARD_NAME_TMP $OPENWIFI_HW_IMG_DIR/boards/$BOARD_NAME_TMP/sdk/system_top.xsa + echo $dtb_filename_tmp + echo $dts_filename_tmp -# build openwifi driver -saved_dir=$(pwd) -cd $OPENWIFI_DIR/driver -./make_all.sh $XILINX_DIR 32 -cd $OPENWIFI_DIR/driver/side_ch -./make_driver.sh $XILINX_DIR 32 -cd $saved_dir + dtc -I dts -O dtb -o $OPENWIFI_DIR/kernel_boot/boards/$BOARD_NAME_TMP/$dtb_filename_tmp $OPENWIFI_DIR/kernel_boot/boards/$BOARD_NAME_TMP/$dts_filename_tmp + sudo mkdir -p $SDCARD_DIR/BOOT/openwifi/$BOARD_NAME_TMP + sudo cp $OPENWIFI_DIR/kernel_boot/boards/$BOARD_NAME_TMP/$dtb_filename_tmp $SDCARD_DIR/BOOT/openwifi/$BOARD_NAME_TMP/ + sudo cp $OPENWIFI_DIR/kernel_boot/boards/$BOARD_NAME_TMP/output_boot_bin/BOOT.BIN $SDCARD_DIR/BOOT/openwifi/$BOARD_NAME_TMP/ + sudo cp ./system_top.bit.bin $SDCARD_DIR/BOOT/openwifi/$BOARD_NAME_TMP/ + sudo true + done -# Copy files to SD card rootfs partition -sudo mkdir $SDCARD_DIR/rootfs/root/openwifi/drv32 -sudo find $OPENWIFI_DIR/driver -name \*.ko -exec cp {} $SDCARD_DIR/rootfs/root/openwifi/drv32 \; + kernel_img_filename_tmp=$OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME64/arch/arm64/boot/Image + sudo cp $kernel_img_filename_tmp $SDCARD_DIR/BOOT/ + kernel_img_filename_tmp=$OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME32/arch/arm/boot/uImage + sudo cp $kernel_img_filename_tmp $SDCARD_DIR/BOOT/ +fi -# build openwifi driver -saved_dir=$(pwd) -cd $OPENWIFI_DIR/driver -./make_all.sh $XILINX_DIR 64 -cd $OPENWIFI_DIR/driver/side_ch -./make_driver.sh $XILINX_DIR 64 -cd $saved_dir +if [ "$SKIP_rootfs" == "0" ]; then + sudo rm -rf $SDCARD_DIR/rootfs/root/openwifi/ + sudo mkdir -p $SDCARD_DIR/rootfs/root/openwifi -# Copy files to SD card rootfs partition -sudo mkdir $SDCARD_DIR/rootfs/root/openwifi/drv64 -sudo find $OPENWIFI_DIR/driver -name \*.ko -exec cp {} $SDCARD_DIR/rootfs/root/openwifi/drv64 \; + saved_dir=$(pwd) + cd $OPENWIFI_DIR/user_space/ + git clean -dxf ./ + cd $saved_dir + sudo cp $OPENWIFI_DIR/user_space/* $SDCARD_DIR/rootfs/root/openwifi/ -rf + sudo mv $SDCARD_DIR/rootfs/root/openwifi/system_top.bit.bin $SDCARD_DIR/rootfs/root/openwifi/system_top.bit.bin.bak + sudo wget -P $SDCARD_DIR/rootfs/root/openwifi/webserver/ https://github.com/open-sdr/openwifi-hw-img/raw/master/openwifi-low-aac.mp4 -sudo mkdir $SDCARD_DIR/rootfs/lib/modules + sudo rm -rf $SDCARD_DIR/rootfs/root/openwifi_BOOT/ + sudo mkdir -p $SDCARD_DIR/rootfs/root/openwifi_BOOT + sudo cp $SDCARD_DIR/BOOT/openwifi/* $SDCARD_DIR/rootfs/root/openwifi_BOOT/ -rf -sudo mkdir $SDCARD_DIR/rootfs/lib/modules/$LINUX_KERNEL_SRC_DIR_NAME32 -sudo find $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME32 -name \*.ko -exec cp {} $SDCARD_DIR/rootfs/lib/modules/$LINUX_KERNEL_SRC_DIR_NAME32/ \; -sudo mv $SDCARD_DIR/rootfs/lib/modules/$LINUX_KERNEL_SRC_DIR_NAME32/xilinx_dma.ko $SDCARD_DIR/rootfs/root/openwifi/drv32 -sudo mv $SDCARD_DIR/rootfs/lib/modules/$LINUX_KERNEL_SRC_DIR_NAME32/ad9361_drv.ko $SDCARD_DIR/rootfs/root/openwifi/drv32 -sudo rm $SDCARD_DIR/rootfs/lib/modules/$LINUX_KERNEL_SRC_DIR_NAME32/{axidmatest.ko,adi_axi_hdmi.ko} -f + ARCH_OPTION_ALL="32 64" + for ARCH_OPTION_TMP in $ARCH_OPTION_ALL + do + # build openwifi driver + saved_dir=$(pwd) + cd $OPENWIFI_DIR/driver/ + git clean -dxf ./ + sync + ./make_all.sh $XILINX_DIR $ARCH_OPTION_TMP + cd $saved_dir -sudo mkdir $SDCARD_DIR/rootfs/lib/modules/$LINUX_KERNEL_SRC_DIR_NAME64 -sudo find $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME64 -name \*.ko -exec cp {} $SDCARD_DIR/rootfs/lib/modules/$LINUX_KERNEL_SRC_DIR_NAME64/ \; -sudo mv $SDCARD_DIR/rootfs/lib/modules/$LINUX_KERNEL_SRC_DIR_NAME64/xilinx_dma.ko $SDCARD_DIR/rootfs/root/openwifi/drv64 -sudo mv $SDCARD_DIR/rootfs/lib/modules/$LINUX_KERNEL_SRC_DIR_NAME64/ad9361_drv.ko $SDCARD_DIR/rootfs/root/openwifi/drv64 -sudo rm $SDCARD_DIR/rootfs/lib/modules/$LINUX_KERNEL_SRC_DIR_NAME64/{axidmatest.ko,adi_axi_hdmi.ko} -f + # Copy files to SD card rootfs partition + sudo rm -rf $SDCARD_DIR/rootfs/root/openwifi$ARCH_OPTION_TMP/ + sudo mkdir -p $SDCARD_DIR/rootfs/root/openwifi$ARCH_OPTION_TMP + sudo find $OPENWIFI_DIR/driver/ -name \*.ko -exec cp {} $SDCARD_DIR/rootfs/root/openwifi$ARCH_OPTION_TMP \; -sudo rm $SDCARD_DIR/rootfs/etc/udev/rules.d/70-persistent-net.rules -sudo cp $OPENWIFI_DIR/kernel_boot/70-persistent-net.rules $SDCARD_DIR/rootfs/etc/udev/rules.d/ -sudo mv $SDCARD_DIR/rootfs/lib/udev/rules.d/75-persistent-net-generator.rules $SDCARD_DIR/rootfs/lib/udev/rules.d/75-persistent-net-generator.rules.bak + sudo rm -rf $SDCARD_DIR/rootfs/root/kernel_modules$ARCH_OPTION_TMP/ + sudo mkdir -p $SDCARD_DIR/rootfs/root/kernel_modules$ARCH_OPTION_TMP -# Some setup -sudo echo -e "\nauto lo eth0\niface lo inet loopback\niface eth0 inet static\naddress 192.168.10.122\nnetmask 255.255.255.0\n" | sudo tee -a $SDCARD_DIR/rootfs/etc/network/interfaces -sudo echo -e "\nnameserver 8.8.8.8\nnameserver 4.4.4.4\n" | sudo tee -a $SDCARD_DIR/rootfs/etc/resolv.conf -sudo echo -e "\nUseDNS no\n" | sudo tee -a $SDCARD_DIR/rootfs/etc/ssh/sshd_config -sudo echo -e "\nnet.ipv4.ip_forward=1\n" | sudo tee -a $SDCARD_DIR/rootfs/etc/sysctl.conf -sudo chmod -x $SDCARD_DIR/rootfs/etc/update-motd.d/90-updates-available -sudo chmod -x $SDCARD_DIR/rootfs/etc/update-motd.d/91-release-upgrade + if [ "$ARCH_OPTION_TMP" == "32" ]; then + sudo find $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME32 -name \*.ko -exec cp {} $SDCARD_DIR/rootfs/root/kernel_modules$ARCH_OPTION_TMP/ \; + sudo cp $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME32/Module.symvers $SDCARD_DIR/rootfs/root/kernel_modules$ARCH_OPTION_TMP/ + sudo cp $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME32/modules.builtin $SDCARD_DIR/rootfs/root/kernel_modules$ARCH_OPTION_TMP/ + sudo cp $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME32/modules.builtin.modinfo $SDCARD_DIR/rootfs/root/kernel_modules$ARCH_OPTION_TMP/ + sudo cp $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME32/modules.order $SDCARD_DIR/rootfs/root/kernel_modules$ARCH_OPTION_TMP/ + else + sudo find $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME64 -name \*.ko -exec cp {} $SDCARD_DIR/rootfs/root/kernel_modules$ARCH_OPTION_TMP/ \; + sudo cp $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME64/Module.symvers $SDCARD_DIR/rootfs/root/kernel_modules$ARCH_OPTION_TMP/ + sudo cp $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME64/modules.builtin $SDCARD_DIR/rootfs/root/kernel_modules$ARCH_OPTION_TMP/ + sudo cp $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME64/modules.builtin.modinfo $SDCARD_DIR/rootfs/root/kernel_modules$ARCH_OPTION_TMP/ + sudo cp $OPENWIFI_DIR/$LINUX_KERNEL_SRC_DIR_NAME64/modules.order $SDCARD_DIR/rootfs/root/kernel_modules$ARCH_OPTION_TMP/ + fi + + sudo rm -rf $SDCARD_DIR/rootfs/lib/modules/*dirty* + sudo rm -rf $SDCARD_DIR/rootfs/root/kernel_modules + + # sudo rm $SDCARD_DIR/rootfs/root/kernel_modules$ARCH_OPTION_TMP/axidmatest.ko -f + # sudo rm $SDCARD_DIR/rootfs/root/kernel_modules$ARCH_OPTION_TMP/adi_axi_hdmi.ko -f + done + +fi cd $SDCARD_DIR/BOOT sync @@ -196,5 +194,5 @@ sync cd $home_dir -umount $SDCARD_DIR/BOOT/ -umount $SDCARD_DIR/rootfs/ +sudo umount $SDCARD_DIR/BOOT/ +sudo umount $SDCARD_DIR/rootfs/ diff --git a/user_space/wgd.sh b/user_space/wgd.sh index d69c286..4f5f479 100755 --- a/user_space/wgd.sh +++ b/user_space/wgd.sh @@ -64,6 +64,13 @@ insert_check_module () { print_usage +insmod ad9361_drv.ko +insmod xilinx_dma.ko +# modprobe ad9361_drv +# modprobe xilinx_dma +modprobe mac80211 +lsmod + TARGET_DIR=./ DOWNLOAD_FLAG=0 test_mode=0 @@ -125,10 +132,14 @@ fi echo " " -service network-manager stop +killall hostapd +service dhcpcd stop #dhcp client. it will get secondary ip for sdr0 which causes trouble +killall dhcpd +killall wpa_supplicant +#service network-manager stop +ifconfig sdr0 down rmmod sdr -insert_check_module ./ ad9361_drv if [ $DOWNLOAD_FLAG -eq 1 ]; then download_module fpga $TARGET_DIR @@ -138,15 +149,10 @@ if [ -f "$TARGET_DIR/system_top.bit.bin" ]; then ./load_fpga_img.sh $TARGET_DIR/system_top.bit.bin else echo $TARGET_DIR/system_top.bit.bin not found. Skip reloading FPGA. - ./load_fpga_img.sh fjdo349ujtrueugjhj + # ./load_fpga_img.sh fjdo349ujtrueugjhj fi ./rf_init_11n.sh -insert_check_module ./ xilinx_dma - -depmod -modprobe mac80211 -lsmod MODULE_ALL="tx_intf rx_intf openofdm_tx openofdm_rx xpu sdr" for MODULE in $MODULE_ALL @@ -161,8 +167,8 @@ do fi done -[ -e /tmp/check_calib_inf.pid ] && kill -0 $(