From d0d5556d26246dff58153b5112e9690001336256 Mon Sep 17 00:00:00 2001 From: Jiao Xianjun Date: Thu, 8 Jun 2023 12:04:57 +0200 Subject: [PATCH] Add FPGA internal loopback inline. --- doc/app_notes/packet-iq-self-loopback-test.md | 1 + 1 file changed, 1 insertion(+) diff --git a/doc/app_notes/packet-iq-self-loopback-test.md b/doc/app_notes/packet-iq-self-loopback-test.md index b140b4c..89ffc7f 100644 --- a/doc/app_notes/packet-iq-self-loopback-test.md +++ b/doc/app_notes/packet-iq-self-loopback-test.md @@ -42,6 +42,7 @@ This makes the IQ sample, WiFi packet and CSI self loopback test possible. Readi ./sdrctl dev sdr0 set reg xpu 1 1 # Set the loopback mode to over-the-air ./side_ch_ctl wh5h0 + (./side_ch_ctl wh5h4 for FPGA internal loopback) # Relay the FPGA IQ capture to the host computer that will show the captured IQ later on) ./side_ch_ctl g0 ```