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Some minor unused comments
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@ -2,6 +2,8 @@
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// SPDX-FileCopyrightText: 2019 UGent
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// SPDX-FileCopyrightText: 2019 UGent
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// SPDX-License-Identifier: AGPL-3.0-or-later
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// SPDX-License-Identifier: AGPL-3.0-or-later
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// #ifndef __HW_DEF_H_FILE__
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// #define __HW_DEF_H_FILE__
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const char *sdr_compatible_str = "sdr,sdr";
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const char *sdr_compatible_str = "sdr,sdr";
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enum openwifi_fpga_type {
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enum openwifi_fpga_type {
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@ -62,7 +64,7 @@ enum tx_intf_mode {
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TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1,
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TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1,
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};
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};
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const int tx_intf_fo_mapping[] = {0, 0, 0, 0,-10,10,-10,10};
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const int tx_intf_fo_mapping[] = {0, 0, 0, 0, 0, -10, 10, -10, 10};
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const u32 dma_symbol_fifo_size_hw_queue[] = {4*1024, 4*1024, 4*1024, 4*1024}; // !!!make sure align to fifo in tx_intf_s_axis.v
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const u32 dma_symbol_fifo_size_hw_queue[] = {4*1024, 4*1024, 4*1024, 4*1024}; // !!!make sure align to fifo in tx_intf_s_axis.v
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struct tx_intf_driver_api {
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struct tx_intf_driver_api {
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@ -422,3 +424,5 @@ struct xpu_driver_api {
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void (*XPU_REG_MAC_ADDR_write)(u8 *mac_addr);
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void (*XPU_REG_MAC_ADDR_write)(u8 *mac_addr);
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};
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};
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// #endif
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