diff --git a/driver/hw_def.h b/driver/hw_def.h
index 46ebcc3..8588508 100644
--- a/driver/hw_def.h
+++ b/driver/hw_def.h
@@ -213,6 +213,36 @@ enum openofdm_rx_mode {
 	OPENOFDM_RX_NORMAL,
 };
 
+#define OPENOFDM_RX_POWER_THRES_INIT 124
+// Above 118 is based on these test result (2022-03-09)
+// FMCOMMS3
+// 2437M
+// 11a/g BPSK 6M, Rx sensitivity level dmesg report -85dBm
+// priv->rssi_correction = 153; rssi_half_db/2 = 153-85=68; rssi_half_db = 136
+// 5180M
+// 11a/g BPSK 6m, Rx sensitivity level dmesg report -84dBm
+// priv->rssi_correction = 145; rssi_half_db/2 = 145-84=61; rssi_half_db = 122
+// 5320M
+// 11a/g BPSK 6m, Rx sensitivity level dmesg report -86dBm
+// priv->rssi_correction = 148; rssi_half_db/2 = 148-86=62; rssi_half_db = 124
+
+// FMCOMMS2
+// 2437M
+// 11a/g BPSK 6M, Rx sensitivity level dmesg report -80dBm
+// priv->rssi_correction = 153; rssi_half_db/2 = 153-80=73; rssi_half_db = 146
+// 5180M
+// 11a/g BPSK 6m, Rx sensitivity level dmesg report -83dBm
+// priv->rssi_correction = 145; rssi_half_db/2 = 145-83=62; rssi_half_db = 124
+// 5320M
+// 11a/g BPSK 6m, Rx sensitivity level dmesg report -86dBm
+// priv->rssi_correction = 148; rssi_half_db/2 = 148-86=62; rssi_half_db = 124
+
+#define OPENOFDM_RX_RSSI_DBM_TH_DEFAULT (-84)
+#define OPENOFDM_RX_DC_RUNNING_SUM_TH_INIT 64
+#define OPENOFDM_RX_MIN_PLATEAU_INIT 100
+
+#define OPENWIFI_MAX_SIGNAL_LEN_TH 1700 //Packet longer than this threshold will result in receiver early termination. It goes to openofdm_rx/xpu/rx_intf
+
 struct openofdm_rx_driver_api {
 	u32 (*hw_init)(enum openofdm_rx_mode mode);
 
diff --git a/driver/openofdm_rx/openofdm_rx.c b/driver/openofdm_rx/openofdm_rx.c
index 828acf7..cb93a5e 100644
--- a/driver/openofdm_rx/openofdm_rx.c
+++ b/driver/openofdm_rx/openofdm_rx.c
@@ -91,9 +91,9 @@ static inline u32 hw_init(enum openofdm_rx_mode mode){
 	printk("%s hw_init input: power_thres %d dc_running_sum_th %d min_plateau %d\n", openofdm_rx_compatible_str, OPENOFDM_RX_POWER_THRES_INIT, OPENOFDM_RX_DC_RUNNING_SUM_TH_INIT, OPENOFDM_RX_MIN_PLATEAU_INIT);
 
 	// 1) power threshold configuration and reset
-	openofdm_rx_api->OPENOFDM_RX_REG_POWER_THRES_write(0);
-	openofdm_rx_api->OPENOFDM_RX_REG_MIN_PLATEAU_write(100);
-	openofdm_rx_api->OPENOFDM_RX_REG_SOFT_DECODING_write(1);
+	openofdm_rx_api->OPENOFDM_RX_REG_POWER_THRES_write((OPENOFDM_RX_DC_RUNNING_SUM_TH_INIT<<16)|OPENOFDM_RX_POWER_THRES_INIT); // turn on signal watchdog by default
+	openofdm_rx_api->OPENOFDM_RX_REG_MIN_PLATEAU_write(OPENOFDM_RX_MIN_PLATEAU_INIT);
+	openofdm_rx_api->OPENOFDM_RX_REG_SOFT_DECODING_write((OPENWIFI_MAX_SIGNAL_LEN_TH<<16)|1); //bit1 enable soft decoding; bit31~16 max pkt length threshold
 
 	//rst
 	for (i=0;i<8;i++)
diff --git a/driver/rx_intf/rx_intf.c b/driver/rx_intf/rx_intf.c
index 8662905..fffb5da 100644
--- a/driver/rx_intf/rx_intf.c
+++ b/driver/rx_intf/rx_intf.c
@@ -320,7 +320,7 @@ static inline u32 hw_init(enum rx_intf_mode mode, u32 num_dma_symbol_to_pl, u32
 		//bit16: 1-auto m_axis rst (sig_valid_from_acc|sig_invalid_from_acc|ht_sig_valid|ht_sig_invalid|ht_unsupported); 0-normal
 		//bit24: 1-disable m_axis fifo_rst_by_fcs_invalid; 0-enable
 		//bit29,28: sig_valid_mode. 0- non-ht sig valid; 1- ht sig valid other- both
-		rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_write(0);
+		rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_write(OPENWIFI_MAX_SIGNAL_LEN_TH<<16); //bit31~16 max pkt length threshold
 		rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_write(0);
 		// 0-wifi_rx packet out; 1-loopback from input of wifi_rx
 		
diff --git a/driver/xpu/xpu.c b/driver/xpu/xpu.c
index a738812..a25cf66 100644
--- a/driver/xpu/xpu.c
+++ b/driver/xpu/xpu.c
@@ -430,7 +430,7 @@ static inline u32 hw_init(enum xpu_mode mode){
 	xpu_api->XPU_REG_RECV_ACK_COUNT_TOP0_write( (((45+2+2)*10 + 15)<<16) | 10 );//2.4GHz. extra 300 clocks are needed when rx core fall into fake ht detection phase (rx mcs 6M)
 	xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_write( (((51+2+2)*10 + 15)<<16) | 10 );//5GHz. extra 300 clocks are needed when rx core fall into fake ht detection phase (rx mcs 6M)
 
-	xpu_api->XPU_REG_DIFS_ADVANCE_write(2); //us
+	xpu_api->XPU_REG_DIFS_ADVANCE_write((OPENWIFI_MAX_SIGNAL_LEN_TH<<16)|2); //us. bit31~16 max pkt length threshold
 
 	printk("%s hw_init err %d\n", xpu_compatible_str, err);
 	return(err);