enable dynamic cw

This commit is contained in:
weiliu 2020-12-28 16:03:51 +01:00
parent a2548b82c9
commit 5680efab70
3 changed files with 9 additions and 6 deletions

View File

@ -442,7 +442,7 @@ static irqreturn_t openwifi_tx_interrupt(int irq, void *dev_id)
struct openwifi_ring *ring;
struct sk_buff *skb;
struct ieee80211_tx_info *info;
u32 reg_val, hw_queue_len, prio, queue_idx, dma_fifo_no_room_flag, loop_count=0;//, i;
u32 reg_val, hw_queue_len, prio, queue_idx, dma_fifo_no_room_flag, cw, loop_count=0;//, i;
u8 tx_result_report;
// u16 prio_rd_idx_store[64]={0};
@ -450,8 +450,9 @@ static irqreturn_t openwifi_tx_interrupt(int irq, void *dev_id)
while(1) { // loop all packets that have been sent by FPGA
reg_val = tx_intf_api->TX_INTF_REG_PKT_INFO_read();
if (reg_val!=0x7FFFF) {
prio = (reg_val>>(5+NUM_BIT_MAX_PHY_TX_SN+NUM_BIT_MAX_NUM_HW_QUEUE));
if (reg_val!=0x7FFFFF) {
prio = ((0x7FFFF & reg_val)>>(5+NUM_BIT_MAX_PHY_TX_SN+NUM_BIT_MAX_NUM_HW_QUEUE));
cw = (reg_val>>(2+5+NUM_BIT_MAX_PHY_TX_SN+NUM_BIT_MAX_NUM_HW_QUEUE));
ring = &(priv->tx_ring[prio]);
ring->bd_rd_idx = ((reg_val>>5)&MAX_PHY_TX_SN);
skb = ring->bds[ring->bd_rd_idx].skb_linked;
@ -506,6 +507,8 @@ static irqreturn_t openwifi_tx_interrupt(int irq, void *dev_id)
if ( (tx_result_report&0x10) && ((priv->drv_tx_reg_val[DRV_TX_REG_IDX_PRINT_CFG])&1) )
printk("%s openwifi_tx_interrupt: WARNING tx_result %02x prio%d wr%d rd%d\n", sdr_compatible_str, tx_result_report, prio, ring->bd_wr_idx, ring->bd_rd_idx);
if ( ((priv->drv_tx_reg_val[DRV_TX_REG_IDX_PRINT_CFG])&2) )
printk("%s openwifi_tx_interrupt: tx_result %02x prio%d wr%d rd%d cw %d\n", sdr_compatible_str, tx_result_report, prio, ring->bd_wr_idx, ring->bd_rd_idx, cw);
ieee80211_tx_status_irqsafe(dev, skb);
@ -981,7 +984,7 @@ static int openwifi_start(struct ieee80211_hw *dev)
xpu_api->hw_init(priv->xpu_cfg);
agc_gain_delay = 50; //samples
rssi_half_db_offset = 150;
rssi_half_db_offset = 134; // to be consistent
xpu_api->XPU_REG_RSSI_DB_CFG_write(0x80000000|((rssi_half_db_offset<<16)|agc_gain_delay) );
xpu_api->XPU_REG_RSSI_DB_CFG_write((~0x80000000)&((rssi_half_db_offset<<16)|agc_gain_delay) );

View File

@ -400,7 +400,7 @@ static inline u32 hw_init(enum xpu_mode mode){
//xpu_api->XPU_REG_CSMA_DEBUG_write((1<<31)|(20<<24)|(4<<19)|(3<<14)|(10<<7)|(5));
xpu_api->XPU_REG_CSMA_DEBUG_write(0);
xpu_api->XPU_REG_CSMA_CFG_write(3); //normal CSMA
xpu_api->XPU_REG_CSMA_CFG_write(268435459); // 0x10000003, min CSMA cw exp = 3, set bit 28 high for dynamic CW
// xpu_api->XPU_REG_CSMA_CFG_write(0xe0000000); //high priority
xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( ((51)<<16)|0 );//now our tx send out I/Q immediately

@ -1 +1 @@
Subproject commit 1106691bafd82c877366e35d0a2458dbdc1bac91
Subproject commit 5871295ebbbc6d1373c2b3ddee567d1c73c4156d