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https://github.com/open-sdr/openwifi.git
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4 fpga queues and better driver/fpga flow control to avoid crash. improved slice cfg and printing (#23)
This commit is contained in:
Jiao Xianjun
GitHub
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commit
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12
README.md
12
README.md
@ -33,12 +33,12 @@ Openwifi code has dual licenses. AGPLv3 is the opensource license. For non-opens
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board_name|board combination|status|SD card img
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-------|-------|----|----
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zc706_fmcs2|Xilinx ZC706 dev board + FMCOMMS2/3/4|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.1.0-taiyuan-2-32bit.img.xz)
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zed_fmcs2|Xilinx zed board + FMCOMMS2/3/4|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.1.0-taiyuan-2-32bit.img.xz)
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adrv9364z7020|ADRV9364Z7020 SOM|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.1.0-taiyuan-2-32bit.img.xz)
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adrv9361z7035|ADRV9361Z7035 SOM|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.1.0-taiyuan-2-32bit.img.xz)
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zc702_fmcs2|Xilinx ZC702 dev board + FMCOMMS2/3/4|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.1.0-taiyuan-2-32bit.img.xz)
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zcu102_fmcs2|Xilinx ZCU102 dev board + FMCOMMS2/3/4|Done|[64bit img](https://drive.google.com/file/d/1x6gvd5t2QOxRUXteSHiewaUZJghCd9bR/view?usp=sharing)
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zc706_fmcs2|Xilinx ZC706 dev board + FMCOMMS2/3/4|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.1.0-taiyuan-3-32bit.img.xz)
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zed_fmcs2|Xilinx zed board + FMCOMMS2/3/4|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.1.0-taiyuan-3-32bit.img.xz)
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adrv9364z7020|ADRV9364Z7020 SOM|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.1.0-taiyuan-3-32bit.img.xz)
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adrv9361z7035|ADRV9361Z7035 SOM|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.1.0-taiyuan-3-32bit.img.xz)
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zc702_fmcs2|Xilinx ZC702 dev board + FMCOMMS2/3/4|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.1.0-taiyuan-3-32bit.img.xz)
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zcu102_fmcs2|Xilinx ZCU102 dev board + FMCOMMS2/3/4|Done|[64bit img](https://users.ugent.be/~xjiao/openwifi-1.1.0-taiyuan-3-64bit.img.xz)
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zcu102_9371|Xilinx ZCU102 dev board + ADRV9371|Future|None
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- board_name is used to identify FPGA design in openwifi-hw/boards/
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@ -25,7 +25,7 @@ openwifi driver (sdr.c) implements following APIs of ieee80211_ops:
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- **bss_info_changed**. It is called when upper layer believe some BSS parameters need to be changed (BSSID, TX power, beacon interval, etc)
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- **conf_tx**. It is called when upper layer needs to config/change some tx parameters (AIFS, CW_MIN, CW_MAX, TXOP, etc)
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- **prepare_multicast**. It is called when upper layer needs to prepare multicast, currently only a empty function hook is present.
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- **configure_filter**. It is called when upper layer wants to config/change the [frame filtering](#rx-packet-flow-and-filtering-config) rule in FPGA.
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- **configure_filter**. It is called when upper layer wants to config/change the [frame filtering](#Rx-packet-flow-and-filtering-config) rule in FPGA.
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- **rfkill_poll**. It is called when upper layer wants to know the RF status (ON/OFF).
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- **get_tsf**. It is called when upper layer wants to get 64bit FPGA timer value (TSF - Timing synchronization function)
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- **set_tsf**. It is called when upper layer wants to set 64bit FPGA timer value
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@ -52,14 +52,11 @@ sdrctl dev sdr0 set para_name value
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```
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para_name|meaning|comment
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---------|-------|----
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addr0|target MAC address of tx slice 0|32bit. for address 6c:fd:b9:4c:b1:c1, you set b94cb1c1
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slice_total0|tx slice 0 cycle length in us|for length 50ms, you set 49999
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slice_start0|tx slice 0 cycle start time in us|for start at 10ms, you set 10000
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slice_end0| tx slice 0 cycle end time in us|for end at 40ms, you set 39999
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addr1|target MAC address of tx slice 1|32bit. for address 6c:fd:b9:4c:b1:c1, you set b94cb1c1
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slice_total1|tx slice 1 cycle length in us|for length 50ms, you set 49999
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slice_start1|tx slice 1 cycle start time in us|for start at 10ms, you set 10000
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slice_end1| tx slice 1 cycle end time in us|for end at 40ms, you set 39999
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slice_idx|the slice that will be set/get|0~3. After finishing all slice config, **set slice_idx to 4** to synchronize all slices. Otherwize the start/end of different slices have different actual time
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addr|target MAC address of tx slice_idx|32bit. for address 6c:fd:b9:4c:b1:c1, you set b94cb1c1
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slice_total|tx slice_idx cycle length in us|for length 50ms, you set 49999
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slice_start|tx slice_idx cycle start time in us|for start at 10ms, you set 10000
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slice_end| tx slice_idx cycle end time in us|for end at 40ms, you set 39999
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tsf| sets TSF value| it requires two values "high_TSF low_TSF". Decimal
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### Get and set a register of a module
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@ -76,6 +73,7 @@ module_name: **drv_rx**
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reg_idx|meaning|comment
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-------|-------|----
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1|rx antenna selection|0:rx1, 1:rx2. After this command, you should down and up sdr0 by ifconfig, but not reload sdr0 driver via ./wgd.sh
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7|dmesg print control|bit0:error msg (0:OFF, 1:ON); bit1:regular msg (0:OFF, 1:ON)
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(In the **comment** column, you may get a list of **decimalvalue(0xhexvalue):explanation** for a register, only use the **decimalvalue** in the sdrctl command)
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@ -85,6 +83,7 @@ reg_idx|meaning|comment
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-------|-------|----
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0|override Linux rate control of tx unicast data packet|4:6M, 5:9M, 6:12M, 7:18M, 8:24M, 9:36M, 10:48M, 11:54M
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1|tx antenna selection|0:tx1, 1:tx2. After this command, you should down and up sdr0 by ifconfig, but not reload sdr0 driver via ./wgd.sh
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7|dmesg print control|bit0:error msg (0:OFF, 1:ON); bit1:regular msg (0:OFF, 1:ON)
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module_name: **drv_xpu**
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@ -134,12 +133,6 @@ reg_idx|meaning|comment
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4|band and channel number setting|see enum openwifi_band in hw_def.h. it will be set automatically by Linux. normally you shouldn't set it
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11|max number of retransmission in FPGA|normally number of retransmissions controlled by Linux in real-time. If you write non-zeros value to this register, it will override Linux real-time setting
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19|CSMA enable/disable|3758096384(0xe0000000): disable, 3:enable
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20|tx slice 0 cycle length in us|for length 50ms, you set 49999
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21|tx slice 0 cycle start time in us|for start at 10ms, you set 10000
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22|tx slice 0 cycle end time in us|for end at 40ms, you set 39999
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23|tx slice 1 cycle length in us|for length 50ms, you set 49999
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24|tx slice 1 cycle start time in us|for start at 10ms, you set 10000
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25|tx slice 1 cycle end time in us|for end at 40ms, you set 39999
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27|FPGA packet filter config|check openwifi_configure_filter in sdr.c. also [mac80211 frame filtering](https://www.kernel.org/doc/html/v4.9/80211/mac80211.html#frame-filtering)
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28|BSSID address low 32bit for BSSID filtering|normally it is set by Linux in real-time automatically
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29|BSSID address high 32bit for BSSID filtering|normally it is set by Linux in real-time automatically
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@ -147,7 +140,6 @@ reg_idx|meaning|comment
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31|openwifi MAC address high 32bit|check XPU_REG_MAC_ADDR_write in sdr.c to see how we set MAC address to FPGA when NIC start
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58|TSF runtime value low 32bit|read only
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59|TSF runtime value high 32bit|read only
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63|version information|read only
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## Rx packet flow and filtering config
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@ -240,42 +232,53 @@ Following figure shows the detailed configuration point in AD9361, driver (sdr.c
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### dmesg
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To debug/see the basic driver behaviour, you could use dmesg command in Linux. openwifi driver prints normal tx/rx packet information when a packet is sent or received. The driver also prints WARNING information if it feels something abnormal happens. You can search "printk" in sdr.c to see all the printing points.
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To debug/see the basic driver behaviour, you could turn on message printing by
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```
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See all printing:
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./sdrctl dev sdr0 set reg drv_tx 7 3
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./sdrctl dev sdr0 set reg drv_rx 7 3
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See only error printing:
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./sdrctl dev sdr0 set reg drv_tx 7 1
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./sdrctl dev sdr0 set reg drv_rx 7 1
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See only regular printing:
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./sdrctl dev sdr0 set reg drv_tx 7 2
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./sdrctl dev sdr0 set reg drv_rx 7 2
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Turn off printing:
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./sdrctl dev sdr0 set reg drv_tx 7 0
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./sdrctl dev sdr0 set reg drv_rx 7 0
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```
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and use dmesg command in Linux to see those messages. openwifi driver prints normal tx/rx packet information when a packet is sent or received. The driver also prints WARNING information if it feels something abnormal happens. You can search "printk" in sdr.c to see all the printing points.
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- tx printing example
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sdr,sdr openwifi_tx: 116bytes 48M FC0208 DI002c addr1/2/3:b827ebe65f1e/66554433224c/66554433224c SC1df0 flag40000012 retry2 ack1 q0 sn1075 R/CTS 00 1M 0us wr/rd 19/19
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sdr,sdr openwifi_tx: 84bytes 48M FC0208 DI002c addr1/2/3:b0481ada2ef2/66554433222a/66554433222a SC2100 flag40000012 retr6 ack1 prio2 q2 wr4 rd3
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- printing from sdr driver, openwifi_tx function.
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- 116bytes: packet size (length field in SIGNAL) is 116 bytes.
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- 48M: MCS (rate field in SIGNAL) is 48Mbps.
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- FC0208: Frame Control field 0x0208, which means type data, subtype data, to DS 0, from DS 1 (a packet from AP to client).
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- 84bytes: packet size (length field in SIGNAL)
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- 48M: MCS (rate field in SIGNAL)
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- FC0208: Frame Control field, which means type data, subtype data, to DS 0, from DS 1 (a packet from AP to client).
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- DI002c: Duration/ID field 0x002c. How many us this packet will occupy the channel (including waiting for ACK).
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- addr1/2/3: address fields. Target MAC address b827ebe65f1e, source MAC address 66554433224c (openwifi).
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- SC1df0: Sequence Control field 0x1df0, which means that the driver inserts sequence number 0x1df0 to the packet under request of upper layer.
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- addr1/2/3: address fields. Target MAC address b0481ada2ef2, source MAC address 66554433222a (openwifi).
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- SC2100: Sequence Control field 0x2100, which means that the driver inserts sequence number 0x2100 to the packet under request of upper layer.
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- flag40000012: flags field from upper layer struct ieee80211_tx_info (first fragment? need ACK? need sequence number insertion? etc.). Here is 0x40000012.
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- retry2: upper layer tells us the maximum number of retransmissions for this packet is 2.
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- retry6: upper layer tells us the maximum number of retransmissions for this packet is 6.
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- ack1: upper layer tells us this packet needs ACK.
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- q0: the packet goes to FPGA queue 0.
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- sn1075: PHY/FPGA sequence number 1075. This is different from Sequence Control asked by upper layer. This is for cross check between FPGA/interrupt and driver.
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- R/CTS 00: upper layer believes this packet doesn't need RTS/CTS mechanism (Because the packet size is below the RTS threshold).
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- 1M 0us: if RTS/CTS is asked to be used by upper layer, it should use xM rate and Xus duration.
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- wr/rd 19/19: the write/read index of buffer (shared buffer between the active openwifi_tx and background openwifi_tx_interrupt).
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- prio2: Linux select priority queue 2 for this packet (0:VO voice, 1:VI video, 2:BE best effort and 3:BK background)
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- q2: the packet goes to FPGA queue 2. (You can change the mapping between Linux priority and FPGA queue in sdr.c)
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- wr4 rd3: the write/read index of buffer (shared buffer between the active openwifi_tx and background openwifi_tx_interrupt).
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- rx printing example
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sdr,sdr openwifi_rx_interrupt: 120bytes ht0 54M FC0108 DI002c addr1/2/3:66554433224c/b827ebe65f1e/66554433224c SCcf20 fcs1 sn117 i117 -36dBm
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sdr,sdr openwifi_rx_interrupt: 28bytes 24M FC0108 DI002c addr1/2/3:66554433222a/b0481ada2ef2/66554433222a SC4760 fcs1 buf_idx13 -30dBm
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- printing from sdr driver, openwifi_rx_interrupt function.
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- 120bytes: packet size (length field in SIGNAL) is 120 bytes.
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- ht0: this is non-ht packet.
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- 54M: MCS (rate field in SIGNAL) is 54Mbps.
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- FC0108: Frame Control field 0x0208, which means type data, subtype data, to DS 1, from DS 0 (a packet client to openwifi AP).
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- 28bytes: packet size (length field in SIGNAL)
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- 24M: MCS (rate field in SIGNAL)
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- FC0108: Frame Control field 0x0108, which means type data, subtype data, to DS 1, from DS 0 (a packet client to openwifi AP).
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- DI002c: Duration/ID field 0x002c. How many us this packet will occupy the channel (including waiting for ACK).
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- addr1/2/3: address fields. Target MAC address 66554433224c (openwifi), source MAC address b827ebe65f1e.
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- SCcf20: Sequence Control field 0x1df0, which means that the packet includes sequence number 0xcf20 (under request of upper layer of the peer).
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- fcs1: FCS/CRC is OK.
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- sn117: HY/FPGA sequence number 117. This is different from Sequence Control asked by upper layer. This is for cross check between FPGA/interrupt and driver.
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- i117: current rx packet DMA buffer index 117.
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- -36dBm: signal strength of this received packet.
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- addr1/2/3: address fields. Target MAC address 66554433222a (openwifi), source MAC address b0481ada2ef2.
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- SC4760: Sequence Control field 0x4760, which means that the packet includes sequence number 0x4760 (under request of upper layer of the peer).
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- fcs1: FCS/CRC is OK. (fcs0 means bad CRC)
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- buf_idx13: current rx packet DMA buffer index 13.
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- -30dBm: signal strength of this received packet.
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### Native Linux tools
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@ -26,11 +26,12 @@ const char *tx_intf_compatible_str = "sdr,tx_intf";
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#define TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_ADDR (8*4)
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#define TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_ADDR (9*4)
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#define TX_INTF_REG_CFG_DATA_TO_ANT_ADDR (10*4)
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#define TX_INTF_REG_S_AXIS_FIFO_TH_ADDR (11*4)
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#define TX_INTF_REG_TX_HOLD_THRESHOLD_ADDR (12*4)
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#define TX_INTF_REG_BB_GAIN_ADDR (13*4)
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#define TX_INTF_REG_INTERRUPT_SEL_ADDR (14*4)
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#define TX_INTF_REG_ANT_SEL_ADDR (16*4)
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#define TX_INTF_REG_S_AXIS_FIFO_DATA_COUNT_ADDR (21*4)
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#define TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_ADDR (21*4)
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#define TX_INTF_REG_PKT_INFO_ADDR (22*4)
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#define TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_ADDR (24*4)
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@ -50,6 +51,7 @@ enum tx_intf_mode {
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};
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const int tx_intf_fo_mapping[] = {0, 0, 0, 0,-10,10,-10,10};
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const u32 dma_symbol_fifo_size_hw_queue[] = {4*1024, 4*1024, 4*1024, 4*1024}; // !!!make sure align to fifo in tx_intf_s_axis.v
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struct tx_intf_driver_api {
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u32 (*hw_init)(enum tx_intf_mode mode, u32 num_dma_symbol_to_pl, u32 num_dma_symbol_to_ps);
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@ -68,11 +70,12 @@ struct tx_intf_driver_api {
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u32 (*TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read)(void);
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u32 (*TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read)(void);
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u32 (*TX_INTF_REG_CFG_DATA_TO_ANT_read)(void);
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u32 (*TX_INTF_REG_S_AXIS_FIFO_TH_read)(void);
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u32 (*TX_INTF_REG_TX_HOLD_THRESHOLD_read)(void);
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u32 (*TX_INTF_REG_INTERRUPT_SEL_read)(void);
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u32 (*TX_INTF_REG_BB_GAIN_read)(void);
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u32 (*TX_INTF_REG_ANT_SEL_read)(void);
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u32 (*TX_INTF_REG_S_AXIS_FIFO_DATA_COUNT_read)(void);
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u32 (*TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_read)(void);
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u32 (*TX_INTF_REG_PKT_INFO_read)(void);
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u32 (*TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_read)(void);
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@ -87,11 +90,12 @@ struct tx_intf_driver_api {
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void (*TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write)(u32 value);
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void (*TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write)(u32 value);
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void (*TX_INTF_REG_CFG_DATA_TO_ANT_write)(u32 value);
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void (*TX_INTF_REG_S_AXIS_FIFO_TH_write)(u32 value);
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void (*TX_INTF_REG_TX_HOLD_THRESHOLD_write)(u32 value);
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void (*TX_INTF_REG_INTERRUPT_SEL_write)(u32 value);
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void (*TX_INTF_REG_BB_GAIN_write)(u32 value);
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void (*TX_INTF_REG_ANT_SEL_write)(u32 value);
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void (*TX_INTF_REG_S_AXIS_FIFO_DATA_COUNT_write)(u32 value);
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void (*TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_write)(u32 value);
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void (*TX_INTF_REG_PKT_INFO_write)(u32 value);
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};
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@ -251,12 +255,9 @@ const char *xpu_compatible_str = "sdr,xpu";
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#define XPU_REG_SEND_ACK_WAIT_TOP_ADDR (18*4)
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#define XPU_REG_CSMA_CFG_ADDR (19*4)
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#define XPU_REG_SLICE_COUNT_TOTAL0_ADDR (20*4)
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#define XPU_REG_SLICE_COUNT_START0_ADDR (21*4)
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#define XPU_REG_SLICE_COUNT_END0_ADDR (22*4)
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#define XPU_REG_SLICE_COUNT_TOTAL1_ADDR (23*4)
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#define XPU_REG_SLICE_COUNT_START1_ADDR (24*4)
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#define XPU_REG_SLICE_COUNT_END1_ADDR (25*4)
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#define XPU_REG_SLICE_COUNT_TOTAL_ADDR (20*4)
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#define XPU_REG_SLICE_COUNT_START_ADDR (21*4)
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#define XPU_REG_SLICE_COUNT_END_ADDR (22*4)
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#define XPU_REG_CTS_TO_RTS_CONFIG_ADDR (26*4)
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#define XPU_REG_FILTER_FLAG_ADDR (27*4)
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@ -364,16 +365,16 @@ struct xpu_driver_api {
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void (*XPU_REG_CSMA_CFG_write)(u32 value);
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u32 (*XPU_REG_CSMA_CFG_read)(void);
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void (*XPU_REG_SLICE_COUNT_TOTAL0_write)(u32 value);
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void (*XPU_REG_SLICE_COUNT_START0_write)(u32 value);
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void (*XPU_REG_SLICE_COUNT_END0_write)(u32 value);
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void (*XPU_REG_SLICE_COUNT_TOTAL_write)(u32 value);
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void (*XPU_REG_SLICE_COUNT_START_write)(u32 value);
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void (*XPU_REG_SLICE_COUNT_END_write)(u32 value);
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void (*XPU_REG_SLICE_COUNT_TOTAL1_write)(u32 value);
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void (*XPU_REG_SLICE_COUNT_START1_write)(u32 value);
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void (*XPU_REG_SLICE_COUNT_END1_write)(u32 value);
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u32 (*XPU_REG_SLICE_COUNT_TOTAL0_read)(void);
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u32 (*XPU_REG_SLICE_COUNT_START0_read)(void);
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u32 (*XPU_REG_SLICE_COUNT_END0_read)(void);
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u32 (*XPU_REG_SLICE_COUNT_TOTAL_read)(void);
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u32 (*XPU_REG_SLICE_COUNT_START_read)(void);
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u32 (*XPU_REG_SLICE_COUNT_END_read)(void);
|
||||
u32 (*XPU_REG_SLICE_COUNT_TOTAL1_read)(void);
|
||||
u32 (*XPU_REG_SLICE_COUNT_START1_read)(void);
|
||||
u32 (*XPU_REG_SLICE_COUNT_END1_read)(void);
|
||||
|
||||
@ -63,7 +63,7 @@ static struct openofdm_rx_driver_api *openofdm_rx_api = &openofdm_rx_driver_api_
|
||||
EXPORT_SYMBOL(openofdm_rx_api);
|
||||
|
||||
static inline u32 hw_init(enum openofdm_rx_mode mode){
|
||||
int err=0;
|
||||
int err=0, i;
|
||||
|
||||
printk("%s hw_init mode %d\n", openofdm_rx_compatible_str, mode);
|
||||
|
||||
@ -95,13 +95,13 @@ static inline u32 hw_init(enum openofdm_rx_mode mode){
|
||||
openofdm_rx_api->OPENOFDM_RX_REG_POWER_THRES_write(0);
|
||||
openofdm_rx_api->OPENOFDM_RX_REG_MIN_PLATEAU_write(100);
|
||||
|
||||
openofdm_rx_api->OPENOFDM_RX_REG_MULTI_RST_write(0xFFFFFFFF);
|
||||
openofdm_rx_api->OPENOFDM_RX_REG_MULTI_RST_write(0xFFFFFFFF);
|
||||
openofdm_rx_api->OPENOFDM_RX_REG_MULTI_RST_write(0xFFFFFFFF);
|
||||
openofdm_rx_api->OPENOFDM_RX_REG_MULTI_RST_write(0xFFFFFFFF);
|
||||
openofdm_rx_api->OPENOFDM_RX_REG_MULTI_RST_write(0xFFFFFFFF);
|
||||
openofdm_rx_api->OPENOFDM_RX_REG_MULTI_RST_write(0xFFFFFFFF);
|
||||
openofdm_rx_api->OPENOFDM_RX_REG_MULTI_RST_write(0);
|
||||
//rst
|
||||
for (i=0;i<8;i++)
|
||||
openofdm_rx_api->OPENOFDM_RX_REG_MULTI_RST_write(0);
|
||||
for (i=0;i<32;i++)
|
||||
openofdm_rx_api->OPENOFDM_RX_REG_MULTI_RST_write(0xFFFFFFFF);
|
||||
for (i=0;i<8;i++)
|
||||
openofdm_rx_api->OPENOFDM_RX_REG_MULTI_RST_write(0);
|
||||
|
||||
printk("%s hw_init err %d\n", openofdm_rx_compatible_str, err);
|
||||
|
||||
|
||||
@ -58,7 +58,7 @@ static struct openofdm_tx_driver_api *openofdm_tx_api = &openofdm_tx_driver_api_
|
||||
EXPORT_SYMBOL(openofdm_tx_api);
|
||||
|
||||
static inline u32 hw_init(enum openofdm_tx_mode mode){
|
||||
int err=0;
|
||||
int err=0, i;
|
||||
|
||||
printk("%s hw_init mode %d\n", openofdm_tx_compatible_str, mode);
|
||||
|
||||
@ -77,13 +77,13 @@ static inline u32 hw_init(enum openofdm_tx_mode mode){
|
||||
err=1;
|
||||
}
|
||||
|
||||
openofdm_tx_api->OPENOFDM_TX_REG_MULTI_RST_write(0xFFFFFFFF);
|
||||
openofdm_tx_api->OPENOFDM_TX_REG_MULTI_RST_write(0xFFFFFFFF);
|
||||
openofdm_tx_api->OPENOFDM_TX_REG_MULTI_RST_write(0xFFFFFFFF);
|
||||
openofdm_tx_api->OPENOFDM_TX_REG_MULTI_RST_write(0xFFFFFFFF);
|
||||
openofdm_tx_api->OPENOFDM_TX_REG_MULTI_RST_write(0xFFFFFFFF);
|
||||
openofdm_tx_api->OPENOFDM_TX_REG_MULTI_RST_write(0xFFFFFFFF);
|
||||
openofdm_tx_api->OPENOFDM_TX_REG_MULTI_RST_write(0);
|
||||
//rst
|
||||
for (i=0;i<8;i++)
|
||||
openofdm_tx_api->OPENOFDM_TX_REG_MULTI_RST_write(0);
|
||||
for (i=0;i<32;i++)
|
||||
openofdm_tx_api->OPENOFDM_TX_REG_MULTI_RST_write(0xFFFFFFFF);
|
||||
for (i=0;i<8;i++)
|
||||
openofdm_tx_api->OPENOFDM_TX_REG_MULTI_RST_write(0);
|
||||
|
||||
openofdm_tx_api->OPENOFDM_TX_REG_INIT_PILOT_STATE_write(0x7E);
|
||||
openofdm_tx_api->OPENOFDM_TX_REG_INIT_DATA_STATE_write(0x7F);
|
||||
|
||||
@ -163,27 +163,25 @@ static const struct of_device_id dev_of_ids[] = {
|
||||
MODULE_DEVICE_TABLE(of, dev_of_ids);
|
||||
|
||||
static struct rx_intf_driver_api rx_intf_driver_api_inst;
|
||||
//EXPORT_SYMBOL(rx_intf_driver_api_inst);
|
||||
static struct rx_intf_driver_api *rx_intf_api = &rx_intf_driver_api_inst;
|
||||
EXPORT_SYMBOL(rx_intf_api);
|
||||
|
||||
static inline u32 hw_init(enum rx_intf_mode mode, u32 num_dma_symbol_to_pl, u32 num_dma_symbol_to_ps){
|
||||
int err=0;
|
||||
int err=0, i;
|
||||
u32 reg_val, mixer_cfg=0, ant_sel=0;
|
||||
|
||||
printk("%s hw_init mode %d\n", rx_intf_compatible_str, mode);
|
||||
|
||||
////rst wifi rx -- slv_reg11[2] is actual rx reset. slv_reg11[0] only reset axi lite of rx
|
||||
//printk("%s hw_init reset wifi rx\n", rx_intf_compatible_str);
|
||||
//rx_intf_api->RX_INTF_REG_RST_START_TO_EXT_write(0);
|
||||
//rx_intf_api->RX_INTF_REG_RST_START_TO_EXT_write(4);
|
||||
//rx_intf_api->RX_INTF_REG_RST_START_TO_EXT_write(0);
|
||||
|
||||
rx_intf_api->RX_INTF_REG_TLAST_TIMEOUT_TOP_write(7000);
|
||||
//rst ddc internal module
|
||||
for (reg_val=0;reg_val<32;reg_val++)
|
||||
|
||||
//rst
|
||||
for (i=0;i<8;i++)
|
||||
rx_intf_api->RX_INTF_REG_MULTI_RST_write(0);
|
||||
for (i=0;i<32;i++)
|
||||
rx_intf_api->RX_INTF_REG_MULTI_RST_write(0xFFFFFFFF);
|
||||
rx_intf_api->RX_INTF_REG_MULTI_RST_write(0);
|
||||
for (i=0;i<8;i++)
|
||||
rx_intf_api->RX_INTF_REG_MULTI_RST_write(0);
|
||||
|
||||
rx_intf_api->RX_INTF_REG_M_AXIS_RST_write(1); // hold M AXIS in reset status. will be released when openwifi_start
|
||||
|
||||
switch(mode)
|
||||
|
||||
923
driver/sdr.c
923
driver/sdr.c
File diff suppressed because it is too large
Load Diff
44
driver/sdr.h
44
driver/sdr.h
@ -26,21 +26,23 @@ struct openwifi_rf_ops {
|
||||
};
|
||||
|
||||
struct openwifi_buffer_descriptor {
|
||||
u32 num_dma_byte;
|
||||
u32 sn;
|
||||
u32 hw_queue_idx;
|
||||
u32 retry_limit;
|
||||
u32 need_ack;
|
||||
// u32 num_dma_byte;
|
||||
// u32 sn;
|
||||
// u32 hw_queue_idx;
|
||||
// u32 retry_limit;
|
||||
// u32 need_ack;
|
||||
struct sk_buff *skb_linked;
|
||||
dma_addr_t dma_mapping_addr;
|
||||
u32 reserved;
|
||||
// u32 reserved;
|
||||
} __packed;
|
||||
|
||||
struct openwifi_ring {
|
||||
struct openwifi_buffer_descriptor *bds;
|
||||
u32 bd_wr_idx;
|
||||
u32 bd_rd_idx;
|
||||
u32 reserved;
|
||||
u32 stop_flag; // track the stop/wake status between tx interrupt and openwifi_tx
|
||||
// u32 num_dma_symbol_request;
|
||||
// u32 reserved;
|
||||
} __packed;
|
||||
|
||||
struct openwifi_vif {
|
||||
@ -62,24 +64,35 @@ union u16_byte2 {
|
||||
u8 c[2];
|
||||
};
|
||||
|
||||
#define MAX_NUM_DRV_REG 32
|
||||
#define MAX_NUM_LED 4
|
||||
#define OPENWIFI_LED_MAX_NAME_LEN 32
|
||||
|
||||
// ------------ software reg definition ------------
|
||||
#define MAX_NUM_DRV_REG 8
|
||||
#define DRV_TX_REG_IDX_RATE 0
|
||||
#define DRV_TX_REG_IDX_FREQ_BW_CFG 1
|
||||
#define DRV_TX_REG_IDX_PRINT_CFG (MAX_NUM_DRV_REG-1)
|
||||
|
||||
#define DRV_RX_REG_IDX_FREQ_BW_CFG 1
|
||||
#define DRV_RX_REG_IDX_PRINT_CFG (MAX_NUM_DRV_REG-1)
|
||||
|
||||
// ------end of software reg definition ------------
|
||||
|
||||
#define MAX_NUM_VIF 4
|
||||
|
||||
#define LEN_PHY_HEADER 16
|
||||
#define LEN_PHY_CRC 4
|
||||
|
||||
#define RING_ROOM_THRESHOLD 4
|
||||
#define NUM_TX_BD 32
|
||||
#define NUM_TX_BD 64 // !!! should align to the fifo size in tx_bit_intf.v
|
||||
#define NUM_RX_BD 16
|
||||
#define TX_BD_BUF_SIZE (8192)
|
||||
#define RX_BD_BUF_SIZE (8192)
|
||||
|
||||
#define NUM_BIT_MAX_NUM_HW_QUEUE 2
|
||||
#define MAX_NUM_HW_QUEUE 2
|
||||
#define NUM_BIT_MAX_PHY_TX_SN 12
|
||||
#define MAX_NUM_HW_QUEUE 4 // number of queue in FPGA
|
||||
#define MAX_NUM_SW_QUEUE 4 // number of queue in Linux, depends on the number we report by dev->queues in openwifi_dev_probe
|
||||
#define NUM_BIT_MAX_PHY_TX_SN 10 // decrease 12 to 10 to reserve 2 bits storing related linux prio idx
|
||||
#define MAX_PHY_TX_SN ((1<<NUM_BIT_MAX_PHY_TX_SN)-1)
|
||||
|
||||
#define AD9361_RADIO_OFF_TX_ATT 89750 //please align with ad9361.c
|
||||
@ -317,20 +330,23 @@ struct openwifi_priv {
|
||||
int irq_rx;
|
||||
int irq_tx;
|
||||
|
||||
// u32 call_counter;
|
||||
u8 *rx_cyclic_buf;
|
||||
dma_addr_t rx_cyclic_buf_dma_mapping_addr;
|
||||
struct dma_chan *rx_chan;
|
||||
struct dma_async_tx_descriptor *rxd;
|
||||
dma_cookie_t rx_cookie;
|
||||
|
||||
struct openwifi_ring tx_ring;
|
||||
struct openwifi_ring tx_ring[MAX_NUM_SW_QUEUE];
|
||||
struct scatterlist tx_sg;
|
||||
struct dma_chan *tx_chan;
|
||||
struct dma_async_tx_descriptor *txd;
|
||||
dma_cookie_t tx_cookie;
|
||||
bool tx_queue_stopped;
|
||||
// struct completion tx_dma_complete;
|
||||
// bool openwifi_tx_first_time_run;
|
||||
|
||||
int phy_tx_sn;
|
||||
// int phy_tx_sn;
|
||||
u32 slice_idx;
|
||||
u32 dest_mac_addr_queue_map[MAX_NUM_HW_QUEUE];
|
||||
u8 mac_addr[ETH_ALEN];
|
||||
u16 seqno;
|
||||
|
||||
@ -78,6 +78,10 @@ static inline u32 TX_INTF_REG_CFG_DATA_TO_ANT_read(void){
|
||||
return reg_read(TX_INTF_REG_CFG_DATA_TO_ANT_ADDR);
|
||||
}
|
||||
|
||||
static inline u32 TX_INTF_REG_S_AXIS_FIFO_TH_read(void){
|
||||
return reg_read(TX_INTF_REG_S_AXIS_FIFO_TH_ADDR);
|
||||
}
|
||||
|
||||
static inline u32 TX_INTF_REG_TX_HOLD_THRESHOLD_read(void){
|
||||
return reg_read(TX_INTF_REG_TX_HOLD_THRESHOLD_ADDR);
|
||||
}
|
||||
@ -94,8 +98,8 @@ static inline u32 TX_INTF_REG_ANT_SEL_read(void){
|
||||
return reg_read(TX_INTF_REG_ANT_SEL_ADDR);
|
||||
}
|
||||
|
||||
static inline u32 TX_INTF_REG_S_AXIS_FIFO_DATA_COUNT_read(void){
|
||||
return reg_read(TX_INTF_REG_S_AXIS_FIFO_DATA_COUNT_ADDR);
|
||||
static inline u32 TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_read(void){
|
||||
return reg_read(TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_ADDR);
|
||||
}
|
||||
|
||||
static inline u32 TX_INTF_REG_PKT_INFO_read(void){
|
||||
@ -152,6 +156,10 @@ static inline void TX_INTF_REG_CFG_DATA_TO_ANT_write(u32 value){
|
||||
reg_write(TX_INTF_REG_CFG_DATA_TO_ANT_ADDR, value);
|
||||
}
|
||||
|
||||
static inline void TX_INTF_REG_S_AXIS_FIFO_TH_write(u32 value){
|
||||
reg_write(TX_INTF_REG_S_AXIS_FIFO_TH_ADDR, value);
|
||||
}
|
||||
|
||||
static inline void TX_INTF_REG_TX_HOLD_THRESHOLD_write(u32 value){
|
||||
reg_write(TX_INTF_REG_TX_HOLD_THRESHOLD_ADDR, value);
|
||||
}
|
||||
@ -168,8 +176,8 @@ static inline void TX_INTF_REG_ANT_SEL_write(u32 value){
|
||||
reg_write(TX_INTF_REG_ANT_SEL_ADDR, value);
|
||||
}
|
||||
|
||||
static inline void TX_INTF_REG_S_AXIS_FIFO_DATA_COUNT_write(u32 value){
|
||||
reg_write(TX_INTF_REG_S_AXIS_FIFO_DATA_COUNT_ADDR, value);
|
||||
static inline void TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_write(u32 value){
|
||||
reg_write(TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_ADDR, value);
|
||||
}
|
||||
|
||||
static inline void TX_INTF_REG_PKT_INFO_write(u32 value){
|
||||
@ -187,16 +195,20 @@ static struct tx_intf_driver_api *tx_intf_api = &tx_intf_driver_api_inst;
|
||||
EXPORT_SYMBOL(tx_intf_api);
|
||||
|
||||
static inline u32 hw_init(enum tx_intf_mode mode, u32 num_dma_symbol_to_pl, u32 num_dma_symbol_to_ps){
|
||||
int err=0;
|
||||
u32 reg_val, mixer_cfg=0, duc_input_ch_sel = 0, ant_sel=0;
|
||||
int err=0, i;
|
||||
u32 mixer_cfg=0, duc_input_ch_sel = 0, ant_sel=0;
|
||||
|
||||
printk("%s hw_init mode %d\n", tx_intf_compatible_str, mode);
|
||||
|
||||
//rst duc internal module
|
||||
for (reg_val=0;reg_val<32;reg_val++)
|
||||
//rst
|
||||
for (i=0;i<8;i++)
|
||||
tx_intf_api->TX_INTF_REG_MULTI_RST_write(0);
|
||||
for (i=0;i<32;i++)
|
||||
tx_intf_api->TX_INTF_REG_MULTI_RST_write(0xFFFFFFFF);
|
||||
tx_intf_api->TX_INTF_REG_MULTI_RST_write(0);
|
||||
for (i=0;i<8;i++)
|
||||
tx_intf_api->TX_INTF_REG_MULTI_RST_write(0);
|
||||
|
||||
tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_TH_write(4096-200); // when only 200 DMA symbol room left in fifo, stop Linux queue
|
||||
switch(mode)
|
||||
{
|
||||
case TX_INTF_AXIS_LOOP_BACK:
|
||||
@ -271,8 +283,8 @@ static inline u32 hw_init(enum tx_intf_mode mode, u32 num_dma_symbol_to_pl, u32
|
||||
tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write(num_dma_symbol_to_ps);
|
||||
tx_intf_api->TX_INTF_REG_CFG_DATA_TO_ANT_write(0);
|
||||
tx_intf_api->TX_INTF_REG_TX_HOLD_THRESHOLD_write(420);
|
||||
tx_intf_api->TX_INTF_REG_INTERRUPT_SEL_write(0x40); //.src_sel0(slv_reg14[2:0]), .src_sel1(slv_reg14[6:4]), 0-s00_axis_tlast,1-ap_start,2-tx_start_from_acc,3-tx_end_from_acc,4-xpu signal
|
||||
tx_intf_api->TX_INTF_REG_INTERRUPT_SEL_write(0x30040); //disable interrupt
|
||||
tx_intf_api->TX_INTF_REG_INTERRUPT_SEL_write(0x4F); //.src_sel0(slv_reg14[2:0]), .src_sel1(slv_reg14[6:4]), 0-s00_axis_tlast,1-ap_start,2-tx_start_from_acc,3-tx_end_from_acc,4-xpu signal
|
||||
tx_intf_api->TX_INTF_REG_INTERRUPT_SEL_write(0x3004F); //disable interrupt
|
||||
tx_intf_api->TX_INTF_REG_BB_GAIN_write(100);
|
||||
tx_intf_api->TX_INTF_REG_ANT_SEL_write(ant_sel);
|
||||
tx_intf_api->TX_INTF_REG_WIFI_TX_MODE_write((1<<3)|(2<<4));
|
||||
@ -325,11 +337,12 @@ static int dev_probe(struct platform_device *pdev)
|
||||
tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read=TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read;
|
||||
tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read=TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read;
|
||||
tx_intf_api->TX_INTF_REG_CFG_DATA_TO_ANT_read=TX_INTF_REG_CFG_DATA_TO_ANT_read;
|
||||
tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_TH_read=TX_INTF_REG_S_AXIS_FIFO_TH_read;
|
||||
tx_intf_api->TX_INTF_REG_TX_HOLD_THRESHOLD_read=TX_INTF_REG_TX_HOLD_THRESHOLD_read;
|
||||
tx_intf_api->TX_INTF_REG_INTERRUPT_SEL_read=TX_INTF_REG_INTERRUPT_SEL_read;
|
||||
tx_intf_api->TX_INTF_REG_BB_GAIN_read=TX_INTF_REG_BB_GAIN_read;
|
||||
tx_intf_api->TX_INTF_REG_ANT_SEL_read=TX_INTF_REG_ANT_SEL_read;
|
||||
tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_DATA_COUNT_read=TX_INTF_REG_S_AXIS_FIFO_DATA_COUNT_read;
|
||||
tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_read=TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_read;
|
||||
tx_intf_api->TX_INTF_REG_PKT_INFO_read=TX_INTF_REG_PKT_INFO_read;
|
||||
tx_intf_api->TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_read=TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_read;
|
||||
|
||||
@ -344,11 +357,12 @@ static int dev_probe(struct platform_device *pdev)
|
||||
tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write=TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write;
|
||||
tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write=TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write;
|
||||
tx_intf_api->TX_INTF_REG_CFG_DATA_TO_ANT_write=TX_INTF_REG_CFG_DATA_TO_ANT_write;
|
||||
tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_TH_write=TX_INTF_REG_S_AXIS_FIFO_TH_write;
|
||||
tx_intf_api->TX_INTF_REG_TX_HOLD_THRESHOLD_write=TX_INTF_REG_TX_HOLD_THRESHOLD_write;
|
||||
tx_intf_api->TX_INTF_REG_INTERRUPT_SEL_write=TX_INTF_REG_INTERRUPT_SEL_write;
|
||||
tx_intf_api->TX_INTF_REG_BB_GAIN_write=TX_INTF_REG_BB_GAIN_write;
|
||||
tx_intf_api->TX_INTF_REG_ANT_SEL_write=TX_INTF_REG_ANT_SEL_write;
|
||||
tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_DATA_COUNT_write=TX_INTF_REG_S_AXIS_FIFO_DATA_COUNT_write;
|
||||
tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_write=TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_write;
|
||||
tx_intf_api->TX_INTF_REG_PKT_INFO_write=TX_INTF_REG_PKT_INFO_write;
|
||||
|
||||
/* Request and map I/O memory */
|
||||
|
||||
113
driver/xpu/xpu.c
113
driver/xpu/xpu.c
@ -222,44 +222,28 @@ static inline u32 XPU_REG_CSMA_CFG_read(void){
|
||||
return reg_read(XPU_REG_CSMA_CFG_ADDR);
|
||||
}
|
||||
|
||||
static inline void XPU_REG_SLICE_COUNT_TOTAL0_write(u32 value){
|
||||
reg_write(XPU_REG_SLICE_COUNT_TOTAL0_ADDR, value);
|
||||
static inline void XPU_REG_SLICE_COUNT_TOTAL_write(u32 value){
|
||||
reg_write(XPU_REG_SLICE_COUNT_TOTAL_ADDR, value);
|
||||
}
|
||||
static inline void XPU_REG_SLICE_COUNT_START0_write(u32 value){
|
||||
reg_write(XPU_REG_SLICE_COUNT_START0_ADDR, value);
|
||||
static inline void XPU_REG_SLICE_COUNT_START_write(u32 value){
|
||||
reg_write(XPU_REG_SLICE_COUNT_START_ADDR, value);
|
||||
}
|
||||
static inline void XPU_REG_SLICE_COUNT_END0_write(u32 value){
|
||||
reg_write(XPU_REG_SLICE_COUNT_END0_ADDR, value);
|
||||
}
|
||||
static inline void XPU_REG_SLICE_COUNT_TOTAL1_write(u32 value){
|
||||
reg_write(XPU_REG_SLICE_COUNT_TOTAL1_ADDR, value);
|
||||
}
|
||||
static inline void XPU_REG_SLICE_COUNT_START1_write(u32 value){
|
||||
reg_write(XPU_REG_SLICE_COUNT_START1_ADDR, value);
|
||||
}
|
||||
static inline void XPU_REG_SLICE_COUNT_END1_write(u32 value){
|
||||
reg_write(XPU_REG_SLICE_COUNT_END1_ADDR, value);
|
||||
static inline void XPU_REG_SLICE_COUNT_END_write(u32 value){
|
||||
reg_write(XPU_REG_SLICE_COUNT_END_ADDR, value);
|
||||
}
|
||||
|
||||
static inline u32 XPU_REG_SLICE_COUNT_TOTAL0_read(void){
|
||||
return reg_read(XPU_REG_SLICE_COUNT_TOTAL0_ADDR);
|
||||
|
||||
static inline u32 XPU_REG_SLICE_COUNT_TOTAL_read(void){
|
||||
return reg_read(XPU_REG_SLICE_COUNT_TOTAL_ADDR);
|
||||
}
|
||||
static inline u32 XPU_REG_SLICE_COUNT_START0_read(void){
|
||||
return reg_read(XPU_REG_SLICE_COUNT_START0_ADDR);
|
||||
static inline u32 XPU_REG_SLICE_COUNT_START_read(void){
|
||||
return reg_read(XPU_REG_SLICE_COUNT_START_ADDR);
|
||||
}
|
||||
static inline u32 XPU_REG_SLICE_COUNT_END0_read(void){
|
||||
return reg_read(XPU_REG_SLICE_COUNT_END0_ADDR);
|
||||
}
|
||||
static inline u32 XPU_REG_SLICE_COUNT_TOTAL1_read(void){
|
||||
return reg_read(XPU_REG_SLICE_COUNT_TOTAL1_ADDR);
|
||||
}
|
||||
static inline u32 XPU_REG_SLICE_COUNT_START1_read(void){
|
||||
return reg_read(XPU_REG_SLICE_COUNT_START1_ADDR);
|
||||
}
|
||||
static inline u32 XPU_REG_SLICE_COUNT_END1_read(void){
|
||||
return reg_read(XPU_REG_SLICE_COUNT_END1_ADDR);
|
||||
static inline u32 XPU_REG_SLICE_COUNT_END_read(void){
|
||||
return reg_read(XPU_REG_SLICE_COUNT_END_ADDR);
|
||||
}
|
||||
|
||||
|
||||
static inline void XPU_REG_BB_RF_DELAY_write(u32 value){
|
||||
reg_write(XPU_REG_BB_RF_DELAY_ADDR, value);
|
||||
}
|
||||
@ -291,16 +275,18 @@ static struct xpu_driver_api *xpu_api = &xpu_driver_api_inst;
|
||||
EXPORT_SYMBOL(xpu_api);
|
||||
|
||||
static inline u32 hw_init(enum xpu_mode mode){
|
||||
int err=0, rssi_half_db_th, rssi_half_db_offset, agc_gain_delay;
|
||||
u32 reg_val;
|
||||
int err=0, i, rssi_half_db_th, rssi_half_db_offset, agc_gain_delay;
|
||||
u32 filter_flag = 0;
|
||||
|
||||
printk("%s hw_init mode %d\n", xpu_compatible_str, mode);
|
||||
|
||||
//rst internal module
|
||||
for (reg_val=0;reg_val<32;reg_val++)
|
||||
//rst
|
||||
for (i=0;i<8;i++)
|
||||
xpu_api->XPU_REG_MULTI_RST_write(0);
|
||||
for (i=0;i<32;i++)
|
||||
xpu_api->XPU_REG_MULTI_RST_write(0xFFFFFFFF);
|
||||
xpu_api->XPU_REG_MULTI_RST_write(0);
|
||||
for (i=0;i<8;i++)
|
||||
xpu_api->XPU_REG_MULTI_RST_write(0);
|
||||
|
||||
// http://www.studioreti.it/slide/802-11-Frame_E_C.pdf
|
||||
// https://mrncciew.com/2014/10/14/cwap-802-11-phy-ppdu/
|
||||
@ -339,9 +325,6 @@ static inline u32 hw_init(enum xpu_mode mode){
|
||||
xpu_api->XPU_REG_FILTER_FLAG_write(filter_flag);
|
||||
xpu_api->XPU_REG_CTS_TO_RTS_CONFIG_write(0xB<<16);//6M 1011:0xB
|
||||
|
||||
////set up FC type filter for packet needs ACK -- no use, FPGA handle by itself
|
||||
//xpu_api->XPU_REG_ACK_FC_FILTER_write((3<<(2+16))|(2<<2)); // low 16 bits target FC 16 bits; high 16 bits -- mask
|
||||
|
||||
// after send data frame wait for ACK, this will be set in real time in function ad9361_rf_set_channel
|
||||
// xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_write( (((51+2)*10)<<16) | 10 ); // high 16 bits to cover sig valid of ACK packet, low 16 bits is adjustment of fcs valid waiting time. let's add 2us for those device that is really "slow"!
|
||||
// xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( 6*10 ); // +6 = 16us for 5GHz
|
||||
@ -350,13 +333,36 @@ static inline u32 hw_init(enum xpu_mode mode){
|
||||
|
||||
xpu_api->XPU_REG_BB_RF_DELAY_write(49);
|
||||
|
||||
xpu_api->XPU_REG_SLICE_COUNT_TOTAL0_write(50000-1); // total 50ms
|
||||
xpu_api->XPU_REG_SLICE_COUNT_START0_write(0); //start 0ms
|
||||
xpu_api->XPU_REG_SLICE_COUNT_END0_write(50000-1); //end 10ms
|
||||
xpu_api->XPU_REG_SLICE_COUNT_TOTAL1_write(50000-1); // total 50ms
|
||||
xpu_api->XPU_REG_SLICE_COUNT_START1_write(0000); //start 0ms
|
||||
xpu_api->XPU_REG_SLICE_COUNT_END1_write(1000-1); //end 1ms
|
||||
// setup time schedule of 4 slices
|
||||
// slice 0
|
||||
xpu_api->XPU_REG_SLICE_COUNT_TOTAL_write(50000-1); // total 50ms
|
||||
xpu_api->XPU_REG_SLICE_COUNT_START_write(0); //start 0ms
|
||||
xpu_api->XPU_REG_SLICE_COUNT_END_write(50000-1); //end 50ms
|
||||
|
||||
// slice 1
|
||||
xpu_api->XPU_REG_SLICE_COUNT_TOTAL_write((1<<20)|(50000-1)); // total 50ms
|
||||
xpu_api->XPU_REG_SLICE_COUNT_START_write((1<<20)|(0)); //start 0ms
|
||||
//xpu_api->XPU_REG_SLICE_COUNT_END_write((1<<20)|(20000-1)); //end 20ms
|
||||
xpu_api->XPU_REG_SLICE_COUNT_END_write((1<<20)|(50000-1)); //end 20ms
|
||||
|
||||
// slice 2
|
||||
xpu_api->XPU_REG_SLICE_COUNT_TOTAL_write((2<<20)|(50000-1)); // total 50ms
|
||||
//xpu_api->XPU_REG_SLICE_COUNT_START_write((2<<20)|(20000)); //start 20ms
|
||||
xpu_api->XPU_REG_SLICE_COUNT_START_write((2<<20)|(0)); //start 20ms
|
||||
//xpu_api->XPU_REG_SLICE_COUNT_END_write((2<<20)|(40000-1)); //end 20ms
|
||||
xpu_api->XPU_REG_SLICE_COUNT_END_write((2<<20)|(50000-1)); //end 20ms
|
||||
|
||||
// slice 3
|
||||
xpu_api->XPU_REG_SLICE_COUNT_TOTAL_write((3<<20)|(50000-1)); // total 50ms
|
||||
//xpu_api->XPU_REG_SLICE_COUNT_START_write((3<<20)|(40000)); //start 40ms
|
||||
xpu_api->XPU_REG_SLICE_COUNT_START_write((3<<20)|(0)); //start 40ms
|
||||
//xpu_api->XPU_REG_SLICE_COUNT_END_write((3<<20)|(50000-1)); //end 20ms
|
||||
xpu_api->XPU_REG_SLICE_COUNT_END_write((3<<20)|(50000-1)); //end 20ms
|
||||
|
||||
// all slice sync rest
|
||||
xpu_api->XPU_REG_MULTI_RST_write(1<<7); //bit7 reset the counter for all queues at the same time
|
||||
xpu_api->XPU_REG_MULTI_RST_write(0<<7);
|
||||
|
||||
switch(mode)
|
||||
{
|
||||
case XPU_TEST:
|
||||
@ -388,7 +394,6 @@ static inline u32 hw_init(enum xpu_mode mode){
|
||||
//xpu_api->XPU_REG_CSMA_CFG_write(3); //normal CSMA
|
||||
xpu_api->XPU_REG_CSMA_CFG_write(0xe0000000); //high priority
|
||||
|
||||
// xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( ((40)<<16)|0 );//high 16bit 5GHz; low 16 bit 2.4GHz (Attention, current tx core has around 1.19us starting delay that makes the ack fall behind 10us SIFS in 2.4GHz! Need to improve TX in 2.4GHz!)
|
||||
xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( ((51)<<16)|0 );//now our tx send out I/Q immediately
|
||||
|
||||
xpu_api->XPU_REG_RECV_ACK_COUNT_TOP0_write( (((45+2+2)*10 + 15)<<16) | 10 );//2.4GHz. extra 300 clocks are needed when rx core fall into fake ht detection phase (rx mcs 6M)
|
||||
@ -480,19 +485,13 @@ static int dev_probe(struct platform_device *pdev)
|
||||
xpu_api->XPU_REG_CSMA_CFG_write=XPU_REG_CSMA_CFG_write;
|
||||
xpu_api->XPU_REG_CSMA_CFG_read=XPU_REG_CSMA_CFG_read;
|
||||
|
||||
xpu_api->XPU_REG_SLICE_COUNT_TOTAL0_write=XPU_REG_SLICE_COUNT_TOTAL0_write;
|
||||
xpu_api->XPU_REG_SLICE_COUNT_START0_write=XPU_REG_SLICE_COUNT_START0_write;
|
||||
xpu_api->XPU_REG_SLICE_COUNT_END0_write=XPU_REG_SLICE_COUNT_END0_write;
|
||||
xpu_api->XPU_REG_SLICE_COUNT_TOTAL1_write=XPU_REG_SLICE_COUNT_TOTAL1_write;
|
||||
xpu_api->XPU_REG_SLICE_COUNT_START1_write=XPU_REG_SLICE_COUNT_START1_write;
|
||||
xpu_api->XPU_REG_SLICE_COUNT_END1_write=XPU_REG_SLICE_COUNT_END1_write;
|
||||
xpu_api->XPU_REG_SLICE_COUNT_TOTAL_write=XPU_REG_SLICE_COUNT_TOTAL_write;
|
||||
xpu_api->XPU_REG_SLICE_COUNT_START_write=XPU_REG_SLICE_COUNT_START_write;
|
||||
xpu_api->XPU_REG_SLICE_COUNT_END_write=XPU_REG_SLICE_COUNT_END_write;
|
||||
|
||||
xpu_api->XPU_REG_SLICE_COUNT_TOTAL0_read=XPU_REG_SLICE_COUNT_TOTAL0_read;
|
||||
xpu_api->XPU_REG_SLICE_COUNT_START0_read=XPU_REG_SLICE_COUNT_START0_read;
|
||||
xpu_api->XPU_REG_SLICE_COUNT_END0_read=XPU_REG_SLICE_COUNT_END0_read;
|
||||
xpu_api->XPU_REG_SLICE_COUNT_TOTAL1_read=XPU_REG_SLICE_COUNT_TOTAL1_read;
|
||||
xpu_api->XPU_REG_SLICE_COUNT_START1_read=XPU_REG_SLICE_COUNT_START1_read;
|
||||
xpu_api->XPU_REG_SLICE_COUNT_END1_read=XPU_REG_SLICE_COUNT_END1_read;
|
||||
xpu_api->XPU_REG_SLICE_COUNT_TOTAL_read=XPU_REG_SLICE_COUNT_TOTAL_read;
|
||||
xpu_api->XPU_REG_SLICE_COUNT_START_read=XPU_REG_SLICE_COUNT_START_read;
|
||||
xpu_api->XPU_REG_SLICE_COUNT_END_read=XPU_REG_SLICE_COUNT_END_read;
|
||||
|
||||
xpu_api->XPU_REG_BB_RF_DELAY_write=XPU_REG_BB_RF_DELAY_write;
|
||||
xpu_api->XPU_REG_MAX_NUM_RETRANS_write=XPU_REG_MAX_NUM_RETRANS_write;
|
||||
|
||||
@ -305,11 +305,12 @@ static int handle_get_rssi_th(struct nl80211_state *state,
|
||||
}
|
||||
COMMAND(get, rssi_th, "<rssi_th in value>", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_get_rssi_th, "get rssi_th");
|
||||
|
||||
static int cb_openwifi_slice_total0_handler(struct nl_msg *msg, void *arg)
|
||||
static int cb_openwifi_slice_total_handler(struct nl_msg *msg, void *arg)
|
||||
{
|
||||
struct nlattr *attrs[NL80211_ATTR_MAX + 1];
|
||||
struct nlattr *tb[OPENWIFI_ATTR_MAX + 1];
|
||||
struct genlmsghdr *gnlh = nlmsg_data(nlmsg_hdr(msg));
|
||||
unsigned int tmp;
|
||||
|
||||
nla_parse(attrs, NL80211_ATTR_MAX, genlmsg_attrdata(gnlh, 0), genlmsg_attrlen(gnlh, 0), NULL);
|
||||
|
||||
@ -318,12 +319,13 @@ static int cb_openwifi_slice_total0_handler(struct nl_msg *msg, void *arg)
|
||||
|
||||
nla_parse(tb, OPENWIFI_ATTR_MAX, nla_data(attrs[NL80211_ATTR_TESTDATA]), nla_len(attrs[NL80211_ATTR_TESTDATA]), NULL);
|
||||
|
||||
printf("openwifi slice_total0 (duration): %dus\n", nla_get_u32(tb[OPENWIFI_ATTR_SLICE_TOTAL0]));
|
||||
tmp = nla_get_u32(tb[OPENWIFI_ATTR_SLICE_TOTAL]);
|
||||
printf("openwifi slice_total (duration) %dus of slice %d\n", tmp&0xFFFFF, tmp>>20);
|
||||
|
||||
return NL_SKIP;
|
||||
}
|
||||
|
||||
static int handle_set_slice_total0(struct nl80211_state *state,
|
||||
static int handle_set_slice_total(struct nl80211_state *state,
|
||||
struct nl_cb *cb,
|
||||
struct nl_msg *msg,
|
||||
int argc, char **argv,
|
||||
@ -344,21 +346,21 @@ static int handle_set_slice_total0(struct nl80211_state *state,
|
||||
return 1;
|
||||
}
|
||||
|
||||
NLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_SET_SLICE_TOTAL0);
|
||||
NLA_PUT_U32(msg, OPENWIFI_ATTR_SLICE_TOTAL0, tmp);
|
||||
NLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_SET_SLICE_TOTAL);
|
||||
NLA_PUT_U32(msg, OPENWIFI_ATTR_SLICE_TOTAL, tmp);
|
||||
|
||||
nla_nest_end(msg, tmdata);
|
||||
|
||||
printf("openwifi slice_total0 (duration): %dus\n", tmp);
|
||||
printf("openwifi slice_total (duration): %dus\n", tmp);
|
||||
|
||||
return 0;
|
||||
|
||||
nla_put_failure:
|
||||
return -ENOBUFS;
|
||||
}
|
||||
COMMAND(set, slice_total0, "<slice_total0(duration) in us>", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_set_slice_total0, "set slice_total0");
|
||||
COMMAND(set, slice_total, "<slice_total(duration) in us>", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_set_slice_total, "set slice_total");
|
||||
|
||||
static int handle_get_slice_total0(struct nl80211_state *state,
|
||||
static int handle_get_slice_total(struct nl80211_state *state,
|
||||
struct nl_cb *cb,
|
||||
struct nl_msg *msg,
|
||||
int argc, char **argv,
|
||||
@ -370,24 +372,102 @@ static int handle_get_slice_total0(struct nl80211_state *state,
|
||||
if (!tmdata)
|
||||
return 1;
|
||||
|
||||
NLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_GET_SLICE_TOTAL0);
|
||||
NLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_GET_SLICE_TOTAL);
|
||||
|
||||
nla_nest_end(msg, tmdata);
|
||||
|
||||
nl_cb_set(cb, NL_CB_VALID, NL_CB_CUSTOM, cb_openwifi_slice_total0_handler, NULL);
|
||||
nl_cb_set(cb, NL_CB_VALID, NL_CB_CUSTOM, cb_openwifi_slice_total_handler, NULL);
|
||||
return 0;
|
||||
|
||||
nla_put_failure:
|
||||
return -ENOBUFS;
|
||||
}
|
||||
COMMAND(get, slice_total0, "<slice_total0(duration) in us>", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_get_slice_total0, "get slice_total0");
|
||||
COMMAND(get, slice_total, "<slice_total(duration) in us>", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_get_slice_total, "get slice_total");
|
||||
|
||||
|
||||
static int cb_openwifi_slice_total1_handler(struct nl_msg *msg, void *arg)
|
||||
// static int cb_openwifi_slice_total1_handler(struct nl_msg *msg, void *arg)
|
||||
// {
|
||||
// struct nlattr *attrs[NL80211_ATTR_MAX + 1];
|
||||
// struct nlattr *tb[OPENWIFI_ATTR_MAX + 1];
|
||||
// struct genlmsghdr *gnlh = nlmsg_data(nlmsg_hdr(msg));
|
||||
|
||||
// nla_parse(attrs, NL80211_ATTR_MAX, genlmsg_attrdata(gnlh, 0), genlmsg_attrlen(gnlh, 0), NULL);
|
||||
|
||||
// if (!attrs[NL80211_ATTR_TESTDATA])
|
||||
// return NL_SKIP;
|
||||
|
||||
// nla_parse(tb, OPENWIFI_ATTR_MAX, nla_data(attrs[NL80211_ATTR_TESTDATA]), nla_len(attrs[NL80211_ATTR_TESTDATA]), NULL);
|
||||
|
||||
// printf("openwifi slice_total1 (duration): %dus\n", nla_get_u32(tb[OPENWIFI_ATTR_SLICE_TOTAL1]));
|
||||
|
||||
// return NL_SKIP;
|
||||
// }
|
||||
|
||||
// static int handle_set_slice_total1(struct nl80211_state *state,
|
||||
// struct nl_cb *cb,
|
||||
// struct nl_msg *msg,
|
||||
// int argc, char **argv,
|
||||
// enum id_input id)
|
||||
// {
|
||||
// struct nlattr *tmdata;
|
||||
// char *end;
|
||||
// unsigned int tmp;
|
||||
|
||||
// tmdata = nla_nest_start(msg, NL80211_ATTR_TESTDATA);
|
||||
// if (!tmdata) {
|
||||
// return 1;
|
||||
// }
|
||||
|
||||
// tmp = strtoul(argv[0], &end, 10);
|
||||
|
||||
// if (*end) {
|
||||
// return 1;
|
||||
// }
|
||||
|
||||
// NLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_SET_SLICE_TOTAL1);
|
||||
// NLA_PUT_U32(msg, OPENWIFI_ATTR_SLICE_TOTAL1, tmp);
|
||||
|
||||
// nla_nest_end(msg, tmdata);
|
||||
|
||||
// printf("openwifi slice_total1 (duration): %dus\n", tmp);
|
||||
|
||||
// return 0;
|
||||
|
||||
// nla_put_failure:
|
||||
// return -ENOBUFS;
|
||||
// }
|
||||
// COMMAND(set, slice_total1, "<slice_total1(duration) in us>", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_set_slice_total1, "set slice_total1");
|
||||
|
||||
// static int handle_get_slice_total1(struct nl80211_state *state,
|
||||
// struct nl_cb *cb,
|
||||
// struct nl_msg *msg,
|
||||
// int argc, char **argv,
|
||||
// enum id_input id)
|
||||
// {
|
||||
// struct nlattr *tmdata;
|
||||
|
||||
// tmdata = nla_nest_start(msg, NL80211_ATTR_TESTDATA);
|
||||
// if (!tmdata)
|
||||
// return 1;
|
||||
|
||||
// NLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_GET_SLICE_TOTAL1);
|
||||
|
||||
// nla_nest_end(msg, tmdata);
|
||||
|
||||
// nl_cb_set(cb, NL_CB_VALID, NL_CB_CUSTOM, cb_openwifi_slice_total1_handler, NULL);
|
||||
// return 0;
|
||||
|
||||
// nla_put_failure:
|
||||
// return -ENOBUFS;
|
||||
// }
|
||||
// COMMAND(get, slice_total1, "<slice_total1(duration) in us>", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_get_slice_total1, "get slice_total1");
|
||||
|
||||
static int cb_openwifi_slice_start_handler(struct nl_msg *msg, void *arg)
|
||||
{
|
||||
struct nlattr *attrs[NL80211_ATTR_MAX + 1];
|
||||
struct nlattr *tb[OPENWIFI_ATTR_MAX + 1];
|
||||
struct genlmsghdr *gnlh = nlmsg_data(nlmsg_hdr(msg));
|
||||
unsigned int tmp;
|
||||
|
||||
nla_parse(attrs, NL80211_ATTR_MAX, genlmsg_attrdata(gnlh, 0), genlmsg_attrlen(gnlh, 0), NULL);
|
||||
|
||||
@ -396,12 +476,13 @@ static int cb_openwifi_slice_total1_handler(struct nl_msg *msg, void *arg)
|
||||
|
||||
nla_parse(tb, OPENWIFI_ATTR_MAX, nla_data(attrs[NL80211_ATTR_TESTDATA]), nla_len(attrs[NL80211_ATTR_TESTDATA]), NULL);
|
||||
|
||||
printf("openwifi slice_total1 (duration): %dus\n", nla_get_u32(tb[OPENWIFI_ATTR_SLICE_TOTAL1]));
|
||||
tmp = nla_get_u32(tb[OPENWIFI_ATTR_SLICE_START]);
|
||||
printf("openwifi slice_start (duration) %dus of slice %d\n", tmp&0xFFFFF, tmp>>20);
|
||||
|
||||
return NL_SKIP;
|
||||
}
|
||||
|
||||
static int handle_set_slice_total1(struct nl80211_state *state,
|
||||
static int handle_set_slice_start(struct nl80211_state *state,
|
||||
struct nl_cb *cb,
|
||||
struct nl_msg *msg,
|
||||
int argc, char **argv,
|
||||
@ -422,21 +503,21 @@ static int handle_set_slice_total1(struct nl80211_state *state,
|
||||
return 1;
|
||||
}
|
||||
|
||||
NLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_SET_SLICE_TOTAL1);
|
||||
NLA_PUT_U32(msg, OPENWIFI_ATTR_SLICE_TOTAL1, tmp);
|
||||
NLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_SET_SLICE_START);
|
||||
NLA_PUT_U32(msg, OPENWIFI_ATTR_SLICE_START, tmp);
|
||||
|
||||
nla_nest_end(msg, tmdata);
|
||||
|
||||
printf("openwifi slice_total1 (duration): %dus\n", tmp);
|
||||
printf("openwifi slice_start (duration): %dus\n", tmp);
|
||||
|
||||
return 0;
|
||||
|
||||
nla_put_failure:
|
||||
return -ENOBUFS;
|
||||
}
|
||||
COMMAND(set, slice_total1, "<slice_total1(duration) in us>", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_set_slice_total1, "set slice_total1");
|
||||
COMMAND(set, slice_start, "<slice_start(duration) in us>", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_set_slice_start, "set slice_start");
|
||||
|
||||
static int handle_get_slice_total1(struct nl80211_state *state,
|
||||
static int handle_get_slice_start(struct nl80211_state *state,
|
||||
struct nl_cb *cb,
|
||||
struct nl_msg *msg,
|
||||
int argc, char **argv,
|
||||
@ -448,24 +529,103 @@ static int handle_get_slice_total1(struct nl80211_state *state,
|
||||
if (!tmdata)
|
||||
return 1;
|
||||
|
||||
NLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_GET_SLICE_TOTAL1);
|
||||
NLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_GET_SLICE_START);
|
||||
|
||||
nla_nest_end(msg, tmdata);
|
||||
|
||||
nl_cb_set(cb, NL_CB_VALID, NL_CB_CUSTOM, cb_openwifi_slice_total1_handler, NULL);
|
||||
nl_cb_set(cb, NL_CB_VALID, NL_CB_CUSTOM, cb_openwifi_slice_start_handler, NULL);
|
||||
return 0;
|
||||
|
||||
nla_put_failure:
|
||||
return -ENOBUFS;
|
||||
}
|
||||
COMMAND(get, slice_total1, "<slice_total1(duration) in us>", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_get_slice_total1, "get slice_total1");
|
||||
COMMAND(get, slice_start, "<slice_start(duration) in us>", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_get_slice_start, "get slice_start");
|
||||
|
||||
|
||||
static int cb_openwifi_slice_start0_handler(struct nl_msg *msg, void *arg)
|
||||
// static int cb_openwifi_slice_start1_handler(struct nl_msg *msg, void *arg)
|
||||
// {
|
||||
// struct nlattr *attrs[NL80211_ATTR_MAX + 1];
|
||||
// struct nlattr *tb[OPENWIFI_ATTR_MAX + 1];
|
||||
// struct genlmsghdr *gnlh = nlmsg_data(nlmsg_hdr(msg));
|
||||
|
||||
// nla_parse(attrs, NL80211_ATTR_MAX, genlmsg_attrdata(gnlh, 0), genlmsg_attrlen(gnlh, 0), NULL);
|
||||
|
||||
// if (!attrs[NL80211_ATTR_TESTDATA])
|
||||
// return NL_SKIP;
|
||||
|
||||
// nla_parse(tb, OPENWIFI_ATTR_MAX, nla_data(attrs[NL80211_ATTR_TESTDATA]), nla_len(attrs[NL80211_ATTR_TESTDATA]), NULL);
|
||||
|
||||
// printf("openwifi slice_start1 (duration): %dus\n", nla_get_u32(tb[OPENWIFI_ATTR_SLICE_START1]));
|
||||
|
||||
// return NL_SKIP;
|
||||
// }
|
||||
|
||||
// static int handle_set_slice_start1(struct nl80211_state *state,
|
||||
// struct nl_cb *cb,
|
||||
// struct nl_msg *msg,
|
||||
// int argc, char **argv,
|
||||
// enum id_input id)
|
||||
// {
|
||||
// struct nlattr *tmdata;
|
||||
// char *end;
|
||||
// unsigned int tmp;
|
||||
|
||||
// tmdata = nla_nest_start(msg, NL80211_ATTR_TESTDATA);
|
||||
// if (!tmdata) {
|
||||
// return 1;
|
||||
// }
|
||||
|
||||
// tmp = strtoul(argv[0], &end, 10);
|
||||
|
||||
// if (*end) {
|
||||
// return 1;
|
||||
// }
|
||||
|
||||
// NLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_SET_SLICE_START1);
|
||||
// NLA_PUT_U32(msg, OPENWIFI_ATTR_SLICE_START1, tmp);
|
||||
|
||||
// nla_nest_end(msg, tmdata);
|
||||
|
||||
// printf("openwifi slice_start1 (duration): %dus\n", tmp);
|
||||
|
||||
// return 0;
|
||||
|
||||
// nla_put_failure:
|
||||
// return -ENOBUFS;
|
||||
// }
|
||||
// COMMAND(set, slice_start1, "<slice_start1(duration) in us>", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_set_slice_start1, "set slice_start1");
|
||||
|
||||
// static int handle_get_slice_start1(struct nl80211_state *state,
|
||||
// struct nl_cb *cb,
|
||||
// struct nl_msg *msg,
|
||||
// int argc, char **argv,
|
||||
// enum id_input id)
|
||||
// {
|
||||
// struct nlattr *tmdata;
|
||||
|
||||
// tmdata = nla_nest_start(msg, NL80211_ATTR_TESTDATA);
|
||||
// if (!tmdata)
|
||||
// return 1;
|
||||
|
||||
// NLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_GET_SLICE_START1);
|
||||
|
||||
// nla_nest_end(msg, tmdata);
|
||||
|
||||
// nl_cb_set(cb, NL_CB_VALID, NL_CB_CUSTOM, cb_openwifi_slice_start1_handler, NULL);
|
||||
// return 0;
|
||||
|
||||
// nla_put_failure:
|
||||
// return -ENOBUFS;
|
||||
// }
|
||||
// COMMAND(get, slice_start1, "<slice_start1(duration) in us>", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_get_slice_start1, "get slice_start1");
|
||||
|
||||
|
||||
static int cb_openwifi_slice_end_handler(struct nl_msg *msg, void *arg)
|
||||
{
|
||||
struct nlattr *attrs[NL80211_ATTR_MAX + 1];
|
||||
struct nlattr *tb[OPENWIFI_ATTR_MAX + 1];
|
||||
struct genlmsghdr *gnlh = nlmsg_data(nlmsg_hdr(msg));
|
||||
unsigned int tmp;
|
||||
|
||||
nla_parse(attrs, NL80211_ATTR_MAX, genlmsg_attrdata(gnlh, 0), genlmsg_attrlen(gnlh, 0), NULL);
|
||||
|
||||
@ -474,12 +634,13 @@ static int cb_openwifi_slice_start0_handler(struct nl_msg *msg, void *arg)
|
||||
|
||||
nla_parse(tb, OPENWIFI_ATTR_MAX, nla_data(attrs[NL80211_ATTR_TESTDATA]), nla_len(attrs[NL80211_ATTR_TESTDATA]), NULL);
|
||||
|
||||
printf("openwifi slice_start0 (duration): %dus\n", nla_get_u32(tb[OPENWIFI_ATTR_SLICE_START0]));
|
||||
tmp = nla_get_u32(tb[OPENWIFI_ATTR_SLICE_END]);
|
||||
printf("openwifi slice_end (duration) %dus of slice %d\n", tmp&0xFFFFF, tmp>>20);
|
||||
|
||||
return NL_SKIP;
|
||||
}
|
||||
|
||||
static int handle_set_slice_start0(struct nl80211_state *state,
|
||||
static int handle_set_slice_end(struct nl80211_state *state,
|
||||
struct nl_cb *cb,
|
||||
struct nl_msg *msg,
|
||||
int argc, char **argv,
|
||||
@ -500,21 +661,21 @@ static int handle_set_slice_start0(struct nl80211_state *state,
|
||||
return 1;
|
||||
}
|
||||
|
||||
NLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_SET_SLICE_START0);
|
||||
NLA_PUT_U32(msg, OPENWIFI_ATTR_SLICE_START0, tmp);
|
||||
NLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_SET_SLICE_END);
|
||||
NLA_PUT_U32(msg, OPENWIFI_ATTR_SLICE_END, tmp);
|
||||
|
||||
nla_nest_end(msg, tmdata);
|
||||
|
||||
printf("openwifi slice_start0 (duration): %dus\n", tmp);
|
||||
printf("openwifi slice_end (duration): %dus\n", tmp);
|
||||
|
||||
return 0;
|
||||
|
||||
nla_put_failure:
|
||||
return -ENOBUFS;
|
||||
}
|
||||
COMMAND(set, slice_start0, "<slice_start0(duration) in us>", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_set_slice_start0, "set slice_start0");
|
||||
COMMAND(set, slice_end, "<slice_end(duration) in us>", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_set_slice_end, "set slice_end");
|
||||
|
||||
static int handle_get_slice_start0(struct nl80211_state *state,
|
||||
static int handle_get_slice_end(struct nl80211_state *state,
|
||||
struct nl_cb *cb,
|
||||
struct nl_msg *msg,
|
||||
int argc, char **argv,
|
||||
@ -526,20 +687,98 @@ static int handle_get_slice_start0(struct nl80211_state *state,
|
||||
if (!tmdata)
|
||||
return 1;
|
||||
|
||||
NLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_GET_SLICE_START0);
|
||||
NLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_GET_SLICE_END);
|
||||
|
||||
nla_nest_end(msg, tmdata);
|
||||
|
||||
nl_cb_set(cb, NL_CB_VALID, NL_CB_CUSTOM, cb_openwifi_slice_start0_handler, NULL);
|
||||
nl_cb_set(cb, NL_CB_VALID, NL_CB_CUSTOM, cb_openwifi_slice_end_handler, NULL);
|
||||
return 0;
|
||||
|
||||
nla_put_failure:
|
||||
return -ENOBUFS;
|
||||
}
|
||||
COMMAND(get, slice_start0, "<slice_start0(duration) in us>", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_get_slice_start0, "get slice_start0");
|
||||
COMMAND(get, slice_end, "<slice_end(duration) in us>", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_get_slice_end, "get slice_end");
|
||||
|
||||
|
||||
static int cb_openwifi_slice_start1_handler(struct nl_msg *msg, void *arg)
|
||||
// static int cb_openwifi_slice_end1_handler(struct nl_msg *msg, void *arg)
|
||||
// {
|
||||
// struct nlattr *attrs[NL80211_ATTR_MAX + 1];
|
||||
// struct nlattr *tb[OPENWIFI_ATTR_MAX + 1];
|
||||
// struct genlmsghdr *gnlh = nlmsg_data(nlmsg_hdr(msg));
|
||||
|
||||
// nla_parse(attrs, NL80211_ATTR_MAX, genlmsg_attrdata(gnlh, 0), genlmsg_attrlen(gnlh, 0), NULL);
|
||||
|
||||
// if (!attrs[NL80211_ATTR_TESTDATA])
|
||||
// return NL_SKIP;
|
||||
|
||||
// nla_parse(tb, OPENWIFI_ATTR_MAX, nla_data(attrs[NL80211_ATTR_TESTDATA]), nla_len(attrs[NL80211_ATTR_TESTDATA]), NULL);
|
||||
|
||||
// printf("openwifi slice_end1 (duration): %dus\n", nla_get_u32(tb[OPENWIFI_ATTR_SLICE_END1]));
|
||||
|
||||
// return NL_SKIP;
|
||||
// }
|
||||
|
||||
// static int handle_set_slice_end1(struct nl80211_state *state,
|
||||
// struct nl_cb *cb,
|
||||
// struct nl_msg *msg,
|
||||
// int argc, char **argv,
|
||||
// enum id_input id)
|
||||
// {
|
||||
// struct nlattr *tmdata;
|
||||
// char *end;
|
||||
// unsigned int tmp;
|
||||
|
||||
// tmdata = nla_nest_start(msg, NL80211_ATTR_TESTDATA);
|
||||
// if (!tmdata) {
|
||||
// return 1;
|
||||
// }
|
||||
|
||||
// tmp = strtoul(argv[0], &end, 10);
|
||||
|
||||
// if (*end) {
|
||||
// return 1;
|
||||
// }
|
||||
|
||||
// NLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_SET_SLICE_END1);
|
||||
// NLA_PUT_U32(msg, OPENWIFI_ATTR_SLICE_END1, tmp);
|
||||
|
||||
// nla_nest_end(msg, tmdata);
|
||||
|
||||
// printf("openwifi slice_end1 (duration): %dus\n", tmp);
|
||||
|
||||
// return 0;
|
||||
|
||||
// nla_put_failure:
|
||||
// return -ENOBUFS;
|
||||
// }
|
||||
// COMMAND(set, slice_end1, "<slice_end1(duration) in us>", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_set_slice_end1, "set slice_end1");
|
||||
|
||||
// static int handle_get_slice_end1(struct nl80211_state *state,
|
||||
// struct nl_cb *cb,
|
||||
// struct nl_msg *msg,
|
||||
// int argc, char **argv,
|
||||
// enum id_input id)
|
||||
// {
|
||||
// struct nlattr *tmdata;
|
||||
|
||||
// tmdata = nla_nest_start(msg, NL80211_ATTR_TESTDATA);
|
||||
// if (!tmdata)
|
||||
// return 1;
|
||||
|
||||
// NLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_GET_SLICE_END1);
|
||||
|
||||
// nla_nest_end(msg, tmdata);
|
||||
|
||||
// nl_cb_set(cb, NL_CB_VALID, NL_CB_CUSTOM, cb_openwifi_slice_end1_handler, NULL);
|
||||
// return 0;
|
||||
|
||||
// nla_put_failure:
|
||||
// return -ENOBUFS;
|
||||
// }
|
||||
// COMMAND(get, slice_end1, "<slice_end1(duration) in us>", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_get_slice_end1, "get slice_end1");
|
||||
|
||||
|
||||
static int cb_openwifi_slice_idx_handler(struct nl_msg *msg, void *arg)
|
||||
{
|
||||
struct nlattr *attrs[NL80211_ATTR_MAX + 1];
|
||||
struct nlattr *tb[OPENWIFI_ATTR_MAX + 1];
|
||||
@ -552,12 +791,12 @@ static int cb_openwifi_slice_start1_handler(struct nl_msg *msg, void *arg)
|
||||
|
||||
nla_parse(tb, OPENWIFI_ATTR_MAX, nla_data(attrs[NL80211_ATTR_TESTDATA]), nla_len(attrs[NL80211_ATTR_TESTDATA]), NULL);
|
||||
|
||||
printf("openwifi slice_start1 (duration): %dus\n", nla_get_u32(tb[OPENWIFI_ATTR_SLICE_START1]));
|
||||
printf("openwifi slice_idx in hex: %08x\n", nla_get_u32(tb[OPENWIFI_ATTR_SLICE_IDX]));
|
||||
|
||||
return NL_SKIP;
|
||||
}
|
||||
|
||||
static int handle_set_slice_start1(struct nl80211_state *state,
|
||||
static int handle_set_slice_idx(struct nl80211_state *state,
|
||||
struct nl_cb *cb,
|
||||
struct nl_msg *msg,
|
||||
int argc, char **argv,
|
||||
@ -565,272 +804,38 @@ static int handle_set_slice_start1(struct nl80211_state *state,
|
||||
{
|
||||
struct nlattr *tmdata;
|
||||
char *end;
|
||||
unsigned int tmp;
|
||||
unsigned int slice_idx;
|
||||
|
||||
tmdata = nla_nest_start(msg, NL80211_ATTR_TESTDATA);
|
||||
if (!tmdata) {
|
||||
return 1;
|
||||
}
|
||||
|
||||
tmp = strtoul(argv[0], &end, 10);
|
||||
|
||||
if (*end) {
|
||||
return 1;
|
||||
}
|
||||
|
||||
NLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_SET_SLICE_START1);
|
||||
NLA_PUT_U32(msg, OPENWIFI_ATTR_SLICE_START1, tmp);
|
||||
|
||||
nla_nest_end(msg, tmdata);
|
||||
|
||||
printf("openwifi slice_start1 (duration): %dus\n", tmp);
|
||||
|
||||
return 0;
|
||||
|
||||
nla_put_failure:
|
||||
return -ENOBUFS;
|
||||
}
|
||||
COMMAND(set, slice_start1, "<slice_start1(duration) in us>", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_set_slice_start1, "set slice_start1");
|
||||
|
||||
static int handle_get_slice_start1(struct nl80211_state *state,
|
||||
struct nl_cb *cb,
|
||||
struct nl_msg *msg,
|
||||
int argc, char **argv,
|
||||
enum id_input id)
|
||||
{
|
||||
struct nlattr *tmdata;
|
||||
|
||||
tmdata = nla_nest_start(msg, NL80211_ATTR_TESTDATA);
|
||||
if (!tmdata)
|
||||
return 1;
|
||||
|
||||
NLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_GET_SLICE_START1);
|
||||
|
||||
nla_nest_end(msg, tmdata);
|
||||
|
||||
nl_cb_set(cb, NL_CB_VALID, NL_CB_CUSTOM, cb_openwifi_slice_start1_handler, NULL);
|
||||
return 0;
|
||||
|
||||
nla_put_failure:
|
||||
return -ENOBUFS;
|
||||
}
|
||||
COMMAND(get, slice_start1, "<slice_start1(duration) in us>", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_get_slice_start1, "get slice_start1");
|
||||
|
||||
|
||||
static int cb_openwifi_slice_end0_handler(struct nl_msg *msg, void *arg)
|
||||
{
|
||||
struct nlattr *attrs[NL80211_ATTR_MAX + 1];
|
||||
struct nlattr *tb[OPENWIFI_ATTR_MAX + 1];
|
||||
struct genlmsghdr *gnlh = nlmsg_data(nlmsg_hdr(msg));
|
||||
|
||||
nla_parse(attrs, NL80211_ATTR_MAX, genlmsg_attrdata(gnlh, 0), genlmsg_attrlen(gnlh, 0), NULL);
|
||||
|
||||
if (!attrs[NL80211_ATTR_TESTDATA])
|
||||
return NL_SKIP;
|
||||
|
||||
nla_parse(tb, OPENWIFI_ATTR_MAX, nla_data(attrs[NL80211_ATTR_TESTDATA]), nla_len(attrs[NL80211_ATTR_TESTDATA]), NULL);
|
||||
|
||||
printf("openwifi slice_end0 (duration): %dus\n", nla_get_u32(tb[OPENWIFI_ATTR_SLICE_END0]));
|
||||
|
||||
return NL_SKIP;
|
||||
}
|
||||
|
||||
static int handle_set_slice_end0(struct nl80211_state *state,
|
||||
struct nl_cb *cb,
|
||||
struct nl_msg *msg,
|
||||
int argc, char **argv,
|
||||
enum id_input id)
|
||||
{
|
||||
struct nlattr *tmdata;
|
||||
char *end;
|
||||
unsigned int tmp;
|
||||
|
||||
tmdata = nla_nest_start(msg, NL80211_ATTR_TESTDATA);
|
||||
if (!tmdata) {
|
||||
return 1;
|
||||
}
|
||||
|
||||
tmp = strtoul(argv[0], &end, 10);
|
||||
|
||||
if (*end) {
|
||||
return 1;
|
||||
}
|
||||
|
||||
NLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_SET_SLICE_END0);
|
||||
NLA_PUT_U32(msg, OPENWIFI_ATTR_SLICE_END0, tmp);
|
||||
|
||||
nla_nest_end(msg, tmdata);
|
||||
|
||||
printf("openwifi slice_end0 (duration): %dus\n", tmp);
|
||||
|
||||
return 0;
|
||||
|
||||
nla_put_failure:
|
||||
return -ENOBUFS;
|
||||
}
|
||||
COMMAND(set, slice_end0, "<slice_end0(duration) in us>", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_set_slice_end0, "set slice_end0");
|
||||
|
||||
static int handle_get_slice_end0(struct nl80211_state *state,
|
||||
struct nl_cb *cb,
|
||||
struct nl_msg *msg,
|
||||
int argc, char **argv,
|
||||
enum id_input id)
|
||||
{
|
||||
struct nlattr *tmdata;
|
||||
|
||||
tmdata = nla_nest_start(msg, NL80211_ATTR_TESTDATA);
|
||||
if (!tmdata)
|
||||
return 1;
|
||||
|
||||
NLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_GET_SLICE_END0);
|
||||
|
||||
nla_nest_end(msg, tmdata);
|
||||
|
||||
nl_cb_set(cb, NL_CB_VALID, NL_CB_CUSTOM, cb_openwifi_slice_end0_handler, NULL);
|
||||
return 0;
|
||||
|
||||
nla_put_failure:
|
||||
return -ENOBUFS;
|
||||
}
|
||||
COMMAND(get, slice_end0, "<slice_end0(duration) in us>", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_get_slice_end0, "get slice_end0");
|
||||
|
||||
|
||||
static int cb_openwifi_slice_end1_handler(struct nl_msg *msg, void *arg)
|
||||
{
|
||||
struct nlattr *attrs[NL80211_ATTR_MAX + 1];
|
||||
struct nlattr *tb[OPENWIFI_ATTR_MAX + 1];
|
||||
struct genlmsghdr *gnlh = nlmsg_data(nlmsg_hdr(msg));
|
||||
|
||||
nla_parse(attrs, NL80211_ATTR_MAX, genlmsg_attrdata(gnlh, 0), genlmsg_attrlen(gnlh, 0), NULL);
|
||||
|
||||
if (!attrs[NL80211_ATTR_TESTDATA])
|
||||
return NL_SKIP;
|
||||
|
||||
nla_parse(tb, OPENWIFI_ATTR_MAX, nla_data(attrs[NL80211_ATTR_TESTDATA]), nla_len(attrs[NL80211_ATTR_TESTDATA]), NULL);
|
||||
|
||||
printf("openwifi slice_end1 (duration): %dus\n", nla_get_u32(tb[OPENWIFI_ATTR_SLICE_END1]));
|
||||
|
||||
return NL_SKIP;
|
||||
}
|
||||
|
||||
static int handle_set_slice_end1(struct nl80211_state *state,
|
||||
struct nl_cb *cb,
|
||||
struct nl_msg *msg,
|
||||
int argc, char **argv,
|
||||
enum id_input id)
|
||||
{
|
||||
struct nlattr *tmdata;
|
||||
char *end;
|
||||
unsigned int tmp;
|
||||
|
||||
tmdata = nla_nest_start(msg, NL80211_ATTR_TESTDATA);
|
||||
if (!tmdata) {
|
||||
return 1;
|
||||
}
|
||||
|
||||
tmp = strtoul(argv[0], &end, 10);
|
||||
|
||||
if (*end) {
|
||||
return 1;
|
||||
}
|
||||
|
||||
NLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_SET_SLICE_END1);
|
||||
NLA_PUT_U32(msg, OPENWIFI_ATTR_SLICE_END1, tmp);
|
||||
|
||||
nla_nest_end(msg, tmdata);
|
||||
|
||||
printf("openwifi slice_end1 (duration): %dus\n", tmp);
|
||||
|
||||
return 0;
|
||||
|
||||
nla_put_failure:
|
||||
return -ENOBUFS;
|
||||
}
|
||||
COMMAND(set, slice_end1, "<slice_end1(duration) in us>", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_set_slice_end1, "set slice_end1");
|
||||
|
||||
static int handle_get_slice_end1(struct nl80211_state *state,
|
||||
struct nl_cb *cb,
|
||||
struct nl_msg *msg,
|
||||
int argc, char **argv,
|
||||
enum id_input id)
|
||||
{
|
||||
struct nlattr *tmdata;
|
||||
|
||||
tmdata = nla_nest_start(msg, NL80211_ATTR_TESTDATA);
|
||||
if (!tmdata)
|
||||
return 1;
|
||||
|
||||
NLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_GET_SLICE_END1);
|
||||
|
||||
nla_nest_end(msg, tmdata);
|
||||
|
||||
nl_cb_set(cb, NL_CB_VALID, NL_CB_CUSTOM, cb_openwifi_slice_end1_handler, NULL);
|
||||
return 0;
|
||||
|
||||
nla_put_failure:
|
||||
return -ENOBUFS;
|
||||
}
|
||||
COMMAND(get, slice_end1, "<slice_end1(duration) in us>", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_get_slice_end1, "get slice_end1");
|
||||
|
||||
|
||||
static int cb_openwifi_slice0_target_mac_addr_handler(struct nl_msg *msg, void *arg)
|
||||
{
|
||||
struct nlattr *attrs[NL80211_ATTR_MAX + 1];
|
||||
struct nlattr *tb[OPENWIFI_ATTR_MAX + 1];
|
||||
struct genlmsghdr *gnlh = nlmsg_data(nlmsg_hdr(msg));
|
||||
|
||||
nla_parse(attrs, NL80211_ATTR_MAX, genlmsg_attrdata(gnlh, 0), genlmsg_attrlen(gnlh, 0), NULL);
|
||||
|
||||
if (!attrs[NL80211_ATTR_TESTDATA])
|
||||
return NL_SKIP;
|
||||
|
||||
nla_parse(tb, OPENWIFI_ATTR_MAX, nla_data(attrs[NL80211_ATTR_TESTDATA]), nla_len(attrs[NL80211_ATTR_TESTDATA]), NULL);
|
||||
|
||||
printf("openwifi slice0_target_mac_addr(low32) in hex: %08x\n", nla_get_u32(tb[OPENWIFI_ATTR_ADDR0]));
|
||||
|
||||
return NL_SKIP;
|
||||
}
|
||||
|
||||
static int handle_set_addr0(struct nl80211_state *state,
|
||||
struct nl_cb *cb,
|
||||
struct nl_msg *msg,
|
||||
int argc, char **argv,
|
||||
enum id_input id)
|
||||
{
|
||||
struct nlattr *tmdata;
|
||||
char *end;
|
||||
unsigned int slice0_target_mac_addr;
|
||||
|
||||
//printf("handle_set_slice0_target_mac_addr\n");
|
||||
//printf("handle_set_slice_idx\n");
|
||||
|
||||
tmdata = nla_nest_start(msg, NL80211_ATTR_TESTDATA);
|
||||
if (!tmdata) {
|
||||
//printf("handle_set_slice0_target_mac_addr 1\n");
|
||||
//printf("handle_set_slice_idx 1\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
slice0_target_mac_addr = strtoul(argv[0], &end, 16);
|
||||
slice_idx = strtoul(argv[0], &end, 16);
|
||||
|
||||
if (*end) {
|
||||
//printf("handle_set_slice0_target_mac_addr 2 %d\n", slice0_target_mac_addr);
|
||||
//printf("handle_set_slice_idx 2 %d\n", slice_idx);
|
||||
return 1;
|
||||
}
|
||||
|
||||
NLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_SET_ADDR0);
|
||||
NLA_PUT_U32(msg, OPENWIFI_ATTR_ADDR0, slice0_target_mac_addr);
|
||||
NLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_SET_SLICE_IDX);
|
||||
NLA_PUT_U32(msg, OPENWIFI_ATTR_SLICE_IDX, slice_idx);
|
||||
|
||||
nla_nest_end(msg, tmdata);
|
||||
|
||||
printf("openwifi slice0_target_mac_addr(low32) in hex: %08x\n", slice0_target_mac_addr);
|
||||
printf("openwifi slice_idx in hex: %08x\n", slice_idx);
|
||||
|
||||
return 0;
|
||||
|
||||
nla_put_failure:
|
||||
return -ENOBUFS;
|
||||
}
|
||||
COMMAND(set, addr0, "<slice0_target_mac_addr(low32) in hex>", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_set_addr0, "set addr0");
|
||||
COMMAND(set, slice_idx, "<slice_idx in hex>", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_set_slice_idx, "set slice_idx");
|
||||
|
||||
static int handle_get_slice0_target_mac_addr(struct nl80211_state *state,
|
||||
static int handle_get_slice_idx(struct nl80211_state *state,
|
||||
struct nl_cb *cb,
|
||||
struct nl_msg *msg,
|
||||
int argc, char **argv,
|
||||
@ -842,19 +847,19 @@ static int handle_get_slice0_target_mac_addr(struct nl80211_state *state,
|
||||
if (!tmdata)
|
||||
return 1;
|
||||
|
||||
NLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_GET_ADDR0);
|
||||
NLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_GET_SLICE_IDX);
|
||||
|
||||
nla_nest_end(msg, tmdata);
|
||||
|
||||
nl_cb_set(cb, NL_CB_VALID, NL_CB_CUSTOM, cb_openwifi_slice0_target_mac_addr_handler, NULL);
|
||||
nl_cb_set(cb, NL_CB_VALID, NL_CB_CUSTOM, cb_openwifi_slice_idx_handler, NULL);
|
||||
return 0;
|
||||
|
||||
nla_put_failure:
|
||||
return -ENOBUFS;
|
||||
}
|
||||
COMMAND(get, addr0, "<slice0_target_mac_addr(low32) in hex>", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_get_slice0_target_mac_addr, "get addr0");
|
||||
COMMAND(get, slice_idx, "<slice_idx in hex>", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_get_slice_idx, "get slice_idx");
|
||||
|
||||
static int cb_openwifi_slice1_target_mac_addr_handler(struct nl_msg *msg, void *arg)
|
||||
static int cb_openwifi_slice_target_mac_addr_handler(struct nl_msg *msg, void *arg)
|
||||
{
|
||||
struct nlattr *attrs[NL80211_ATTR_MAX + 1];
|
||||
struct nlattr *tb[OPENWIFI_ATTR_MAX + 1];
|
||||
@ -867,12 +872,12 @@ static int cb_openwifi_slice1_target_mac_addr_handler(struct nl_msg *msg, void *
|
||||
|
||||
nla_parse(tb, OPENWIFI_ATTR_MAX, nla_data(attrs[NL80211_ATTR_TESTDATA]), nla_len(attrs[NL80211_ATTR_TESTDATA]), NULL);
|
||||
|
||||
printf("openwifi slice1_target_mac_addr(low32) in hex: %08x\n", nla_get_u32(tb[OPENWIFI_ATTR_ADDR1]));
|
||||
printf("openwifi slice_target_mac_addr(low32) in hex: %08x\n", nla_get_u32(tb[OPENWIFI_ATTR_ADDR]));
|
||||
|
||||
return NL_SKIP;
|
||||
}
|
||||
|
||||
static int handle_set_slice1_target_mac_addr(struct nl80211_state *state,
|
||||
static int handle_set_slice_target_mac_addr(struct nl80211_state *state,
|
||||
struct nl_cb *cb,
|
||||
struct nl_msg *msg,
|
||||
int argc, char **argv,
|
||||
@ -880,32 +885,32 @@ static int handle_set_slice1_target_mac_addr(struct nl80211_state *state,
|
||||
{
|
||||
struct nlattr *tmdata;
|
||||
char *end;
|
||||
unsigned int slice1_target_mac_addr;
|
||||
unsigned int slice_target_mac_addr;
|
||||
|
||||
tmdata = nla_nest_start(msg, NL80211_ATTR_TESTDATA);
|
||||
if (!tmdata)
|
||||
return 1;
|
||||
|
||||
slice1_target_mac_addr = strtoul(argv[0], &end, 16);
|
||||
slice_target_mac_addr = strtoul(argv[0], &end, 16);
|
||||
|
||||
if (*end)
|
||||
return 1;
|
||||
|
||||
NLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_SET_ADDR1);
|
||||
NLA_PUT_U32(msg, OPENWIFI_ATTR_ADDR1, slice1_target_mac_addr);
|
||||
NLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_SET_ADDR);
|
||||
NLA_PUT_U32(msg, OPENWIFI_ATTR_ADDR, slice_target_mac_addr);
|
||||
|
||||
nla_nest_end(msg, tmdata);
|
||||
|
||||
printf("openwifi slice1_target_mac_addr(low32) in hex: %08x\n", slice1_target_mac_addr);
|
||||
printf("openwifi slice_target_mac_addr(low32) in hex: %08x\n", slice_target_mac_addr);
|
||||
|
||||
return 0;
|
||||
|
||||
nla_put_failure:
|
||||
return -ENOBUFS;
|
||||
}
|
||||
COMMAND(set, addr1, "<slice1_target_mac_addr(low32) in hex>", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_set_slice1_target_mac_addr, "set addr1");
|
||||
COMMAND(set, addr, "<slice_target_mac_addr(low32) in hex>", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_set_slice_target_mac_addr, "set addr");
|
||||
|
||||
static int handle_get_slice1_target_mac_addr(struct nl80211_state *state,
|
||||
static int handle_get_slice_target_mac_addr(struct nl80211_state *state,
|
||||
struct nl_cb *cb,
|
||||
struct nl_msg *msg,
|
||||
int argc, char **argv,
|
||||
@ -917,17 +922,17 @@ static int handle_get_slice1_target_mac_addr(struct nl80211_state *state,
|
||||
if (!tmdata)
|
||||
return 1;
|
||||
|
||||
NLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_GET_ADDR1);
|
||||
NLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_GET_ADDR);
|
||||
|
||||
nla_nest_end(msg, tmdata);
|
||||
|
||||
nl_cb_set(cb, NL_CB_VALID, NL_CB_CUSTOM, cb_openwifi_slice1_target_mac_addr_handler, NULL);
|
||||
nl_cb_set(cb, NL_CB_VALID, NL_CB_CUSTOM, cb_openwifi_slice_target_mac_addr_handler, NULL);
|
||||
return 0;
|
||||
|
||||
nla_put_failure:
|
||||
return -ENOBUFS;
|
||||
}
|
||||
COMMAND(get, addr1, "<slice1_target_mac_addr(low32) in hex>", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_get_slice1_target_mac_addr, "get addr1");
|
||||
COMMAND(get, addr, "<slice_target_mac_addr(low32) in hex>", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_get_slice_target_mac_addr, "get addr");
|
||||
|
||||
static int cb_openwifi_gap_handler(struct nl_msg *msg, void *arg)
|
||||
{
|
||||
|
||||
@ -1,61 +0,0 @@
|
||||
#ifndef __IEEE80211
|
||||
#define __IEEE80211
|
||||
|
||||
/* 802.11n HT capability AMPDU settings (for ampdu_params_info) */
|
||||
#define IEEE80211_HT_AMPDU_PARM_FACTOR 0x03
|
||||
#define IEEE80211_HT_AMPDU_PARM_DENSITY 0x1C
|
||||
|
||||
#define IEEE80211_HT_CAP_SUP_WIDTH_20_40 0x0002
|
||||
#define IEEE80211_HT_CAP_SGI_40 0x0040
|
||||
#define IEEE80211_HT_CAP_MAX_AMSDU 0x0800
|
||||
|
||||
#define IEEE80211_HT_MCS_MASK_LEN 10
|
||||
|
||||
/**
|
||||
* struct ieee80211_mcs_info - MCS information
|
||||
* @rx_mask: RX mask
|
||||
* @rx_highest: highest supported RX rate. If set represents
|
||||
* the highest supported RX data rate in units of 1 Mbps.
|
||||
* If this field is 0 this value should not be used to
|
||||
* consider the highest RX data rate supported.
|
||||
* @tx_params: TX parameters
|
||||
*/
|
||||
struct ieee80211_mcs_info {
|
||||
__u8 rx_mask[IEEE80211_HT_MCS_MASK_LEN];
|
||||
__u16 rx_highest;
|
||||
__u8 tx_params;
|
||||
__u8 reserved[3];
|
||||
} __attribute__ ((packed));
|
||||
|
||||
|
||||
/**
|
||||
* struct ieee80211_ht_cap - HT capabilities
|
||||
*
|
||||
* This structure is the "HT capabilities element" as
|
||||
* described in 802.11n D5.0 7.3.2.57
|
||||
*/
|
||||
struct ieee80211_ht_cap {
|
||||
__u16 cap_info;
|
||||
__u8 ampdu_params_info;
|
||||
|
||||
/* 16 bytes MCS information */
|
||||
struct ieee80211_mcs_info mcs;
|
||||
|
||||
__u16 extended_ht_cap_info;
|
||||
__u32 tx_BF_cap_info;
|
||||
__u8 antenna_selection_info;
|
||||
} __attribute__ ((packed));
|
||||
|
||||
struct ieee80211_vht_mcs_info {
|
||||
__u16 rx_vht_mcs;
|
||||
__u16 rx_highest;
|
||||
__u16 tx_vht_mcs;
|
||||
__u16 tx_highest;
|
||||
} __attribute__ ((packed));
|
||||
|
||||
struct ieee80211_vht_cap {
|
||||
__u32 cap_info;
|
||||
struct ieee80211_vht_mcs_info mcs;
|
||||
} __attribute__ ((packed));
|
||||
|
||||
#endif /* __IEEE80211 */
|
||||
File diff suppressed because it is too large
Load Diff
@ -5,14 +5,14 @@ enum openwifi_testmode_attr {
|
||||
__OPENWIFI_ATTR_INVALID = 0,
|
||||
OPENWIFI_ATTR_CMD = 1,
|
||||
OPENWIFI_ATTR_GAP = 2,
|
||||
OPENWIFI_ATTR_ADDR0 = 3,
|
||||
OPENWIFI_ATTR_ADDR1 = 4,
|
||||
OPENWIFI_ATTR_SLICE_TOTAL0 = 5,
|
||||
OPENWIFI_ATTR_SLICE_START0 = 6,
|
||||
OPENWIFI_ATTR_SLICE_END0 = 7,
|
||||
OPENWIFI_ATTR_SLICE_TOTAL1 = 8,
|
||||
OPENWIFI_ATTR_SLICE_START1 = 9,
|
||||
OPENWIFI_ATTR_SLICE_END1 = 10,
|
||||
OPENWIFI_ATTR_SLICE_IDX = 3,
|
||||
OPENWIFI_ATTR_ADDR = 4,
|
||||
OPENWIFI_ATTR_SLICE_TOTAL = 5,
|
||||
OPENWIFI_ATTR_SLICE_START = 6,
|
||||
OPENWIFI_ATTR_SLICE_END = 7,
|
||||
// OPENWIFI_ATTR_SLICE_TOTAL1 = 8,
|
||||
// OPENWIFI_ATTR_SLICE_START1 = 9,
|
||||
// OPENWIFI_ATTR_SLICE_END1 = 10,
|
||||
OPENWIFI_ATTR_RSSI_TH = 11,
|
||||
OPENWIFI_ATTR_HIGH_TSF = 12,
|
||||
OPENWIFI_ATTR_LOW_TSF = 13,
|
||||
@ -29,29 +29,29 @@ enum openwifi_testmode_cmd {
|
||||
OPENWIFI_CMD_SET_GAP = 0,
|
||||
OPENWIFI_CMD_GET_GAP = 1,
|
||||
|
||||
OPENWIFI_CMD_SET_ADDR0 = 2,
|
||||
OPENWIFI_CMD_GET_ADDR0 = 3,
|
||||
OPENWIFI_CMD_SET_SLICE_IDX = 2,
|
||||
OPENWIFI_CMD_GET_SLICE_IDX = 3,
|
||||
|
||||
OPENWIFI_CMD_SET_ADDR1 = 4,
|
||||
OPENWIFI_CMD_GET_ADDR1 = 5,
|
||||
OPENWIFI_CMD_SET_ADDR = 4,
|
||||
OPENWIFI_CMD_GET_ADDR = 5,
|
||||
|
||||
OPENWIFI_CMD_SET_SLICE_TOTAL0 = 6,
|
||||
OPENWIFI_CMD_GET_SLICE_TOTAL0 = 7,
|
||||
OPENWIFI_CMD_SET_SLICE_TOTAL = 6,
|
||||
OPENWIFI_CMD_GET_SLICE_TOTAL = 7,
|
||||
|
||||
OPENWIFI_CMD_SET_SLICE_START0 = 8,
|
||||
OPENWIFI_CMD_GET_SLICE_START0 = 9,
|
||||
OPENWIFI_CMD_SET_SLICE_START = 8,
|
||||
OPENWIFI_CMD_GET_SLICE_START = 9,
|
||||
|
||||
OPENWIFI_CMD_SET_SLICE_END0 = 10,
|
||||
OPENWIFI_CMD_GET_SLICE_END0 = 11,
|
||||
OPENWIFI_CMD_SET_SLICE_END = 10,
|
||||
OPENWIFI_CMD_GET_SLICE_END = 11,
|
||||
|
||||
OPENWIFI_CMD_SET_SLICE_TOTAL1 = 12,
|
||||
OPENWIFI_CMD_GET_SLICE_TOTAL1 = 13,
|
||||
// OPENWIFI_CMD_SET_SLICE_TOTAL1 = 12,
|
||||
// OPENWIFI_CMD_GET_SLICE_TOTAL1 = 13,
|
||||
|
||||
OPENWIFI_CMD_SET_SLICE_START1 = 14,
|
||||
OPENWIFI_CMD_GET_SLICE_START1 = 15,
|
||||
// OPENWIFI_CMD_SET_SLICE_START1 = 14,
|
||||
// OPENWIFI_CMD_GET_SLICE_START1 = 15,
|
||||
|
||||
OPENWIFI_CMD_SET_SLICE_END1 = 16,
|
||||
OPENWIFI_CMD_GET_SLICE_END1 = 17,
|
||||
// OPENWIFI_CMD_SET_SLICE_END1 = 16,
|
||||
// OPENWIFI_CMD_GET_SLICE_END1 = 17,
|
||||
|
||||
OPENWIFI_CMD_SET_RSSI_TH = 18,
|
||||
OPENWIFI_CMD_GET_RSSI_TH = 19,
|
||||
@ -65,14 +65,14 @@ enum openwifi_testmode_cmd {
|
||||
static const struct nla_policy openwifi_testmode_policy[OPENWIFI_ATTR_MAX + 1] = {
|
||||
[OPENWIFI_ATTR_CMD] = { .type = NLA_U32 },
|
||||
[OPENWIFI_ATTR_GAP] = { .type = NLA_U32 },
|
||||
[OPENWIFI_ATTR_ADDR0] = { .type = NLA_U32 },
|
||||
[OPENWIFI_ATTR_ADDR1] = { .type = NLA_U32 },
|
||||
[OPENWIFI_ATTR_SLICE_TOTAL0] = { .type = NLA_U32 },
|
||||
[OPENWIFI_ATTR_SLICE_START0] = { .type = NLA_U32 },
|
||||
[OPENWIFI_ATTR_SLICE_END0] = { .type = NLA_U32 },
|
||||
[OPENWIFI_ATTR_SLICE_TOTAL1] = { .type = NLA_U32 },
|
||||
[OPENWIFI_ATTR_SLICE_START1] = { .type = NLA_U32 },
|
||||
[OPENWIFI_ATTR_SLICE_END1] = { .type = NLA_U32 },
|
||||
[OPENWIFI_ATTR_SLICE_IDX] = { .type = NLA_U32 },
|
||||
[OPENWIFI_ATTR_ADDR] = { .type = NLA_U32 },
|
||||
[OPENWIFI_ATTR_SLICE_TOTAL] = { .type = NLA_U32 },
|
||||
[OPENWIFI_ATTR_SLICE_START] = { .type = NLA_U32 },
|
||||
[OPENWIFI_ATTR_SLICE_END] = { .type = NLA_U32 },
|
||||
// [OPENWIFI_ATTR_SLICE_TOTAL1] = { .type = NLA_U32 },
|
||||
// [OPENWIFI_ATTR_SLICE_START1] = { .type = NLA_U32 },
|
||||
// [OPENWIFI_ATTR_SLICE_END1] = { .type = NLA_U32 },
|
||||
[OPENWIFI_ATTR_RSSI_TH] = { .type = NLA_U32 },
|
||||
[OPENWIFI_ATTR_HIGH_TSF] = { .type = NLA_U32 },
|
||||
[OPENWIFI_ATTR_LOW_TSF] = { .type = NLA_U32 },
|
||||
|
||||
@ -9,7 +9,7 @@
|
||||
#include <endian.h>
|
||||
|
||||
#include "nl80211.h"
|
||||
#include "ieee80211.h"
|
||||
//#include "ieee80211.h"
|
||||
|
||||
#define ETH_ALEN 6
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user