From 26825b8b77c556b386f70cd6b83f4d1fac53cd8d Mon Sep 17 00:00:00 2001 From: Xianjun Jiao Date: Tue, 17 Jan 2023 13:14:59 +0100 Subject: [PATCH] Add OPENWIFI_MIN_SIGNAL_LEN_TH 14 to set min pkt length threshold for FPGA signal watchdog --- driver/hw_def.h | 5 ++++- driver/openofdm_rx/openofdm_rx.c | 2 +- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/driver/hw_def.h b/driver/hw_def.h index 3ca68ee..baddf57 100644 --- a/driver/hw_def.h +++ b/driver/hw_def.h @@ -240,7 +240,10 @@ enum openofdm_rx_mode { #define OPENOFDM_RX_DC_RUNNING_SUM_TH_INIT 64 #define OPENOFDM_RX_MIN_PLATEAU_INIT 100 -#define OPENWIFI_MAX_SIGNAL_LEN_TH 1700 //Packet longer than this threshold will result in receiver early termination. It goes to openofdm_rx/xpu/rx_intf +#define OPENWIFI_MAX_SIGNAL_LEN_TH 1700 //Packet longer than this threshold will result in receiver early termination. It goes to openofdm_rx/xpu/rx_intf + +#define OPENWIFI_MIN_SIGNAL_LEN_TH 14 //Packet shorter than this threshold will result in receiver early termination. It goes to openofdm_rx/xpu/rx_intf + //due to CRC32, at least 4 bytes needed to push out expected CRC result struct openofdm_rx_driver_api { u32 (*hw_init)(enum openofdm_rx_mode mode); diff --git a/driver/openofdm_rx/openofdm_rx.c b/driver/openofdm_rx/openofdm_rx.c index cb93a5e..dabe91a 100644 --- a/driver/openofdm_rx/openofdm_rx.c +++ b/driver/openofdm_rx/openofdm_rx.c @@ -93,7 +93,7 @@ static inline u32 hw_init(enum openofdm_rx_mode mode){ // 1) power threshold configuration and reset openofdm_rx_api->OPENOFDM_RX_REG_POWER_THRES_write((OPENOFDM_RX_DC_RUNNING_SUM_TH_INIT<<16)|OPENOFDM_RX_POWER_THRES_INIT); // turn on signal watchdog by default openofdm_rx_api->OPENOFDM_RX_REG_MIN_PLATEAU_write(OPENOFDM_RX_MIN_PLATEAU_INIT); - openofdm_rx_api->OPENOFDM_RX_REG_SOFT_DECODING_write((OPENWIFI_MAX_SIGNAL_LEN_TH<<16)|1); //bit1 enable soft decoding; bit31~16 max pkt length threshold + openofdm_rx_api->OPENOFDM_RX_REG_SOFT_DECODING_write((OPENWIFI_MAX_SIGNAL_LEN_TH<<16)|(OPENWIFI_MIN_SIGNAL_LEN_TH<<12)|1); //bit1 enable soft decoding; bit15~12 min pkt length threshold; bit31~16 max pkt length threshold //rst for (i=0;i<8;i++)