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65 lines
2.4 KiB
Markdown
65 lines
2.4 KiB
Markdown
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Author: Xianjun jiao
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SPDX-FileCopyrightText: 2019 UGent
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SPDX-License-Identifier: AGPL-3.0-or-later
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-->
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Counter/statistics (number of TX packet, RX packet, etc.) in FPGA is offered via side channel register write/read.
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The 1st step is alway loading the side channel kernel module:
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```
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insmod side_ch.ko
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```
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The register write command is:
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```
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./side_ch_ctl whXdY
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X -- register index
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Y -- decimal value to be written
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./side_ch_ctl whXhY
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X -- register index
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Y -- hex value to be written (useful for MAC address)
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```
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Write register 26~31 with arbitrary value to reset the corresponding counter to 0.
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The register read command is:
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```
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./side_ch_ctl rhX
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X -- register index
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```
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## Register definition
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The register 26~31 readback value represents the number of event happened. Each register has two event sources that can be selected via bit in register 19.
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register idx|source selection reg19|event
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------------|----------------------|-----------
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26 |reg19[0] == 0 |short_preamble_detected
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26 |reg19[0] == 1 |phy_tx_start
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27 |reg19[4] == 0 |long_preamble_detected
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27 |reg19[4] == 1 |phy_tx_done
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28 |reg19[8] == 0 |pkt_header_valid_strobe
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28 |reg19[8] == 1 |rssi_above_th
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29 |reg19[12] == 0 |pkt_header_valid_strobe&pkt_header_valid
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29 |reg19[12] == 1 |gain_change
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30 |reg19[16] == 0 |((fcs_in_strobe&addr2_match)&pkt_for_me)&is_data
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30 |reg19[16] == 1 |agc_lock
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31 |reg19[20] == 0 |(((fcs_in_strobe&fcs_ok)&addr2_match)&pkt_for_me)&is_data
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31 |reg19[20] == 1 |tx_pkt_need_ack
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Note: fcs_in_strobe means decoding is done (not necessarily CRC is correct); fcs_ok 1 means CRC correct; fcs_ok 0 means CRC not correct.
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Note: addr2_match means addr2 matches to the register (addr2_target) value; pkt_for_me means addr1 matches self mac addr; is_data means the packet type is data.
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Configuration register:
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register idx|meaning |note
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------------|----------------------|-----------
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7 |addr2 target value |fcs event always needs addr2 match
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9 |threshold for event rssi_above_th|check auto_lbt_th in ad9361_rf_set_channel of sdr.c to estimate a proper value
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Note: addr2 (source/sender's MAC address) target setting uses only 32bit. For address 6c:fd:b9:4c:b1:c1, you set b94cb1c1
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Note: read register 37 of xpu for some addr2 captured by the receiver
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