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32 lines
506 B
Verilog
32 lines
506 B
Verilog
/*
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* A wrapper of Xilinx Viterbi IP core
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* Added strobe signal.
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*/
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module viterbi
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(
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input clock,
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input enable,
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input reset,
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input [2:0] sym0,
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input [2:0] sym1,
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input [1:0] erase,
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input input_strobe,
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output out_bit,
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output output_strobe
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);
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viterbi_v7_0 viterbi_inst (
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.clk(clock),
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.ce(reset | (enable & input_strobe)),
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.sclr(reset),
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.data_in0(sym0),
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.data_in1(sym1),
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.erase(erase),
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.rdy(output_strobe),
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.data_out(out_bit)
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);
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endmodule
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