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45 lines
509 B
Verilog
45 lines
509 B
Verilog
module rand_gen_tb;
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reg clock;
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reg reset;
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reg enable;
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wire [7:0] rnd;
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integer fd;
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rand_gen inst (
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.clock(clock),
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.enable(enable),
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.reset(reset),
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.rnd(rnd)
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);
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initial begin
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clock = 0;
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reset = 1;
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enable = 0;
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fd = $fopen("./sim_out/rand_gen.txt", "w");
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# 10 reset = 0;
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enable = 1;
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# 10000000 $finish;
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end
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always begin
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#1 clock <= ~clock;
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end
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always @(posedge clock) begin
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if (enable) begin
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$fwrite(fd, "%d\n", rnd);
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end
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end
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endmodule
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