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44 lines
924 B
Verilog
44 lines
924 B
Verilog
/*
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* xianjun.jiao@imec.be; putaoshu@msn.com
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* DELAY: 36 cycles -- this is old parameter
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* The new div_gen 5.x allow the valid signal, auto delay or manual delay config
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*/
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module divider (
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input clock,
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input reset,
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input enable,
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input signed [31:0] dividend,
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input signed [23:0] divisor,
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input input_strobe,
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output signed [31:0] quotient,
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output output_strobe
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);
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div_gen div_inst (
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.clk(clock),
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.dividend(dividend),
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.divisor(divisor),
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.input_strobe(input_strobe),
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.output_strobe(output_strobe),
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.quotient(quotient)
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);
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// // --------old one---------------
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// div_gen_v3_0 div_inst (
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// .clk(clock),
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// .dividend(dividend),
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// .divisor(divisor),
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// .quotient(quotient)
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// );
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// delayT #(.DATA_WIDTH(1), .DELAY(36)) out_inst (
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// .clock(clock),
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// .reset(reset),
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// .data_in(input_strobe),
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// .data_out(output_strobe)
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// );
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endmodule
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